commit 243d4a66ec19fca4f0ca8291a48a20bb21d3648b
author Pirmin Vogel <vogelpi@lowrisc.org> Tue Feb 02 12:25:21 2021 +0100
committer Philipp Wagner <mail@philipp-wagner.com> Tue Feb 02 15:16:21 2021 +0000
tree 14b8c2daeff304bc0e39955554cc3f4748ba450c
parent de15468cc0ab71d3196e86637abf25406023446c

[fpga] Fix boot ROM splice script for NexysVideo

Signed-off-by: Pirmin Vogel <vogelpi@lowrisc.org>

util/fpga/bram_load.mmi

diff --git a/util/fpga/bram_load.mmi b/util/fpga/bram_load.mmi
index 5a7cce8..15697c2 100644
--- a/util/fpga/bram_load.mmi
+++ b/util/fpga/bram_load.mmi
@@ -1,7 +1,7 @@
 <?xml version="1.0" encoding="UTF-8"?>
 <MemInfo Version="1" Minor="0">
   <Processor Endianness="Little" InstPath="dummy">
-  <AddressSpace Name="brom" Begin="0" End="4095">
+  <AddressSpace Name="brom" Begin="0" End="16383">
       <BusBlock>
         <BitLane MemType="RAMB32" Placement="X4Y18">
           <DataWidth MSB="7" LSB="0"/>

util/fpga/splice_nexysvideo.sh

diff --git a/util/fpga/splice_nexysvideo.sh b/util/fpga/splice_nexysvideo.sh
index fe3bdbf..98d9990 100755
--- a/util/fpga/splice_nexysvideo.sh
+++ b/util/fpga/splice_nexysvideo.sh
@@ -9,30 +9,41 @@
 #   cd $REPO_TOP
 #   ./util/fpga/splice_nexysvideo.sh
 
-# Updated bitfile located : at the same place as raw vivado bitfile @
+# Updated bitfile located at the same place as raw vivado bitfile at
 # $REPO_TOP/build/lowrisc_systems_top_earlgrey_nexysvideo_0.1/synth-vivado/
-#  lowrisc_systems_top_earlgrey_nexysvideo_0.1.splice.bit
+#  lowrisc_systems_top_earlgrey_nexysvideo_0.1.bit
+# A copy of the original bitfile is created at
+# $REPO_TOP/build/lowrisc_systems_top_earlgrey_nexysvideo_0.1/synth-vivado/
+#  lowrisc_systems_top_earlgrey_nexysvideo_0.1.bit.orig
 set -e
 
 . util/build_consts.sh
 
-TARGET_PREFIX="sw/device/boot_rom/boot_rom_fpga_nexysvideo"
-TARGET="${BIN_DIR}/${TARGET_PREFIX}"
+TARGET_PREFIX="sw/device/boot_rom/"
+TARGET_EXPORT="${TARGET_PREFIX}/boot_rom_export_fpga_nexysvideo"
+TARGET="${BIN_DIR}/${TARGET_PREFIX}/boot_rom_fpga_nexysvideo"
+
 FPGA_BUILD_DIR=build/lowrisc_systems_top_earlgrey_nexysvideo_0.1/synth-vivado/
 FPGA_BIT_NAME=lowrisc_systems_top_earlgrey_nexysvideo_0.1
 
 ./meson_init.sh
-ninja -C "$BIN_DIR" "${TARGET_PREFIX}.bin"
+ninja -C "${OBJ_DIR}" "${TARGET_EXPORT}"
 
 srec_cat "${TARGET}.bin" -binary -offset 0x0 -o "${TARGET}.brammem" \
   -vmem -Output_Block_Size 4;
 
 util/fpga/addr4x.py -i "${TARGET}.brammem" -o "${TARGET}.mem"
 
+# The --debug flag is undocumented and causes updatemem to print out the INIT_XX
+# values of the four BRAM cells. These values are also oberservable when opening
+# the implemented design in Vivado and then inspecting the cell properties of
+# the corresponding BRAM cells. This information is very useful when debugging
+# the splicing flow.
 updatemem -force --meminfo util/fpga/bram_load.mmi \
   --data "${TARGET}.mem" \
   --bit "${FPGA_BUILD_DIR}/${FPGA_BIT_NAME}.bit"  --proc dummy \
-  --out "${FPGA_BUILD_DIR}/${FPGA_BIT_NAME}.splice.bit"
+  --out "${FPGA_BUILD_DIR}/${FPGA_BIT_NAME}.splice.bit" \
+  --debug
 
 mv ${FPGA_BUILD_DIR}/${FPGA_BIT_NAME}.bit ${FPGA_BUILD_DIR}/${FPGA_BIT_NAME}.bit.orig
 mv ${FPGA_BUILD_DIR}/${FPGA_BIT_NAME}.splice.bit ${FPGA_BUILD_DIR}/${FPGA_BIT_NAME}.bit