[i2c, rtl] Fixes to Lint Errors and Changes to Clock Stretching by Target
1. Fixed Lint errors related to FIFO depth
2. Modified clock stretching by target after matching an address:
- en_addr_tx and stop_tx for transmit (read) transactions
- en_addr_acq and stop_acq for acquire (write) transactions
3. Disabled clock stretching by target after transmitting or acquiring a data byte
Signed-off-by: Igor Kouznetsov <igor.kouznetsov@wdc.com>
diff --git a/hw/ip/i2c/data/i2c.hjson b/hw/ip/i2c/data/i2c.hjson
index f432c1b..ab31da6 100644
--- a/hw/ip/i2c/data/i2c.hjson
+++ b/hw/ip/i2c/data/i2c.hjson
@@ -511,23 +511,23 @@
fields: [
{ bits: "0"
hwaccess: "hro"
- name: "ENABLEADDR"
- desc: "Enable clock stretching after address matching completes"
+ name: "EN_ADDR_TX"
+ desc: "Enable clock stretching after address matching completes for transmit (read)"
}
{ bits: "1"
hwaccess: "hro"
- name: "ENABLETX"
- desc: "Enable clock stretching after ongoing transmit (read) transaction completes"
+ name: "EN_ADDR_ACQ"
+ desc: "Enable clock stretching after address matching completes for acquire (write)"
}
{ bits: "2"
- hwaccess: "hro"
- name: "ENABLEACQ"
- desc: "Enable clock stretching after ongoing acquire (write) transaction completes"
+ hwaccess: "hrw"
+ name: "STOP_TX"
+ desc: "Stop clock stretching for transmit (read) and resume normal operation"
}
{ bits: "3"
hwaccess: "hrw"
- name: "STOP"
- desc: "Stop clock stretching and resume normal operation"
+ name: "STOP_ACQ"
+ desc: "Stop clock stretching for acquire (write) and resume normal operation"
}
]
}
diff --git a/hw/ip/i2c/rtl/i2c_core.sv b/hw/ip/i2c/rtl/i2c_core.sv
index f5c1f36..abe2d8a 100644
--- a/hw/ip/i2c/rtl/i2c_core.sv
+++ b/hw/ip/i2c/rtl/i2c_core.sv
@@ -46,11 +46,12 @@
logic [15:0] t_buf;
logic [30:0] stretch_timeout;
logic timeout_enable;
- logic stretch_en_addr;
- logic stretch_en_tx;
- logic stretch_en_acq;
- logic stretch_stop;
- logic stretch_stop_clr;
+ logic stretch_en_addr_tx;
+ logic stretch_en_addr_acq;
+ logic stretch_stop_tx;
+ logic stretch_stop_acq;
+ logic stretch_stop_tx_clr;
+ logic stretch_stop_acq_clr;
logic [31:0] host_timeout;
logic scl_sync;
@@ -83,7 +84,7 @@
logic fmt_fifo_wvalid;
logic fmt_fifo_wready;
logic [12:0] fmt_fifo_wdata;
- logic [5:0] fmt_fifo_depth;
+ logic [6:0] fmt_fifo_depth;
logic fmt_fifo_rvalid;
logic fmt_fifo_rready;
logic [12:0] fmt_fifo_rdata;
@@ -102,7 +103,7 @@
logic rx_fifo_wvalid;
logic rx_fifo_wready;
logic [7:0] rx_fifo_wdata;
- logic [5:0] rx_fifo_depth;
+ logic [6:0] rx_fifo_depth;
logic rx_fifo_rvalid;
logic rx_fifo_rready;
logic [7:0] rx_fifo_rdata;
@@ -115,7 +116,7 @@
logic tx_fifo_wvalid;
logic tx_fifo_wready;
logic [7:0] tx_fifo_wdata;
- logic [5:0] tx_fifo_depth;
+ logic [6:0] tx_fifo_depth;
logic tx_fifo_rvalid;
logic tx_fifo_rready;
logic [7:0] tx_fifo_rdata;
@@ -123,7 +124,7 @@
logic acq_fifo_wvalid;
logic acq_fifo_wready;
logic [9:0] acq_fifo_wdata;
- logic [5:0] acq_fifo_depth;
+ logic [6:0] acq_fifo_depth;
logic acq_fifo_rvalid;
logic acq_fifo_rready;
logic [9:0] acq_fifo_rdata;
@@ -170,8 +171,10 @@
assign hw2reg.fifo_status.acqlvl.d = acq_fifo_depth;
assign hw2reg.acqdata.abyte.d = line_loopback ? 8'hff : acq_fifo_rdata[7:0];
assign hw2reg.acqdata.signal.d = line_loopback ? 2'b11 : acq_fifo_rdata[9:8];
- assign hw2reg.stretch_ctrl.stop.d = 1'b0;
- assign hw2reg.stretch_ctrl.stop.de = stretch_stop_clr;
+ assign hw2reg.stretch_ctrl.stop_tx.d = 1'b0;
+ assign hw2reg.stretch_ctrl.stop_tx.de = stretch_stop_tx_clr;
+ assign hw2reg.stretch_ctrl.stop_acq.d = 1'b0;
+ assign hw2reg.stretch_ctrl.stop_acq.de = stretch_stop_acq_clr;
assign override = reg2hw.ovrd.txovrden;
@@ -210,12 +213,13 @@
assign t_buf = reg2hw.timing4.t_buf.q;
assign stretch_timeout = reg2hw.timeout_ctrl.val.q;
assign timeout_enable = reg2hw.timeout_ctrl.en.q;
- assign stretch_en_addr = reg2hw.stretch_ctrl.enableaddr.q;
- assign stretch_en_tx = reg2hw.stretch_ctrl.enabletx.q;
- assign stretch_en_acq = reg2hw.stretch_ctrl.enableacq.q;
- assign stretch_stop = reg2hw.stretch_ctrl.stop.q;
assign host_timeout = reg2hw.host_timeout_ctrl.q;
+ assign stretch_en_addr_tx = reg2hw.stretch_ctrl.en_addr_tx.q;
+ assign stretch_en_addr_acq = reg2hw.stretch_ctrl.en_addr_acq.q;
+ assign stretch_stop_tx = reg2hw.stretch_ctrl.stop_tx.q;
+ assign stretch_stop_acq = reg2hw.stretch_ctrl.stop_acq.q;
+
assign i2c_fifo_rxrst = reg2hw.fifo_ctrl.rxrst.q & reg2hw.fifo_ctrl.rxrst.qe;
assign i2c_fifo_fmtrst = reg2hw.fifo_ctrl.fmtrst.q & reg2hw.fifo_ctrl.fmtrst.qe;
assign i2c_fifo_rxilvl = reg2hw.fifo_ctrl.rxilvl.q;
@@ -448,18 +452,20 @@
.t_buf_i (t_buf),
.stretch_timeout_i (stretch_timeout),
.timeout_enable_i (timeout_enable),
- .stretch_en_addr_i (stretch_en_addr),
- .stretch_en_tx_i (stretch_en_tx),
- .stretch_en_acq_i (stretch_en_acq),
- .stretch_stop_i (stretch_stop),
.host_timeout_i (host_timeout),
+ .stretch_en_addr_tx_i (stretch_en_addr_tx),
+ .stretch_en_addr_acq_i (stretch_en_addr_acq),
+ .stretch_stop_tx_i (stretch_stop_tx),
+ .stretch_stop_acq_i (stretch_stop_acq),
+
.target_address0_i (target_address0),
.target_mask0_i (target_mask0),
.target_address1_i (target_address1),
.target_mask1_i (target_mask1),
- .stretch_stop_clr_o (stretch_stop_clr),
+ .stretch_stop_tx_clr_o (stretch_stop_tx_clr),
+ .stretch_stop_acq_clr_o (stretch_stop_acq_clr),
.event_nak_o (event_nak),
.event_scl_interference_o(event_scl_interference),
diff --git a/hw/ip/i2c/rtl/i2c_fsm.sv b/hw/ip/i2c/rtl/i2c_fsm.sv
index 64a947b..4daf75a 100644
--- a/hw/ip/i2c/rtl/i2c_fsm.sv
+++ b/hw/ip/i2c/rtl/i2c_fsm.sv
@@ -55,18 +55,20 @@
input [15:0] t_buf_i, // bus free time between STOP and START in clock units
input [30:0] stretch_timeout_i, // max time target may stretch the clock
input timeout_enable_i, // assert if target stretches clock past max
- input stretch_en_addr_i, // enable target stretching clock after address matching
- input stretch_en_tx_i, // enable target stretching clock after transmit transaction
- input stretch_en_acq_i, // enable target stretching clock after acquire transaction
- input stretch_stop_i, // stop stretching clock and resume normal operation
input [31:0] host_timeout_i, // max time target waits for host to pull clock down
+ input stretch_en_addr_tx_i, // target stretches clock after address matching for transmit
+ input stretch_en_addr_acq_i, // target stretches clock after address matching for acquire
+ input stretch_stop_tx_i, // stop stretching clock for transmit, resume normal operation
+ input stretch_stop_acq_i, // stop stretching clock for acquire, resume normal operation
+
input logic [6:0] target_address0_i,
input logic [6:0] target_mask0_i,
input logic [6:0] target_address1_i,
input logic [6:0] target_mask1_i,
- output logic stretch_stop_clr_o, // hardware to deassert stretch_stop bit
+ output logic stretch_stop_tx_clr_o, // hardware to deassert stretch_stop_tx bit
+ output logic stretch_stop_acq_clr_o, // hardware to deassert stretch_stop_acq bit
output logic event_nak_o, // target didn't Ack when expected
output logic event_scl_interference_o, // other device forcing SCL low
@@ -117,8 +119,10 @@
logic [7:0] input_byte; // register for reads from host
logic input_byte_clr;// clear input_byte contents
logic [31:0] scl_high_cnt; // counter for continuously released scl_i
- logic addr_stop; // indicates stretch_stop and stretch_en_addr are both asserted
- logic stretch_stop_clr;
+ logic addr_stop_tx; // indicates stretch_stop_tx and stretch_en_addr_tx are asserted
+ logic addr_stop_acq; // indicates stretch_stop_acq and stretch_en_addr_acq are asserted
+ logic stretch_stop_tx_clr;
+ logic stretch_stop_acq_clr;
// Target bit counter variables
logic [3:0] bit_idx; // bit index including ack/nack
@@ -323,16 +327,27 @@
end
end
- // Deasserting stretch_stop bit after the first target address match
- always_ff @ (posedge clk_i or negedge rst_ni) begin : stretch_addr_sp
+ // Deasserting stretch_stop_tx bit after the first target address match for transmit
+ always_ff @ (posedge clk_i or negedge rst_ni) begin : stretch_addr_sp_tx
if (!rst_ni) begin
- stretch_stop_clr <= 1'b0;
- end else if (addr_stop) begin
- stretch_stop_clr <= 1'b1;
+ stretch_stop_tx_clr <= 1'b0;
+ end else if (addr_stop_tx) begin
+ stretch_stop_tx_clr <= 1'b1;
end
end
- assign stretch_stop_clr_o = stretch_stop_clr;
+ assign stretch_stop_tx_clr_o = stretch_stop_tx_clr;
+
+ // Deasserting stretch_stop_acq bit after the first target address match for acquire
+ always_ff @ (posedge clk_i or negedge rst_ni) begin : stretch_addr_sp_acq
+ if (!rst_ni) begin
+ stretch_stop_acq_clr <= 1'b0;
+ end else if (addr_stop_acq) begin
+ stretch_stop_acq_clr <= 1'b1;
+ end
+ end
+
+ assign stretch_stop_acq_clr_o = stretch_stop_acq_clr;
// State definitions
typedef enum logic [5:0] {
@@ -345,8 +360,8 @@
AcquireStart, AddrRead, AddrAckWait, AddrAckSetup, AddrAckPulse, AddrAckHold,
TransmitWait, TransmitSetup, TransmitPulse, TransmitHold, TransmitAck,
AcquireByte, AcquireAckWait, AcquireAckSetup, AcquireAckPulse, AcquireAckHold,
- PopTxFifo, AcquireSrP, StretchTxEmpty, StretchAcqFull, StretchAddr,
- StretchAcquire, StretchTransmit, StretchTransmitWait
+ PopTxFifo, AcquireSrP, StretchTxEmpty, StretchAcqFull, StretchAddrTransmit,
+ StretchAddrAcquire
} state_e;
state_e state_q, state_d;
@@ -658,22 +673,13 @@
acq_fifo_wvalid_o = 1'b1;
if (tx_fifo_depth_i != '0) event_tx_nonempty_o = 1'b1;
end
- // StretchAddr: target stretches the clock after matching an address
- StretchAddr : begin
+ // StretchAddrTransmit: target stretches the clock after matching an address for transmit
+ StretchAddrTransmit : begin
target_idle_o = 1'b0;
scl_temp = 1'b0;
end
- // StretchAcquire: target stretches the clock after acquiring a byte
- StretchAcquire : begin
- target_idle_o = 1'b0;
- scl_temp = 1'b0;
- end
- // StretchTransmitWait: target waits for host to pull SCL low before stretching the clock
- StretchTransmitWait : begin
- target_idle_o = 1'b0;
- end
- // StretchTransmit: target stretches the clock after transmitting a byte
- StretchTransmit : begin
+ // StretchAddrAcquire: target stretches the clock after matching an address for acquire
+ StretchAddrAcquire : begin
target_idle_o = 1'b0;
scl_temp = 1'b0;
end
@@ -729,7 +735,8 @@
log_stop = 1'b0;
restart = 1'b0;
input_byte_clr = 1'b0;
- addr_stop = 1'b0;
+ addr_stop_tx = 1'b0;
+ addr_stop_acq = 1'b0;
unique case (state_q)
// Idle: initial state, SDA and SCL are released (high)
@@ -1026,11 +1033,19 @@
AddrAckWait : begin
if (tcount_q == 20'd1) begin
if (!scl_i) begin
- if (stretch_en_addr_i && !stretch_stop_i) state_d = StretchAddr;
- else if (stretch_en_addr_i && stretch_stop_i) begin
- state_d = AddrAckSetup;
- addr_stop = 1'b1;
- end else state_d = AddrAckSetup;
+ if (rw_bit) begin
+ if (stretch_en_addr_tx_i && !stretch_stop_tx_i) state_d = StretchAddrTransmit;
+ else if (stretch_en_addr_tx_i && stretch_stop_tx_i) begin
+ state_d = AddrAckSetup;
+ addr_stop_tx = 1'b1;
+ end else state_d = AddrAckSetup;
+ end else begin
+ if (stretch_en_addr_acq_i && !stretch_stop_acq_i) state_d = StretchAddrAcquire;
+ else if (stretch_en_addr_acq_i && stretch_stop_acq_i) begin
+ state_d = AddrAckSetup;
+ addr_stop_acq = 1'b1;
+ end else state_d = AddrAckSetup;
+ end
end
end
end
@@ -1096,8 +1111,7 @@
TransmitAck : begin
if (scl_i) begin
if (host_ack) begin
- if (stretch_en_tx_i) state_d = StretchTransmitWait;
- else state_d = PopTxFifo;
+ state_d = PopTxFifo;
end else begin
if (start_det || stop_det) state_d = AcquireSrP;
end
@@ -1129,10 +1143,7 @@
// AcquireAckWait: pause before acknowledging
AcquireAckWait : begin
if (tcount_q == 20'd1) begin
- if (!scl_i) begin
- if (stretch_en_acq_i) state_d = StretchAcquire;
- else state_d = AcquireAckSetup;
- end
+ if (!scl_i) state_d = AcquireAckSetup;
end
end
// AcquireAckSetup: target pulls SDA low while SCL is low
@@ -1162,27 +1173,16 @@
state_d = Idle;
end
- // StretchAddr: target stretches the clock after matching an address
- StretchAddr : begin
- if (!stretch_stop_i) state_d = StretchAddr;
+ // StretchAddrTransmit: target stretches the clock after matching an address for transmit
+ StretchAddrTransmit : begin
+ if (!stretch_stop_tx_i) state_d = StretchAddrTransmit;
else state_d = AddrAckSetup;
end
- // StretchAcquire: target stretches the clock after acquiring a byte
- StretchAcquire : begin
- if (!stretch_stop_i) state_d = StretchAcquire;
- else state_d = AcquireAckSetup;
- end
-
- // StretchTransmitWait: target waits for host to pull SCL low before stretching the clock
- StretchTransmitWait : begin
- if (!scl_i) state_d = StretchTransmit;
- end
-
- // StretchTransmit: target stretches the clock after transmitting a byte
- StretchTransmit : begin
- if (!stretch_stop_i) state_d = StretchTransmit;
- else state_d = PopTxFifo;
+ // StretchAddrAcquire: target stretches the clock after matching an address for acquire
+ StretchAddrAcquire : begin
+ if (!stretch_stop_acq_i) state_d = StretchAddrAcquire;
+ else state_d = AddrAckSetup;
end
// StretchTxEmpty: target stretches the clock when tx_fifo is empty
@@ -1217,7 +1217,8 @@
log_stop = 1'b0;
restart = 1'b0;
input_byte_clr = 1'b0;
- addr_stop = 1'b0;
+ addr_stop_tx = 1'b0;
+ addr_stop_acq = 1'b0;
end
endcase
end
diff --git a/hw/ip/i2c/rtl/i2c_reg_pkg.sv b/hw/ip/i2c/rtl/i2c_reg_pkg.sv
index 9eceb8a..d6c5b77 100644
--- a/hw/ip/i2c/rtl/i2c_reg_pkg.sv
+++ b/hw/ip/i2c/rtl/i2c_reg_pkg.sv
@@ -353,16 +353,16 @@
typedef struct packed {
struct packed {
logic q;
- } enableaddr;
+ } en_addr_tx;
struct packed {
logic q;
- } enabletx;
+ } en_addr_acq;
struct packed {
logic q;
- } enableacq;
+ } stop_tx;
struct packed {
logic q;
- } stop;
+ } stop_acq;
} i2c_reg2hw_stretch_ctrl_reg_t;
typedef struct packed {
@@ -510,7 +510,11 @@
struct packed {
logic d;
logic de;
- } stop;
+ } stop_tx;
+ struct packed {
+ logic d;
+ logic de;
+ } stop_acq;
} i2c_hw2reg_stretch_ctrl_reg_t;
// Register -> HW type
@@ -538,13 +542,13 @@
// HW -> register type
typedef struct packed {
- i2c_hw2reg_intr_state_reg_t intr_state; // [117:86]
- i2c_hw2reg_status_reg_t status; // [85:76]
- i2c_hw2reg_rdata_reg_t rdata; // [75:68]
- i2c_hw2reg_fifo_status_reg_t fifo_status; // [67:44]
- i2c_hw2reg_val_reg_t val; // [43:12]
- i2c_hw2reg_acqdata_reg_t acqdata; // [11:2]
- i2c_hw2reg_stretch_ctrl_reg_t stretch_ctrl; // [1:0]
+ i2c_hw2reg_intr_state_reg_t intr_state; // [119:88]
+ i2c_hw2reg_status_reg_t status; // [87:78]
+ i2c_hw2reg_rdata_reg_t rdata; // [77:70]
+ i2c_hw2reg_fifo_status_reg_t fifo_status; // [69:46]
+ i2c_hw2reg_val_reg_t val; // [45:14]
+ i2c_hw2reg_acqdata_reg_t acqdata; // [13:4]
+ i2c_hw2reg_stretch_ctrl_reg_t stretch_ctrl; // [3:0]
} i2c_hw2reg_t;
// Register offsets
diff --git a/hw/ip/i2c/rtl/i2c_reg_top.sv b/hw/ip/i2c/rtl/i2c_reg_top.sv
index 1665b78..c6f377c 100644
--- a/hw/ip/i2c/rtl/i2c_reg_top.sv
+++ b/hw/ip/i2c/rtl/i2c_reg_top.sv
@@ -364,18 +364,18 @@
logic acqdata_signal_re;
logic [7:0] txdata_wd;
logic txdata_we;
- logic stretch_ctrl_enableaddr_qs;
- logic stretch_ctrl_enableaddr_wd;
- logic stretch_ctrl_enableaddr_we;
- logic stretch_ctrl_enabletx_qs;
- logic stretch_ctrl_enabletx_wd;
- logic stretch_ctrl_enabletx_we;
- logic stretch_ctrl_enableacq_qs;
- logic stretch_ctrl_enableacq_wd;
- logic stretch_ctrl_enableacq_we;
- logic stretch_ctrl_stop_qs;
- logic stretch_ctrl_stop_wd;
- logic stretch_ctrl_stop_we;
+ logic stretch_ctrl_en_addr_tx_qs;
+ logic stretch_ctrl_en_addr_tx_wd;
+ logic stretch_ctrl_en_addr_tx_we;
+ logic stretch_ctrl_en_addr_acq_qs;
+ logic stretch_ctrl_en_addr_acq_wd;
+ logic stretch_ctrl_en_addr_acq_we;
+ logic stretch_ctrl_stop_tx_qs;
+ logic stretch_ctrl_stop_tx_wd;
+ logic stretch_ctrl_stop_tx_we;
+ logic stretch_ctrl_stop_acq_qs;
+ logic stretch_ctrl_stop_acq_wd;
+ logic stretch_ctrl_stop_acq_we;
logic [31:0] host_timeout_ctrl_qs;
logic [31:0] host_timeout_ctrl_wd;
logic host_timeout_ctrl_we;
@@ -2677,18 +2677,18 @@
// R[stretch_ctrl]: V(False)
- // F[enableaddr]: 0:0
+ // F[en_addr_tx]: 0:0
prim_subreg #(
.DW (1),
.SWACCESS("RW"),
.RESVAL (1'h0)
- ) u_stretch_ctrl_enableaddr (
+ ) u_stretch_ctrl_en_addr_tx (
.clk_i (clk_i ),
.rst_ni (rst_ni ),
// from register interface
- .we (stretch_ctrl_enableaddr_we),
- .wd (stretch_ctrl_enableaddr_wd),
+ .we (stretch_ctrl_en_addr_tx_we),
+ .wd (stretch_ctrl_en_addr_tx_wd),
// from internal hardware
.de (1'b0),
@@ -2696,25 +2696,25 @@
// to internal hardware
.qe (),
- .q (reg2hw.stretch_ctrl.enableaddr.q ),
+ .q (reg2hw.stretch_ctrl.en_addr_tx.q ),
// to register interface (read)
- .qs (stretch_ctrl_enableaddr_qs)
+ .qs (stretch_ctrl_en_addr_tx_qs)
);
- // F[enabletx]: 1:1
+ // F[en_addr_acq]: 1:1
prim_subreg #(
.DW (1),
.SWACCESS("RW"),
.RESVAL (1'h0)
- ) u_stretch_ctrl_enabletx (
+ ) u_stretch_ctrl_en_addr_acq (
.clk_i (clk_i ),
.rst_ni (rst_ni ),
// from register interface
- .we (stretch_ctrl_enabletx_we),
- .wd (stretch_ctrl_enabletx_wd),
+ .we (stretch_ctrl_en_addr_acq_we),
+ .wd (stretch_ctrl_en_addr_acq_wd),
// from internal hardware
.de (1'b0),
@@ -2722,62 +2722,62 @@
// to internal hardware
.qe (),
- .q (reg2hw.stretch_ctrl.enabletx.q ),
+ .q (reg2hw.stretch_ctrl.en_addr_acq.q ),
// to register interface (read)
- .qs (stretch_ctrl_enabletx_qs)
+ .qs (stretch_ctrl_en_addr_acq_qs)
);
- // F[enableacq]: 2:2
+ // F[stop_tx]: 2:2
prim_subreg #(
.DW (1),
.SWACCESS("RW"),
.RESVAL (1'h0)
- ) u_stretch_ctrl_enableacq (
+ ) u_stretch_ctrl_stop_tx (
.clk_i (clk_i ),
.rst_ni (rst_ni ),
// from register interface
- .we (stretch_ctrl_enableacq_we),
- .wd (stretch_ctrl_enableacq_wd),
+ .we (stretch_ctrl_stop_tx_we),
+ .wd (stretch_ctrl_stop_tx_wd),
// from internal hardware
- .de (1'b0),
- .d ('0 ),
+ .de (hw2reg.stretch_ctrl.stop_tx.de),
+ .d (hw2reg.stretch_ctrl.stop_tx.d ),
// to internal hardware
.qe (),
- .q (reg2hw.stretch_ctrl.enableacq.q ),
+ .q (reg2hw.stretch_ctrl.stop_tx.q ),
// to register interface (read)
- .qs (stretch_ctrl_enableacq_qs)
+ .qs (stretch_ctrl_stop_tx_qs)
);
- // F[stop]: 3:3
+ // F[stop_acq]: 3:3
prim_subreg #(
.DW (1),
.SWACCESS("RW"),
.RESVAL (1'h0)
- ) u_stretch_ctrl_stop (
+ ) u_stretch_ctrl_stop_acq (
.clk_i (clk_i ),
.rst_ni (rst_ni ),
// from register interface
- .we (stretch_ctrl_stop_we),
- .wd (stretch_ctrl_stop_wd),
+ .we (stretch_ctrl_stop_acq_we),
+ .wd (stretch_ctrl_stop_acq_wd),
// from internal hardware
- .de (hw2reg.stretch_ctrl.stop.de),
- .d (hw2reg.stretch_ctrl.stop.d ),
+ .de (hw2reg.stretch_ctrl.stop_acq.de),
+ .d (hw2reg.stretch_ctrl.stop_acq.d ),
// to internal hardware
.qe (),
- .q (reg2hw.stretch_ctrl.stop.q ),
+ .q (reg2hw.stretch_ctrl.stop_acq.q ),
// to register interface (read)
- .qs (stretch_ctrl_stop_qs)
+ .qs (stretch_ctrl_stop_acq_qs)
);
@@ -3153,17 +3153,17 @@
assign txdata_we = addr_hit[19] & reg_we & !reg_error;
assign txdata_wd = reg_wdata[7:0];
- assign stretch_ctrl_enableaddr_we = addr_hit[20] & reg_we & !reg_error;
- assign stretch_ctrl_enableaddr_wd = reg_wdata[0];
+ assign stretch_ctrl_en_addr_tx_we = addr_hit[20] & reg_we & !reg_error;
+ assign stretch_ctrl_en_addr_tx_wd = reg_wdata[0];
- assign stretch_ctrl_enabletx_we = addr_hit[20] & reg_we & !reg_error;
- assign stretch_ctrl_enabletx_wd = reg_wdata[1];
+ assign stretch_ctrl_en_addr_acq_we = addr_hit[20] & reg_we & !reg_error;
+ assign stretch_ctrl_en_addr_acq_wd = reg_wdata[1];
- assign stretch_ctrl_enableacq_we = addr_hit[20] & reg_we & !reg_error;
- assign stretch_ctrl_enableacq_wd = reg_wdata[2];
+ assign stretch_ctrl_stop_tx_we = addr_hit[20] & reg_we & !reg_error;
+ assign stretch_ctrl_stop_tx_wd = reg_wdata[2];
- assign stretch_ctrl_stop_we = addr_hit[20] & reg_we & !reg_error;
- assign stretch_ctrl_stop_wd = reg_wdata[3];
+ assign stretch_ctrl_stop_acq_we = addr_hit[20] & reg_we & !reg_error;
+ assign stretch_ctrl_stop_acq_wd = reg_wdata[3];
assign host_timeout_ctrl_we = addr_hit[21] & reg_we & !reg_error;
assign host_timeout_ctrl_wd = reg_wdata[31:0];
@@ -3335,10 +3335,10 @@
end
addr_hit[20]: begin
- reg_rdata_next[0] = stretch_ctrl_enableaddr_qs;
- reg_rdata_next[1] = stretch_ctrl_enabletx_qs;
- reg_rdata_next[2] = stretch_ctrl_enableacq_qs;
- reg_rdata_next[3] = stretch_ctrl_stop_qs;
+ reg_rdata_next[0] = stretch_ctrl_en_addr_tx_qs;
+ reg_rdata_next[1] = stretch_ctrl_en_addr_acq_qs;
+ reg_rdata_next[2] = stretch_ctrl_stop_tx_qs;
+ reg_rdata_next[3] = stretch_ctrl_stop_acq_qs;
end
addr_hit[21]: begin
