| commit | 22e570635916f7d901bce9ffe0c090031a9ea2f5 | [log] [tgz] |
|---|---|---|
| author | Cindy Chen <chencindy@google.com> | Wed Sep 09 10:51:06 2020 -0700 |
| committer | cindychip <cindy.chen0316@gmail.com> | Thu Sep 10 13:46:46 2020 -0700 |
| tree | a4d253ab5a4cb1730431ab2cb578f60f24471404 | |
| parent | cf37d9e4932be7066aa83b28b7be63336939f62b [diff] |
[hmac/fix] corner case for error sequences While modifying hmac scb I found a corner case where in hmac error sequence. In sanity sequence, if hmac msg stream in msg is partial (length is not a multiple of 4), there is one clock cycle that is wavied to check fifo_empty interrupt. So in sanity sequence I used `msg_q % 4` to gate it. But in hmac_error seq, we are not always stream in `msg_q`, if we found the sequence causes an error, we will resend some other random messages. This could potentially stream in partial message. So this PR resolves this issue by gating the error_sequence as well. Signed-off-by: Cindy Chen <chencindy@google.com>
OpenTitan is an open source silicon Root of Trust (RoT) project. OpenTitan will make the silicon RoT design and implementation more transparent, trustworthy, and secure for enterprises, platform providers, and chip manufacturers. OpenTitan is administered by lowRISC CIC as a collaborative project to produce high quality, open IP for instantiation as a full-featured product. See the OpenTitan site and OpenTitan docs for more information about the project.
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