[top / flash] Auto generate files
Signed-off-by: Timothy Chen <timothytim@google.com>
diff --git a/hw/ip/flash_ctrl/data/flash_ctrl.hjson b/hw/ip/flash_ctrl/data/flash_ctrl.hjson
index 7147fe4..86dc88e 100644
--- a/hw/ip/flash_ctrl/data/flash_ctrl.hjson
+++ b/hw/ip/flash_ctrl/data/flash_ctrl.hjson
@@ -31,7 +31,21 @@
{ struct: "lc_tx",
type: "uni",
- name: "lc_provision_en",
+ name: "lc_provision_wr_en",
+ act: "rcv",
+ package: "lc_ctrl_pkg"
+ },
+
+ { struct: "lc_tx",
+ type: "uni",
+ name: "lc_provision_rd_en",
+ act: "rcv",
+ package: "lc_ctrl_pkg"
+ },
+
+ { struct: "lc_tx",
+ type: "uni",
+ name: "lc_iso_flash_wr_en",
act: "rcv",
package: "lc_ctrl_pkg"
},
diff --git a/hw/ip/flash_ctrl/rtl/flash_ctrl.sv b/hw/ip/flash_ctrl/rtl/flash_ctrl.sv
index 46f53e2..aaeb93a 100644
--- a/hw/ip/flash_ctrl/rtl/flash_ctrl.sv
+++ b/hw/ip/flash_ctrl/rtl/flash_ctrl.sv
@@ -13,7 +13,9 @@
input rst_ni,
// life cycle interface
- lc_ctrl_pkg::lc_tx_t lc_provision_en_i,
+ lc_ctrl_pkg::lc_tx_t lc_provision_wr_en_i,
+ lc_ctrl_pkg::lc_tx_t lc_provision_rd_en_i,
+ lc_ctrl_pkg::lc_tx_t lc_iso_flash_wr_en_i,
// Bus Interface
input tlul_pkg::tl_h2d_t tl_i,
@@ -103,7 +105,7 @@
logic prog_done, rd_done, erase_done;
logic prog_err, rd_err, erase_err;
- // Flash Memory Protection Connections
+ // Flash Memory Properties Connections
logic [BusAddrW-1:0] flash_addr;
logic flash_req;
logic flash_rd_done, flash_prog_done, flash_erase_done;
@@ -165,18 +167,38 @@
logic lfsr_en;
// life cycle connections
- lc_ctrl_pkg::lc_tx_t [FlashLcLast-1:0] lc_provision_en;
+ lc_ctrl_pkg::lc_tx_t [FlashWrLcLast-1:0] lc_provision_wr_en;
+ lc_ctrl_pkg::lc_tx_t [FlashRdLcLast-1:0] lc_provision_rd_en;
+ lc_ctrl_pkg::lc_tx_t lc_iso_flash_wr_en;
// synchronize provision enable into local domain
prim_lc_sync #(
- .NumCopies(int'(FlashLcLast))
- ) u_lc_provision_en_sync (
+ .NumCopies(int'(FlashWrLcLast))
+ ) u_lc_provision_wr_en_sync (
.clk_i,
.rst_ni,
- .lc_en_i(lc_provision_en_i),
- .lc_en_o(lc_provision_en)
+ .lc_en_i(lc_provision_wr_en_i),
+ .lc_en_o(lc_provision_wr_en)
);
+ prim_lc_sync #(
+ .NumCopies(int'(FlashRdLcLast))
+ ) u_lc_provision_rd_en_sync (
+ .clk_i,
+ .rst_ni,
+ .lc_en_i(lc_provision_rd_en_i),
+ .lc_en_o(lc_provision_rd_en)
+ );
+ prim_lc_sync #(
+ .NumCopies(1)
+ ) u_lc_iso_flash_en_sync (
+ .clk_i,
+ .rst_ni,
+ .lc_en_i(lc_iso_flash_wr_en_i),
+ .lc_en_o(lc_iso_flash_wr_en)
+ );
+
+
prim_lfsr #(
.DefaultSeed(),
.EntropyDw(4),
@@ -279,12 +301,21 @@
// hardware interface
// software only has privilege to change creator seed when provision enable is set and
- // before the the seed is set as valid in otp
- assign creator_seed_priv = lc_provision_en[FlashLcCreatorSeedPriv] == lc_ctrl_pkg::On &
+ // before the the seed is set as valid in otp.
+ // lc provision write enable is used here as creator assets can only be changed when
+ // creator secrets are not yet locked.
+ assign creator_seed_priv = (lc_provision_wr_en[FlashWrLcCreatorSeedPriv] == lc_ctrl_pkg::On) &
~otp_i.seed_valid;
// owner seed is under software control and can be modided whenever provision enable is set
- assign owner_seed_priv = lc_provision_en[FlashLcOwnerSeedPriv] == lc_ctrl_pkg::On;
+ // read enable is used here as this is mostly under the control of creator software and just
+ // needs to be locked out from specific life cycle states.
+ assign owner_seed_priv = lc_provision_rd_en[FlashRdLcOwnerSeedPriv] == lc_ctrl_pkg::On;
+
+ // the seed is only readable after it has been written and locked.
+ logic seed_rd_en;
+ assign seed_rd_en = lc_provision_wr_en[FlashWrLcMgrIf] == lc_ctrl_pkg::Off &
+ lc_provision_rd_en[FlashRdLcMgrIf] == lc_ctrl_pkg::On;
flash_ctrl_lcmgr u_flash_hw_if (
.clk_i,
@@ -292,7 +323,7 @@
.init_i(pwrmgr_i.flash_init),
.init_done_o(pwrmgr_o.flash_done),
- .provision_en_i(lc_provision_en[FlashLcMgrIf] == lc_ctrl_pkg::On),
+ .provision_en_i(seed_rd_en),
// interface to ctrl arb control ports
.ctrl_o(hw_ctrl),
@@ -522,7 +553,7 @@
end
//////////////////////////////////////
- // Data partition protection configuration
+ // Data partition properties configuration
//////////////////////////////////////
// extra region is the default region
mp_region_cfg_t [MpRegions:0] region_cfgs;
@@ -537,9 +568,10 @@
assign region_cfgs[MpRegions].erase_en.q = reg2hw.default_region.erase_en.q;
assign region_cfgs[MpRegions].scramble_en.q = reg2hw.default_region.scramble_en.q;
assign region_cfgs[MpRegions].ecc_en.q = reg2hw.default_region.ecc_en.q;
+ assign region_cfgs[MpRegions].he_en.q = reg2hw.default_region.he_en.q;
//////////////////////////////////////
- // Info partition protection configuration
+ // Info partition properties configuration
//////////////////////////////////////
info_page_cfg_t [NumBanks-1:0][InfoTypes-1:0][InfosPerBank-1:0] reg2hw_info_page_cfgs;
info_page_cfg_t [NumBanks-1:0][InfoTypes-1:0][InfosPerBank-1:0] info_page_cfgs;
@@ -551,6 +583,10 @@
assign reg2hw_info_page_cfgs[1][1] = reg2hw.bank1_info1_page_cfg;
// qualify reg2hw settings with creator / owner privileges
+ logic iso_flash_wr_en;
+ assign iso_flash_wr_en = lc_provision_wr_en[FlashWrLcInfoCfg] == lc_ctrl_pkg::On |
+ lc_iso_flash_wr_en == lc_ctrl_pkg::On;
+
for(genvar i = 0; i < NumBanks; i++) begin : gen_info_priv_bank
for (genvar j = 0; j < InfoTypes; j++) begin : gen_info_priv_type
flash_ctrl_info_cfg # (
@@ -560,14 +596,15 @@
.cfgs_i(reg2hw_info_page_cfgs[i][j]),
.creator_seed_priv_i(creator_seed_priv),
.owner_seed_priv_i(owner_seed_priv),
- .provision_en_i(lc_provision_en[FlashLcInfoCfg] == lc_ctrl_pkg::On),
+ .iso_flash_wr_en_i(iso_flash_wr_en),
+ .iso_flash_rd_en_i(lc_provision_rd_en[FlashRdLcInfoCfg] == lc_ctrl_pkg::On),
.cfgs_o(info_page_cfgs[i][j])
);
end
end
//////////////////////////////////////
- // flash memory protection
+ // flash memory properties
//////////////////////////////////////
// direct assignment since prog/rd/erase_ctrl do not make use of op_part
flash_part_e flash_part_sel;
@@ -575,8 +612,8 @@
assign flash_part_sel = op_part;
assign flash_info_sel = op_info_sel;
- // Flash memory protection
- // Memory protection is page based and thus should use phy addressing
+ // Flash memory Properties
+ // Memory property is page based and thus should use phy addressing
// This should move to flash_phy long term
flash_mp u_flash_mp (
.clk_i,
@@ -613,6 +650,7 @@
.req_o(flash_o.req),
.scramble_en_o(flash_o.scramble_en),
.ecc_en_o(flash_o.ecc_en),
+ .he_en_o(flash_o.he_en),
.rd_o(flash_o.rd),
.prog_o(flash_o.prog),
.pg_erase_o(flash_o.pg_erase),
diff --git a/hw/ip/flash_ctrl/rtl/flash_ctrl_pkg.sv b/hw/ip/flash_ctrl/rtl/flash_ctrl_pkg.sv
index a97b900..0c871d0 100644
--- a/hw/ip/flash_ctrl/rtl/flash_ctrl_pkg.sv
+++ b/hw/ip/flash_ctrl/rtl/flash_ctrl_pkg.sv
@@ -76,14 +76,21 @@
// parameters for connected components
parameter int SeedWidth = 256;
- // life cycle provision enable usage
- typedef enum logic [2:0] {
- FlashLcCreatorSeedPriv,
- FlashLcOwnerSeedPriv,
- FlashLcMgrIf,
- FlashLcInfoCfg,
- FlashLcLast
- } flash_lc_provision_en_e;
+ // life cycle provision write enable usage
+ typedef enum logic [1:0] {
+ FlashWrLcCreatorSeedPriv,
+ FlashWrLcMgrIf,
+ FlashWrLcInfoCfg,
+ FlashWrLcLast
+ } flash_lc_provision_wr_en_e;
+
+ // life cycle provision read enable usage
+ typedef enum logic [1:0] {
+ FlashRdLcOwnerSeedPriv,
+ FlashRdLcMgrIf,
+ FlashRdLcInfoCfg,
+ FlashRdLcLast
+ } flash_lc_provision_rd_en_e;
// lcmgr phase enum
typedef enum logic [1:0] {
@@ -156,7 +163,8 @@
prog_en: 1'b0,
erase_en: 1'b0,
scramble_en: 1'b0,
- ecc_en: 1'b0 // TBD, update to 1 once tb supports ECC
+ ecc_en: 1'b0, // TBD, update to 1 once tb supports ECC
+ he_en: 1'b1
};
parameter info_page_cfg_t CfgAllowReadErase = '{
@@ -165,7 +173,8 @@
prog_en: 1'b0,
erase_en: 1'b1,
scramble_en: 1'b0,
- ecc_en: 1'b0 // TBD, update to 1 once tb supports ECC
+ ecc_en: 1'b0, // TBD, update to 1 once tb supports ECC
+ he_en: 1'b1 // HW assumes high endurance
};
parameter info_page_attr_t HwInfoPageAttr[HwInfoRules] = '{
@@ -198,6 +207,7 @@
erase_en: 1'b1,
scramble_en: 1'b0,
ecc_en: 1'b0,
+ he_en: 1'b1, // HW assumes high endurance
base: '0,
size: '{default:'1}
}
@@ -254,6 +264,7 @@
logic req;
logic scramble_en;
logic ecc_en;
+ logic he_en;
logic rd;
logic prog;
logic pg_erase;
@@ -274,6 +285,7 @@
req: 1'b0,
scramble_en: 1'b0,
ecc_en: 1'b0,
+ he_en: 1'b0,
rd: 1'b0,
prog: 1'b0,
pg_erase: 1'b0,
@@ -375,6 +387,14 @@
entropy: '0
};
+ // dft_en jtag selection
+ typedef enum logic [2:0] {
+ FlashLcTckSel,
+ FlashLcTdiSel,
+ FlashLcTmsSel,
+ FlashLcTdoSel,
+ FlashLcJtagLast
+ } flash_lc_jtag_e;
// find the max number pages among info types
function automatic integer max_info_pages(int infos[InfoTypes]);
diff --git a/hw/ip/flash_ctrl/rtl/flash_ctrl_reg_pkg.sv b/hw/ip/flash_ctrl/rtl/flash_ctrl_reg_pkg.sv
index e72974f..27992fe 100644
--- a/hw/ip/flash_ctrl/rtl/flash_ctrl_reg_pkg.sv
+++ b/hw/ip/flash_ctrl/rtl/flash_ctrl_reg_pkg.sv
@@ -138,6 +138,9 @@
logic q;
} ecc_en;
struct packed {
+ logic q;
+ } he_en;
+ struct packed {
logic [8:0] q;
} base;
struct packed {
@@ -161,6 +164,9 @@
struct packed {
logic q;
} ecc_en;
+ struct packed {
+ logic q;
+ } he_en;
} flash_ctrl_reg2hw_default_region_reg_t;
typedef struct packed {
@@ -182,6 +188,9 @@
struct packed {
logic q;
} ecc_en;
+ struct packed {
+ logic q;
+ } he_en;
} flash_ctrl_reg2hw_bank0_info0_page_cfg_mreg_t;
typedef struct packed {
@@ -203,6 +212,9 @@
struct packed {
logic q;
} ecc_en;
+ struct packed {
+ logic q;
+ } he_en;
} flash_ctrl_reg2hw_bank0_info1_page_cfg_mreg_t;
typedef struct packed {
@@ -224,6 +236,9 @@
struct packed {
logic q;
} ecc_en;
+ struct packed {
+ logic q;
+ } he_en;
} flash_ctrl_reg2hw_bank1_info0_page_cfg_mreg_t;
typedef struct packed {
@@ -245,6 +260,9 @@
struct packed {
logic q;
} ecc_en;
+ struct packed {
+ logic q;
+ } he_en;
} flash_ctrl_reg2hw_bank1_info1_page_cfg_mreg_t;
typedef struct packed {
@@ -365,17 +383,17 @@
// Register to internal design logic //
///////////////////////////////////////
typedef struct packed {
- flash_ctrl_reg2hw_intr_state_reg_t intr_state; // [420:415]
- flash_ctrl_reg2hw_intr_enable_reg_t intr_enable; // [414:409]
- flash_ctrl_reg2hw_intr_test_reg_t intr_test; // [408:397]
- flash_ctrl_reg2hw_control_reg_t control; // [396:378]
- flash_ctrl_reg2hw_addr_reg_t addr; // [377:346]
- flash_ctrl_reg2hw_mp_region_cfg_mreg_t [7:0] mp_region_cfg; // [345:146]
- flash_ctrl_reg2hw_default_region_reg_t default_region; // [145:141]
- flash_ctrl_reg2hw_bank0_info0_page_cfg_mreg_t [3:0] bank0_info0_page_cfg; // [140:117]
- flash_ctrl_reg2hw_bank0_info1_page_cfg_mreg_t [3:0] bank0_info1_page_cfg; // [116:93]
- flash_ctrl_reg2hw_bank1_info0_page_cfg_mreg_t [3:0] bank1_info0_page_cfg; // [92:69]
- flash_ctrl_reg2hw_bank1_info1_page_cfg_mreg_t [3:0] bank1_info1_page_cfg; // [68:45]
+ flash_ctrl_reg2hw_intr_state_reg_t intr_state; // [445:440]
+ flash_ctrl_reg2hw_intr_enable_reg_t intr_enable; // [439:434]
+ flash_ctrl_reg2hw_intr_test_reg_t intr_test; // [433:422]
+ flash_ctrl_reg2hw_control_reg_t control; // [421:403]
+ flash_ctrl_reg2hw_addr_reg_t addr; // [402:371]
+ flash_ctrl_reg2hw_mp_region_cfg_mreg_t [7:0] mp_region_cfg; // [370:163]
+ flash_ctrl_reg2hw_default_region_reg_t default_region; // [162:157]
+ flash_ctrl_reg2hw_bank0_info0_page_cfg_mreg_t [3:0] bank0_info0_page_cfg; // [156:129]
+ flash_ctrl_reg2hw_bank0_info1_page_cfg_mreg_t [3:0] bank0_info1_page_cfg; // [128:101]
+ flash_ctrl_reg2hw_bank1_info0_page_cfg_mreg_t [3:0] bank1_info0_page_cfg; // [100:73]
+ flash_ctrl_reg2hw_bank1_info1_page_cfg_mreg_t [3:0] bank1_info1_page_cfg; // [72:45]
flash_ctrl_reg2hw_mp_bank_cfg_mreg_t [1:0] mp_bank_cfg; // [44:43]
flash_ctrl_reg2hw_scratch_reg_t scratch; // [42:11]
flash_ctrl_reg2hw_fifo_lvl_reg_t fifo_lvl; // [10:1]
diff --git a/hw/ip/flash_ctrl/rtl/flash_ctrl_reg_top.sv b/hw/ip/flash_ctrl/rtl/flash_ctrl_reg_top.sv
index b9791d7..eba5983 100644
--- a/hw/ip/flash_ctrl/rtl/flash_ctrl_reg_top.sv
+++ b/hw/ip/flash_ctrl/rtl/flash_ctrl_reg_top.sv
@@ -237,6 +237,9 @@
logic mp_region_cfg_0_ecc_en_0_qs;
logic mp_region_cfg_0_ecc_en_0_wd;
logic mp_region_cfg_0_ecc_en_0_we;
+ logic mp_region_cfg_0_he_en_0_qs;
+ logic mp_region_cfg_0_he_en_0_wd;
+ logic mp_region_cfg_0_he_en_0_we;
logic [8:0] mp_region_cfg_0_base_0_qs;
logic [8:0] mp_region_cfg_0_base_0_wd;
logic mp_region_cfg_0_base_0_we;
@@ -261,6 +264,9 @@
logic mp_region_cfg_1_ecc_en_1_qs;
logic mp_region_cfg_1_ecc_en_1_wd;
logic mp_region_cfg_1_ecc_en_1_we;
+ logic mp_region_cfg_1_he_en_1_qs;
+ logic mp_region_cfg_1_he_en_1_wd;
+ logic mp_region_cfg_1_he_en_1_we;
logic [8:0] mp_region_cfg_1_base_1_qs;
logic [8:0] mp_region_cfg_1_base_1_wd;
logic mp_region_cfg_1_base_1_we;
@@ -285,6 +291,9 @@
logic mp_region_cfg_2_ecc_en_2_qs;
logic mp_region_cfg_2_ecc_en_2_wd;
logic mp_region_cfg_2_ecc_en_2_we;
+ logic mp_region_cfg_2_he_en_2_qs;
+ logic mp_region_cfg_2_he_en_2_wd;
+ logic mp_region_cfg_2_he_en_2_we;
logic [8:0] mp_region_cfg_2_base_2_qs;
logic [8:0] mp_region_cfg_2_base_2_wd;
logic mp_region_cfg_2_base_2_we;
@@ -309,6 +318,9 @@
logic mp_region_cfg_3_ecc_en_3_qs;
logic mp_region_cfg_3_ecc_en_3_wd;
logic mp_region_cfg_3_ecc_en_3_we;
+ logic mp_region_cfg_3_he_en_3_qs;
+ logic mp_region_cfg_3_he_en_3_wd;
+ logic mp_region_cfg_3_he_en_3_we;
logic [8:0] mp_region_cfg_3_base_3_qs;
logic [8:0] mp_region_cfg_3_base_3_wd;
logic mp_region_cfg_3_base_3_we;
@@ -333,6 +345,9 @@
logic mp_region_cfg_4_ecc_en_4_qs;
logic mp_region_cfg_4_ecc_en_4_wd;
logic mp_region_cfg_4_ecc_en_4_we;
+ logic mp_region_cfg_4_he_en_4_qs;
+ logic mp_region_cfg_4_he_en_4_wd;
+ logic mp_region_cfg_4_he_en_4_we;
logic [8:0] mp_region_cfg_4_base_4_qs;
logic [8:0] mp_region_cfg_4_base_4_wd;
logic mp_region_cfg_4_base_4_we;
@@ -357,6 +372,9 @@
logic mp_region_cfg_5_ecc_en_5_qs;
logic mp_region_cfg_5_ecc_en_5_wd;
logic mp_region_cfg_5_ecc_en_5_we;
+ logic mp_region_cfg_5_he_en_5_qs;
+ logic mp_region_cfg_5_he_en_5_wd;
+ logic mp_region_cfg_5_he_en_5_we;
logic [8:0] mp_region_cfg_5_base_5_qs;
logic [8:0] mp_region_cfg_5_base_5_wd;
logic mp_region_cfg_5_base_5_we;
@@ -381,6 +399,9 @@
logic mp_region_cfg_6_ecc_en_6_qs;
logic mp_region_cfg_6_ecc_en_6_wd;
logic mp_region_cfg_6_ecc_en_6_we;
+ logic mp_region_cfg_6_he_en_6_qs;
+ logic mp_region_cfg_6_he_en_6_wd;
+ logic mp_region_cfg_6_he_en_6_we;
logic [8:0] mp_region_cfg_6_base_6_qs;
logic [8:0] mp_region_cfg_6_base_6_wd;
logic mp_region_cfg_6_base_6_we;
@@ -405,6 +426,9 @@
logic mp_region_cfg_7_ecc_en_7_qs;
logic mp_region_cfg_7_ecc_en_7_wd;
logic mp_region_cfg_7_ecc_en_7_we;
+ logic mp_region_cfg_7_he_en_7_qs;
+ logic mp_region_cfg_7_he_en_7_wd;
+ logic mp_region_cfg_7_he_en_7_we;
logic [8:0] mp_region_cfg_7_base_7_qs;
logic [8:0] mp_region_cfg_7_base_7_wd;
logic mp_region_cfg_7_base_7_we;
@@ -426,6 +450,9 @@
logic default_region_ecc_en_qs;
logic default_region_ecc_en_wd;
logic default_region_ecc_en_we;
+ logic default_region_he_en_qs;
+ logic default_region_he_en_wd;
+ logic default_region_he_en_we;
logic bank0_info0_regwen_0_qs;
logic bank0_info0_regwen_0_wd;
logic bank0_info0_regwen_0_we;
@@ -456,6 +483,9 @@
logic bank0_info0_page_cfg_0_ecc_en_0_qs;
logic bank0_info0_page_cfg_0_ecc_en_0_wd;
logic bank0_info0_page_cfg_0_ecc_en_0_we;
+ logic bank0_info0_page_cfg_0_he_en_0_qs;
+ logic bank0_info0_page_cfg_0_he_en_0_wd;
+ logic bank0_info0_page_cfg_0_he_en_0_we;
logic bank0_info0_page_cfg_1_en_1_qs;
logic bank0_info0_page_cfg_1_en_1_wd;
logic bank0_info0_page_cfg_1_en_1_we;
@@ -474,6 +504,9 @@
logic bank0_info0_page_cfg_1_ecc_en_1_qs;
logic bank0_info0_page_cfg_1_ecc_en_1_wd;
logic bank0_info0_page_cfg_1_ecc_en_1_we;
+ logic bank0_info0_page_cfg_1_he_en_1_qs;
+ logic bank0_info0_page_cfg_1_he_en_1_wd;
+ logic bank0_info0_page_cfg_1_he_en_1_we;
logic bank0_info0_page_cfg_2_en_2_qs;
logic bank0_info0_page_cfg_2_en_2_wd;
logic bank0_info0_page_cfg_2_en_2_we;
@@ -492,6 +525,9 @@
logic bank0_info0_page_cfg_2_ecc_en_2_qs;
logic bank0_info0_page_cfg_2_ecc_en_2_wd;
logic bank0_info0_page_cfg_2_ecc_en_2_we;
+ logic bank0_info0_page_cfg_2_he_en_2_qs;
+ logic bank0_info0_page_cfg_2_he_en_2_wd;
+ logic bank0_info0_page_cfg_2_he_en_2_we;
logic bank0_info0_page_cfg_3_en_3_qs;
logic bank0_info0_page_cfg_3_en_3_wd;
logic bank0_info0_page_cfg_3_en_3_we;
@@ -510,6 +546,9 @@
logic bank0_info0_page_cfg_3_ecc_en_3_qs;
logic bank0_info0_page_cfg_3_ecc_en_3_wd;
logic bank0_info0_page_cfg_3_ecc_en_3_we;
+ logic bank0_info0_page_cfg_3_he_en_3_qs;
+ logic bank0_info0_page_cfg_3_he_en_3_wd;
+ logic bank0_info0_page_cfg_3_he_en_3_we;
logic bank0_info1_regwen_0_qs;
logic bank0_info1_regwen_0_wd;
logic bank0_info1_regwen_0_we;
@@ -540,6 +579,9 @@
logic bank0_info1_page_cfg_0_ecc_en_0_qs;
logic bank0_info1_page_cfg_0_ecc_en_0_wd;
logic bank0_info1_page_cfg_0_ecc_en_0_we;
+ logic bank0_info1_page_cfg_0_he_en_0_qs;
+ logic bank0_info1_page_cfg_0_he_en_0_wd;
+ logic bank0_info1_page_cfg_0_he_en_0_we;
logic bank0_info1_page_cfg_1_en_1_qs;
logic bank0_info1_page_cfg_1_en_1_wd;
logic bank0_info1_page_cfg_1_en_1_we;
@@ -558,6 +600,9 @@
logic bank0_info1_page_cfg_1_ecc_en_1_qs;
logic bank0_info1_page_cfg_1_ecc_en_1_wd;
logic bank0_info1_page_cfg_1_ecc_en_1_we;
+ logic bank0_info1_page_cfg_1_he_en_1_qs;
+ logic bank0_info1_page_cfg_1_he_en_1_wd;
+ logic bank0_info1_page_cfg_1_he_en_1_we;
logic bank0_info1_page_cfg_2_en_2_qs;
logic bank0_info1_page_cfg_2_en_2_wd;
logic bank0_info1_page_cfg_2_en_2_we;
@@ -576,6 +621,9 @@
logic bank0_info1_page_cfg_2_ecc_en_2_qs;
logic bank0_info1_page_cfg_2_ecc_en_2_wd;
logic bank0_info1_page_cfg_2_ecc_en_2_we;
+ logic bank0_info1_page_cfg_2_he_en_2_qs;
+ logic bank0_info1_page_cfg_2_he_en_2_wd;
+ logic bank0_info1_page_cfg_2_he_en_2_we;
logic bank0_info1_page_cfg_3_en_3_qs;
logic bank0_info1_page_cfg_3_en_3_wd;
logic bank0_info1_page_cfg_3_en_3_we;
@@ -594,6 +642,9 @@
logic bank0_info1_page_cfg_3_ecc_en_3_qs;
logic bank0_info1_page_cfg_3_ecc_en_3_wd;
logic bank0_info1_page_cfg_3_ecc_en_3_we;
+ logic bank0_info1_page_cfg_3_he_en_3_qs;
+ logic bank0_info1_page_cfg_3_he_en_3_wd;
+ logic bank0_info1_page_cfg_3_he_en_3_we;
logic bank1_info0_regwen_0_qs;
logic bank1_info0_regwen_0_wd;
logic bank1_info0_regwen_0_we;
@@ -624,6 +675,9 @@
logic bank1_info0_page_cfg_0_ecc_en_0_qs;
logic bank1_info0_page_cfg_0_ecc_en_0_wd;
logic bank1_info0_page_cfg_0_ecc_en_0_we;
+ logic bank1_info0_page_cfg_0_he_en_0_qs;
+ logic bank1_info0_page_cfg_0_he_en_0_wd;
+ logic bank1_info0_page_cfg_0_he_en_0_we;
logic bank1_info0_page_cfg_1_en_1_qs;
logic bank1_info0_page_cfg_1_en_1_wd;
logic bank1_info0_page_cfg_1_en_1_we;
@@ -642,6 +696,9 @@
logic bank1_info0_page_cfg_1_ecc_en_1_qs;
logic bank1_info0_page_cfg_1_ecc_en_1_wd;
logic bank1_info0_page_cfg_1_ecc_en_1_we;
+ logic bank1_info0_page_cfg_1_he_en_1_qs;
+ logic bank1_info0_page_cfg_1_he_en_1_wd;
+ logic bank1_info0_page_cfg_1_he_en_1_we;
logic bank1_info0_page_cfg_2_en_2_qs;
logic bank1_info0_page_cfg_2_en_2_wd;
logic bank1_info0_page_cfg_2_en_2_we;
@@ -660,6 +717,9 @@
logic bank1_info0_page_cfg_2_ecc_en_2_qs;
logic bank1_info0_page_cfg_2_ecc_en_2_wd;
logic bank1_info0_page_cfg_2_ecc_en_2_we;
+ logic bank1_info0_page_cfg_2_he_en_2_qs;
+ logic bank1_info0_page_cfg_2_he_en_2_wd;
+ logic bank1_info0_page_cfg_2_he_en_2_we;
logic bank1_info0_page_cfg_3_en_3_qs;
logic bank1_info0_page_cfg_3_en_3_wd;
logic bank1_info0_page_cfg_3_en_3_we;
@@ -678,6 +738,9 @@
logic bank1_info0_page_cfg_3_ecc_en_3_qs;
logic bank1_info0_page_cfg_3_ecc_en_3_wd;
logic bank1_info0_page_cfg_3_ecc_en_3_we;
+ logic bank1_info0_page_cfg_3_he_en_3_qs;
+ logic bank1_info0_page_cfg_3_he_en_3_wd;
+ logic bank1_info0_page_cfg_3_he_en_3_we;
logic bank1_info1_regwen_0_qs;
logic bank1_info1_regwen_0_wd;
logic bank1_info1_regwen_0_we;
@@ -708,6 +771,9 @@
logic bank1_info1_page_cfg_0_ecc_en_0_qs;
logic bank1_info1_page_cfg_0_ecc_en_0_wd;
logic bank1_info1_page_cfg_0_ecc_en_0_we;
+ logic bank1_info1_page_cfg_0_he_en_0_qs;
+ logic bank1_info1_page_cfg_0_he_en_0_wd;
+ logic bank1_info1_page_cfg_0_he_en_0_we;
logic bank1_info1_page_cfg_1_en_1_qs;
logic bank1_info1_page_cfg_1_en_1_wd;
logic bank1_info1_page_cfg_1_en_1_we;
@@ -726,6 +792,9 @@
logic bank1_info1_page_cfg_1_ecc_en_1_qs;
logic bank1_info1_page_cfg_1_ecc_en_1_wd;
logic bank1_info1_page_cfg_1_ecc_en_1_we;
+ logic bank1_info1_page_cfg_1_he_en_1_qs;
+ logic bank1_info1_page_cfg_1_he_en_1_wd;
+ logic bank1_info1_page_cfg_1_he_en_1_we;
logic bank1_info1_page_cfg_2_en_2_qs;
logic bank1_info1_page_cfg_2_en_2_wd;
logic bank1_info1_page_cfg_2_en_2_we;
@@ -744,6 +813,9 @@
logic bank1_info1_page_cfg_2_ecc_en_2_qs;
logic bank1_info1_page_cfg_2_ecc_en_2_wd;
logic bank1_info1_page_cfg_2_ecc_en_2_we;
+ logic bank1_info1_page_cfg_2_he_en_2_qs;
+ logic bank1_info1_page_cfg_2_he_en_2_wd;
+ logic bank1_info1_page_cfg_2_he_en_2_we;
logic bank1_info1_page_cfg_3_en_3_qs;
logic bank1_info1_page_cfg_3_en_3_wd;
logic bank1_info1_page_cfg_3_en_3_we;
@@ -762,6 +834,9 @@
logic bank1_info1_page_cfg_3_ecc_en_3_qs;
logic bank1_info1_page_cfg_3_ecc_en_3_wd;
logic bank1_info1_page_cfg_3_ecc_en_3_we;
+ logic bank1_info1_page_cfg_3_he_en_3_qs;
+ logic bank1_info1_page_cfg_3_he_en_3_wd;
+ logic bank1_info1_page_cfg_3_he_en_3_we;
logic bank_cfg_regwen_qs;
logic bank_cfg_regwen_wd;
logic bank_cfg_regwen_we;
@@ -1813,6 +1888,32 @@
);
+ // F[he_en_0]: 6:6
+ prim_subreg #(
+ .DW (1),
+ .SWACCESS("RW"),
+ .RESVAL (1'h0)
+ ) u_mp_region_cfg_0_he_en_0 (
+ .clk_i (clk_i ),
+ .rst_ni (rst_ni ),
+
+ // from register interface (qualified with register enable)
+ .we (mp_region_cfg_0_he_en_0_we & region_cfg_regwen_0_qs),
+ .wd (mp_region_cfg_0_he_en_0_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0 ),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.mp_region_cfg[0].he_en.q ),
+
+ // to register interface (read)
+ .qs (mp_region_cfg_0_he_en_0_qs)
+ );
+
+
// F[base_0]: 16:8
prim_subreg #(
.DW (9),
@@ -2024,6 +2125,32 @@
);
+ // F[he_en_1]: 6:6
+ prim_subreg #(
+ .DW (1),
+ .SWACCESS("RW"),
+ .RESVAL (1'h0)
+ ) u_mp_region_cfg_1_he_en_1 (
+ .clk_i (clk_i ),
+ .rst_ni (rst_ni ),
+
+ // from register interface (qualified with register enable)
+ .we (mp_region_cfg_1_he_en_1_we & region_cfg_regwen_1_qs),
+ .wd (mp_region_cfg_1_he_en_1_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0 ),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.mp_region_cfg[1].he_en.q ),
+
+ // to register interface (read)
+ .qs (mp_region_cfg_1_he_en_1_qs)
+ );
+
+
// F[base_1]: 16:8
prim_subreg #(
.DW (9),
@@ -2235,6 +2362,32 @@
);
+ // F[he_en_2]: 6:6
+ prim_subreg #(
+ .DW (1),
+ .SWACCESS("RW"),
+ .RESVAL (1'h0)
+ ) u_mp_region_cfg_2_he_en_2 (
+ .clk_i (clk_i ),
+ .rst_ni (rst_ni ),
+
+ // from register interface (qualified with register enable)
+ .we (mp_region_cfg_2_he_en_2_we & region_cfg_regwen_2_qs),
+ .wd (mp_region_cfg_2_he_en_2_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0 ),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.mp_region_cfg[2].he_en.q ),
+
+ // to register interface (read)
+ .qs (mp_region_cfg_2_he_en_2_qs)
+ );
+
+
// F[base_2]: 16:8
prim_subreg #(
.DW (9),
@@ -2446,6 +2599,32 @@
);
+ // F[he_en_3]: 6:6
+ prim_subreg #(
+ .DW (1),
+ .SWACCESS("RW"),
+ .RESVAL (1'h0)
+ ) u_mp_region_cfg_3_he_en_3 (
+ .clk_i (clk_i ),
+ .rst_ni (rst_ni ),
+
+ // from register interface (qualified with register enable)
+ .we (mp_region_cfg_3_he_en_3_we & region_cfg_regwen_3_qs),
+ .wd (mp_region_cfg_3_he_en_3_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0 ),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.mp_region_cfg[3].he_en.q ),
+
+ // to register interface (read)
+ .qs (mp_region_cfg_3_he_en_3_qs)
+ );
+
+
// F[base_3]: 16:8
prim_subreg #(
.DW (9),
@@ -2657,6 +2836,32 @@
);
+ // F[he_en_4]: 6:6
+ prim_subreg #(
+ .DW (1),
+ .SWACCESS("RW"),
+ .RESVAL (1'h0)
+ ) u_mp_region_cfg_4_he_en_4 (
+ .clk_i (clk_i ),
+ .rst_ni (rst_ni ),
+
+ // from register interface (qualified with register enable)
+ .we (mp_region_cfg_4_he_en_4_we & region_cfg_regwen_4_qs),
+ .wd (mp_region_cfg_4_he_en_4_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0 ),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.mp_region_cfg[4].he_en.q ),
+
+ // to register interface (read)
+ .qs (mp_region_cfg_4_he_en_4_qs)
+ );
+
+
// F[base_4]: 16:8
prim_subreg #(
.DW (9),
@@ -2868,6 +3073,32 @@
);
+ // F[he_en_5]: 6:6
+ prim_subreg #(
+ .DW (1),
+ .SWACCESS("RW"),
+ .RESVAL (1'h0)
+ ) u_mp_region_cfg_5_he_en_5 (
+ .clk_i (clk_i ),
+ .rst_ni (rst_ni ),
+
+ // from register interface (qualified with register enable)
+ .we (mp_region_cfg_5_he_en_5_we & region_cfg_regwen_5_qs),
+ .wd (mp_region_cfg_5_he_en_5_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0 ),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.mp_region_cfg[5].he_en.q ),
+
+ // to register interface (read)
+ .qs (mp_region_cfg_5_he_en_5_qs)
+ );
+
+
// F[base_5]: 16:8
prim_subreg #(
.DW (9),
@@ -3079,6 +3310,32 @@
);
+ // F[he_en_6]: 6:6
+ prim_subreg #(
+ .DW (1),
+ .SWACCESS("RW"),
+ .RESVAL (1'h0)
+ ) u_mp_region_cfg_6_he_en_6 (
+ .clk_i (clk_i ),
+ .rst_ni (rst_ni ),
+
+ // from register interface (qualified with register enable)
+ .we (mp_region_cfg_6_he_en_6_we & region_cfg_regwen_6_qs),
+ .wd (mp_region_cfg_6_he_en_6_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0 ),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.mp_region_cfg[6].he_en.q ),
+
+ // to register interface (read)
+ .qs (mp_region_cfg_6_he_en_6_qs)
+ );
+
+
// F[base_6]: 16:8
prim_subreg #(
.DW (9),
@@ -3290,6 +3547,32 @@
);
+ // F[he_en_7]: 6:6
+ prim_subreg #(
+ .DW (1),
+ .SWACCESS("RW"),
+ .RESVAL (1'h0)
+ ) u_mp_region_cfg_7_he_en_7 (
+ .clk_i (clk_i ),
+ .rst_ni (rst_ni ),
+
+ // from register interface (qualified with register enable)
+ .we (mp_region_cfg_7_he_en_7_we & region_cfg_regwen_7_qs),
+ .wd (mp_region_cfg_7_he_en_7_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0 ),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.mp_region_cfg[7].he_en.q ),
+
+ // to register interface (read)
+ .qs (mp_region_cfg_7_he_en_7_qs)
+ );
+
+
// F[base_7]: 16:8
prim_subreg #(
.DW (9),
@@ -3475,6 +3758,32 @@
);
+ // F[he_en]: 5:5
+ prim_subreg #(
+ .DW (1),
+ .SWACCESS("RW"),
+ .RESVAL (1'h0)
+ ) u_default_region_he_en (
+ .clk_i (clk_i ),
+ .rst_ni (rst_ni ),
+
+ // from register interface
+ .we (default_region_he_en_we),
+ .wd (default_region_he_en_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0 ),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.default_region.he_en.q ),
+
+ // to register interface (read)
+ .qs (default_region_he_en_qs)
+ );
+
+
// Subregister 0 of Multireg bank0_info0_regwen
// R[bank0_info0_regwen_0]: V(False)
@@ -3745,6 +4054,32 @@
);
+ // F[he_en_0]: 6:6
+ prim_subreg #(
+ .DW (1),
+ .SWACCESS("RW"),
+ .RESVAL (1'h0)
+ ) u_bank0_info0_page_cfg_0_he_en_0 (
+ .clk_i (clk_i ),
+ .rst_ni (rst_ni ),
+
+ // from register interface (qualified with register enable)
+ .we (bank0_info0_page_cfg_0_he_en_0_we & bank0_info0_regwen_0_qs),
+ .wd (bank0_info0_page_cfg_0_he_en_0_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0 ),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.bank0_info0_page_cfg[0].he_en.q ),
+
+ // to register interface (read)
+ .qs (bank0_info0_page_cfg_0_he_en_0_qs)
+ );
+
+
// Subregister 1 of Multireg bank0_info0_page_cfg
// R[bank0_info0_page_cfg_1]: V(False)
@@ -3904,6 +4239,32 @@
);
+ // F[he_en_1]: 6:6
+ prim_subreg #(
+ .DW (1),
+ .SWACCESS("RW"),
+ .RESVAL (1'h0)
+ ) u_bank0_info0_page_cfg_1_he_en_1 (
+ .clk_i (clk_i ),
+ .rst_ni (rst_ni ),
+
+ // from register interface (qualified with register enable)
+ .we (bank0_info0_page_cfg_1_he_en_1_we & bank0_info0_regwen_1_qs),
+ .wd (bank0_info0_page_cfg_1_he_en_1_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0 ),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.bank0_info0_page_cfg[1].he_en.q ),
+
+ // to register interface (read)
+ .qs (bank0_info0_page_cfg_1_he_en_1_qs)
+ );
+
+
// Subregister 2 of Multireg bank0_info0_page_cfg
// R[bank0_info0_page_cfg_2]: V(False)
@@ -4063,6 +4424,32 @@
);
+ // F[he_en_2]: 6:6
+ prim_subreg #(
+ .DW (1),
+ .SWACCESS("RW"),
+ .RESVAL (1'h0)
+ ) u_bank0_info0_page_cfg_2_he_en_2 (
+ .clk_i (clk_i ),
+ .rst_ni (rst_ni ),
+
+ // from register interface (qualified with register enable)
+ .we (bank0_info0_page_cfg_2_he_en_2_we & bank0_info0_regwen_2_qs),
+ .wd (bank0_info0_page_cfg_2_he_en_2_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0 ),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.bank0_info0_page_cfg[2].he_en.q ),
+
+ // to register interface (read)
+ .qs (bank0_info0_page_cfg_2_he_en_2_qs)
+ );
+
+
// Subregister 3 of Multireg bank0_info0_page_cfg
// R[bank0_info0_page_cfg_3]: V(False)
@@ -4222,6 +4609,32 @@
);
+ // F[he_en_3]: 6:6
+ prim_subreg #(
+ .DW (1),
+ .SWACCESS("RW"),
+ .RESVAL (1'h0)
+ ) u_bank0_info0_page_cfg_3_he_en_3 (
+ .clk_i (clk_i ),
+ .rst_ni (rst_ni ),
+
+ // from register interface (qualified with register enable)
+ .we (bank0_info0_page_cfg_3_he_en_3_we & bank0_info0_regwen_3_qs),
+ .wd (bank0_info0_page_cfg_3_he_en_3_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0 ),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.bank0_info0_page_cfg[3].he_en.q ),
+
+ // to register interface (read)
+ .qs (bank0_info0_page_cfg_3_he_en_3_qs)
+ );
+
+
// Subregister 0 of Multireg bank0_info1_regwen
@@ -4493,6 +4906,32 @@
);
+ // F[he_en_0]: 6:6
+ prim_subreg #(
+ .DW (1),
+ .SWACCESS("RW"),
+ .RESVAL (1'h0)
+ ) u_bank0_info1_page_cfg_0_he_en_0 (
+ .clk_i (clk_i ),
+ .rst_ni (rst_ni ),
+
+ // from register interface (qualified with register enable)
+ .we (bank0_info1_page_cfg_0_he_en_0_we & bank0_info1_regwen_0_qs),
+ .wd (bank0_info1_page_cfg_0_he_en_0_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0 ),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.bank0_info1_page_cfg[0].he_en.q ),
+
+ // to register interface (read)
+ .qs (bank0_info1_page_cfg_0_he_en_0_qs)
+ );
+
+
// Subregister 1 of Multireg bank0_info1_page_cfg
// R[bank0_info1_page_cfg_1]: V(False)
@@ -4652,6 +5091,32 @@
);
+ // F[he_en_1]: 6:6
+ prim_subreg #(
+ .DW (1),
+ .SWACCESS("RW"),
+ .RESVAL (1'h0)
+ ) u_bank0_info1_page_cfg_1_he_en_1 (
+ .clk_i (clk_i ),
+ .rst_ni (rst_ni ),
+
+ // from register interface (qualified with register enable)
+ .we (bank0_info1_page_cfg_1_he_en_1_we & bank0_info1_regwen_1_qs),
+ .wd (bank0_info1_page_cfg_1_he_en_1_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0 ),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.bank0_info1_page_cfg[1].he_en.q ),
+
+ // to register interface (read)
+ .qs (bank0_info1_page_cfg_1_he_en_1_qs)
+ );
+
+
// Subregister 2 of Multireg bank0_info1_page_cfg
// R[bank0_info1_page_cfg_2]: V(False)
@@ -4811,6 +5276,32 @@
);
+ // F[he_en_2]: 6:6
+ prim_subreg #(
+ .DW (1),
+ .SWACCESS("RW"),
+ .RESVAL (1'h0)
+ ) u_bank0_info1_page_cfg_2_he_en_2 (
+ .clk_i (clk_i ),
+ .rst_ni (rst_ni ),
+
+ // from register interface (qualified with register enable)
+ .we (bank0_info1_page_cfg_2_he_en_2_we & bank0_info1_regwen_2_qs),
+ .wd (bank0_info1_page_cfg_2_he_en_2_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0 ),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.bank0_info1_page_cfg[2].he_en.q ),
+
+ // to register interface (read)
+ .qs (bank0_info1_page_cfg_2_he_en_2_qs)
+ );
+
+
// Subregister 3 of Multireg bank0_info1_page_cfg
// R[bank0_info1_page_cfg_3]: V(False)
@@ -4970,6 +5461,32 @@
);
+ // F[he_en_3]: 6:6
+ prim_subreg #(
+ .DW (1),
+ .SWACCESS("RW"),
+ .RESVAL (1'h0)
+ ) u_bank0_info1_page_cfg_3_he_en_3 (
+ .clk_i (clk_i ),
+ .rst_ni (rst_ni ),
+
+ // from register interface (qualified with register enable)
+ .we (bank0_info1_page_cfg_3_he_en_3_we & bank0_info1_regwen_3_qs),
+ .wd (bank0_info1_page_cfg_3_he_en_3_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0 ),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.bank0_info1_page_cfg[3].he_en.q ),
+
+ // to register interface (read)
+ .qs (bank0_info1_page_cfg_3_he_en_3_qs)
+ );
+
+
// Subregister 0 of Multireg bank1_info0_regwen
@@ -5241,6 +5758,32 @@
);
+ // F[he_en_0]: 6:6
+ prim_subreg #(
+ .DW (1),
+ .SWACCESS("RW"),
+ .RESVAL (1'h0)
+ ) u_bank1_info0_page_cfg_0_he_en_0 (
+ .clk_i (clk_i ),
+ .rst_ni (rst_ni ),
+
+ // from register interface (qualified with register enable)
+ .we (bank1_info0_page_cfg_0_he_en_0_we & bank1_info0_regwen_0_qs),
+ .wd (bank1_info0_page_cfg_0_he_en_0_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0 ),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.bank1_info0_page_cfg[0].he_en.q ),
+
+ // to register interface (read)
+ .qs (bank1_info0_page_cfg_0_he_en_0_qs)
+ );
+
+
// Subregister 1 of Multireg bank1_info0_page_cfg
// R[bank1_info0_page_cfg_1]: V(False)
@@ -5400,6 +5943,32 @@
);
+ // F[he_en_1]: 6:6
+ prim_subreg #(
+ .DW (1),
+ .SWACCESS("RW"),
+ .RESVAL (1'h0)
+ ) u_bank1_info0_page_cfg_1_he_en_1 (
+ .clk_i (clk_i ),
+ .rst_ni (rst_ni ),
+
+ // from register interface (qualified with register enable)
+ .we (bank1_info0_page_cfg_1_he_en_1_we & bank1_info0_regwen_1_qs),
+ .wd (bank1_info0_page_cfg_1_he_en_1_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0 ),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.bank1_info0_page_cfg[1].he_en.q ),
+
+ // to register interface (read)
+ .qs (bank1_info0_page_cfg_1_he_en_1_qs)
+ );
+
+
// Subregister 2 of Multireg bank1_info0_page_cfg
// R[bank1_info0_page_cfg_2]: V(False)
@@ -5559,6 +6128,32 @@
);
+ // F[he_en_2]: 6:6
+ prim_subreg #(
+ .DW (1),
+ .SWACCESS("RW"),
+ .RESVAL (1'h0)
+ ) u_bank1_info0_page_cfg_2_he_en_2 (
+ .clk_i (clk_i ),
+ .rst_ni (rst_ni ),
+
+ // from register interface (qualified with register enable)
+ .we (bank1_info0_page_cfg_2_he_en_2_we & bank1_info0_regwen_2_qs),
+ .wd (bank1_info0_page_cfg_2_he_en_2_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0 ),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.bank1_info0_page_cfg[2].he_en.q ),
+
+ // to register interface (read)
+ .qs (bank1_info0_page_cfg_2_he_en_2_qs)
+ );
+
+
// Subregister 3 of Multireg bank1_info0_page_cfg
// R[bank1_info0_page_cfg_3]: V(False)
@@ -5718,6 +6313,32 @@
);
+ // F[he_en_3]: 6:6
+ prim_subreg #(
+ .DW (1),
+ .SWACCESS("RW"),
+ .RESVAL (1'h0)
+ ) u_bank1_info0_page_cfg_3_he_en_3 (
+ .clk_i (clk_i ),
+ .rst_ni (rst_ni ),
+
+ // from register interface (qualified with register enable)
+ .we (bank1_info0_page_cfg_3_he_en_3_we & bank1_info0_regwen_3_qs),
+ .wd (bank1_info0_page_cfg_3_he_en_3_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0 ),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.bank1_info0_page_cfg[3].he_en.q ),
+
+ // to register interface (read)
+ .qs (bank1_info0_page_cfg_3_he_en_3_qs)
+ );
+
+
// Subregister 0 of Multireg bank1_info1_regwen
@@ -5989,6 +6610,32 @@
);
+ // F[he_en_0]: 6:6
+ prim_subreg #(
+ .DW (1),
+ .SWACCESS("RW"),
+ .RESVAL (1'h0)
+ ) u_bank1_info1_page_cfg_0_he_en_0 (
+ .clk_i (clk_i ),
+ .rst_ni (rst_ni ),
+
+ // from register interface (qualified with register enable)
+ .we (bank1_info1_page_cfg_0_he_en_0_we & bank1_info1_regwen_0_qs),
+ .wd (bank1_info1_page_cfg_0_he_en_0_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0 ),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.bank1_info1_page_cfg[0].he_en.q ),
+
+ // to register interface (read)
+ .qs (bank1_info1_page_cfg_0_he_en_0_qs)
+ );
+
+
// Subregister 1 of Multireg bank1_info1_page_cfg
// R[bank1_info1_page_cfg_1]: V(False)
@@ -6148,6 +6795,32 @@
);
+ // F[he_en_1]: 6:6
+ prim_subreg #(
+ .DW (1),
+ .SWACCESS("RW"),
+ .RESVAL (1'h0)
+ ) u_bank1_info1_page_cfg_1_he_en_1 (
+ .clk_i (clk_i ),
+ .rst_ni (rst_ni ),
+
+ // from register interface (qualified with register enable)
+ .we (bank1_info1_page_cfg_1_he_en_1_we & bank1_info1_regwen_1_qs),
+ .wd (bank1_info1_page_cfg_1_he_en_1_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0 ),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.bank1_info1_page_cfg[1].he_en.q ),
+
+ // to register interface (read)
+ .qs (bank1_info1_page_cfg_1_he_en_1_qs)
+ );
+
+
// Subregister 2 of Multireg bank1_info1_page_cfg
// R[bank1_info1_page_cfg_2]: V(False)
@@ -6307,6 +6980,32 @@
);
+ // F[he_en_2]: 6:6
+ prim_subreg #(
+ .DW (1),
+ .SWACCESS("RW"),
+ .RESVAL (1'h0)
+ ) u_bank1_info1_page_cfg_2_he_en_2 (
+ .clk_i (clk_i ),
+ .rst_ni (rst_ni ),
+
+ // from register interface (qualified with register enable)
+ .we (bank1_info1_page_cfg_2_he_en_2_we & bank1_info1_regwen_2_qs),
+ .wd (bank1_info1_page_cfg_2_he_en_2_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0 ),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.bank1_info1_page_cfg[2].he_en.q ),
+
+ // to register interface (read)
+ .qs (bank1_info1_page_cfg_2_he_en_2_qs)
+ );
+
+
// Subregister 3 of Multireg bank1_info1_page_cfg
// R[bank1_info1_page_cfg_3]: V(False)
@@ -6466,6 +7165,32 @@
);
+ // F[he_en_3]: 6:6
+ prim_subreg #(
+ .DW (1),
+ .SWACCESS("RW"),
+ .RESVAL (1'h0)
+ ) u_bank1_info1_page_cfg_3_he_en_3 (
+ .clk_i (clk_i ),
+ .rst_ni (rst_ni ),
+
+ // from register interface (qualified with register enable)
+ .we (bank1_info1_page_cfg_3_he_en_3_we & bank1_info1_regwen_3_qs),
+ .wd (bank1_info1_page_cfg_3_he_en_3_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0 ),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.bank1_info1_page_cfg[3].he_en.q ),
+
+ // to register interface (read)
+ .qs (bank1_info1_page_cfg_3_he_en_3_qs)
+ );
+
+
// R[bank_cfg_regwen]: V(False)
@@ -7204,6 +7929,9 @@
assign mp_region_cfg_0_ecc_en_0_we = addr_hit[14] & reg_we & ~wr_err;
assign mp_region_cfg_0_ecc_en_0_wd = reg_wdata[5];
+ assign mp_region_cfg_0_he_en_0_we = addr_hit[14] & reg_we & ~wr_err;
+ assign mp_region_cfg_0_he_en_0_wd = reg_wdata[6];
+
assign mp_region_cfg_0_base_0_we = addr_hit[14] & reg_we & ~wr_err;
assign mp_region_cfg_0_base_0_wd = reg_wdata[16:8];
@@ -7228,6 +7956,9 @@
assign mp_region_cfg_1_ecc_en_1_we = addr_hit[15] & reg_we & ~wr_err;
assign mp_region_cfg_1_ecc_en_1_wd = reg_wdata[5];
+ assign mp_region_cfg_1_he_en_1_we = addr_hit[15] & reg_we & ~wr_err;
+ assign mp_region_cfg_1_he_en_1_wd = reg_wdata[6];
+
assign mp_region_cfg_1_base_1_we = addr_hit[15] & reg_we & ~wr_err;
assign mp_region_cfg_1_base_1_wd = reg_wdata[16:8];
@@ -7252,6 +7983,9 @@
assign mp_region_cfg_2_ecc_en_2_we = addr_hit[16] & reg_we & ~wr_err;
assign mp_region_cfg_2_ecc_en_2_wd = reg_wdata[5];
+ assign mp_region_cfg_2_he_en_2_we = addr_hit[16] & reg_we & ~wr_err;
+ assign mp_region_cfg_2_he_en_2_wd = reg_wdata[6];
+
assign mp_region_cfg_2_base_2_we = addr_hit[16] & reg_we & ~wr_err;
assign mp_region_cfg_2_base_2_wd = reg_wdata[16:8];
@@ -7276,6 +8010,9 @@
assign mp_region_cfg_3_ecc_en_3_we = addr_hit[17] & reg_we & ~wr_err;
assign mp_region_cfg_3_ecc_en_3_wd = reg_wdata[5];
+ assign mp_region_cfg_3_he_en_3_we = addr_hit[17] & reg_we & ~wr_err;
+ assign mp_region_cfg_3_he_en_3_wd = reg_wdata[6];
+
assign mp_region_cfg_3_base_3_we = addr_hit[17] & reg_we & ~wr_err;
assign mp_region_cfg_3_base_3_wd = reg_wdata[16:8];
@@ -7300,6 +8037,9 @@
assign mp_region_cfg_4_ecc_en_4_we = addr_hit[18] & reg_we & ~wr_err;
assign mp_region_cfg_4_ecc_en_4_wd = reg_wdata[5];
+ assign mp_region_cfg_4_he_en_4_we = addr_hit[18] & reg_we & ~wr_err;
+ assign mp_region_cfg_4_he_en_4_wd = reg_wdata[6];
+
assign mp_region_cfg_4_base_4_we = addr_hit[18] & reg_we & ~wr_err;
assign mp_region_cfg_4_base_4_wd = reg_wdata[16:8];
@@ -7324,6 +8064,9 @@
assign mp_region_cfg_5_ecc_en_5_we = addr_hit[19] & reg_we & ~wr_err;
assign mp_region_cfg_5_ecc_en_5_wd = reg_wdata[5];
+ assign mp_region_cfg_5_he_en_5_we = addr_hit[19] & reg_we & ~wr_err;
+ assign mp_region_cfg_5_he_en_5_wd = reg_wdata[6];
+
assign mp_region_cfg_5_base_5_we = addr_hit[19] & reg_we & ~wr_err;
assign mp_region_cfg_5_base_5_wd = reg_wdata[16:8];
@@ -7348,6 +8091,9 @@
assign mp_region_cfg_6_ecc_en_6_we = addr_hit[20] & reg_we & ~wr_err;
assign mp_region_cfg_6_ecc_en_6_wd = reg_wdata[5];
+ assign mp_region_cfg_6_he_en_6_we = addr_hit[20] & reg_we & ~wr_err;
+ assign mp_region_cfg_6_he_en_6_wd = reg_wdata[6];
+
assign mp_region_cfg_6_base_6_we = addr_hit[20] & reg_we & ~wr_err;
assign mp_region_cfg_6_base_6_wd = reg_wdata[16:8];
@@ -7372,6 +8118,9 @@
assign mp_region_cfg_7_ecc_en_7_we = addr_hit[21] & reg_we & ~wr_err;
assign mp_region_cfg_7_ecc_en_7_wd = reg_wdata[5];
+ assign mp_region_cfg_7_he_en_7_we = addr_hit[21] & reg_we & ~wr_err;
+ assign mp_region_cfg_7_he_en_7_wd = reg_wdata[6];
+
assign mp_region_cfg_7_base_7_we = addr_hit[21] & reg_we & ~wr_err;
assign mp_region_cfg_7_base_7_wd = reg_wdata[16:8];
@@ -7393,6 +8142,9 @@
assign default_region_ecc_en_we = addr_hit[22] & reg_we & ~wr_err;
assign default_region_ecc_en_wd = reg_wdata[4];
+ assign default_region_he_en_we = addr_hit[22] & reg_we & ~wr_err;
+ assign default_region_he_en_wd = reg_wdata[5];
+
assign bank0_info0_regwen_0_we = addr_hit[23] & reg_we & ~wr_err;
assign bank0_info0_regwen_0_wd = reg_wdata[0];
@@ -7423,6 +8175,9 @@
assign bank0_info0_page_cfg_0_ecc_en_0_we = addr_hit[27] & reg_we & ~wr_err;
assign bank0_info0_page_cfg_0_ecc_en_0_wd = reg_wdata[5];
+ assign bank0_info0_page_cfg_0_he_en_0_we = addr_hit[27] & reg_we & ~wr_err;
+ assign bank0_info0_page_cfg_0_he_en_0_wd = reg_wdata[6];
+
assign bank0_info0_page_cfg_1_en_1_we = addr_hit[28] & reg_we & ~wr_err;
assign bank0_info0_page_cfg_1_en_1_wd = reg_wdata[0];
@@ -7441,6 +8196,9 @@
assign bank0_info0_page_cfg_1_ecc_en_1_we = addr_hit[28] & reg_we & ~wr_err;
assign bank0_info0_page_cfg_1_ecc_en_1_wd = reg_wdata[5];
+ assign bank0_info0_page_cfg_1_he_en_1_we = addr_hit[28] & reg_we & ~wr_err;
+ assign bank0_info0_page_cfg_1_he_en_1_wd = reg_wdata[6];
+
assign bank0_info0_page_cfg_2_en_2_we = addr_hit[29] & reg_we & ~wr_err;
assign bank0_info0_page_cfg_2_en_2_wd = reg_wdata[0];
@@ -7459,6 +8217,9 @@
assign bank0_info0_page_cfg_2_ecc_en_2_we = addr_hit[29] & reg_we & ~wr_err;
assign bank0_info0_page_cfg_2_ecc_en_2_wd = reg_wdata[5];
+ assign bank0_info0_page_cfg_2_he_en_2_we = addr_hit[29] & reg_we & ~wr_err;
+ assign bank0_info0_page_cfg_2_he_en_2_wd = reg_wdata[6];
+
assign bank0_info0_page_cfg_3_en_3_we = addr_hit[30] & reg_we & ~wr_err;
assign bank0_info0_page_cfg_3_en_3_wd = reg_wdata[0];
@@ -7477,6 +8238,9 @@
assign bank0_info0_page_cfg_3_ecc_en_3_we = addr_hit[30] & reg_we & ~wr_err;
assign bank0_info0_page_cfg_3_ecc_en_3_wd = reg_wdata[5];
+ assign bank0_info0_page_cfg_3_he_en_3_we = addr_hit[30] & reg_we & ~wr_err;
+ assign bank0_info0_page_cfg_3_he_en_3_wd = reg_wdata[6];
+
assign bank0_info1_regwen_0_we = addr_hit[31] & reg_we & ~wr_err;
assign bank0_info1_regwen_0_wd = reg_wdata[0];
@@ -7507,6 +8271,9 @@
assign bank0_info1_page_cfg_0_ecc_en_0_we = addr_hit[35] & reg_we & ~wr_err;
assign bank0_info1_page_cfg_0_ecc_en_0_wd = reg_wdata[5];
+ assign bank0_info1_page_cfg_0_he_en_0_we = addr_hit[35] & reg_we & ~wr_err;
+ assign bank0_info1_page_cfg_0_he_en_0_wd = reg_wdata[6];
+
assign bank0_info1_page_cfg_1_en_1_we = addr_hit[36] & reg_we & ~wr_err;
assign bank0_info1_page_cfg_1_en_1_wd = reg_wdata[0];
@@ -7525,6 +8292,9 @@
assign bank0_info1_page_cfg_1_ecc_en_1_we = addr_hit[36] & reg_we & ~wr_err;
assign bank0_info1_page_cfg_1_ecc_en_1_wd = reg_wdata[5];
+ assign bank0_info1_page_cfg_1_he_en_1_we = addr_hit[36] & reg_we & ~wr_err;
+ assign bank0_info1_page_cfg_1_he_en_1_wd = reg_wdata[6];
+
assign bank0_info1_page_cfg_2_en_2_we = addr_hit[37] & reg_we & ~wr_err;
assign bank0_info1_page_cfg_2_en_2_wd = reg_wdata[0];
@@ -7543,6 +8313,9 @@
assign bank0_info1_page_cfg_2_ecc_en_2_we = addr_hit[37] & reg_we & ~wr_err;
assign bank0_info1_page_cfg_2_ecc_en_2_wd = reg_wdata[5];
+ assign bank0_info1_page_cfg_2_he_en_2_we = addr_hit[37] & reg_we & ~wr_err;
+ assign bank0_info1_page_cfg_2_he_en_2_wd = reg_wdata[6];
+
assign bank0_info1_page_cfg_3_en_3_we = addr_hit[38] & reg_we & ~wr_err;
assign bank0_info1_page_cfg_3_en_3_wd = reg_wdata[0];
@@ -7561,6 +8334,9 @@
assign bank0_info1_page_cfg_3_ecc_en_3_we = addr_hit[38] & reg_we & ~wr_err;
assign bank0_info1_page_cfg_3_ecc_en_3_wd = reg_wdata[5];
+ assign bank0_info1_page_cfg_3_he_en_3_we = addr_hit[38] & reg_we & ~wr_err;
+ assign bank0_info1_page_cfg_3_he_en_3_wd = reg_wdata[6];
+
assign bank1_info0_regwen_0_we = addr_hit[39] & reg_we & ~wr_err;
assign bank1_info0_regwen_0_wd = reg_wdata[0];
@@ -7591,6 +8367,9 @@
assign bank1_info0_page_cfg_0_ecc_en_0_we = addr_hit[43] & reg_we & ~wr_err;
assign bank1_info0_page_cfg_0_ecc_en_0_wd = reg_wdata[5];
+ assign bank1_info0_page_cfg_0_he_en_0_we = addr_hit[43] & reg_we & ~wr_err;
+ assign bank1_info0_page_cfg_0_he_en_0_wd = reg_wdata[6];
+
assign bank1_info0_page_cfg_1_en_1_we = addr_hit[44] & reg_we & ~wr_err;
assign bank1_info0_page_cfg_1_en_1_wd = reg_wdata[0];
@@ -7609,6 +8388,9 @@
assign bank1_info0_page_cfg_1_ecc_en_1_we = addr_hit[44] & reg_we & ~wr_err;
assign bank1_info0_page_cfg_1_ecc_en_1_wd = reg_wdata[5];
+ assign bank1_info0_page_cfg_1_he_en_1_we = addr_hit[44] & reg_we & ~wr_err;
+ assign bank1_info0_page_cfg_1_he_en_1_wd = reg_wdata[6];
+
assign bank1_info0_page_cfg_2_en_2_we = addr_hit[45] & reg_we & ~wr_err;
assign bank1_info0_page_cfg_2_en_2_wd = reg_wdata[0];
@@ -7627,6 +8409,9 @@
assign bank1_info0_page_cfg_2_ecc_en_2_we = addr_hit[45] & reg_we & ~wr_err;
assign bank1_info0_page_cfg_2_ecc_en_2_wd = reg_wdata[5];
+ assign bank1_info0_page_cfg_2_he_en_2_we = addr_hit[45] & reg_we & ~wr_err;
+ assign bank1_info0_page_cfg_2_he_en_2_wd = reg_wdata[6];
+
assign bank1_info0_page_cfg_3_en_3_we = addr_hit[46] & reg_we & ~wr_err;
assign bank1_info0_page_cfg_3_en_3_wd = reg_wdata[0];
@@ -7645,6 +8430,9 @@
assign bank1_info0_page_cfg_3_ecc_en_3_we = addr_hit[46] & reg_we & ~wr_err;
assign bank1_info0_page_cfg_3_ecc_en_3_wd = reg_wdata[5];
+ assign bank1_info0_page_cfg_3_he_en_3_we = addr_hit[46] & reg_we & ~wr_err;
+ assign bank1_info0_page_cfg_3_he_en_3_wd = reg_wdata[6];
+
assign bank1_info1_regwen_0_we = addr_hit[47] & reg_we & ~wr_err;
assign bank1_info1_regwen_0_wd = reg_wdata[0];
@@ -7675,6 +8463,9 @@
assign bank1_info1_page_cfg_0_ecc_en_0_we = addr_hit[51] & reg_we & ~wr_err;
assign bank1_info1_page_cfg_0_ecc_en_0_wd = reg_wdata[5];
+ assign bank1_info1_page_cfg_0_he_en_0_we = addr_hit[51] & reg_we & ~wr_err;
+ assign bank1_info1_page_cfg_0_he_en_0_wd = reg_wdata[6];
+
assign bank1_info1_page_cfg_1_en_1_we = addr_hit[52] & reg_we & ~wr_err;
assign bank1_info1_page_cfg_1_en_1_wd = reg_wdata[0];
@@ -7693,6 +8484,9 @@
assign bank1_info1_page_cfg_1_ecc_en_1_we = addr_hit[52] & reg_we & ~wr_err;
assign bank1_info1_page_cfg_1_ecc_en_1_wd = reg_wdata[5];
+ assign bank1_info1_page_cfg_1_he_en_1_we = addr_hit[52] & reg_we & ~wr_err;
+ assign bank1_info1_page_cfg_1_he_en_1_wd = reg_wdata[6];
+
assign bank1_info1_page_cfg_2_en_2_we = addr_hit[53] & reg_we & ~wr_err;
assign bank1_info1_page_cfg_2_en_2_wd = reg_wdata[0];
@@ -7711,6 +8505,9 @@
assign bank1_info1_page_cfg_2_ecc_en_2_we = addr_hit[53] & reg_we & ~wr_err;
assign bank1_info1_page_cfg_2_ecc_en_2_wd = reg_wdata[5];
+ assign bank1_info1_page_cfg_2_he_en_2_we = addr_hit[53] & reg_we & ~wr_err;
+ assign bank1_info1_page_cfg_2_he_en_2_wd = reg_wdata[6];
+
assign bank1_info1_page_cfg_3_en_3_we = addr_hit[54] & reg_we & ~wr_err;
assign bank1_info1_page_cfg_3_en_3_wd = reg_wdata[0];
@@ -7729,6 +8526,9 @@
assign bank1_info1_page_cfg_3_ecc_en_3_we = addr_hit[54] & reg_we & ~wr_err;
assign bank1_info1_page_cfg_3_ecc_en_3_wd = reg_wdata[5];
+ assign bank1_info1_page_cfg_3_he_en_3_we = addr_hit[54] & reg_we & ~wr_err;
+ assign bank1_info1_page_cfg_3_he_en_3_wd = reg_wdata[6];
+
assign bank_cfg_regwen_we = addr_hit[55] & reg_we & ~wr_err;
assign bank_cfg_regwen_wd = reg_wdata[0];
@@ -7853,6 +8653,7 @@
reg_rdata_next[3] = mp_region_cfg_0_erase_en_0_qs;
reg_rdata_next[4] = mp_region_cfg_0_scramble_en_0_qs;
reg_rdata_next[5] = mp_region_cfg_0_ecc_en_0_qs;
+ reg_rdata_next[6] = mp_region_cfg_0_he_en_0_qs;
reg_rdata_next[16:8] = mp_region_cfg_0_base_0_qs;
reg_rdata_next[29:20] = mp_region_cfg_0_size_0_qs;
end
@@ -7864,6 +8665,7 @@
reg_rdata_next[3] = mp_region_cfg_1_erase_en_1_qs;
reg_rdata_next[4] = mp_region_cfg_1_scramble_en_1_qs;
reg_rdata_next[5] = mp_region_cfg_1_ecc_en_1_qs;
+ reg_rdata_next[6] = mp_region_cfg_1_he_en_1_qs;
reg_rdata_next[16:8] = mp_region_cfg_1_base_1_qs;
reg_rdata_next[29:20] = mp_region_cfg_1_size_1_qs;
end
@@ -7875,6 +8677,7 @@
reg_rdata_next[3] = mp_region_cfg_2_erase_en_2_qs;
reg_rdata_next[4] = mp_region_cfg_2_scramble_en_2_qs;
reg_rdata_next[5] = mp_region_cfg_2_ecc_en_2_qs;
+ reg_rdata_next[6] = mp_region_cfg_2_he_en_2_qs;
reg_rdata_next[16:8] = mp_region_cfg_2_base_2_qs;
reg_rdata_next[29:20] = mp_region_cfg_2_size_2_qs;
end
@@ -7886,6 +8689,7 @@
reg_rdata_next[3] = mp_region_cfg_3_erase_en_3_qs;
reg_rdata_next[4] = mp_region_cfg_3_scramble_en_3_qs;
reg_rdata_next[5] = mp_region_cfg_3_ecc_en_3_qs;
+ reg_rdata_next[6] = mp_region_cfg_3_he_en_3_qs;
reg_rdata_next[16:8] = mp_region_cfg_3_base_3_qs;
reg_rdata_next[29:20] = mp_region_cfg_3_size_3_qs;
end
@@ -7897,6 +8701,7 @@
reg_rdata_next[3] = mp_region_cfg_4_erase_en_4_qs;
reg_rdata_next[4] = mp_region_cfg_4_scramble_en_4_qs;
reg_rdata_next[5] = mp_region_cfg_4_ecc_en_4_qs;
+ reg_rdata_next[6] = mp_region_cfg_4_he_en_4_qs;
reg_rdata_next[16:8] = mp_region_cfg_4_base_4_qs;
reg_rdata_next[29:20] = mp_region_cfg_4_size_4_qs;
end
@@ -7908,6 +8713,7 @@
reg_rdata_next[3] = mp_region_cfg_5_erase_en_5_qs;
reg_rdata_next[4] = mp_region_cfg_5_scramble_en_5_qs;
reg_rdata_next[5] = mp_region_cfg_5_ecc_en_5_qs;
+ reg_rdata_next[6] = mp_region_cfg_5_he_en_5_qs;
reg_rdata_next[16:8] = mp_region_cfg_5_base_5_qs;
reg_rdata_next[29:20] = mp_region_cfg_5_size_5_qs;
end
@@ -7919,6 +8725,7 @@
reg_rdata_next[3] = mp_region_cfg_6_erase_en_6_qs;
reg_rdata_next[4] = mp_region_cfg_6_scramble_en_6_qs;
reg_rdata_next[5] = mp_region_cfg_6_ecc_en_6_qs;
+ reg_rdata_next[6] = mp_region_cfg_6_he_en_6_qs;
reg_rdata_next[16:8] = mp_region_cfg_6_base_6_qs;
reg_rdata_next[29:20] = mp_region_cfg_6_size_6_qs;
end
@@ -7930,6 +8737,7 @@
reg_rdata_next[3] = mp_region_cfg_7_erase_en_7_qs;
reg_rdata_next[4] = mp_region_cfg_7_scramble_en_7_qs;
reg_rdata_next[5] = mp_region_cfg_7_ecc_en_7_qs;
+ reg_rdata_next[6] = mp_region_cfg_7_he_en_7_qs;
reg_rdata_next[16:8] = mp_region_cfg_7_base_7_qs;
reg_rdata_next[29:20] = mp_region_cfg_7_size_7_qs;
end
@@ -7940,6 +8748,7 @@
reg_rdata_next[2] = default_region_erase_en_qs;
reg_rdata_next[3] = default_region_scramble_en_qs;
reg_rdata_next[4] = default_region_ecc_en_qs;
+ reg_rdata_next[5] = default_region_he_en_qs;
end
addr_hit[23]: begin
@@ -7965,6 +8774,7 @@
reg_rdata_next[3] = bank0_info0_page_cfg_0_erase_en_0_qs;
reg_rdata_next[4] = bank0_info0_page_cfg_0_scramble_en_0_qs;
reg_rdata_next[5] = bank0_info0_page_cfg_0_ecc_en_0_qs;
+ reg_rdata_next[6] = bank0_info0_page_cfg_0_he_en_0_qs;
end
addr_hit[28]: begin
@@ -7974,6 +8784,7 @@
reg_rdata_next[3] = bank0_info0_page_cfg_1_erase_en_1_qs;
reg_rdata_next[4] = bank0_info0_page_cfg_1_scramble_en_1_qs;
reg_rdata_next[5] = bank0_info0_page_cfg_1_ecc_en_1_qs;
+ reg_rdata_next[6] = bank0_info0_page_cfg_1_he_en_1_qs;
end
addr_hit[29]: begin
@@ -7983,6 +8794,7 @@
reg_rdata_next[3] = bank0_info0_page_cfg_2_erase_en_2_qs;
reg_rdata_next[4] = bank0_info0_page_cfg_2_scramble_en_2_qs;
reg_rdata_next[5] = bank0_info0_page_cfg_2_ecc_en_2_qs;
+ reg_rdata_next[6] = bank0_info0_page_cfg_2_he_en_2_qs;
end
addr_hit[30]: begin
@@ -7992,6 +8804,7 @@
reg_rdata_next[3] = bank0_info0_page_cfg_3_erase_en_3_qs;
reg_rdata_next[4] = bank0_info0_page_cfg_3_scramble_en_3_qs;
reg_rdata_next[5] = bank0_info0_page_cfg_3_ecc_en_3_qs;
+ reg_rdata_next[6] = bank0_info0_page_cfg_3_he_en_3_qs;
end
addr_hit[31]: begin
@@ -8017,6 +8830,7 @@
reg_rdata_next[3] = bank0_info1_page_cfg_0_erase_en_0_qs;
reg_rdata_next[4] = bank0_info1_page_cfg_0_scramble_en_0_qs;
reg_rdata_next[5] = bank0_info1_page_cfg_0_ecc_en_0_qs;
+ reg_rdata_next[6] = bank0_info1_page_cfg_0_he_en_0_qs;
end
addr_hit[36]: begin
@@ -8026,6 +8840,7 @@
reg_rdata_next[3] = bank0_info1_page_cfg_1_erase_en_1_qs;
reg_rdata_next[4] = bank0_info1_page_cfg_1_scramble_en_1_qs;
reg_rdata_next[5] = bank0_info1_page_cfg_1_ecc_en_1_qs;
+ reg_rdata_next[6] = bank0_info1_page_cfg_1_he_en_1_qs;
end
addr_hit[37]: begin
@@ -8035,6 +8850,7 @@
reg_rdata_next[3] = bank0_info1_page_cfg_2_erase_en_2_qs;
reg_rdata_next[4] = bank0_info1_page_cfg_2_scramble_en_2_qs;
reg_rdata_next[5] = bank0_info1_page_cfg_2_ecc_en_2_qs;
+ reg_rdata_next[6] = bank0_info1_page_cfg_2_he_en_2_qs;
end
addr_hit[38]: begin
@@ -8044,6 +8860,7 @@
reg_rdata_next[3] = bank0_info1_page_cfg_3_erase_en_3_qs;
reg_rdata_next[4] = bank0_info1_page_cfg_3_scramble_en_3_qs;
reg_rdata_next[5] = bank0_info1_page_cfg_3_ecc_en_3_qs;
+ reg_rdata_next[6] = bank0_info1_page_cfg_3_he_en_3_qs;
end
addr_hit[39]: begin
@@ -8069,6 +8886,7 @@
reg_rdata_next[3] = bank1_info0_page_cfg_0_erase_en_0_qs;
reg_rdata_next[4] = bank1_info0_page_cfg_0_scramble_en_0_qs;
reg_rdata_next[5] = bank1_info0_page_cfg_0_ecc_en_0_qs;
+ reg_rdata_next[6] = bank1_info0_page_cfg_0_he_en_0_qs;
end
addr_hit[44]: begin
@@ -8078,6 +8896,7 @@
reg_rdata_next[3] = bank1_info0_page_cfg_1_erase_en_1_qs;
reg_rdata_next[4] = bank1_info0_page_cfg_1_scramble_en_1_qs;
reg_rdata_next[5] = bank1_info0_page_cfg_1_ecc_en_1_qs;
+ reg_rdata_next[6] = bank1_info0_page_cfg_1_he_en_1_qs;
end
addr_hit[45]: begin
@@ -8087,6 +8906,7 @@
reg_rdata_next[3] = bank1_info0_page_cfg_2_erase_en_2_qs;
reg_rdata_next[4] = bank1_info0_page_cfg_2_scramble_en_2_qs;
reg_rdata_next[5] = bank1_info0_page_cfg_2_ecc_en_2_qs;
+ reg_rdata_next[6] = bank1_info0_page_cfg_2_he_en_2_qs;
end
addr_hit[46]: begin
@@ -8096,6 +8916,7 @@
reg_rdata_next[3] = bank1_info0_page_cfg_3_erase_en_3_qs;
reg_rdata_next[4] = bank1_info0_page_cfg_3_scramble_en_3_qs;
reg_rdata_next[5] = bank1_info0_page_cfg_3_ecc_en_3_qs;
+ reg_rdata_next[6] = bank1_info0_page_cfg_3_he_en_3_qs;
end
addr_hit[47]: begin
@@ -8121,6 +8942,7 @@
reg_rdata_next[3] = bank1_info1_page_cfg_0_erase_en_0_qs;
reg_rdata_next[4] = bank1_info1_page_cfg_0_scramble_en_0_qs;
reg_rdata_next[5] = bank1_info1_page_cfg_0_ecc_en_0_qs;
+ reg_rdata_next[6] = bank1_info1_page_cfg_0_he_en_0_qs;
end
addr_hit[52]: begin
@@ -8130,6 +8952,7 @@
reg_rdata_next[3] = bank1_info1_page_cfg_1_erase_en_1_qs;
reg_rdata_next[4] = bank1_info1_page_cfg_1_scramble_en_1_qs;
reg_rdata_next[5] = bank1_info1_page_cfg_1_ecc_en_1_qs;
+ reg_rdata_next[6] = bank1_info1_page_cfg_1_he_en_1_qs;
end
addr_hit[53]: begin
@@ -8139,6 +8962,7 @@
reg_rdata_next[3] = bank1_info1_page_cfg_2_erase_en_2_qs;
reg_rdata_next[4] = bank1_info1_page_cfg_2_scramble_en_2_qs;
reg_rdata_next[5] = bank1_info1_page_cfg_2_ecc_en_2_qs;
+ reg_rdata_next[6] = bank1_info1_page_cfg_2_he_en_2_qs;
end
addr_hit[54]: begin
@@ -8148,6 +8972,7 @@
reg_rdata_next[3] = bank1_info1_page_cfg_3_erase_en_3_qs;
reg_rdata_next[4] = bank1_info1_page_cfg_3_scramble_en_3_qs;
reg_rdata_next[5] = bank1_info1_page_cfg_3_ecc_en_3_qs;
+ reg_rdata_next[6] = bank1_info1_page_cfg_3_he_en_3_qs;
end
addr_hit[55]: begin
diff --git a/hw/top_earlgrey/data/autogen/top_earlgrey.gen.hjson b/hw/top_earlgrey/data/autogen/top_earlgrey.gen.hjson
index 00803f8..b2c4335 100644
--- a/hw/top_earlgrey/data/autogen/top_earlgrey.gen.hjson
+++ b/hw/top_earlgrey/data/autogen/top_earlgrey.gen.hjson
@@ -2374,7 +2374,25 @@
{
struct: lc_tx
type: uni
- name: lc_provision_en
+ name: lc_provision_wr_en
+ act: rcv
+ package: lc_ctrl_pkg
+ inst_name: flash_ctrl
+ index: -1
+ }
+ {
+ struct: lc_tx
+ type: uni
+ name: lc_provision_rd_en
+ act: rcv
+ package: lc_ctrl_pkg
+ inst_name: flash_ctrl
+ index: -1
+ }
+ {
+ struct: lc_tx
+ type: uni
+ name: lc_iso_flash_wr_en
act: rcv
package: lc_ctrl_pkg
inst_name: flash_ctrl
@@ -4341,6 +4359,15 @@
top_signame: flash_test_voltage_h
index: -1
}
+ {
+ struct: lc_tx
+ package: lc_ctrl
+ type: uni
+ act: rcv
+ name: lc_dft_en
+ inst_name: eflash
+ index: -1
+ }
]
clock_reset_export: []
clock_connections:
@@ -7824,7 +7851,25 @@
{
struct: lc_tx
type: uni
- name: lc_provision_en
+ name: lc_provision_wr_en
+ act: rcv
+ package: lc_ctrl_pkg
+ inst_name: flash_ctrl
+ index: -1
+ }
+ {
+ struct: lc_tx
+ type: uni
+ name: lc_provision_rd_en
+ act: rcv
+ package: lc_ctrl_pkg
+ inst_name: flash_ctrl
+ index: -1
+ }
+ {
+ struct: lc_tx
+ type: uni
+ name: lc_iso_flash_wr_en
act: rcv
package: lc_ctrl_pkg
inst_name: flash_ctrl
@@ -8479,6 +8524,15 @@
index: -1
}
{
+ struct: lc_tx
+ package: lc_ctrl
+ type: uni
+ act: rcv
+ name: lc_dft_en
+ inst_name: eflash
+ index: -1
+ }
+ {
struct: tl
type: req_rsp
name: tl_corei
diff --git a/hw/top_earlgrey/ip/flash_ctrl/data/autogen/flash_ctrl.hjson b/hw/top_earlgrey/ip/flash_ctrl/data/autogen/flash_ctrl.hjson
index 20f7d3b..0ed3014 100644
--- a/hw/top_earlgrey/ip/flash_ctrl/data/autogen/flash_ctrl.hjson
+++ b/hw/top_earlgrey/ip/flash_ctrl/data/autogen/flash_ctrl.hjson
@@ -37,7 +37,21 @@
{ struct: "lc_tx",
type: "uni",
- name: "lc_provision_en",
+ name: "lc_provision_wr_en",
+ act: "rcv",
+ package: "lc_ctrl_pkg"
+ },
+
+ { struct: "lc_tx",
+ type: "uni",
+ name: "lc_provision_rd_en",
+ act: "rcv",
+ package: "lc_ctrl_pkg"
+ },
+
+ { struct: "lc_tx",
+ type: "uni",
+ name: "lc_iso_flash_wr_en",
act: "rcv",
package: "lc_ctrl_pkg"
},
@@ -331,7 +345,7 @@
]
},
- // Data partition memory protection region setup
+ // Data partition memory properties region setup
{ multireg: {
cname: "FLASH_CTRL",
name: "REGION_CFG_REGWEN"
@@ -367,7 +381,7 @@
{ multireg: {
cname: "FLASH_CTRL",
name: "MP_REGION_CFG",
- desc: "Memory protection configuration for data partition",
+ desc: "Memory property configuration for data partition",
count: "NumRegions",
swaccess: "rw",
hwaccess: "hro",
@@ -416,6 +430,13 @@
''',
resval: "0"
}
+ { bits: "6",
+ name: "HE_EN",
+ desc: '''
+ Region is high endurance enabled.
+ ''',
+ resval: "0"
+ }
{ bits: "16:8",
name: "BASE",
desc: '''
@@ -434,9 +455,9 @@
},
},
- // Default region permissions for data partition memory protection
+ // Default region properties for data partition
{ name: "DEFAULT_REGION",
- desc: "Default region permissions",
+ desc: "Default region properties",
swaccess: "rw",
hwaccess: "hro",
resval: "0",
@@ -476,10 +497,17 @@
''',
resval: "0"
}
+ { bits: "5",
+ name: "HE_EN",
+ desc: '''
+ Region is high endurance enabled
+ ''',
+ resval: "0"
+ }
]
},
- // Info partition memory protection setup
+ // Info partition memory properties setup
{ multireg: {
cname: "FLASH_CTRL",
name: "BANK0_INFO0_REGWEN"
@@ -516,8 +544,8 @@
cname: "FLASH_CTRL",
name: "BANK0_INFO0_PAGE_CFG",
desc: '''
- Memory protection configuration for info partition in bank0,
- Unlike data partition, each page is individually protected.
+ Memory property configuration for info partition in bank0,
+ Unlike data partition, each page is individually configured.
'''
count: "NumInfos0",
swaccess: "rw",
@@ -567,6 +595,13 @@
''',
resval: "0"
}
+ { bits: "6",
+ name: "HE_EN",
+ desc: '''
+ Region is high endurance enabled.
+ ''',
+ resval: "0"
+ }
],
},
},
@@ -606,8 +641,8 @@
cname: "FLASH_CTRL",
name: "BANK0_INFO1_PAGE_CFG",
desc: '''
- Memory protection configuration for info partition in bank0,
- Unlike data partition, each page is individually protected.
+ Memory property configuration for info partition in bank0,
+ Unlike data partition, each page is individually configured.
'''
count: "NumInfos1",
swaccess: "rw",
@@ -657,6 +692,13 @@
''',
resval: "0"
}
+ { bits: "6",
+ name: "HE_EN",
+ desc: '''
+ Region is high endurance enabled.
+ ''',
+ resval: "0"
+ }
],
},
},
@@ -696,8 +738,8 @@
cname: "FLASH_CTRL",
name: "BANK1_INFO0_PAGE_CFG",
desc: '''
- Memory protection configuration for info partition in bank1,
- Unlike data partition, each page is individually protected.
+ Memory property configuration for info partition in bank1,
+ Unlike data partition, each page is individually configured.
'''
count: "NumInfos0",
swaccess: "rw",
@@ -747,6 +789,13 @@
''',
resval: "0"
}
+ { bits: "6",
+ name: "HE_EN",
+ desc: '''
+ Region is high endurance enabled.
+ ''',
+ resval: "0"
+ }
],
},
},
@@ -786,8 +835,8 @@
cname: "FLASH_CTRL",
name: "BANK1_INFO1_PAGE_CFG",
desc: '''
- Memory protection configuration for info partition in bank1,
- Unlike data partition, each page is individually protected.
+ Memory property configuration for info partition in bank1,
+ Unlike data partition, each page is individually configured.
'''
count: "NumInfos1",
swaccess: "rw",
@@ -837,6 +886,13 @@
''',
resval: "0"
}
+ { bits: "6",
+ name: "HE_EN",
+ desc: '''
+ Region is high endurance enabled.
+ ''',
+ resval: "0"
+ }
],
},
},
@@ -871,7 +927,7 @@
{ multireg: {
cname: "FLASH_CTRL",
name: "MP_BANK_CFG",
- desc: "Memory protect bank configuration",
+ desc: "Memory properties bank configuration",
count: "RegNumBanks",
swaccess: "rw",
hwaccess: "hro",
diff --git a/hw/top_earlgrey/ip/flash_ctrl/rtl/autogen/flash_ctrl.sv b/hw/top_earlgrey/ip/flash_ctrl/rtl/autogen/flash_ctrl.sv
index 5ab7857..e527e57 100644
--- a/hw/top_earlgrey/ip/flash_ctrl/rtl/autogen/flash_ctrl.sv
+++ b/hw/top_earlgrey/ip/flash_ctrl/rtl/autogen/flash_ctrl.sv
@@ -19,7 +19,9 @@
input rst_ni,
// life cycle interface
- lc_ctrl_pkg::lc_tx_t lc_provision_en_i,
+ lc_ctrl_pkg::lc_tx_t lc_provision_wr_en_i,
+ lc_ctrl_pkg::lc_tx_t lc_provision_rd_en_i,
+ lc_ctrl_pkg::lc_tx_t lc_iso_flash_wr_en_i,
// Bus Interface
input tlul_pkg::tl_h2d_t tl_i,
@@ -109,7 +111,7 @@
logic prog_done, rd_done, erase_done;
logic prog_err, rd_err, erase_err;
- // Flash Memory Protection Connections
+ // Flash Memory Properties Connections
logic [BusAddrW-1:0] flash_addr;
logic flash_req;
logic flash_rd_done, flash_prog_done, flash_erase_done;
@@ -171,18 +173,38 @@
logic lfsr_en;
// life cycle connections
- lc_ctrl_pkg::lc_tx_t [FlashLcLast-1:0] lc_provision_en;
+ lc_ctrl_pkg::lc_tx_t [FlashWrLcLast-1:0] lc_provision_wr_en;
+ lc_ctrl_pkg::lc_tx_t [FlashRdLcLast-1:0] lc_provision_rd_en;
+ lc_ctrl_pkg::lc_tx_t lc_iso_flash_wr_en;
// synchronize provision enable into local domain
prim_lc_sync #(
- .NumCopies(int'(FlashLcLast))
- ) u_lc_provision_en_sync (
+ .NumCopies(int'(FlashWrLcLast))
+ ) u_lc_provision_wr_en_sync (
.clk_i,
.rst_ni,
- .lc_en_i(lc_provision_en_i),
- .lc_en_o(lc_provision_en)
+ .lc_en_i(lc_provision_wr_en_i),
+ .lc_en_o(lc_provision_wr_en)
);
+ prim_lc_sync #(
+ .NumCopies(int'(FlashRdLcLast))
+ ) u_lc_provision_rd_en_sync (
+ .clk_i,
+ .rst_ni,
+ .lc_en_i(lc_provision_rd_en_i),
+ .lc_en_o(lc_provision_rd_en)
+ );
+ prim_lc_sync #(
+ .NumCopies(1)
+ ) u_lc_iso_flash_en_sync (
+ .clk_i,
+ .rst_ni,
+ .lc_en_i(lc_iso_flash_wr_en_i),
+ .lc_en_o(lc_iso_flash_wr_en)
+ );
+
+
prim_lfsr #(
.DefaultSeed(),
.EntropyDw(4),
@@ -285,12 +307,21 @@
// hardware interface
// software only has privilege to change creator seed when provision enable is set and
- // before the the seed is set as valid in otp
- assign creator_seed_priv = lc_provision_en[FlashLcCreatorSeedPriv] == lc_ctrl_pkg::On &
+ // before the the seed is set as valid in otp.
+ // lc provision write enable is used here as creator assets can only be changed when
+ // creator secrets are not yet locked.
+ assign creator_seed_priv = (lc_provision_wr_en[FlashWrLcCreatorSeedPriv] == lc_ctrl_pkg::On) &
~otp_i.seed_valid;
// owner seed is under software control and can be modided whenever provision enable is set
- assign owner_seed_priv = lc_provision_en[FlashLcOwnerSeedPriv] == lc_ctrl_pkg::On;
+ // read enable is used here as this is mostly under the control of creator software and just
+ // needs to be locked out from specific life cycle states.
+ assign owner_seed_priv = lc_provision_rd_en[FlashRdLcOwnerSeedPriv] == lc_ctrl_pkg::On;
+
+ // the seed is only readable after it has been written and locked.
+ logic seed_rd_en;
+ assign seed_rd_en = lc_provision_wr_en[FlashWrLcMgrIf] == lc_ctrl_pkg::Off &
+ lc_provision_rd_en[FlashRdLcMgrIf] == lc_ctrl_pkg::On;
flash_ctrl_lcmgr u_flash_hw_if (
.clk_i,
@@ -298,7 +329,7 @@
.init_i(pwrmgr_i.flash_init),
.init_done_o(pwrmgr_o.flash_done),
- .provision_en_i(lc_provision_en[FlashLcMgrIf] == lc_ctrl_pkg::On),
+ .provision_en_i(seed_rd_en),
// interface to ctrl arb control ports
.ctrl_o(hw_ctrl),
@@ -528,7 +559,7 @@
end
//////////////////////////////////////
- // Data partition protection configuration
+ // Data partition properties configuration
//////////////////////////////////////
// extra region is the default region
mp_region_cfg_t [MpRegions:0] region_cfgs;
@@ -543,9 +574,10 @@
assign region_cfgs[MpRegions].erase_en.q = reg2hw.default_region.erase_en.q;
assign region_cfgs[MpRegions].scramble_en.q = reg2hw.default_region.scramble_en.q;
assign region_cfgs[MpRegions].ecc_en.q = reg2hw.default_region.ecc_en.q;
+ assign region_cfgs[MpRegions].he_en.q = reg2hw.default_region.he_en.q;
//////////////////////////////////////
- // Info partition protection configuration
+ // Info partition properties configuration
//////////////////////////////////////
info_page_cfg_t [NumBanks-1:0][InfoTypes-1:0][InfosPerBank-1:0] reg2hw_info_page_cfgs;
info_page_cfg_t [NumBanks-1:0][InfoTypes-1:0][InfosPerBank-1:0] info_page_cfgs;
@@ -557,6 +589,10 @@
assign reg2hw_info_page_cfgs[1][1] = reg2hw.bank1_info1_page_cfg;
// qualify reg2hw settings with creator / owner privileges
+ logic iso_flash_wr_en;
+ assign iso_flash_wr_en = lc_provision_wr_en[FlashWrLcInfoCfg] == lc_ctrl_pkg::On |
+ lc_iso_flash_wr_en == lc_ctrl_pkg::On;
+
for(genvar i = 0; i < NumBanks; i++) begin : gen_info_priv_bank
for (genvar j = 0; j < InfoTypes; j++) begin : gen_info_priv_type
flash_ctrl_info_cfg # (
@@ -566,14 +602,15 @@
.cfgs_i(reg2hw_info_page_cfgs[i][j]),
.creator_seed_priv_i(creator_seed_priv),
.owner_seed_priv_i(owner_seed_priv),
- .provision_en_i(lc_provision_en[FlashLcInfoCfg] == lc_ctrl_pkg::On),
+ .iso_flash_wr_en_i(iso_flash_wr_en),
+ .iso_flash_rd_en_i(lc_provision_rd_en[FlashRdLcInfoCfg] == lc_ctrl_pkg::On),
.cfgs_o(info_page_cfgs[i][j])
);
end
end
//////////////////////////////////////
- // flash memory protection
+ // flash memory properties
//////////////////////////////////////
// direct assignment since prog/rd/erase_ctrl do not make use of op_part
flash_part_e flash_part_sel;
@@ -581,8 +618,8 @@
assign flash_part_sel = op_part;
assign flash_info_sel = op_info_sel;
- // Flash memory protection
- // Memory protection is page based and thus should use phy addressing
+ // Flash memory Properties
+ // Memory property is page based and thus should use phy addressing
// This should move to flash_phy long term
flash_mp u_flash_mp (
.clk_i,
@@ -619,6 +656,7 @@
.req_o(flash_o.req),
.scramble_en_o(flash_o.scramble_en),
.ecc_en_o(flash_o.ecc_en),
+ .he_en_o(flash_o.he_en),
.rd_o(flash_o.rd),
.prog_o(flash_o.prog),
.pg_erase_o(flash_o.pg_erase),
diff --git a/hw/top_earlgrey/ip/flash_ctrl/rtl/autogen/flash_ctrl_pkg.sv b/hw/top_earlgrey/ip/flash_ctrl/rtl/autogen/flash_ctrl_pkg.sv
index fd8c5a7..9410e0c 100644
--- a/hw/top_earlgrey/ip/flash_ctrl/rtl/autogen/flash_ctrl_pkg.sv
+++ b/hw/top_earlgrey/ip/flash_ctrl/rtl/autogen/flash_ctrl_pkg.sv
@@ -82,14 +82,21 @@
// parameters for connected components
parameter int SeedWidth = 256;
- // life cycle provision enable usage
- typedef enum logic [2:0] {
- FlashLcCreatorSeedPriv,
- FlashLcOwnerSeedPriv,
- FlashLcMgrIf,
- FlashLcInfoCfg,
- FlashLcLast
- } flash_lc_provision_en_e;
+ // life cycle provision write enable usage
+ typedef enum logic [1:0] {
+ FlashWrLcCreatorSeedPriv,
+ FlashWrLcMgrIf,
+ FlashWrLcInfoCfg,
+ FlashWrLcLast
+ } flash_lc_provision_wr_en_e;
+
+ // life cycle provision read enable usage
+ typedef enum logic [1:0] {
+ FlashRdLcOwnerSeedPriv,
+ FlashRdLcMgrIf,
+ FlashRdLcInfoCfg,
+ FlashRdLcLast
+ } flash_lc_provision_rd_en_e;
// lcmgr phase enum
typedef enum logic [1:0] {
@@ -162,7 +169,8 @@
prog_en: 1'b0,
erase_en: 1'b0,
scramble_en: 1'b0,
- ecc_en: 1'b0 // TBD, update to 1 once tb supports ECC
+ ecc_en: 1'b0, // TBD, update to 1 once tb supports ECC
+ he_en: 1'b1
};
parameter info_page_cfg_t CfgAllowReadErase = '{
@@ -171,7 +179,8 @@
prog_en: 1'b0,
erase_en: 1'b1,
scramble_en: 1'b0,
- ecc_en: 1'b0 // TBD, update to 1 once tb supports ECC
+ ecc_en: 1'b0, // TBD, update to 1 once tb supports ECC
+ he_en: 1'b1 // HW assumes high endurance
};
parameter info_page_attr_t HwInfoPageAttr[HwInfoRules] = '{
@@ -204,6 +213,7 @@
erase_en: 1'b1,
scramble_en: 1'b0,
ecc_en: 1'b0,
+ he_en: 1'b1, // HW assumes high endurance
base: '0,
size: '{default:'1}
}
@@ -260,6 +270,7 @@
logic req;
logic scramble_en;
logic ecc_en;
+ logic he_en;
logic rd;
logic prog;
logic pg_erase;
@@ -280,6 +291,7 @@
req: 1'b0,
scramble_en: 1'b0,
ecc_en: 1'b0,
+ he_en: 1'b0,
rd: 1'b0,
prog: 1'b0,
pg_erase: 1'b0,
@@ -381,6 +393,14 @@
entropy: '0
};
+ // dft_en jtag selection
+ typedef enum logic [2:0] {
+ FlashLcTckSel,
+ FlashLcTdiSel,
+ FlashLcTmsSel,
+ FlashLcTdoSel,
+ FlashLcJtagLast
+ } flash_lc_jtag_e;
// find the max number pages among info types
function automatic integer max_info_pages(int infos[InfoTypes]);
diff --git a/hw/top_earlgrey/ip/flash_ctrl/rtl/autogen/flash_ctrl_reg_pkg.sv b/hw/top_earlgrey/ip/flash_ctrl/rtl/autogen/flash_ctrl_reg_pkg.sv
index e72974f..27992fe 100644
--- a/hw/top_earlgrey/ip/flash_ctrl/rtl/autogen/flash_ctrl_reg_pkg.sv
+++ b/hw/top_earlgrey/ip/flash_ctrl/rtl/autogen/flash_ctrl_reg_pkg.sv
@@ -138,6 +138,9 @@
logic q;
} ecc_en;
struct packed {
+ logic q;
+ } he_en;
+ struct packed {
logic [8:0] q;
} base;
struct packed {
@@ -161,6 +164,9 @@
struct packed {
logic q;
} ecc_en;
+ struct packed {
+ logic q;
+ } he_en;
} flash_ctrl_reg2hw_default_region_reg_t;
typedef struct packed {
@@ -182,6 +188,9 @@
struct packed {
logic q;
} ecc_en;
+ struct packed {
+ logic q;
+ } he_en;
} flash_ctrl_reg2hw_bank0_info0_page_cfg_mreg_t;
typedef struct packed {
@@ -203,6 +212,9 @@
struct packed {
logic q;
} ecc_en;
+ struct packed {
+ logic q;
+ } he_en;
} flash_ctrl_reg2hw_bank0_info1_page_cfg_mreg_t;
typedef struct packed {
@@ -224,6 +236,9 @@
struct packed {
logic q;
} ecc_en;
+ struct packed {
+ logic q;
+ } he_en;
} flash_ctrl_reg2hw_bank1_info0_page_cfg_mreg_t;
typedef struct packed {
@@ -245,6 +260,9 @@
struct packed {
logic q;
} ecc_en;
+ struct packed {
+ logic q;
+ } he_en;
} flash_ctrl_reg2hw_bank1_info1_page_cfg_mreg_t;
typedef struct packed {
@@ -365,17 +383,17 @@
// Register to internal design logic //
///////////////////////////////////////
typedef struct packed {
- flash_ctrl_reg2hw_intr_state_reg_t intr_state; // [420:415]
- flash_ctrl_reg2hw_intr_enable_reg_t intr_enable; // [414:409]
- flash_ctrl_reg2hw_intr_test_reg_t intr_test; // [408:397]
- flash_ctrl_reg2hw_control_reg_t control; // [396:378]
- flash_ctrl_reg2hw_addr_reg_t addr; // [377:346]
- flash_ctrl_reg2hw_mp_region_cfg_mreg_t [7:0] mp_region_cfg; // [345:146]
- flash_ctrl_reg2hw_default_region_reg_t default_region; // [145:141]
- flash_ctrl_reg2hw_bank0_info0_page_cfg_mreg_t [3:0] bank0_info0_page_cfg; // [140:117]
- flash_ctrl_reg2hw_bank0_info1_page_cfg_mreg_t [3:0] bank0_info1_page_cfg; // [116:93]
- flash_ctrl_reg2hw_bank1_info0_page_cfg_mreg_t [3:0] bank1_info0_page_cfg; // [92:69]
- flash_ctrl_reg2hw_bank1_info1_page_cfg_mreg_t [3:0] bank1_info1_page_cfg; // [68:45]
+ flash_ctrl_reg2hw_intr_state_reg_t intr_state; // [445:440]
+ flash_ctrl_reg2hw_intr_enable_reg_t intr_enable; // [439:434]
+ flash_ctrl_reg2hw_intr_test_reg_t intr_test; // [433:422]
+ flash_ctrl_reg2hw_control_reg_t control; // [421:403]
+ flash_ctrl_reg2hw_addr_reg_t addr; // [402:371]
+ flash_ctrl_reg2hw_mp_region_cfg_mreg_t [7:0] mp_region_cfg; // [370:163]
+ flash_ctrl_reg2hw_default_region_reg_t default_region; // [162:157]
+ flash_ctrl_reg2hw_bank0_info0_page_cfg_mreg_t [3:0] bank0_info0_page_cfg; // [156:129]
+ flash_ctrl_reg2hw_bank0_info1_page_cfg_mreg_t [3:0] bank0_info1_page_cfg; // [128:101]
+ flash_ctrl_reg2hw_bank1_info0_page_cfg_mreg_t [3:0] bank1_info0_page_cfg; // [100:73]
+ flash_ctrl_reg2hw_bank1_info1_page_cfg_mreg_t [3:0] bank1_info1_page_cfg; // [72:45]
flash_ctrl_reg2hw_mp_bank_cfg_mreg_t [1:0] mp_bank_cfg; // [44:43]
flash_ctrl_reg2hw_scratch_reg_t scratch; // [42:11]
flash_ctrl_reg2hw_fifo_lvl_reg_t fifo_lvl; // [10:1]
diff --git a/hw/top_earlgrey/ip/flash_ctrl/rtl/autogen/flash_ctrl_reg_top.sv b/hw/top_earlgrey/ip/flash_ctrl/rtl/autogen/flash_ctrl_reg_top.sv
index b9791d7..eba5983 100644
--- a/hw/top_earlgrey/ip/flash_ctrl/rtl/autogen/flash_ctrl_reg_top.sv
+++ b/hw/top_earlgrey/ip/flash_ctrl/rtl/autogen/flash_ctrl_reg_top.sv
@@ -237,6 +237,9 @@
logic mp_region_cfg_0_ecc_en_0_qs;
logic mp_region_cfg_0_ecc_en_0_wd;
logic mp_region_cfg_0_ecc_en_0_we;
+ logic mp_region_cfg_0_he_en_0_qs;
+ logic mp_region_cfg_0_he_en_0_wd;
+ logic mp_region_cfg_0_he_en_0_we;
logic [8:0] mp_region_cfg_0_base_0_qs;
logic [8:0] mp_region_cfg_0_base_0_wd;
logic mp_region_cfg_0_base_0_we;
@@ -261,6 +264,9 @@
logic mp_region_cfg_1_ecc_en_1_qs;
logic mp_region_cfg_1_ecc_en_1_wd;
logic mp_region_cfg_1_ecc_en_1_we;
+ logic mp_region_cfg_1_he_en_1_qs;
+ logic mp_region_cfg_1_he_en_1_wd;
+ logic mp_region_cfg_1_he_en_1_we;
logic [8:0] mp_region_cfg_1_base_1_qs;
logic [8:0] mp_region_cfg_1_base_1_wd;
logic mp_region_cfg_1_base_1_we;
@@ -285,6 +291,9 @@
logic mp_region_cfg_2_ecc_en_2_qs;
logic mp_region_cfg_2_ecc_en_2_wd;
logic mp_region_cfg_2_ecc_en_2_we;
+ logic mp_region_cfg_2_he_en_2_qs;
+ logic mp_region_cfg_2_he_en_2_wd;
+ logic mp_region_cfg_2_he_en_2_we;
logic [8:0] mp_region_cfg_2_base_2_qs;
logic [8:0] mp_region_cfg_2_base_2_wd;
logic mp_region_cfg_2_base_2_we;
@@ -309,6 +318,9 @@
logic mp_region_cfg_3_ecc_en_3_qs;
logic mp_region_cfg_3_ecc_en_3_wd;
logic mp_region_cfg_3_ecc_en_3_we;
+ logic mp_region_cfg_3_he_en_3_qs;
+ logic mp_region_cfg_3_he_en_3_wd;
+ logic mp_region_cfg_3_he_en_3_we;
logic [8:0] mp_region_cfg_3_base_3_qs;
logic [8:0] mp_region_cfg_3_base_3_wd;
logic mp_region_cfg_3_base_3_we;
@@ -333,6 +345,9 @@
logic mp_region_cfg_4_ecc_en_4_qs;
logic mp_region_cfg_4_ecc_en_4_wd;
logic mp_region_cfg_4_ecc_en_4_we;
+ logic mp_region_cfg_4_he_en_4_qs;
+ logic mp_region_cfg_4_he_en_4_wd;
+ logic mp_region_cfg_4_he_en_4_we;
logic [8:0] mp_region_cfg_4_base_4_qs;
logic [8:0] mp_region_cfg_4_base_4_wd;
logic mp_region_cfg_4_base_4_we;
@@ -357,6 +372,9 @@
logic mp_region_cfg_5_ecc_en_5_qs;
logic mp_region_cfg_5_ecc_en_5_wd;
logic mp_region_cfg_5_ecc_en_5_we;
+ logic mp_region_cfg_5_he_en_5_qs;
+ logic mp_region_cfg_5_he_en_5_wd;
+ logic mp_region_cfg_5_he_en_5_we;
logic [8:0] mp_region_cfg_5_base_5_qs;
logic [8:0] mp_region_cfg_5_base_5_wd;
logic mp_region_cfg_5_base_5_we;
@@ -381,6 +399,9 @@
logic mp_region_cfg_6_ecc_en_6_qs;
logic mp_region_cfg_6_ecc_en_6_wd;
logic mp_region_cfg_6_ecc_en_6_we;
+ logic mp_region_cfg_6_he_en_6_qs;
+ logic mp_region_cfg_6_he_en_6_wd;
+ logic mp_region_cfg_6_he_en_6_we;
logic [8:0] mp_region_cfg_6_base_6_qs;
logic [8:0] mp_region_cfg_6_base_6_wd;
logic mp_region_cfg_6_base_6_we;
@@ -405,6 +426,9 @@
logic mp_region_cfg_7_ecc_en_7_qs;
logic mp_region_cfg_7_ecc_en_7_wd;
logic mp_region_cfg_7_ecc_en_7_we;
+ logic mp_region_cfg_7_he_en_7_qs;
+ logic mp_region_cfg_7_he_en_7_wd;
+ logic mp_region_cfg_7_he_en_7_we;
logic [8:0] mp_region_cfg_7_base_7_qs;
logic [8:0] mp_region_cfg_7_base_7_wd;
logic mp_region_cfg_7_base_7_we;
@@ -426,6 +450,9 @@
logic default_region_ecc_en_qs;
logic default_region_ecc_en_wd;
logic default_region_ecc_en_we;
+ logic default_region_he_en_qs;
+ logic default_region_he_en_wd;
+ logic default_region_he_en_we;
logic bank0_info0_regwen_0_qs;
logic bank0_info0_regwen_0_wd;
logic bank0_info0_regwen_0_we;
@@ -456,6 +483,9 @@
logic bank0_info0_page_cfg_0_ecc_en_0_qs;
logic bank0_info0_page_cfg_0_ecc_en_0_wd;
logic bank0_info0_page_cfg_0_ecc_en_0_we;
+ logic bank0_info0_page_cfg_0_he_en_0_qs;
+ logic bank0_info0_page_cfg_0_he_en_0_wd;
+ logic bank0_info0_page_cfg_0_he_en_0_we;
logic bank0_info0_page_cfg_1_en_1_qs;
logic bank0_info0_page_cfg_1_en_1_wd;
logic bank0_info0_page_cfg_1_en_1_we;
@@ -474,6 +504,9 @@
logic bank0_info0_page_cfg_1_ecc_en_1_qs;
logic bank0_info0_page_cfg_1_ecc_en_1_wd;
logic bank0_info0_page_cfg_1_ecc_en_1_we;
+ logic bank0_info0_page_cfg_1_he_en_1_qs;
+ logic bank0_info0_page_cfg_1_he_en_1_wd;
+ logic bank0_info0_page_cfg_1_he_en_1_we;
logic bank0_info0_page_cfg_2_en_2_qs;
logic bank0_info0_page_cfg_2_en_2_wd;
logic bank0_info0_page_cfg_2_en_2_we;
@@ -492,6 +525,9 @@
logic bank0_info0_page_cfg_2_ecc_en_2_qs;
logic bank0_info0_page_cfg_2_ecc_en_2_wd;
logic bank0_info0_page_cfg_2_ecc_en_2_we;
+ logic bank0_info0_page_cfg_2_he_en_2_qs;
+ logic bank0_info0_page_cfg_2_he_en_2_wd;
+ logic bank0_info0_page_cfg_2_he_en_2_we;
logic bank0_info0_page_cfg_3_en_3_qs;
logic bank0_info0_page_cfg_3_en_3_wd;
logic bank0_info0_page_cfg_3_en_3_we;
@@ -510,6 +546,9 @@
logic bank0_info0_page_cfg_3_ecc_en_3_qs;
logic bank0_info0_page_cfg_3_ecc_en_3_wd;
logic bank0_info0_page_cfg_3_ecc_en_3_we;
+ logic bank0_info0_page_cfg_3_he_en_3_qs;
+ logic bank0_info0_page_cfg_3_he_en_3_wd;
+ logic bank0_info0_page_cfg_3_he_en_3_we;
logic bank0_info1_regwen_0_qs;
logic bank0_info1_regwen_0_wd;
logic bank0_info1_regwen_0_we;
@@ -540,6 +579,9 @@
logic bank0_info1_page_cfg_0_ecc_en_0_qs;
logic bank0_info1_page_cfg_0_ecc_en_0_wd;
logic bank0_info1_page_cfg_0_ecc_en_0_we;
+ logic bank0_info1_page_cfg_0_he_en_0_qs;
+ logic bank0_info1_page_cfg_0_he_en_0_wd;
+ logic bank0_info1_page_cfg_0_he_en_0_we;
logic bank0_info1_page_cfg_1_en_1_qs;
logic bank0_info1_page_cfg_1_en_1_wd;
logic bank0_info1_page_cfg_1_en_1_we;
@@ -558,6 +600,9 @@
logic bank0_info1_page_cfg_1_ecc_en_1_qs;
logic bank0_info1_page_cfg_1_ecc_en_1_wd;
logic bank0_info1_page_cfg_1_ecc_en_1_we;
+ logic bank0_info1_page_cfg_1_he_en_1_qs;
+ logic bank0_info1_page_cfg_1_he_en_1_wd;
+ logic bank0_info1_page_cfg_1_he_en_1_we;
logic bank0_info1_page_cfg_2_en_2_qs;
logic bank0_info1_page_cfg_2_en_2_wd;
logic bank0_info1_page_cfg_2_en_2_we;
@@ -576,6 +621,9 @@
logic bank0_info1_page_cfg_2_ecc_en_2_qs;
logic bank0_info1_page_cfg_2_ecc_en_2_wd;
logic bank0_info1_page_cfg_2_ecc_en_2_we;
+ logic bank0_info1_page_cfg_2_he_en_2_qs;
+ logic bank0_info1_page_cfg_2_he_en_2_wd;
+ logic bank0_info1_page_cfg_2_he_en_2_we;
logic bank0_info1_page_cfg_3_en_3_qs;
logic bank0_info1_page_cfg_3_en_3_wd;
logic bank0_info1_page_cfg_3_en_3_we;
@@ -594,6 +642,9 @@
logic bank0_info1_page_cfg_3_ecc_en_3_qs;
logic bank0_info1_page_cfg_3_ecc_en_3_wd;
logic bank0_info1_page_cfg_3_ecc_en_3_we;
+ logic bank0_info1_page_cfg_3_he_en_3_qs;
+ logic bank0_info1_page_cfg_3_he_en_3_wd;
+ logic bank0_info1_page_cfg_3_he_en_3_we;
logic bank1_info0_regwen_0_qs;
logic bank1_info0_regwen_0_wd;
logic bank1_info0_regwen_0_we;
@@ -624,6 +675,9 @@
logic bank1_info0_page_cfg_0_ecc_en_0_qs;
logic bank1_info0_page_cfg_0_ecc_en_0_wd;
logic bank1_info0_page_cfg_0_ecc_en_0_we;
+ logic bank1_info0_page_cfg_0_he_en_0_qs;
+ logic bank1_info0_page_cfg_0_he_en_0_wd;
+ logic bank1_info0_page_cfg_0_he_en_0_we;
logic bank1_info0_page_cfg_1_en_1_qs;
logic bank1_info0_page_cfg_1_en_1_wd;
logic bank1_info0_page_cfg_1_en_1_we;
@@ -642,6 +696,9 @@
logic bank1_info0_page_cfg_1_ecc_en_1_qs;
logic bank1_info0_page_cfg_1_ecc_en_1_wd;
logic bank1_info0_page_cfg_1_ecc_en_1_we;
+ logic bank1_info0_page_cfg_1_he_en_1_qs;
+ logic bank1_info0_page_cfg_1_he_en_1_wd;
+ logic bank1_info0_page_cfg_1_he_en_1_we;
logic bank1_info0_page_cfg_2_en_2_qs;
logic bank1_info0_page_cfg_2_en_2_wd;
logic bank1_info0_page_cfg_2_en_2_we;
@@ -660,6 +717,9 @@
logic bank1_info0_page_cfg_2_ecc_en_2_qs;
logic bank1_info0_page_cfg_2_ecc_en_2_wd;
logic bank1_info0_page_cfg_2_ecc_en_2_we;
+ logic bank1_info0_page_cfg_2_he_en_2_qs;
+ logic bank1_info0_page_cfg_2_he_en_2_wd;
+ logic bank1_info0_page_cfg_2_he_en_2_we;
logic bank1_info0_page_cfg_3_en_3_qs;
logic bank1_info0_page_cfg_3_en_3_wd;
logic bank1_info0_page_cfg_3_en_3_we;
@@ -678,6 +738,9 @@
logic bank1_info0_page_cfg_3_ecc_en_3_qs;
logic bank1_info0_page_cfg_3_ecc_en_3_wd;
logic bank1_info0_page_cfg_3_ecc_en_3_we;
+ logic bank1_info0_page_cfg_3_he_en_3_qs;
+ logic bank1_info0_page_cfg_3_he_en_3_wd;
+ logic bank1_info0_page_cfg_3_he_en_3_we;
logic bank1_info1_regwen_0_qs;
logic bank1_info1_regwen_0_wd;
logic bank1_info1_regwen_0_we;
@@ -708,6 +771,9 @@
logic bank1_info1_page_cfg_0_ecc_en_0_qs;
logic bank1_info1_page_cfg_0_ecc_en_0_wd;
logic bank1_info1_page_cfg_0_ecc_en_0_we;
+ logic bank1_info1_page_cfg_0_he_en_0_qs;
+ logic bank1_info1_page_cfg_0_he_en_0_wd;
+ logic bank1_info1_page_cfg_0_he_en_0_we;
logic bank1_info1_page_cfg_1_en_1_qs;
logic bank1_info1_page_cfg_1_en_1_wd;
logic bank1_info1_page_cfg_1_en_1_we;
@@ -726,6 +792,9 @@
logic bank1_info1_page_cfg_1_ecc_en_1_qs;
logic bank1_info1_page_cfg_1_ecc_en_1_wd;
logic bank1_info1_page_cfg_1_ecc_en_1_we;
+ logic bank1_info1_page_cfg_1_he_en_1_qs;
+ logic bank1_info1_page_cfg_1_he_en_1_wd;
+ logic bank1_info1_page_cfg_1_he_en_1_we;
logic bank1_info1_page_cfg_2_en_2_qs;
logic bank1_info1_page_cfg_2_en_2_wd;
logic bank1_info1_page_cfg_2_en_2_we;
@@ -744,6 +813,9 @@
logic bank1_info1_page_cfg_2_ecc_en_2_qs;
logic bank1_info1_page_cfg_2_ecc_en_2_wd;
logic bank1_info1_page_cfg_2_ecc_en_2_we;
+ logic bank1_info1_page_cfg_2_he_en_2_qs;
+ logic bank1_info1_page_cfg_2_he_en_2_wd;
+ logic bank1_info1_page_cfg_2_he_en_2_we;
logic bank1_info1_page_cfg_3_en_3_qs;
logic bank1_info1_page_cfg_3_en_3_wd;
logic bank1_info1_page_cfg_3_en_3_we;
@@ -762,6 +834,9 @@
logic bank1_info1_page_cfg_3_ecc_en_3_qs;
logic bank1_info1_page_cfg_3_ecc_en_3_wd;
logic bank1_info1_page_cfg_3_ecc_en_3_we;
+ logic bank1_info1_page_cfg_3_he_en_3_qs;
+ logic bank1_info1_page_cfg_3_he_en_3_wd;
+ logic bank1_info1_page_cfg_3_he_en_3_we;
logic bank_cfg_regwen_qs;
logic bank_cfg_regwen_wd;
logic bank_cfg_regwen_we;
@@ -1813,6 +1888,32 @@
);
+ // F[he_en_0]: 6:6
+ prim_subreg #(
+ .DW (1),
+ .SWACCESS("RW"),
+ .RESVAL (1'h0)
+ ) u_mp_region_cfg_0_he_en_0 (
+ .clk_i (clk_i ),
+ .rst_ni (rst_ni ),
+
+ // from register interface (qualified with register enable)
+ .we (mp_region_cfg_0_he_en_0_we & region_cfg_regwen_0_qs),
+ .wd (mp_region_cfg_0_he_en_0_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0 ),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.mp_region_cfg[0].he_en.q ),
+
+ // to register interface (read)
+ .qs (mp_region_cfg_0_he_en_0_qs)
+ );
+
+
// F[base_0]: 16:8
prim_subreg #(
.DW (9),
@@ -2024,6 +2125,32 @@
);
+ // F[he_en_1]: 6:6
+ prim_subreg #(
+ .DW (1),
+ .SWACCESS("RW"),
+ .RESVAL (1'h0)
+ ) u_mp_region_cfg_1_he_en_1 (
+ .clk_i (clk_i ),
+ .rst_ni (rst_ni ),
+
+ // from register interface (qualified with register enable)
+ .we (mp_region_cfg_1_he_en_1_we & region_cfg_regwen_1_qs),
+ .wd (mp_region_cfg_1_he_en_1_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0 ),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.mp_region_cfg[1].he_en.q ),
+
+ // to register interface (read)
+ .qs (mp_region_cfg_1_he_en_1_qs)
+ );
+
+
// F[base_1]: 16:8
prim_subreg #(
.DW (9),
@@ -2235,6 +2362,32 @@
);
+ // F[he_en_2]: 6:6
+ prim_subreg #(
+ .DW (1),
+ .SWACCESS("RW"),
+ .RESVAL (1'h0)
+ ) u_mp_region_cfg_2_he_en_2 (
+ .clk_i (clk_i ),
+ .rst_ni (rst_ni ),
+
+ // from register interface (qualified with register enable)
+ .we (mp_region_cfg_2_he_en_2_we & region_cfg_regwen_2_qs),
+ .wd (mp_region_cfg_2_he_en_2_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0 ),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.mp_region_cfg[2].he_en.q ),
+
+ // to register interface (read)
+ .qs (mp_region_cfg_2_he_en_2_qs)
+ );
+
+
// F[base_2]: 16:8
prim_subreg #(
.DW (9),
@@ -2446,6 +2599,32 @@
);
+ // F[he_en_3]: 6:6
+ prim_subreg #(
+ .DW (1),
+ .SWACCESS("RW"),
+ .RESVAL (1'h0)
+ ) u_mp_region_cfg_3_he_en_3 (
+ .clk_i (clk_i ),
+ .rst_ni (rst_ni ),
+
+ // from register interface (qualified with register enable)
+ .we (mp_region_cfg_3_he_en_3_we & region_cfg_regwen_3_qs),
+ .wd (mp_region_cfg_3_he_en_3_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0 ),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.mp_region_cfg[3].he_en.q ),
+
+ // to register interface (read)
+ .qs (mp_region_cfg_3_he_en_3_qs)
+ );
+
+
// F[base_3]: 16:8
prim_subreg #(
.DW (9),
@@ -2657,6 +2836,32 @@
);
+ // F[he_en_4]: 6:6
+ prim_subreg #(
+ .DW (1),
+ .SWACCESS("RW"),
+ .RESVAL (1'h0)
+ ) u_mp_region_cfg_4_he_en_4 (
+ .clk_i (clk_i ),
+ .rst_ni (rst_ni ),
+
+ // from register interface (qualified with register enable)
+ .we (mp_region_cfg_4_he_en_4_we & region_cfg_regwen_4_qs),
+ .wd (mp_region_cfg_4_he_en_4_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0 ),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.mp_region_cfg[4].he_en.q ),
+
+ // to register interface (read)
+ .qs (mp_region_cfg_4_he_en_4_qs)
+ );
+
+
// F[base_4]: 16:8
prim_subreg #(
.DW (9),
@@ -2868,6 +3073,32 @@
);
+ // F[he_en_5]: 6:6
+ prim_subreg #(
+ .DW (1),
+ .SWACCESS("RW"),
+ .RESVAL (1'h0)
+ ) u_mp_region_cfg_5_he_en_5 (
+ .clk_i (clk_i ),
+ .rst_ni (rst_ni ),
+
+ // from register interface (qualified with register enable)
+ .we (mp_region_cfg_5_he_en_5_we & region_cfg_regwen_5_qs),
+ .wd (mp_region_cfg_5_he_en_5_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0 ),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.mp_region_cfg[5].he_en.q ),
+
+ // to register interface (read)
+ .qs (mp_region_cfg_5_he_en_5_qs)
+ );
+
+
// F[base_5]: 16:8
prim_subreg #(
.DW (9),
@@ -3079,6 +3310,32 @@
);
+ // F[he_en_6]: 6:6
+ prim_subreg #(
+ .DW (1),
+ .SWACCESS("RW"),
+ .RESVAL (1'h0)
+ ) u_mp_region_cfg_6_he_en_6 (
+ .clk_i (clk_i ),
+ .rst_ni (rst_ni ),
+
+ // from register interface (qualified with register enable)
+ .we (mp_region_cfg_6_he_en_6_we & region_cfg_regwen_6_qs),
+ .wd (mp_region_cfg_6_he_en_6_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0 ),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.mp_region_cfg[6].he_en.q ),
+
+ // to register interface (read)
+ .qs (mp_region_cfg_6_he_en_6_qs)
+ );
+
+
// F[base_6]: 16:8
prim_subreg #(
.DW (9),
@@ -3290,6 +3547,32 @@
);
+ // F[he_en_7]: 6:6
+ prim_subreg #(
+ .DW (1),
+ .SWACCESS("RW"),
+ .RESVAL (1'h0)
+ ) u_mp_region_cfg_7_he_en_7 (
+ .clk_i (clk_i ),
+ .rst_ni (rst_ni ),
+
+ // from register interface (qualified with register enable)
+ .we (mp_region_cfg_7_he_en_7_we & region_cfg_regwen_7_qs),
+ .wd (mp_region_cfg_7_he_en_7_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0 ),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.mp_region_cfg[7].he_en.q ),
+
+ // to register interface (read)
+ .qs (mp_region_cfg_7_he_en_7_qs)
+ );
+
+
// F[base_7]: 16:8
prim_subreg #(
.DW (9),
@@ -3475,6 +3758,32 @@
);
+ // F[he_en]: 5:5
+ prim_subreg #(
+ .DW (1),
+ .SWACCESS("RW"),
+ .RESVAL (1'h0)
+ ) u_default_region_he_en (
+ .clk_i (clk_i ),
+ .rst_ni (rst_ni ),
+
+ // from register interface
+ .we (default_region_he_en_we),
+ .wd (default_region_he_en_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0 ),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.default_region.he_en.q ),
+
+ // to register interface (read)
+ .qs (default_region_he_en_qs)
+ );
+
+
// Subregister 0 of Multireg bank0_info0_regwen
// R[bank0_info0_regwen_0]: V(False)
@@ -3745,6 +4054,32 @@
);
+ // F[he_en_0]: 6:6
+ prim_subreg #(
+ .DW (1),
+ .SWACCESS("RW"),
+ .RESVAL (1'h0)
+ ) u_bank0_info0_page_cfg_0_he_en_0 (
+ .clk_i (clk_i ),
+ .rst_ni (rst_ni ),
+
+ // from register interface (qualified with register enable)
+ .we (bank0_info0_page_cfg_0_he_en_0_we & bank0_info0_regwen_0_qs),
+ .wd (bank0_info0_page_cfg_0_he_en_0_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0 ),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.bank0_info0_page_cfg[0].he_en.q ),
+
+ // to register interface (read)
+ .qs (bank0_info0_page_cfg_0_he_en_0_qs)
+ );
+
+
// Subregister 1 of Multireg bank0_info0_page_cfg
// R[bank0_info0_page_cfg_1]: V(False)
@@ -3904,6 +4239,32 @@
);
+ // F[he_en_1]: 6:6
+ prim_subreg #(
+ .DW (1),
+ .SWACCESS("RW"),
+ .RESVAL (1'h0)
+ ) u_bank0_info0_page_cfg_1_he_en_1 (
+ .clk_i (clk_i ),
+ .rst_ni (rst_ni ),
+
+ // from register interface (qualified with register enable)
+ .we (bank0_info0_page_cfg_1_he_en_1_we & bank0_info0_regwen_1_qs),
+ .wd (bank0_info0_page_cfg_1_he_en_1_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0 ),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.bank0_info0_page_cfg[1].he_en.q ),
+
+ // to register interface (read)
+ .qs (bank0_info0_page_cfg_1_he_en_1_qs)
+ );
+
+
// Subregister 2 of Multireg bank0_info0_page_cfg
// R[bank0_info0_page_cfg_2]: V(False)
@@ -4063,6 +4424,32 @@
);
+ // F[he_en_2]: 6:6
+ prim_subreg #(
+ .DW (1),
+ .SWACCESS("RW"),
+ .RESVAL (1'h0)
+ ) u_bank0_info0_page_cfg_2_he_en_2 (
+ .clk_i (clk_i ),
+ .rst_ni (rst_ni ),
+
+ // from register interface (qualified with register enable)
+ .we (bank0_info0_page_cfg_2_he_en_2_we & bank0_info0_regwen_2_qs),
+ .wd (bank0_info0_page_cfg_2_he_en_2_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0 ),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.bank0_info0_page_cfg[2].he_en.q ),
+
+ // to register interface (read)
+ .qs (bank0_info0_page_cfg_2_he_en_2_qs)
+ );
+
+
// Subregister 3 of Multireg bank0_info0_page_cfg
// R[bank0_info0_page_cfg_3]: V(False)
@@ -4222,6 +4609,32 @@
);
+ // F[he_en_3]: 6:6
+ prim_subreg #(
+ .DW (1),
+ .SWACCESS("RW"),
+ .RESVAL (1'h0)
+ ) u_bank0_info0_page_cfg_3_he_en_3 (
+ .clk_i (clk_i ),
+ .rst_ni (rst_ni ),
+
+ // from register interface (qualified with register enable)
+ .we (bank0_info0_page_cfg_3_he_en_3_we & bank0_info0_regwen_3_qs),
+ .wd (bank0_info0_page_cfg_3_he_en_3_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0 ),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.bank0_info0_page_cfg[3].he_en.q ),
+
+ // to register interface (read)
+ .qs (bank0_info0_page_cfg_3_he_en_3_qs)
+ );
+
+
// Subregister 0 of Multireg bank0_info1_regwen
@@ -4493,6 +4906,32 @@
);
+ // F[he_en_0]: 6:6
+ prim_subreg #(
+ .DW (1),
+ .SWACCESS("RW"),
+ .RESVAL (1'h0)
+ ) u_bank0_info1_page_cfg_0_he_en_0 (
+ .clk_i (clk_i ),
+ .rst_ni (rst_ni ),
+
+ // from register interface (qualified with register enable)
+ .we (bank0_info1_page_cfg_0_he_en_0_we & bank0_info1_regwen_0_qs),
+ .wd (bank0_info1_page_cfg_0_he_en_0_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0 ),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.bank0_info1_page_cfg[0].he_en.q ),
+
+ // to register interface (read)
+ .qs (bank0_info1_page_cfg_0_he_en_0_qs)
+ );
+
+
// Subregister 1 of Multireg bank0_info1_page_cfg
// R[bank0_info1_page_cfg_1]: V(False)
@@ -4652,6 +5091,32 @@
);
+ // F[he_en_1]: 6:6
+ prim_subreg #(
+ .DW (1),
+ .SWACCESS("RW"),
+ .RESVAL (1'h0)
+ ) u_bank0_info1_page_cfg_1_he_en_1 (
+ .clk_i (clk_i ),
+ .rst_ni (rst_ni ),
+
+ // from register interface (qualified with register enable)
+ .we (bank0_info1_page_cfg_1_he_en_1_we & bank0_info1_regwen_1_qs),
+ .wd (bank0_info1_page_cfg_1_he_en_1_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0 ),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.bank0_info1_page_cfg[1].he_en.q ),
+
+ // to register interface (read)
+ .qs (bank0_info1_page_cfg_1_he_en_1_qs)
+ );
+
+
// Subregister 2 of Multireg bank0_info1_page_cfg
// R[bank0_info1_page_cfg_2]: V(False)
@@ -4811,6 +5276,32 @@
);
+ // F[he_en_2]: 6:6
+ prim_subreg #(
+ .DW (1),
+ .SWACCESS("RW"),
+ .RESVAL (1'h0)
+ ) u_bank0_info1_page_cfg_2_he_en_2 (
+ .clk_i (clk_i ),
+ .rst_ni (rst_ni ),
+
+ // from register interface (qualified with register enable)
+ .we (bank0_info1_page_cfg_2_he_en_2_we & bank0_info1_regwen_2_qs),
+ .wd (bank0_info1_page_cfg_2_he_en_2_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0 ),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.bank0_info1_page_cfg[2].he_en.q ),
+
+ // to register interface (read)
+ .qs (bank0_info1_page_cfg_2_he_en_2_qs)
+ );
+
+
// Subregister 3 of Multireg bank0_info1_page_cfg
// R[bank0_info1_page_cfg_3]: V(False)
@@ -4970,6 +5461,32 @@
);
+ // F[he_en_3]: 6:6
+ prim_subreg #(
+ .DW (1),
+ .SWACCESS("RW"),
+ .RESVAL (1'h0)
+ ) u_bank0_info1_page_cfg_3_he_en_3 (
+ .clk_i (clk_i ),
+ .rst_ni (rst_ni ),
+
+ // from register interface (qualified with register enable)
+ .we (bank0_info1_page_cfg_3_he_en_3_we & bank0_info1_regwen_3_qs),
+ .wd (bank0_info1_page_cfg_3_he_en_3_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0 ),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.bank0_info1_page_cfg[3].he_en.q ),
+
+ // to register interface (read)
+ .qs (bank0_info1_page_cfg_3_he_en_3_qs)
+ );
+
+
// Subregister 0 of Multireg bank1_info0_regwen
@@ -5241,6 +5758,32 @@
);
+ // F[he_en_0]: 6:6
+ prim_subreg #(
+ .DW (1),
+ .SWACCESS("RW"),
+ .RESVAL (1'h0)
+ ) u_bank1_info0_page_cfg_0_he_en_0 (
+ .clk_i (clk_i ),
+ .rst_ni (rst_ni ),
+
+ // from register interface (qualified with register enable)
+ .we (bank1_info0_page_cfg_0_he_en_0_we & bank1_info0_regwen_0_qs),
+ .wd (bank1_info0_page_cfg_0_he_en_0_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0 ),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.bank1_info0_page_cfg[0].he_en.q ),
+
+ // to register interface (read)
+ .qs (bank1_info0_page_cfg_0_he_en_0_qs)
+ );
+
+
// Subregister 1 of Multireg bank1_info0_page_cfg
// R[bank1_info0_page_cfg_1]: V(False)
@@ -5400,6 +5943,32 @@
);
+ // F[he_en_1]: 6:6
+ prim_subreg #(
+ .DW (1),
+ .SWACCESS("RW"),
+ .RESVAL (1'h0)
+ ) u_bank1_info0_page_cfg_1_he_en_1 (
+ .clk_i (clk_i ),
+ .rst_ni (rst_ni ),
+
+ // from register interface (qualified with register enable)
+ .we (bank1_info0_page_cfg_1_he_en_1_we & bank1_info0_regwen_1_qs),
+ .wd (bank1_info0_page_cfg_1_he_en_1_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0 ),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.bank1_info0_page_cfg[1].he_en.q ),
+
+ // to register interface (read)
+ .qs (bank1_info0_page_cfg_1_he_en_1_qs)
+ );
+
+
// Subregister 2 of Multireg bank1_info0_page_cfg
// R[bank1_info0_page_cfg_2]: V(False)
@@ -5559,6 +6128,32 @@
);
+ // F[he_en_2]: 6:6
+ prim_subreg #(
+ .DW (1),
+ .SWACCESS("RW"),
+ .RESVAL (1'h0)
+ ) u_bank1_info0_page_cfg_2_he_en_2 (
+ .clk_i (clk_i ),
+ .rst_ni (rst_ni ),
+
+ // from register interface (qualified with register enable)
+ .we (bank1_info0_page_cfg_2_he_en_2_we & bank1_info0_regwen_2_qs),
+ .wd (bank1_info0_page_cfg_2_he_en_2_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0 ),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.bank1_info0_page_cfg[2].he_en.q ),
+
+ // to register interface (read)
+ .qs (bank1_info0_page_cfg_2_he_en_2_qs)
+ );
+
+
// Subregister 3 of Multireg bank1_info0_page_cfg
// R[bank1_info0_page_cfg_3]: V(False)
@@ -5718,6 +6313,32 @@
);
+ // F[he_en_3]: 6:6
+ prim_subreg #(
+ .DW (1),
+ .SWACCESS("RW"),
+ .RESVAL (1'h0)
+ ) u_bank1_info0_page_cfg_3_he_en_3 (
+ .clk_i (clk_i ),
+ .rst_ni (rst_ni ),
+
+ // from register interface (qualified with register enable)
+ .we (bank1_info0_page_cfg_3_he_en_3_we & bank1_info0_regwen_3_qs),
+ .wd (bank1_info0_page_cfg_3_he_en_3_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0 ),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.bank1_info0_page_cfg[3].he_en.q ),
+
+ // to register interface (read)
+ .qs (bank1_info0_page_cfg_3_he_en_3_qs)
+ );
+
+
// Subregister 0 of Multireg bank1_info1_regwen
@@ -5989,6 +6610,32 @@
);
+ // F[he_en_0]: 6:6
+ prim_subreg #(
+ .DW (1),
+ .SWACCESS("RW"),
+ .RESVAL (1'h0)
+ ) u_bank1_info1_page_cfg_0_he_en_0 (
+ .clk_i (clk_i ),
+ .rst_ni (rst_ni ),
+
+ // from register interface (qualified with register enable)
+ .we (bank1_info1_page_cfg_0_he_en_0_we & bank1_info1_regwen_0_qs),
+ .wd (bank1_info1_page_cfg_0_he_en_0_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0 ),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.bank1_info1_page_cfg[0].he_en.q ),
+
+ // to register interface (read)
+ .qs (bank1_info1_page_cfg_0_he_en_0_qs)
+ );
+
+
// Subregister 1 of Multireg bank1_info1_page_cfg
// R[bank1_info1_page_cfg_1]: V(False)
@@ -6148,6 +6795,32 @@
);
+ // F[he_en_1]: 6:6
+ prim_subreg #(
+ .DW (1),
+ .SWACCESS("RW"),
+ .RESVAL (1'h0)
+ ) u_bank1_info1_page_cfg_1_he_en_1 (
+ .clk_i (clk_i ),
+ .rst_ni (rst_ni ),
+
+ // from register interface (qualified with register enable)
+ .we (bank1_info1_page_cfg_1_he_en_1_we & bank1_info1_regwen_1_qs),
+ .wd (bank1_info1_page_cfg_1_he_en_1_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0 ),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.bank1_info1_page_cfg[1].he_en.q ),
+
+ // to register interface (read)
+ .qs (bank1_info1_page_cfg_1_he_en_1_qs)
+ );
+
+
// Subregister 2 of Multireg bank1_info1_page_cfg
// R[bank1_info1_page_cfg_2]: V(False)
@@ -6307,6 +6980,32 @@
);
+ // F[he_en_2]: 6:6
+ prim_subreg #(
+ .DW (1),
+ .SWACCESS("RW"),
+ .RESVAL (1'h0)
+ ) u_bank1_info1_page_cfg_2_he_en_2 (
+ .clk_i (clk_i ),
+ .rst_ni (rst_ni ),
+
+ // from register interface (qualified with register enable)
+ .we (bank1_info1_page_cfg_2_he_en_2_we & bank1_info1_regwen_2_qs),
+ .wd (bank1_info1_page_cfg_2_he_en_2_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0 ),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.bank1_info1_page_cfg[2].he_en.q ),
+
+ // to register interface (read)
+ .qs (bank1_info1_page_cfg_2_he_en_2_qs)
+ );
+
+
// Subregister 3 of Multireg bank1_info1_page_cfg
// R[bank1_info1_page_cfg_3]: V(False)
@@ -6466,6 +7165,32 @@
);
+ // F[he_en_3]: 6:6
+ prim_subreg #(
+ .DW (1),
+ .SWACCESS("RW"),
+ .RESVAL (1'h0)
+ ) u_bank1_info1_page_cfg_3_he_en_3 (
+ .clk_i (clk_i ),
+ .rst_ni (rst_ni ),
+
+ // from register interface (qualified with register enable)
+ .we (bank1_info1_page_cfg_3_he_en_3_we & bank1_info1_regwen_3_qs),
+ .wd (bank1_info1_page_cfg_3_he_en_3_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0 ),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.bank1_info1_page_cfg[3].he_en.q ),
+
+ // to register interface (read)
+ .qs (bank1_info1_page_cfg_3_he_en_3_qs)
+ );
+
+
// R[bank_cfg_regwen]: V(False)
@@ -7204,6 +7929,9 @@
assign mp_region_cfg_0_ecc_en_0_we = addr_hit[14] & reg_we & ~wr_err;
assign mp_region_cfg_0_ecc_en_0_wd = reg_wdata[5];
+ assign mp_region_cfg_0_he_en_0_we = addr_hit[14] & reg_we & ~wr_err;
+ assign mp_region_cfg_0_he_en_0_wd = reg_wdata[6];
+
assign mp_region_cfg_0_base_0_we = addr_hit[14] & reg_we & ~wr_err;
assign mp_region_cfg_0_base_0_wd = reg_wdata[16:8];
@@ -7228,6 +7956,9 @@
assign mp_region_cfg_1_ecc_en_1_we = addr_hit[15] & reg_we & ~wr_err;
assign mp_region_cfg_1_ecc_en_1_wd = reg_wdata[5];
+ assign mp_region_cfg_1_he_en_1_we = addr_hit[15] & reg_we & ~wr_err;
+ assign mp_region_cfg_1_he_en_1_wd = reg_wdata[6];
+
assign mp_region_cfg_1_base_1_we = addr_hit[15] & reg_we & ~wr_err;
assign mp_region_cfg_1_base_1_wd = reg_wdata[16:8];
@@ -7252,6 +7983,9 @@
assign mp_region_cfg_2_ecc_en_2_we = addr_hit[16] & reg_we & ~wr_err;
assign mp_region_cfg_2_ecc_en_2_wd = reg_wdata[5];
+ assign mp_region_cfg_2_he_en_2_we = addr_hit[16] & reg_we & ~wr_err;
+ assign mp_region_cfg_2_he_en_2_wd = reg_wdata[6];
+
assign mp_region_cfg_2_base_2_we = addr_hit[16] & reg_we & ~wr_err;
assign mp_region_cfg_2_base_2_wd = reg_wdata[16:8];
@@ -7276,6 +8010,9 @@
assign mp_region_cfg_3_ecc_en_3_we = addr_hit[17] & reg_we & ~wr_err;
assign mp_region_cfg_3_ecc_en_3_wd = reg_wdata[5];
+ assign mp_region_cfg_3_he_en_3_we = addr_hit[17] & reg_we & ~wr_err;
+ assign mp_region_cfg_3_he_en_3_wd = reg_wdata[6];
+
assign mp_region_cfg_3_base_3_we = addr_hit[17] & reg_we & ~wr_err;
assign mp_region_cfg_3_base_3_wd = reg_wdata[16:8];
@@ -7300,6 +8037,9 @@
assign mp_region_cfg_4_ecc_en_4_we = addr_hit[18] & reg_we & ~wr_err;
assign mp_region_cfg_4_ecc_en_4_wd = reg_wdata[5];
+ assign mp_region_cfg_4_he_en_4_we = addr_hit[18] & reg_we & ~wr_err;
+ assign mp_region_cfg_4_he_en_4_wd = reg_wdata[6];
+
assign mp_region_cfg_4_base_4_we = addr_hit[18] & reg_we & ~wr_err;
assign mp_region_cfg_4_base_4_wd = reg_wdata[16:8];
@@ -7324,6 +8064,9 @@
assign mp_region_cfg_5_ecc_en_5_we = addr_hit[19] & reg_we & ~wr_err;
assign mp_region_cfg_5_ecc_en_5_wd = reg_wdata[5];
+ assign mp_region_cfg_5_he_en_5_we = addr_hit[19] & reg_we & ~wr_err;
+ assign mp_region_cfg_5_he_en_5_wd = reg_wdata[6];
+
assign mp_region_cfg_5_base_5_we = addr_hit[19] & reg_we & ~wr_err;
assign mp_region_cfg_5_base_5_wd = reg_wdata[16:8];
@@ -7348,6 +8091,9 @@
assign mp_region_cfg_6_ecc_en_6_we = addr_hit[20] & reg_we & ~wr_err;
assign mp_region_cfg_6_ecc_en_6_wd = reg_wdata[5];
+ assign mp_region_cfg_6_he_en_6_we = addr_hit[20] & reg_we & ~wr_err;
+ assign mp_region_cfg_6_he_en_6_wd = reg_wdata[6];
+
assign mp_region_cfg_6_base_6_we = addr_hit[20] & reg_we & ~wr_err;
assign mp_region_cfg_6_base_6_wd = reg_wdata[16:8];
@@ -7372,6 +8118,9 @@
assign mp_region_cfg_7_ecc_en_7_we = addr_hit[21] & reg_we & ~wr_err;
assign mp_region_cfg_7_ecc_en_7_wd = reg_wdata[5];
+ assign mp_region_cfg_7_he_en_7_we = addr_hit[21] & reg_we & ~wr_err;
+ assign mp_region_cfg_7_he_en_7_wd = reg_wdata[6];
+
assign mp_region_cfg_7_base_7_we = addr_hit[21] & reg_we & ~wr_err;
assign mp_region_cfg_7_base_7_wd = reg_wdata[16:8];
@@ -7393,6 +8142,9 @@
assign default_region_ecc_en_we = addr_hit[22] & reg_we & ~wr_err;
assign default_region_ecc_en_wd = reg_wdata[4];
+ assign default_region_he_en_we = addr_hit[22] & reg_we & ~wr_err;
+ assign default_region_he_en_wd = reg_wdata[5];
+
assign bank0_info0_regwen_0_we = addr_hit[23] & reg_we & ~wr_err;
assign bank0_info0_regwen_0_wd = reg_wdata[0];
@@ -7423,6 +8175,9 @@
assign bank0_info0_page_cfg_0_ecc_en_0_we = addr_hit[27] & reg_we & ~wr_err;
assign bank0_info0_page_cfg_0_ecc_en_0_wd = reg_wdata[5];
+ assign bank0_info0_page_cfg_0_he_en_0_we = addr_hit[27] & reg_we & ~wr_err;
+ assign bank0_info0_page_cfg_0_he_en_0_wd = reg_wdata[6];
+
assign bank0_info0_page_cfg_1_en_1_we = addr_hit[28] & reg_we & ~wr_err;
assign bank0_info0_page_cfg_1_en_1_wd = reg_wdata[0];
@@ -7441,6 +8196,9 @@
assign bank0_info0_page_cfg_1_ecc_en_1_we = addr_hit[28] & reg_we & ~wr_err;
assign bank0_info0_page_cfg_1_ecc_en_1_wd = reg_wdata[5];
+ assign bank0_info0_page_cfg_1_he_en_1_we = addr_hit[28] & reg_we & ~wr_err;
+ assign bank0_info0_page_cfg_1_he_en_1_wd = reg_wdata[6];
+
assign bank0_info0_page_cfg_2_en_2_we = addr_hit[29] & reg_we & ~wr_err;
assign bank0_info0_page_cfg_2_en_2_wd = reg_wdata[0];
@@ -7459,6 +8217,9 @@
assign bank0_info0_page_cfg_2_ecc_en_2_we = addr_hit[29] & reg_we & ~wr_err;
assign bank0_info0_page_cfg_2_ecc_en_2_wd = reg_wdata[5];
+ assign bank0_info0_page_cfg_2_he_en_2_we = addr_hit[29] & reg_we & ~wr_err;
+ assign bank0_info0_page_cfg_2_he_en_2_wd = reg_wdata[6];
+
assign bank0_info0_page_cfg_3_en_3_we = addr_hit[30] & reg_we & ~wr_err;
assign bank0_info0_page_cfg_3_en_3_wd = reg_wdata[0];
@@ -7477,6 +8238,9 @@
assign bank0_info0_page_cfg_3_ecc_en_3_we = addr_hit[30] & reg_we & ~wr_err;
assign bank0_info0_page_cfg_3_ecc_en_3_wd = reg_wdata[5];
+ assign bank0_info0_page_cfg_3_he_en_3_we = addr_hit[30] & reg_we & ~wr_err;
+ assign bank0_info0_page_cfg_3_he_en_3_wd = reg_wdata[6];
+
assign bank0_info1_regwen_0_we = addr_hit[31] & reg_we & ~wr_err;
assign bank0_info1_regwen_0_wd = reg_wdata[0];
@@ -7507,6 +8271,9 @@
assign bank0_info1_page_cfg_0_ecc_en_0_we = addr_hit[35] & reg_we & ~wr_err;
assign bank0_info1_page_cfg_0_ecc_en_0_wd = reg_wdata[5];
+ assign bank0_info1_page_cfg_0_he_en_0_we = addr_hit[35] & reg_we & ~wr_err;
+ assign bank0_info1_page_cfg_0_he_en_0_wd = reg_wdata[6];
+
assign bank0_info1_page_cfg_1_en_1_we = addr_hit[36] & reg_we & ~wr_err;
assign bank0_info1_page_cfg_1_en_1_wd = reg_wdata[0];
@@ -7525,6 +8292,9 @@
assign bank0_info1_page_cfg_1_ecc_en_1_we = addr_hit[36] & reg_we & ~wr_err;
assign bank0_info1_page_cfg_1_ecc_en_1_wd = reg_wdata[5];
+ assign bank0_info1_page_cfg_1_he_en_1_we = addr_hit[36] & reg_we & ~wr_err;
+ assign bank0_info1_page_cfg_1_he_en_1_wd = reg_wdata[6];
+
assign bank0_info1_page_cfg_2_en_2_we = addr_hit[37] & reg_we & ~wr_err;
assign bank0_info1_page_cfg_2_en_2_wd = reg_wdata[0];
@@ -7543,6 +8313,9 @@
assign bank0_info1_page_cfg_2_ecc_en_2_we = addr_hit[37] & reg_we & ~wr_err;
assign bank0_info1_page_cfg_2_ecc_en_2_wd = reg_wdata[5];
+ assign bank0_info1_page_cfg_2_he_en_2_we = addr_hit[37] & reg_we & ~wr_err;
+ assign bank0_info1_page_cfg_2_he_en_2_wd = reg_wdata[6];
+
assign bank0_info1_page_cfg_3_en_3_we = addr_hit[38] & reg_we & ~wr_err;
assign bank0_info1_page_cfg_3_en_3_wd = reg_wdata[0];
@@ -7561,6 +8334,9 @@
assign bank0_info1_page_cfg_3_ecc_en_3_we = addr_hit[38] & reg_we & ~wr_err;
assign bank0_info1_page_cfg_3_ecc_en_3_wd = reg_wdata[5];
+ assign bank0_info1_page_cfg_3_he_en_3_we = addr_hit[38] & reg_we & ~wr_err;
+ assign bank0_info1_page_cfg_3_he_en_3_wd = reg_wdata[6];
+
assign bank1_info0_regwen_0_we = addr_hit[39] & reg_we & ~wr_err;
assign bank1_info0_regwen_0_wd = reg_wdata[0];
@@ -7591,6 +8367,9 @@
assign bank1_info0_page_cfg_0_ecc_en_0_we = addr_hit[43] & reg_we & ~wr_err;
assign bank1_info0_page_cfg_0_ecc_en_0_wd = reg_wdata[5];
+ assign bank1_info0_page_cfg_0_he_en_0_we = addr_hit[43] & reg_we & ~wr_err;
+ assign bank1_info0_page_cfg_0_he_en_0_wd = reg_wdata[6];
+
assign bank1_info0_page_cfg_1_en_1_we = addr_hit[44] & reg_we & ~wr_err;
assign bank1_info0_page_cfg_1_en_1_wd = reg_wdata[0];
@@ -7609,6 +8388,9 @@
assign bank1_info0_page_cfg_1_ecc_en_1_we = addr_hit[44] & reg_we & ~wr_err;
assign bank1_info0_page_cfg_1_ecc_en_1_wd = reg_wdata[5];
+ assign bank1_info0_page_cfg_1_he_en_1_we = addr_hit[44] & reg_we & ~wr_err;
+ assign bank1_info0_page_cfg_1_he_en_1_wd = reg_wdata[6];
+
assign bank1_info0_page_cfg_2_en_2_we = addr_hit[45] & reg_we & ~wr_err;
assign bank1_info0_page_cfg_2_en_2_wd = reg_wdata[0];
@@ -7627,6 +8409,9 @@
assign bank1_info0_page_cfg_2_ecc_en_2_we = addr_hit[45] & reg_we & ~wr_err;
assign bank1_info0_page_cfg_2_ecc_en_2_wd = reg_wdata[5];
+ assign bank1_info0_page_cfg_2_he_en_2_we = addr_hit[45] & reg_we & ~wr_err;
+ assign bank1_info0_page_cfg_2_he_en_2_wd = reg_wdata[6];
+
assign bank1_info0_page_cfg_3_en_3_we = addr_hit[46] & reg_we & ~wr_err;
assign bank1_info0_page_cfg_3_en_3_wd = reg_wdata[0];
@@ -7645,6 +8430,9 @@
assign bank1_info0_page_cfg_3_ecc_en_3_we = addr_hit[46] & reg_we & ~wr_err;
assign bank1_info0_page_cfg_3_ecc_en_3_wd = reg_wdata[5];
+ assign bank1_info0_page_cfg_3_he_en_3_we = addr_hit[46] & reg_we & ~wr_err;
+ assign bank1_info0_page_cfg_3_he_en_3_wd = reg_wdata[6];
+
assign bank1_info1_regwen_0_we = addr_hit[47] & reg_we & ~wr_err;
assign bank1_info1_regwen_0_wd = reg_wdata[0];
@@ -7675,6 +8463,9 @@
assign bank1_info1_page_cfg_0_ecc_en_0_we = addr_hit[51] & reg_we & ~wr_err;
assign bank1_info1_page_cfg_0_ecc_en_0_wd = reg_wdata[5];
+ assign bank1_info1_page_cfg_0_he_en_0_we = addr_hit[51] & reg_we & ~wr_err;
+ assign bank1_info1_page_cfg_0_he_en_0_wd = reg_wdata[6];
+
assign bank1_info1_page_cfg_1_en_1_we = addr_hit[52] & reg_we & ~wr_err;
assign bank1_info1_page_cfg_1_en_1_wd = reg_wdata[0];
@@ -7693,6 +8484,9 @@
assign bank1_info1_page_cfg_1_ecc_en_1_we = addr_hit[52] & reg_we & ~wr_err;
assign bank1_info1_page_cfg_1_ecc_en_1_wd = reg_wdata[5];
+ assign bank1_info1_page_cfg_1_he_en_1_we = addr_hit[52] & reg_we & ~wr_err;
+ assign bank1_info1_page_cfg_1_he_en_1_wd = reg_wdata[6];
+
assign bank1_info1_page_cfg_2_en_2_we = addr_hit[53] & reg_we & ~wr_err;
assign bank1_info1_page_cfg_2_en_2_wd = reg_wdata[0];
@@ -7711,6 +8505,9 @@
assign bank1_info1_page_cfg_2_ecc_en_2_we = addr_hit[53] & reg_we & ~wr_err;
assign bank1_info1_page_cfg_2_ecc_en_2_wd = reg_wdata[5];
+ assign bank1_info1_page_cfg_2_he_en_2_we = addr_hit[53] & reg_we & ~wr_err;
+ assign bank1_info1_page_cfg_2_he_en_2_wd = reg_wdata[6];
+
assign bank1_info1_page_cfg_3_en_3_we = addr_hit[54] & reg_we & ~wr_err;
assign bank1_info1_page_cfg_3_en_3_wd = reg_wdata[0];
@@ -7729,6 +8526,9 @@
assign bank1_info1_page_cfg_3_ecc_en_3_we = addr_hit[54] & reg_we & ~wr_err;
assign bank1_info1_page_cfg_3_ecc_en_3_wd = reg_wdata[5];
+ assign bank1_info1_page_cfg_3_he_en_3_we = addr_hit[54] & reg_we & ~wr_err;
+ assign bank1_info1_page_cfg_3_he_en_3_wd = reg_wdata[6];
+
assign bank_cfg_regwen_we = addr_hit[55] & reg_we & ~wr_err;
assign bank_cfg_regwen_wd = reg_wdata[0];
@@ -7853,6 +8653,7 @@
reg_rdata_next[3] = mp_region_cfg_0_erase_en_0_qs;
reg_rdata_next[4] = mp_region_cfg_0_scramble_en_0_qs;
reg_rdata_next[5] = mp_region_cfg_0_ecc_en_0_qs;
+ reg_rdata_next[6] = mp_region_cfg_0_he_en_0_qs;
reg_rdata_next[16:8] = mp_region_cfg_0_base_0_qs;
reg_rdata_next[29:20] = mp_region_cfg_0_size_0_qs;
end
@@ -7864,6 +8665,7 @@
reg_rdata_next[3] = mp_region_cfg_1_erase_en_1_qs;
reg_rdata_next[4] = mp_region_cfg_1_scramble_en_1_qs;
reg_rdata_next[5] = mp_region_cfg_1_ecc_en_1_qs;
+ reg_rdata_next[6] = mp_region_cfg_1_he_en_1_qs;
reg_rdata_next[16:8] = mp_region_cfg_1_base_1_qs;
reg_rdata_next[29:20] = mp_region_cfg_1_size_1_qs;
end
@@ -7875,6 +8677,7 @@
reg_rdata_next[3] = mp_region_cfg_2_erase_en_2_qs;
reg_rdata_next[4] = mp_region_cfg_2_scramble_en_2_qs;
reg_rdata_next[5] = mp_region_cfg_2_ecc_en_2_qs;
+ reg_rdata_next[6] = mp_region_cfg_2_he_en_2_qs;
reg_rdata_next[16:8] = mp_region_cfg_2_base_2_qs;
reg_rdata_next[29:20] = mp_region_cfg_2_size_2_qs;
end
@@ -7886,6 +8689,7 @@
reg_rdata_next[3] = mp_region_cfg_3_erase_en_3_qs;
reg_rdata_next[4] = mp_region_cfg_3_scramble_en_3_qs;
reg_rdata_next[5] = mp_region_cfg_3_ecc_en_3_qs;
+ reg_rdata_next[6] = mp_region_cfg_3_he_en_3_qs;
reg_rdata_next[16:8] = mp_region_cfg_3_base_3_qs;
reg_rdata_next[29:20] = mp_region_cfg_3_size_3_qs;
end
@@ -7897,6 +8701,7 @@
reg_rdata_next[3] = mp_region_cfg_4_erase_en_4_qs;
reg_rdata_next[4] = mp_region_cfg_4_scramble_en_4_qs;
reg_rdata_next[5] = mp_region_cfg_4_ecc_en_4_qs;
+ reg_rdata_next[6] = mp_region_cfg_4_he_en_4_qs;
reg_rdata_next[16:8] = mp_region_cfg_4_base_4_qs;
reg_rdata_next[29:20] = mp_region_cfg_4_size_4_qs;
end
@@ -7908,6 +8713,7 @@
reg_rdata_next[3] = mp_region_cfg_5_erase_en_5_qs;
reg_rdata_next[4] = mp_region_cfg_5_scramble_en_5_qs;
reg_rdata_next[5] = mp_region_cfg_5_ecc_en_5_qs;
+ reg_rdata_next[6] = mp_region_cfg_5_he_en_5_qs;
reg_rdata_next[16:8] = mp_region_cfg_5_base_5_qs;
reg_rdata_next[29:20] = mp_region_cfg_5_size_5_qs;
end
@@ -7919,6 +8725,7 @@
reg_rdata_next[3] = mp_region_cfg_6_erase_en_6_qs;
reg_rdata_next[4] = mp_region_cfg_6_scramble_en_6_qs;
reg_rdata_next[5] = mp_region_cfg_6_ecc_en_6_qs;
+ reg_rdata_next[6] = mp_region_cfg_6_he_en_6_qs;
reg_rdata_next[16:8] = mp_region_cfg_6_base_6_qs;
reg_rdata_next[29:20] = mp_region_cfg_6_size_6_qs;
end
@@ -7930,6 +8737,7 @@
reg_rdata_next[3] = mp_region_cfg_7_erase_en_7_qs;
reg_rdata_next[4] = mp_region_cfg_7_scramble_en_7_qs;
reg_rdata_next[5] = mp_region_cfg_7_ecc_en_7_qs;
+ reg_rdata_next[6] = mp_region_cfg_7_he_en_7_qs;
reg_rdata_next[16:8] = mp_region_cfg_7_base_7_qs;
reg_rdata_next[29:20] = mp_region_cfg_7_size_7_qs;
end
@@ -7940,6 +8748,7 @@
reg_rdata_next[2] = default_region_erase_en_qs;
reg_rdata_next[3] = default_region_scramble_en_qs;
reg_rdata_next[4] = default_region_ecc_en_qs;
+ reg_rdata_next[5] = default_region_he_en_qs;
end
addr_hit[23]: begin
@@ -7965,6 +8774,7 @@
reg_rdata_next[3] = bank0_info0_page_cfg_0_erase_en_0_qs;
reg_rdata_next[4] = bank0_info0_page_cfg_0_scramble_en_0_qs;
reg_rdata_next[5] = bank0_info0_page_cfg_0_ecc_en_0_qs;
+ reg_rdata_next[6] = bank0_info0_page_cfg_0_he_en_0_qs;
end
addr_hit[28]: begin
@@ -7974,6 +8784,7 @@
reg_rdata_next[3] = bank0_info0_page_cfg_1_erase_en_1_qs;
reg_rdata_next[4] = bank0_info0_page_cfg_1_scramble_en_1_qs;
reg_rdata_next[5] = bank0_info0_page_cfg_1_ecc_en_1_qs;
+ reg_rdata_next[6] = bank0_info0_page_cfg_1_he_en_1_qs;
end
addr_hit[29]: begin
@@ -7983,6 +8794,7 @@
reg_rdata_next[3] = bank0_info0_page_cfg_2_erase_en_2_qs;
reg_rdata_next[4] = bank0_info0_page_cfg_2_scramble_en_2_qs;
reg_rdata_next[5] = bank0_info0_page_cfg_2_ecc_en_2_qs;
+ reg_rdata_next[6] = bank0_info0_page_cfg_2_he_en_2_qs;
end
addr_hit[30]: begin
@@ -7992,6 +8804,7 @@
reg_rdata_next[3] = bank0_info0_page_cfg_3_erase_en_3_qs;
reg_rdata_next[4] = bank0_info0_page_cfg_3_scramble_en_3_qs;
reg_rdata_next[5] = bank0_info0_page_cfg_3_ecc_en_3_qs;
+ reg_rdata_next[6] = bank0_info0_page_cfg_3_he_en_3_qs;
end
addr_hit[31]: begin
@@ -8017,6 +8830,7 @@
reg_rdata_next[3] = bank0_info1_page_cfg_0_erase_en_0_qs;
reg_rdata_next[4] = bank0_info1_page_cfg_0_scramble_en_0_qs;
reg_rdata_next[5] = bank0_info1_page_cfg_0_ecc_en_0_qs;
+ reg_rdata_next[6] = bank0_info1_page_cfg_0_he_en_0_qs;
end
addr_hit[36]: begin
@@ -8026,6 +8840,7 @@
reg_rdata_next[3] = bank0_info1_page_cfg_1_erase_en_1_qs;
reg_rdata_next[4] = bank0_info1_page_cfg_1_scramble_en_1_qs;
reg_rdata_next[5] = bank0_info1_page_cfg_1_ecc_en_1_qs;
+ reg_rdata_next[6] = bank0_info1_page_cfg_1_he_en_1_qs;
end
addr_hit[37]: begin
@@ -8035,6 +8850,7 @@
reg_rdata_next[3] = bank0_info1_page_cfg_2_erase_en_2_qs;
reg_rdata_next[4] = bank0_info1_page_cfg_2_scramble_en_2_qs;
reg_rdata_next[5] = bank0_info1_page_cfg_2_ecc_en_2_qs;
+ reg_rdata_next[6] = bank0_info1_page_cfg_2_he_en_2_qs;
end
addr_hit[38]: begin
@@ -8044,6 +8860,7 @@
reg_rdata_next[3] = bank0_info1_page_cfg_3_erase_en_3_qs;
reg_rdata_next[4] = bank0_info1_page_cfg_3_scramble_en_3_qs;
reg_rdata_next[5] = bank0_info1_page_cfg_3_ecc_en_3_qs;
+ reg_rdata_next[6] = bank0_info1_page_cfg_3_he_en_3_qs;
end
addr_hit[39]: begin
@@ -8069,6 +8886,7 @@
reg_rdata_next[3] = bank1_info0_page_cfg_0_erase_en_0_qs;
reg_rdata_next[4] = bank1_info0_page_cfg_0_scramble_en_0_qs;
reg_rdata_next[5] = bank1_info0_page_cfg_0_ecc_en_0_qs;
+ reg_rdata_next[6] = bank1_info0_page_cfg_0_he_en_0_qs;
end
addr_hit[44]: begin
@@ -8078,6 +8896,7 @@
reg_rdata_next[3] = bank1_info0_page_cfg_1_erase_en_1_qs;
reg_rdata_next[4] = bank1_info0_page_cfg_1_scramble_en_1_qs;
reg_rdata_next[5] = bank1_info0_page_cfg_1_ecc_en_1_qs;
+ reg_rdata_next[6] = bank1_info0_page_cfg_1_he_en_1_qs;
end
addr_hit[45]: begin
@@ -8087,6 +8906,7 @@
reg_rdata_next[3] = bank1_info0_page_cfg_2_erase_en_2_qs;
reg_rdata_next[4] = bank1_info0_page_cfg_2_scramble_en_2_qs;
reg_rdata_next[5] = bank1_info0_page_cfg_2_ecc_en_2_qs;
+ reg_rdata_next[6] = bank1_info0_page_cfg_2_he_en_2_qs;
end
addr_hit[46]: begin
@@ -8096,6 +8916,7 @@
reg_rdata_next[3] = bank1_info0_page_cfg_3_erase_en_3_qs;
reg_rdata_next[4] = bank1_info0_page_cfg_3_scramble_en_3_qs;
reg_rdata_next[5] = bank1_info0_page_cfg_3_ecc_en_3_qs;
+ reg_rdata_next[6] = bank1_info0_page_cfg_3_he_en_3_qs;
end
addr_hit[47]: begin
@@ -8121,6 +8942,7 @@
reg_rdata_next[3] = bank1_info1_page_cfg_0_erase_en_0_qs;
reg_rdata_next[4] = bank1_info1_page_cfg_0_scramble_en_0_qs;
reg_rdata_next[5] = bank1_info1_page_cfg_0_ecc_en_0_qs;
+ reg_rdata_next[6] = bank1_info1_page_cfg_0_he_en_0_qs;
end
addr_hit[52]: begin
@@ -8130,6 +8952,7 @@
reg_rdata_next[3] = bank1_info1_page_cfg_1_erase_en_1_qs;
reg_rdata_next[4] = bank1_info1_page_cfg_1_scramble_en_1_qs;
reg_rdata_next[5] = bank1_info1_page_cfg_1_ecc_en_1_qs;
+ reg_rdata_next[6] = bank1_info1_page_cfg_1_he_en_1_qs;
end
addr_hit[53]: begin
@@ -8139,6 +8962,7 @@
reg_rdata_next[3] = bank1_info1_page_cfg_2_erase_en_2_qs;
reg_rdata_next[4] = bank1_info1_page_cfg_2_scramble_en_2_qs;
reg_rdata_next[5] = bank1_info1_page_cfg_2_ecc_en_2_qs;
+ reg_rdata_next[6] = bank1_info1_page_cfg_2_he_en_2_qs;
end
addr_hit[54]: begin
@@ -8148,6 +8972,7 @@
reg_rdata_next[3] = bank1_info1_page_cfg_3_erase_en_3_qs;
reg_rdata_next[4] = bank1_info1_page_cfg_3_scramble_en_3_qs;
reg_rdata_next[5] = bank1_info1_page_cfg_3_ecc_en_3_qs;
+ reg_rdata_next[6] = bank1_info1_page_cfg_3_he_en_3_qs;
end
addr_hit[55]: begin
diff --git a/hw/top_earlgrey/rtl/autogen/top_earlgrey.sv b/hw/top_earlgrey/rtl/autogen/top_earlgrey.sv
index fa9f911..36ef80c 100644
--- a/hw/top_earlgrey/rtl/autogen/top_earlgrey.sv
+++ b/hw/top_earlgrey/rtl/autogen/top_earlgrey.sv
@@ -664,6 +664,11 @@
.host_rdata_o (flash_host_rdata),
.flash_ctrl_i (flash_ctrl_flash_req),
.flash_ctrl_o (flash_ctrl_flash_rsp),
+ .lc_dft_en_i (lc_ctrl_pkg::LC_TX_DEFAULT),
+ .tck_i ('0),
+ .tdi_i ('0),
+ .tms_i ('0),
+ .tdo_o (),
.flash_power_down_h_i,
.flash_power_ready_h_i,
.flash_test_mode_a_i,
@@ -1018,7 +1023,9 @@
.flash_o(flash_ctrl_flash_req),
.flash_i(flash_ctrl_flash_rsp),
.otp_i(flash_ctrl_pkg::OTP_FLASH_DEFAULT),
- .lc_provision_en_i(lc_ctrl_pkg::LC_TX_DEFAULT),
+ .lc_provision_wr_en_i(lc_ctrl_pkg::LC_TX_DEFAULT),
+ .lc_provision_rd_en_i(lc_ctrl_pkg::LC_TX_DEFAULT),
+ .lc_iso_flash_wr_en_i(lc_ctrl_pkg::LC_TX_DEFAULT),
.lc_i(flash_ctrl_pkg::LC_FLASH_REQ_DEFAULT),
.lc_o(),
.edn_i(flash_ctrl_pkg::EDN_ENTROPY_DEFAULT),
