commit 2280cadd3530b47ca6d56d62d00d9c36cf438ae6
author Guillermo Maturana <maturana@google.com> Fri Sep 24 15:47:18 2021 -0700
committer Matute <maturana@google.com> Mon Sep 27 08:33:19 2021 -0700
tree 1f8f28e5549acb71071cfc506b4e8c19d08dde17
parent 2fb857a1a2ac3ea86e3812fe40134aa2a61d59d4

[formal/conn] Fix clkmgr peri clock

Remove units that are not connected to peripheral clocks.
Add missing peripheral clock connections.

Signed-off-by: Guillermo Maturana <maturana@google.com>

hw/top_earlgrey/formal/conn_csvs/top_earlgrey_conn.csv

diff --git a/hw/top_earlgrey/formal/conn_csvs/top_earlgrey_conn.csv b/hw/top_earlgrey/formal/conn_csvs/top_earlgrey_conn.csv
index be3db39..63d46b5 100644
--- a/hw/top_earlgrey/formal/conn_csvs/top_earlgrey_conn.csv
+++ b/hw/top_earlgrey/formal/conn_csvs/top_earlgrey_conn.csv
@@ -22,10 +22,12 @@
 CONNECTION,CLKMGR_PERI_CLK0_I2C1,top_earlgrey.u_clkmgr_aon,clocks_o.clk_io_div4_peri,top_earlgrey.u_i2c1,clk_i
 CONNECTION,CLKMGR_PERI_CLK0_I2C2,top_earlgrey.u_clkmgr_aon,clocks_o.clk_io_div4_peri,top_earlgrey.u_i2c2,clk_i
 CONNECTION,CLKMGR_PERI_CLK0_PATTGEN,top_earlgrey.u_clkmgr_aon,clocks_o.clk_io_div4_peri,top_earlgrey.u_pattgen,clk_i
+CONNECTION,CLKMGR_PERI_CLK0_UART0,top_earlgrey.u_clkmgr_aon,clocks_o.clk_io_div4_peri,top_earlgrey.u_uart0,clk_i
+CONNECTION,CLKMGR_PERI_CLK0_UART1,top_earlgrey.u_clkmgr_aon,clocks_o.clk_io_div4_peri,top_earlgrey.u_uart1,clk_i
+CONNECTION,CLKMGR_PERI_CLK0_UART2,top_earlgrey.u_clkmgr_aon,clocks_o.clk_io_div4_peri,top_earlgrey.u_uart2,clk_i
+CONNECTION,CLKMGR_PERI_CLK0_UART3,top_earlgrey.u_clkmgr_aon,clocks_o.clk_io_div4_peri,top_earlgrey.u_uart3,clk_i
 CONNECTION,CLKMGR_PERI_CLK0_USBDEV,top_earlgrey.u_clkmgr_aon,clocks_o.clk_io_div4_peri,top_earlgrey.u_usbdev,clk_i
 CONNECTION,CLKMGR_PERI_CLK0_ADC_CTRL_AON,top_earlgrey.u_clkmgr_aon,clocks_o.clk_io_div4_peri,top_earlgrey.u_adc_ctrl_aon,clk_i
-CONNECTION,CLKMGR_PERI_CLK0_SRAM_CTRL_RET_AON,top_earlgrey.u_clkmgr_aon,clocks_o.clk_io_div4_peri,top_earlgrey.u_sram_ctrl_ret_aon,clk_i
-CONNECTION,CLKMGR_PERI_CLK0_SRAM_CTRL_RET_AON_OTP,top_earlgrey.u_clkmgr_aon,clocks_o.clk_io_div4_peri,top_earlgrey.u_sram_ctrl_ret_aon,clk_otp_i
 CONNECTION,CLKMGR_PERI_CLK1_SPI_DEVICE,top_earlgrey.u_clkmgr_aon,clocks_o.clk_io_div2_peri,top_earlgrey.u_spi_device,scan_clk_i
 CONNECTION,CLKMGR_PERI_CLK1_SPI_HOST0,top_earlgrey.u_clkmgr_aon,clocks_o.clk_io_peri,top_earlgrey.u_spi_host0,clk_core_i
 CONNECTION,CLKMGR_PERI_CLK1_SPI_HOST1,top_earlgrey.u_clkmgr_aon,clocks_o.clk_io_div2_peri,top_earlgrey.u_spi_host1,clk_core_i