[i2c, rtl] Initial incomplete implementation of i2c target mode
1. Added registers for i2c target mode
2. Added target tx and acq fifos
3. Added target ports to FSM (FSM not functional in target mode yet)
4. Added dv fixes to CI errors
Signed-off-by: Igor Kouznetsov <igor.kouznetsov@wdc.com>
diff --git a/hw/ip/i2c/data/i2c.hjson b/hw/ip/i2c/data/i2c.hjson
index 2ca317a..a12bf0f 100644
--- a/hw/ip/i2c/data/i2c.hjson
+++ b/hw/ip/i2c/data/i2c.hjson
@@ -43,6 +43,21 @@
{ name: "trans_complete"
desc: "raised if the host terminates the transaction by issuing STOP or repeated START."
}
+ { name: "tx_empty"
+ desc: "raised if the target needs data to transmit and TX FIFO is empty."
+ }
+ { name: "tx_nonempty"
+ desc: "raised if there are extra bytes left in TX FIFO at the end of a read."
+ }
+ { name: "tx_overflow"
+ desc: "raised if TX FIFO has overflowed."
+ }
+ { name: "acq_overflow"
+ desc: "raised if ACQ FIFO has overflowed."
+ }
+ { name: "ack_stop"
+ desc: "raised if STOP is received after ACK (host sends both signals)."
+ }
]
// REGISTER definition
@@ -61,6 +76,13 @@
Enable Host I2C functionality
'''
}
+ { bits: "1"
+ resval: "0"
+ name: "ENABLETARGET"
+ desc: '''
+ Enable Target I2C functionality
+ '''
+ }
]
}
{ name: "STATUS"
@@ -97,6 +119,24 @@
desc: "Target functionality is idle. No Target transaction is in progress"
resval: "1"
}
+ { bits: "6"
+ name: "TXFULL"
+ desc: "TX FIFO is full"
+ }
+ { bits: "7"
+ name: "ACQFULL"
+ desc: "ACQ FIFO is full"
+ }
+ { bits: "8"
+ name: "TXEMPTY"
+ desc: "TX FIFO is empty"
+ resval: "1"
+ }
+ { bits: "9"
+ name: "ACQEMPTY"
+ desc: "ACQ FIFO is empty"
+ resval: "1"
+ }
]
tags: [// Updated by the hw. Exclude from write-checks.
"excl:CsrNonInitTests:CsrExclWriteCheck"]
@@ -213,6 +253,16 @@
}
]
}
+ { bits: "7"
+ swaccess: "wo"
+ name: "ACQRST"
+ desc: "ACQ FIFO reset. Write 1 to the register resets it. Read returns 0"
+ }
+ { bits: "8"
+ swaccess: "wo"
+ name: "TXRST"
+ desc: "TX FIFO reset. Write 1 to the register resets it. Read returns 0"
+ }
]
}
{ name: "FIFO_STATUS"
@@ -229,6 +279,14 @@
name: "RXLVL"
desc: "Current fill level of RX fifo"
}
+ { bits: "13:8"
+ name: "TXLVL"
+ desc: "Current fill level of TX fifo"
+ }
+ { bits: "29:24"
+ name: "ACQLVL"
+ desc: "Current fill level of ACQ fifo"
+ }
]
tags: [// Updated by the hw. Exclude from write-checks.
"excl:CsrNonInitTests:CsrExclWriteCheck"]
@@ -383,5 +441,57 @@
}
]
}
+ { name: "TARGET_ID"
+ desc: "I2C target address and mask pairs"
+ swaccess: "rw"
+ hwaccess: "hro"
+ fields: [
+ { bits: "6:0"
+ name: "ADDRESS0"
+ desc: "I2C target address number 0"
+ }
+ { bits: "13:7"
+ name: "MASK0"
+ desc: "I2C target mask number 0"
+ }
+ { bits: "20:14"
+ name: "ADDRESS1"
+ desc: "I2C target address number 1"
+ }
+ { bits: "27:21"
+ name: "MASK1"
+ desc: "I2C target mask number 1"
+ }
+ ]
+ }
+ { name: "ACQDATA"
+ desc: "I2C target acquired data"
+ swaccess: "ro"
+ hwaccess: "hrw"
+ hwext: "true"
+ hwre: "true"
+ fields: [
+ { bits: "7:0"
+ name: "ABYTE"
+ desc: "Address for accepted transaction or acquired byte"
+ }
+ { bits: "9:8"
+ name: "SIGNAL"
+ desc: "Host issued a START before transmitting ABYTE, a STOP or a RESTART after the preceeding ABYTE"
+ }
+ ]
+ tags: [// Updated by the hw. Exclude from init and write-checks.
+ // Without actual I2C traffic, read from this FIFO returns Xs.
+ "excl:CsrAllTests:CsrExclCheck"]
+ }
+ { name: "TXDATA"
+ desc: "I2C target transmit data"
+ swaccess: "wo"
+ hwaccess: "hro"
+ hwqe: "true"
+ fields: [
+ { bits: "7:0" }
+ ]
+ }
]
}
diff --git a/hw/ip/i2c/dv/env/i2c_env_pkg.sv b/hw/ip/i2c/dv/env/i2c_env_pkg.sv
index 08d3909..c72de37 100644
--- a/hw/ip/i2c/dv/env/i2c_env_pkg.sv
+++ b/hw/ip/i2c/dv/env/i2c_env_pkg.sv
@@ -30,7 +30,12 @@
StretchTimeout = 7,
SdaUnstable = 8,
TransComplete = 9,
- NumI2cIntr = 10
+ TxEmpty = 10,
+ TxNonEmpty = 11,
+ TxOverflow = 12,
+ AcqOverflow = 13,
+ AckStop = 14,
+ NumI2cIntr = 15
} i2c_intr_e;
typedef enum int {
diff --git a/hw/ip/i2c/dv/env/seq_lib/i2c_base_vseq.sv b/hw/ip/i2c/dv/env/seq_lib/i2c_base_vseq.sv
index 5147dff..5f4e63a 100644
--- a/hw/ip/i2c/dv/env/seq_lib/i2c_base_vseq.sv
+++ b/hw/ip/i2c/dv/env/seq_lib/i2c_base_vseq.sv
@@ -151,6 +151,11 @@
ral.ctrl.enablehost.set(1'b1);
csr_update(ral.ctrl);
+ // enable host
+ ral.ctrl.enablehost.set(1'b1);
+ ral.ctrl.enabletarget.set(1'b0);
+ csr_update(ral.ctrl);
+
// diable override
ral.ovrd.txovrden.set(1'b0);
csr_update(ral.ovrd);
diff --git a/hw/ip/i2c/dv/tb/tb.sv b/hw/ip/i2c/dv/tb/tb.sv
index bb3f0e7..9d551e8 100644
--- a/hw/ip/i2c/dv/tb/tb.sv
+++ b/hw/ip/i2c/dv/tb/tb.sv
@@ -25,6 +25,11 @@
wire intr_stretch_timeout;
wire intr_sda_unstable;
wire intr_trans_complete;
+ wire intr_tx_empty;
+ wire intr_tx_nonempty;
+ wire intr_tx_overflow;
+ wire intr_acq_overflow;
+ wire intr_ack_stop;
wire [NUM_MAX_INTERRUPTS-1:0] interrupts;
wire cio_scl_i;
@@ -66,7 +71,12 @@
.intr_sda_interference_o (intr_sda_interference ),
.intr_stretch_timeout_o (intr_stretch_timeout ),
.intr_sda_unstable_o (intr_sda_unstable ),
- .intr_trans_complete_o (intr_trans_complete )
+ .intr_trans_complete_o (intr_trans_complete ),
+ .intr_tx_empty_o (intr_tx_empty ),
+ .intr_tx_nonempty_o (intr_tx_nonempty ),
+ .intr_tx_overflow_o (intr_tx_overflow ),
+ .intr_acq_overflow_o (intr_acq_overflow ),
+ .intr_ack_stop_o (intr_ack_stop )
);
// virtual open drain
@@ -90,6 +100,11 @@
assign interrupts[StretchTimeout] = intr_stretch_timeout;
assign interrupts[SdaUnstable] = intr_sda_unstable;
assign interrupts[TransComplete] = intr_trans_complete;
+ assign interrupts[TxEmpty] = intr_tx_empty;
+ assign interrupts[TxNonEmpty] = intr_tx_nonempty;
+ assign interrupts[TxOverflow] = intr_tx_overflow;
+ assign interrupts[AcqOverflow] = intr_acq_overflow;
+ assign interrupts[AckStop] = intr_ack_stop;
initial begin
// drive clk and rst_n from clk_if
diff --git a/hw/ip/i2c/rtl/i2c.sv b/hw/ip/i2c/rtl/i2c.sv
index 3aec210..c24a22e 100644
--- a/hw/ip/i2c/rtl/i2c.sv
+++ b/hw/ip/i2c/rtl/i2c.sv
@@ -32,7 +32,12 @@
output logic intr_sda_interference_o,
output logic intr_stretch_timeout_o,
output logic intr_sda_unstable_o,
- output logic intr_trans_complete_o
+ output logic intr_trans_complete_o,
+ output logic intr_tx_empty_o,
+ output logic intr_tx_nonempty_o,
+ output logic intr_tx_overflow_o,
+ output logic intr_acq_overflow_o,
+ output logic intr_ack_stop_o
);
import i2c_reg_pkg::*;
@@ -73,7 +78,12 @@
.intr_sda_interference_o,
.intr_stretch_timeout_o,
.intr_sda_unstable_o,
- .intr_trans_complete_o
+ .intr_trans_complete_o,
+ .intr_tx_empty_o,
+ .intr_tx_nonempty_o,
+ .intr_tx_overflow_o,
+ .intr_acq_overflow_o,
+ .intr_ack_stop_o
);
// For I2C, in standard, fast and fast-plus modes, outputs simulated as open-drain outputs.
@@ -102,5 +112,10 @@
`ASSERT_KNOWN(IntrStretchTimeoutKnownO_A, intr_stretch_timeout_o)
`ASSERT_KNOWN(IntrSdaUnstableKnownO_A, intr_sda_unstable_o)
`ASSERT_KNOWN(IntrTransCompleteKnownO_A, intr_trans_complete_o)
+ `ASSERT_KNOWN(IntrTxEmptyKnownO_A, intr_tx_empty_o)
+ `ASSERT_KNOWN(IntrTxNonemptyKnownO_A, intr_tx_nonempty_o)
+ `ASSERT_KNOWN(IntrTxOflwKnownO_A, intr_tx_overflow_o)
+ `ASSERT_KNOWN(IntrAcqOflwKnownO_A, intr_acq_overflow_o)
+ `ASSERT_KNOWN(IntrAckStopKnownO_A, intr_ack_stop_o)
endmodule
diff --git a/hw/ip/i2c/rtl/i2c_core.sv b/hw/ip/i2c/rtl/i2c_core.sv
index e00bf6f..ec1fce4 100644
--- a/hw/ip/i2c/rtl/i2c_core.sv
+++ b/hw/ip/i2c/rtl/i2c_core.sv
@@ -25,7 +25,12 @@
output logic intr_sda_interference_o,
output logic intr_stretch_timeout_o,
output logic intr_sda_unstable_o,
- output logic intr_trans_complete_o
+ output logic intr_trans_complete_o,
+ output logic intr_tx_empty_o,
+ output logic intr_tx_nonempty_o,
+ output logic intr_tx_overflow_o,
+ output logic intr_acq_overflow_o,
+ output logic intr_ack_stop_o
);
logic [15:0] thigh;
@@ -54,6 +59,11 @@
logic event_stretch_timeout;
logic event_sda_unstable;
logic event_trans_complete;
+ logic event_tx_empty;
+ logic event_tx_nonempty;
+ logic event_tx_overflow;
+ logic event_acq_overflow;
+ logic event_ack_stop;
logic [15:0] scl_rx_val;
logic [15:0] sda_rx_val;
@@ -92,18 +102,42 @@
logic rx_watermark_d;
logic rx_watermark_q;
+ logic tx_fifo_wvalid;
+ logic tx_fifo_wready;
+ logic [7:0] tx_fifo_wdata;
+ logic [5:0] tx_fifo_depth;
+ logic tx_fifo_rvalid;
+ logic tx_fifo_rready;
+ logic [7:0] tx_fifo_rdata;
+
+ logic acq_fifo_wvalid;
+ logic acq_fifo_wready;
+ logic [9:0] acq_fifo_wdata;
+ logic [5:0] acq_fifo_depth;
+ logic acq_fifo_rvalid;
+ logic acq_fifo_rready;
+ logic [9:0] acq_fifo_rdata;
+
+ logic i2c_fifo_txrst;
+ logic i2c_fifo_acqrst;
+
logic host_idle;
logic target_idle;
logic host_enable;
+ logic target_enable;
+
+ logic [6:0] target_address0;
+ logic [6:0] target_mask0;
+ logic [6:0] target_address1;
+ logic [6:0] target_mask1;
// Unused parts of exposed bits
logic unused_fifo_ctrl_rxilvl_qe;
logic unused_fifo_ctrl_fmtilvl_qe;
logic [7:0] unused_rx_fifo_rdata_q;
-
- // placeholder: no target functionality yet;
- assign target_idle = 1'b1;
+ logic [7:0] unused_acq_fifo_adata_q;
+ logic [1:0] unused_acq_fifo_signal_q;
assign hw2reg.status.fmtfull.d = ~fmt_fifo_wready;
assign hw2reg.status.rxfull.d = ~rx_fifo_wready;
@@ -117,12 +151,27 @@
assign hw2reg.val.scl_rx.d = scl_rx_val;
assign hw2reg.val.sda_rx.d = sda_rx_val;
+ assign hw2reg.status.txfull.d = ~tx_fifo_wready;
+ assign hw2reg.status.acqfull.d = ~acq_fifo_wready;
+ assign hw2reg.status.txempty.d = ~tx_fifo_rvalid;
+ assign hw2reg.status.acqempty.d = ~acq_fifo_rvalid;
+ assign hw2reg.fifo_status.txlvl.d = tx_fifo_depth;
+ assign hw2reg.fifo_status.acqlvl.d = acq_fifo_depth;
+ assign hw2reg.acqdata.abyte.d = acq_fifo_rdata[7:0];
+ assign hw2reg.acqdata.signal.d = acq_fifo_rdata[9:8];
+
assign override = reg2hw.ovrd.txovrden;
assign scl_o = override ? reg2hw.ovrd.sclval : scl_out_fsm;
assign sda_o = override ? reg2hw.ovrd.sdaval : sda_out_fsm;
- assign host_enable = reg2hw.ctrl.q;
+ assign host_enable = reg2hw.ctrl.enablehost.q;
+ assign target_enable = reg2hw.ctrl.enabletarget.q;
+
+ assign target_address0 = reg2hw.target_id.address0.q;
+ assign target_mask0 = reg2hw.target_id.mask0.q;
+ assign target_address1 = reg2hw.target_id.address1.q;
+ assign target_mask1 = reg2hw.target_id.mask1.q;
// Sample scl_i and sda_i at system clock
always_ff @ (posedge clk_i or negedge rst_ni) begin : rx_oversampling
@@ -153,6 +202,9 @@
assign i2c_fifo_rxilvl = reg2hw.fifo_ctrl.rxilvl.q;
assign i2c_fifo_fmtilvl = reg2hw.fifo_ctrl.fmtilvl.q;
+ assign i2c_fifo_txrst = reg2hw.fifo_ctrl.txrst.q & reg2hw.fifo_ctrl.txrst.qe;
+ assign i2c_fifo_acqrst = reg2hw.fifo_ctrl.acqrst.q & reg2hw.fifo_ctrl.acqrst.qe;
+
always_ff @ (posedge clk_i or negedge rst_ni) begin : watermark_transition
if (!rst_ni) begin
fmt_watermark_q <= 1'b1; // true by default
@@ -217,6 +269,8 @@
assign unused_fifo_ctrl_rxilvl_qe = reg2hw.fifo_ctrl.rxilvl.qe;
assign unused_fifo_ctrl_fmtilvl_qe = reg2hw.fifo_ctrl.fmtilvl.qe;
assign unused_rx_fifo_rdata_q = reg2hw.rdata.q;
+ assign unused_acq_fifo_adata_q = reg2hw.acqdata.abyte.q;
+ assign unused_acq_fifo_signal_q = reg2hw.acqdata.signal.q;
prim_fifo_sync #(
.Width (13),
@@ -254,6 +308,49 @@
.rdata_o (rx_fifo_rdata)
);
+ // Target TX and ACQ FIFOs
+ assign event_tx_overflow = tx_fifo_wvalid & ~tx_fifo_wready;
+ assign event_acq_overflow = acq_fifo_wvalid & ~acq_fifo_wready;
+
+ assign tx_fifo_wvalid = reg2hw.txdata.qe;
+ assign tx_fifo_wdata = reg2hw.txdata.q;
+
+ prim_fifo_sync #(
+ .Width(8),
+ .Pass(1'b1),
+ .Depth(32)
+ ) u_i2c_txfifo (
+ .clk_i,
+ .rst_ni,
+ .clr_i (i2c_fifo_txrst),
+ .wvalid_i(tx_fifo_wvalid),
+ .wready_o(tx_fifo_wready),
+ .wdata_i (tx_fifo_wdata),
+ .depth_o (tx_fifo_depth),
+ .rvalid_o(tx_fifo_rvalid),
+ .rready_i(tx_fifo_rready),
+ .rdata_o (tx_fifo_rdata)
+ );
+
+ assign acq_fifo_rready = reg2hw.acqdata.abyte.re & reg2hw.acqdata.signal.re;
+
+ prim_fifo_sync #(
+ .Width(10),
+ .Pass(1'b0),
+ .Depth(32)
+ ) u_i2c_acqfifo (
+ .clk_i,
+ .rst_ni,
+ .clr_i (i2c_fifo_acqrst),
+ .wvalid_i(acq_fifo_wvalid),
+ .wready_o(acq_fifo_wready),
+ .wdata_i (acq_fifo_wdata),
+ .depth_o (acq_fifo_depth),
+ .rvalid_o(acq_fifo_rvalid),
+ .rready_i(acq_fifo_rready),
+ .rdata_o (acq_fifo_rdata)
+ );
+
i2c_fsm u_i2c_fsm (
.clk_i,
.rst_ni,
@@ -264,6 +361,7 @@
.sda_o (sda_out_fsm),
.host_enable_i (host_enable),
+ .target_enable_i (target_enable),
.fmt_fifo_rvalid_i (fmt_fifo_rvalid),
.fmt_fifo_wvalid_i (fmt_fifo_wvalid),
@@ -280,7 +378,15 @@
.rx_fifo_wvalid_o (rx_fifo_wvalid),
.rx_fifo_wdata_o (rx_fifo_wdata),
+ .tx_fifo_rvalid_i (tx_fifo_rvalid),
+ .tx_fifo_rready_o (tx_fifo_rready),
+ .tx_fifo_rdata_i (tx_fifo_rdata),
+
+ .acq_fifo_wvalid_o (acq_fifo_wvalid),
+ .acq_fifo_wdata_o (acq_fifo_wdata),
+
.host_idle_o (host_idle),
+ .target_idle_o (target_idle),
.thigh_i (thigh),
.tlow_i (tlow),
@@ -295,12 +401,20 @@
.stretch_timeout_i (stretch_timeout),
.timeout_enable_i (timeout_enable),
+ .target_address0_i (target_address0),
+ .target_mask0_i (target_mask0),
+ .target_address1_i (target_address1),
+ .target_mask1_i (target_mask1),
+
.event_nak_o (event_nak),
.event_scl_interference_o(event_scl_interference),
.event_sda_interference_o(event_sda_interference),
.event_stretch_timeout_o (event_stretch_timeout),
.event_sda_unstable_o (event_sda_unstable),
- .event_trans_complete_o (event_trans_complete)
+ .event_trans_complete_o (event_trans_complete),
+ .event_tx_empty_o (event_tx_empty),
+ .event_tx_nonempty_o (event_tx_nonempty),
+ .event_ack_stop_o (event_ack_stop)
);
prim_intr_hw #(.Width(1)) intr_hw_fmt_watermark (
@@ -413,4 +527,59 @@
.intr_o (intr_trans_complete_o)
);
+ prim_intr_hw #(.Width(1)) intr_hw_tx_empty (
+ .event_intr_i (event_tx_empty),
+ .reg2hw_intr_enable_q_i (reg2hw.intr_enable.tx_empty.q),
+ .reg2hw_intr_test_q_i (reg2hw.intr_test.tx_empty.q),
+ .reg2hw_intr_test_qe_i (reg2hw.intr_test.tx_empty.qe),
+ .reg2hw_intr_state_q_i (reg2hw.intr_state.tx_empty.q),
+ .hw2reg_intr_state_de_o (hw2reg.intr_state.tx_empty.de),
+ .hw2reg_intr_state_d_o (hw2reg.intr_state.tx_empty.d),
+ .intr_o (intr_tx_empty_o)
+ );
+
+ prim_intr_hw #(.Width(1)) intr_hw_tx_nonempty (
+ .event_intr_i (event_tx_nonempty),
+ .reg2hw_intr_enable_q_i (reg2hw.intr_enable.tx_nonempty.q),
+ .reg2hw_intr_test_q_i (reg2hw.intr_test.tx_nonempty.q),
+ .reg2hw_intr_test_qe_i (reg2hw.intr_test.tx_nonempty.qe),
+ .reg2hw_intr_state_q_i (reg2hw.intr_state.tx_nonempty.q),
+ .hw2reg_intr_state_de_o (hw2reg.intr_state.tx_nonempty.de),
+ .hw2reg_intr_state_d_o (hw2reg.intr_state.tx_nonempty.d),
+ .intr_o (intr_tx_nonempty_o)
+ );
+
+ prim_intr_hw #(.Width(1)) intr_hw_tx_overflow (
+ .event_intr_i (event_tx_overflow),
+ .reg2hw_intr_enable_q_i (reg2hw.intr_enable.tx_overflow.q),
+ .reg2hw_intr_test_q_i (reg2hw.intr_test.tx_overflow.q),
+ .reg2hw_intr_test_qe_i (reg2hw.intr_test.tx_overflow.qe),
+ .reg2hw_intr_state_q_i (reg2hw.intr_state.tx_overflow.q),
+ .hw2reg_intr_state_de_o (hw2reg.intr_state.tx_overflow.de),
+ .hw2reg_intr_state_d_o (hw2reg.intr_state.tx_overflow.d),
+ .intr_o (intr_tx_overflow_o)
+ );
+
+ prim_intr_hw #(.Width(1)) intr_hw_acq_overflow (
+ .event_intr_i (event_acq_overflow),
+ .reg2hw_intr_enable_q_i (reg2hw.intr_enable.acq_overflow.q),
+ .reg2hw_intr_test_q_i (reg2hw.intr_test.acq_overflow.q),
+ .reg2hw_intr_test_qe_i (reg2hw.intr_test.acq_overflow.qe),
+ .reg2hw_intr_state_q_i (reg2hw.intr_state.acq_overflow.q),
+ .hw2reg_intr_state_de_o (hw2reg.intr_state.acq_overflow.de),
+ .hw2reg_intr_state_d_o (hw2reg.intr_state.acq_overflow.d),
+ .intr_o (intr_acq_overflow_o)
+ );
+
+ prim_intr_hw #(.Width(1)) intr_hw_ack_stop (
+ .event_intr_i (event_ack_stop),
+ .reg2hw_intr_enable_q_i (reg2hw.intr_enable.ack_stop.q),
+ .reg2hw_intr_test_q_i (reg2hw.intr_test.ack_stop.q),
+ .reg2hw_intr_test_qe_i (reg2hw.intr_test.ack_stop.qe),
+ .reg2hw_intr_state_q_i (reg2hw.intr_state.ack_stop.q),
+ .hw2reg_intr_state_de_o (hw2reg.intr_state.ack_stop.de),
+ .hw2reg_intr_state_d_o (hw2reg.intr_state.ack_stop.d),
+ .intr_o (intr_ack_stop_o)
+ );
+
endmodule
diff --git a/hw/ip/i2c/rtl/i2c_fsm.sv b/hw/ip/i2c/rtl/i2c_fsm.sv
index a6d6126..d653117 100644
--- a/hw/ip/i2c/rtl/i2c_fsm.sv
+++ b/hw/ip/i2c/rtl/i2c_fsm.sv
@@ -14,6 +14,7 @@
output sda_o, // serial data output to i2c bus
input host_enable_i, // enable host functionality
+ input target_enable_i, // enable target functionality
input fmt_fifo_rvalid_i, // indicates there is valid data in fmt_fifo
input fmt_fifo_wvalid_i, // indicates data is being put into fmt_fifo
@@ -29,7 +30,15 @@
output logic rx_fifo_wvalid_o, // high if there is valid data in rx_fifo
output logic [7:0] rx_fifo_wdata_o, // byte in rx_fifo read from target
+ input tx_fifo_rvalid_i, // indicates there is valid data in tx_fifo
+ output logic tx_fifo_rready_o, // populates tx_fifo
+ input [7:0] tx_fifo_rdata_i, // byte in tx_fifo to be sent to host
+
+ output logic acq_fifo_wvalid_o, // high if there is valid data in acq_fifo
+ output logic [9:0] acq_fifo_wdata_o, // byte and signal in acq_fifo read from target
+
output logic host_idle_o, // indicates the host is idle
+ output logic target_idle_o, // indicates the target is idle
input [15:0] thigh_i, // high period of the SCL in clock units
input [15:0] tlow_i, // low period of the SCL in clock units
@@ -44,12 +53,20 @@
input [30:0] stretch_timeout_i, // max time target may stretch the clock
input timeout_enable_i, // assert if target stretches clock past max
+ input logic [6:0] target_address0_i,
+ input logic [6:0] target_mask0_i,
+ input logic [6:0] target_address1_i,
+ input logic [6:0] target_mask1_i,
+
output logic event_nak_o, // target didn't Ack when expected
output logic event_scl_interference_o, // other device forcing SCL low
output logic event_sda_interference_o, // other device forcing SDA low
output logic event_stretch_timeout_o, // target stretches clock past max time
output logic event_sda_unstable_o, // SDA is not constant during SCL pulse
- output logic event_trans_complete_o // Transaction is complete
+ output logic event_trans_complete_o, // Transaction is complete
+ output logic event_tx_empty_o, // tx_fifo is empty but data is needed
+ output logic event_tx_nonempty_o, // tx_fifo is nonempty after stop
+ output logic event_ack_stop_o // target received stop after ack
);
// I2C bus clock timing variables
@@ -80,6 +97,14 @@
logic log_stop; // indicates stop is been issued
logic restart; // indicates repeated start state is entered into
+ // Temporary assignments
+ assign tx_fifo_rready_o = tx_fifo_rvalid_i;
+ assign acq_fifo_wdata_o = {tx_fifo_rdata_i, 1'b0, 1'b0};
+ assign target_idle_o = 1'b1;
+ assign event_tx_empty_o = 1'b0;
+ assign event_tx_nonempty_o = 1'b0;
+ assign event_ack_stop_o = 1'b0;
+
// Clock counter implementation
typedef enum logic [3:0] {
tSetupStart, tHoldStart, tClockLow, tSetupBit, tClockPulse, tHoldBit,
@@ -219,6 +244,7 @@
fmt_fifo_rready_o = 1'b0;
rx_fifo_wvalid_o = 1'b0;
rx_fifo_wdata_o = 8'h00;
+ acq_fifo_wvalid_o = 1'b0;
event_nak_o = 1'b0;
event_scl_interference_o = 1'b0;
event_sda_interference_o = 1'b0;
@@ -232,6 +258,9 @@
sda_temp = 1'b1;
scl_temp = 1'b1;
if (sda_i == 0) event_sda_interference_o = 1'b1;
+ if (!target_address0_i && !target_mask0_i && !target_address1_i && !target_mask1_i) begin
+ acq_fifo_wvalid_o = 1'b0;
+ end
end
// SetupStart: SDA and SCL are released
SetupStart : begin
@@ -423,6 +452,7 @@
fmt_fifo_rready_o = 1'b0;
rx_fifo_wvalid_o = 1'b0;
rx_fifo_wdata_o = 8'h00;
+ acq_fifo_wvalid_o = 1'b0;
event_nak_o = 1'b0;
event_scl_interference_o = 1'b0;
event_sda_interference_o = 1'b0;
@@ -451,7 +481,7 @@
unique case (state_q)
// Idle: initial state, SDA and SCL are released (high)
Idle : begin
- if (!host_enable_i) state_d = Idle; // Idle unless host is enabled
+ if (!host_enable_i && !target_enable_i) state_d = Idle; // Idle unless host is enabled
else if (!fmt_fifo_rvalid_i) state_d = Idle;
else state_d = Active;
end
diff --git a/hw/ip/i2c/rtl/i2c_reg_pkg.sv b/hw/ip/i2c/rtl/i2c_reg_pkg.sv
index dbfe332..27d2d39 100644
--- a/hw/ip/i2c/rtl/i2c_reg_pkg.sv
+++ b/hw/ip/i2c/rtl/i2c_reg_pkg.sv
@@ -40,6 +40,21 @@
struct packed {
logic q;
} trans_complete;
+ struct packed {
+ logic q;
+ } tx_empty;
+ struct packed {
+ logic q;
+ } tx_nonempty;
+ struct packed {
+ logic q;
+ } tx_overflow;
+ struct packed {
+ logic q;
+ } acq_overflow;
+ struct packed {
+ logic q;
+ } ack_stop;
} i2c_reg2hw_intr_state_reg_t;
typedef struct packed {
@@ -73,6 +88,21 @@
struct packed {
logic q;
} trans_complete;
+ struct packed {
+ logic q;
+ } tx_empty;
+ struct packed {
+ logic q;
+ } tx_nonempty;
+ struct packed {
+ logic q;
+ } tx_overflow;
+ struct packed {
+ logic q;
+ } acq_overflow;
+ struct packed {
+ logic q;
+ } ack_stop;
} i2c_reg2hw_intr_enable_reg_t;
typedef struct packed {
@@ -116,10 +146,35 @@
logic q;
logic qe;
} trans_complete;
+ struct packed {
+ logic q;
+ logic qe;
+ } tx_empty;
+ struct packed {
+ logic q;
+ logic qe;
+ } tx_nonempty;
+ struct packed {
+ logic q;
+ logic qe;
+ } tx_overflow;
+ struct packed {
+ logic q;
+ logic qe;
+ } acq_overflow;
+ struct packed {
+ logic q;
+ logic qe;
+ } ack_stop;
} i2c_reg2hw_intr_test_reg_t;
typedef struct packed {
- logic q;
+ struct packed {
+ logic q;
+ } enablehost;
+ struct packed {
+ logic q;
+ } enabletarget;
} i2c_reg2hw_ctrl_reg_t;
typedef struct packed {
@@ -171,6 +226,14 @@
logic [1:0] q;
logic qe;
} fmtilvl;
+ struct packed {
+ logic q;
+ logic qe;
+ } acqrst;
+ struct packed {
+ logic q;
+ logic qe;
+ } txrst;
} i2c_reg2hw_fifo_ctrl_reg_t;
typedef struct packed {
@@ -239,6 +302,37 @@
} en;
} i2c_reg2hw_timeout_ctrl_reg_t;
+ typedef struct packed {
+ struct packed {
+ logic [6:0] q;
+ } address0;
+ struct packed {
+ logic [6:0] q;
+ } mask0;
+ struct packed {
+ logic [6:0] q;
+ } address1;
+ struct packed {
+ logic [6:0] q;
+ } mask1;
+ } i2c_reg2hw_target_id_reg_t;
+
+ typedef struct packed {
+ struct packed {
+ logic [7:0] q;
+ logic re;
+ } abyte;
+ struct packed {
+ logic [1:0] q;
+ logic re;
+ } signal;
+ } i2c_reg2hw_acqdata_reg_t;
+
+ typedef struct packed {
+ logic [7:0] q;
+ logic qe;
+ } i2c_reg2hw_txdata_reg_t;
+
typedef struct packed {
struct packed {
@@ -281,6 +375,26 @@
logic d;
logic de;
} trans_complete;
+ struct packed {
+ logic d;
+ logic de;
+ } tx_empty;
+ struct packed {
+ logic d;
+ logic de;
+ } tx_nonempty;
+ struct packed {
+ logic d;
+ logic de;
+ } tx_overflow;
+ struct packed {
+ logic d;
+ logic de;
+ } acq_overflow;
+ struct packed {
+ logic d;
+ logic de;
+ } ack_stop;
} i2c_hw2reg_intr_state_reg_t;
typedef struct packed {
@@ -302,6 +416,18 @@
struct packed {
logic d;
} rxempty;
+ struct packed {
+ logic d;
+ } txfull;
+ struct packed {
+ logic d;
+ } acqfull;
+ struct packed {
+ logic d;
+ } txempty;
+ struct packed {
+ logic d;
+ } acqempty;
} i2c_hw2reg_status_reg_t;
typedef struct packed {
@@ -314,7 +440,13 @@
} fmtlvl;
struct packed {
logic [5:0] d;
+ } txlvl;
+ struct packed {
+ logic [5:0] d;
} rxlvl;
+ struct packed {
+ logic [5:0] d;
+ } acqlvl;
} i2c_hw2reg_fifo_status_reg_t;
typedef struct packed {
@@ -326,36 +458,49 @@
} sda_rx;
} i2c_hw2reg_val_reg_t;
+ typedef struct packed {
+ struct packed {
+ logic [7:0] d;
+ } abyte;
+ struct packed {
+ logic [1:0] d;
+ } signal;
+ } i2c_hw2reg_acqdata_reg_t;
+
///////////////////////////////////////
// Register to internal design logic //
///////////////////////////////////////
typedef struct packed {
- i2c_reg2hw_intr_state_reg_t intr_state; // [274:265]
- i2c_reg2hw_intr_enable_reg_t intr_enable; // [264:255]
- i2c_reg2hw_intr_test_reg_t intr_test; // [254:235]
- i2c_reg2hw_ctrl_reg_t ctrl; // [234:234]
- i2c_reg2hw_rdata_reg_t rdata; // [233:225]
- i2c_reg2hw_fdata_reg_t fdata; // [224:206]
- i2c_reg2hw_fifo_ctrl_reg_t fifo_ctrl; // [205:195]
- i2c_reg2hw_ovrd_reg_t ovrd; // [194:192]
- i2c_reg2hw_timing0_reg_t timing0; // [191:160]
- i2c_reg2hw_timing1_reg_t timing1; // [159:128]
- i2c_reg2hw_timing2_reg_t timing2; // [127:96]
- i2c_reg2hw_timing3_reg_t timing3; // [95:64]
- i2c_reg2hw_timing4_reg_t timing4; // [63:32]
- i2c_reg2hw_timeout_ctrl_reg_t timeout_ctrl; // [31:0]
+ i2c_reg2hw_intr_state_reg_t intr_state; // [348:334]
+ i2c_reg2hw_intr_enable_reg_t intr_enable; // [333:319]
+ i2c_reg2hw_intr_test_reg_t intr_test; // [318:289]
+ i2c_reg2hw_ctrl_reg_t ctrl; // [288:287]
+ i2c_reg2hw_rdata_reg_t rdata; // [286:278]
+ i2c_reg2hw_fdata_reg_t fdata; // [277:259]
+ i2c_reg2hw_fifo_ctrl_reg_t fifo_ctrl; // [258:244]
+ i2c_reg2hw_ovrd_reg_t ovrd; // [243:241]
+ i2c_reg2hw_timing0_reg_t timing0; // [240:209]
+ i2c_reg2hw_timing1_reg_t timing1; // [208:177]
+ i2c_reg2hw_timing2_reg_t timing2; // [176:145]
+ i2c_reg2hw_timing3_reg_t timing3; // [144:113]
+ i2c_reg2hw_timing4_reg_t timing4; // [112:81]
+ i2c_reg2hw_timeout_ctrl_reg_t timeout_ctrl; // [80:49]
+ i2c_reg2hw_target_id_reg_t target_id; // [48:21]
+ i2c_reg2hw_acqdata_reg_t acqdata; // [20:9]
+ i2c_reg2hw_txdata_reg_t txdata; // [8:0]
} i2c_reg2hw_t;
///////////////////////////////////////
// Internal design logic to register //
///////////////////////////////////////
typedef struct packed {
- i2c_hw2reg_intr_state_reg_t intr_state; // [77:68]
- i2c_hw2reg_status_reg_t status; // [67:68]
- i2c_hw2reg_rdata_reg_t rdata; // [67:59]
- i2c_hw2reg_fifo_status_reg_t fifo_status; // [58:59]
- i2c_hw2reg_val_reg_t val; // [58:59]
+ i2c_hw2reg_intr_state_reg_t intr_state; // [113:99]
+ i2c_hw2reg_status_reg_t status; // [98:99]
+ i2c_hw2reg_rdata_reg_t rdata; // [98:90]
+ i2c_hw2reg_fifo_status_reg_t fifo_status; // [89:90]
+ i2c_hw2reg_val_reg_t val; // [89:90]
+ i2c_hw2reg_acqdata_reg_t acqdata; // [89:78]
} i2c_hw2reg_t;
// Register Address
@@ -376,6 +521,9 @@
parameter logic [6:0] I2C_TIMING3_OFFSET = 7'h 38;
parameter logic [6:0] I2C_TIMING4_OFFSET = 7'h 3c;
parameter logic [6:0] I2C_TIMEOUT_CTRL_OFFSET = 7'h 40;
+ parameter logic [6:0] I2C_TARGET_ID_OFFSET = 7'h 44;
+ parameter logic [6:0] I2C_ACQDATA_OFFSET = 7'h 48;
+ parameter logic [6:0] I2C_TXDATA_OFFSET = 7'h 4c;
// Register Index
@@ -396,20 +544,23 @@
I2C_TIMING2,
I2C_TIMING3,
I2C_TIMING4,
- I2C_TIMEOUT_CTRL
+ I2C_TIMEOUT_CTRL,
+ I2C_TARGET_ID,
+ I2C_ACQDATA,
+ I2C_TXDATA
} i2c_id_e;
// Register width information to check illegal writes
- parameter logic [3:0] I2C_PERMIT [17] = '{
+ parameter logic [3:0] I2C_PERMIT [20] = '{
4'b 0011, // index[ 0] I2C_INTR_STATE
4'b 0011, // index[ 1] I2C_INTR_ENABLE
4'b 0011, // index[ 2] I2C_INTR_TEST
4'b 0001, // index[ 3] I2C_CTRL
- 4'b 0001, // index[ 4] I2C_STATUS
+ 4'b 0011, // index[ 4] I2C_STATUS
4'b 0001, // index[ 5] I2C_RDATA
4'b 0011, // index[ 6] I2C_FDATA
- 4'b 0001, // index[ 7] I2C_FIFO_CTRL
- 4'b 0111, // index[ 8] I2C_FIFO_STATUS
+ 4'b 0011, // index[ 7] I2C_FIFO_CTRL
+ 4'b 1111, // index[ 8] I2C_FIFO_STATUS
4'b 0001, // index[ 9] I2C_OVRD
4'b 1111, // index[10] I2C_VAL
4'b 1111, // index[11] I2C_TIMING0
@@ -417,7 +568,10 @@
4'b 1111, // index[13] I2C_TIMING2
4'b 1111, // index[14] I2C_TIMING3
4'b 1111, // index[15] I2C_TIMING4
- 4'b 1111 // index[16] I2C_TIMEOUT_CTRL
+ 4'b 1111, // index[16] I2C_TIMEOUT_CTRL
+ 4'b 1111, // index[17] I2C_TARGET_ID
+ 4'b 0011, // index[18] I2C_ACQDATA
+ 4'b 0001 // index[19] I2C_TXDATA
};
endpackage
diff --git a/hw/ip/i2c/rtl/i2c_reg_top.sv b/hw/ip/i2c/rtl/i2c_reg_top.sv
index 4bb3b64..3bbbbcd 100644
--- a/hw/ip/i2c/rtl/i2c_reg_top.sv
+++ b/hw/ip/i2c/rtl/i2c_reg_top.sv
@@ -101,6 +101,21 @@
logic intr_state_trans_complete_qs;
logic intr_state_trans_complete_wd;
logic intr_state_trans_complete_we;
+ logic intr_state_tx_empty_qs;
+ logic intr_state_tx_empty_wd;
+ logic intr_state_tx_empty_we;
+ logic intr_state_tx_nonempty_qs;
+ logic intr_state_tx_nonempty_wd;
+ logic intr_state_tx_nonempty_we;
+ logic intr_state_tx_overflow_qs;
+ logic intr_state_tx_overflow_wd;
+ logic intr_state_tx_overflow_we;
+ logic intr_state_acq_overflow_qs;
+ logic intr_state_acq_overflow_wd;
+ logic intr_state_acq_overflow_we;
+ logic intr_state_ack_stop_qs;
+ logic intr_state_ack_stop_wd;
+ logic intr_state_ack_stop_we;
logic intr_enable_fmt_watermark_qs;
logic intr_enable_fmt_watermark_wd;
logic intr_enable_fmt_watermark_we;
@@ -131,6 +146,21 @@
logic intr_enable_trans_complete_qs;
logic intr_enable_trans_complete_wd;
logic intr_enable_trans_complete_we;
+ logic intr_enable_tx_empty_qs;
+ logic intr_enable_tx_empty_wd;
+ logic intr_enable_tx_empty_we;
+ logic intr_enable_tx_nonempty_qs;
+ logic intr_enable_tx_nonempty_wd;
+ logic intr_enable_tx_nonempty_we;
+ logic intr_enable_tx_overflow_qs;
+ logic intr_enable_tx_overflow_wd;
+ logic intr_enable_tx_overflow_we;
+ logic intr_enable_acq_overflow_qs;
+ logic intr_enable_acq_overflow_wd;
+ logic intr_enable_acq_overflow_we;
+ logic intr_enable_ack_stop_qs;
+ logic intr_enable_ack_stop_wd;
+ logic intr_enable_ack_stop_we;
logic intr_test_fmt_watermark_wd;
logic intr_test_fmt_watermark_we;
logic intr_test_rx_watermark_wd;
@@ -151,9 +181,22 @@
logic intr_test_sda_unstable_we;
logic intr_test_trans_complete_wd;
logic intr_test_trans_complete_we;
- logic ctrl_qs;
- logic ctrl_wd;
- logic ctrl_we;
+ logic intr_test_tx_empty_wd;
+ logic intr_test_tx_empty_we;
+ logic intr_test_tx_nonempty_wd;
+ logic intr_test_tx_nonempty_we;
+ logic intr_test_tx_overflow_wd;
+ logic intr_test_tx_overflow_we;
+ logic intr_test_acq_overflow_wd;
+ logic intr_test_acq_overflow_we;
+ logic intr_test_ack_stop_wd;
+ logic intr_test_ack_stop_we;
+ logic ctrl_enablehost_qs;
+ logic ctrl_enablehost_wd;
+ logic ctrl_enablehost_we;
+ logic ctrl_enabletarget_qs;
+ logic ctrl_enabletarget_wd;
+ logic ctrl_enabletarget_we;
logic status_fmtfull_qs;
logic status_fmtfull_re;
logic status_rxfull_qs;
@@ -166,6 +209,14 @@
logic status_targetidle_re;
logic status_rxempty_qs;
logic status_rxempty_re;
+ logic status_txfull_qs;
+ logic status_txfull_re;
+ logic status_acqfull_qs;
+ logic status_acqfull_re;
+ logic status_txempty_qs;
+ logic status_txempty_re;
+ logic status_acqempty_qs;
+ logic status_acqempty_re;
logic [7:0] rdata_qs;
logic rdata_re;
logic [7:0] fdata_fbyte_wd;
@@ -190,10 +241,18 @@
logic [1:0] fifo_ctrl_fmtilvl_qs;
logic [1:0] fifo_ctrl_fmtilvl_wd;
logic fifo_ctrl_fmtilvl_we;
+ logic fifo_ctrl_acqrst_wd;
+ logic fifo_ctrl_acqrst_we;
+ logic fifo_ctrl_txrst_wd;
+ logic fifo_ctrl_txrst_we;
logic [5:0] fifo_status_fmtlvl_qs;
logic fifo_status_fmtlvl_re;
+ logic [5:0] fifo_status_txlvl_qs;
+ logic fifo_status_txlvl_re;
logic [5:0] fifo_status_rxlvl_qs;
logic fifo_status_rxlvl_re;
+ logic [5:0] fifo_status_acqlvl_qs;
+ logic fifo_status_acqlvl_re;
logic ovrd_txovrden_qs;
logic ovrd_txovrden_wd;
logic ovrd_txovrden_we;
@@ -243,6 +302,24 @@
logic timeout_ctrl_en_qs;
logic timeout_ctrl_en_wd;
logic timeout_ctrl_en_we;
+ logic [6:0] target_id_address0_qs;
+ logic [6:0] target_id_address0_wd;
+ logic target_id_address0_we;
+ logic [6:0] target_id_mask0_qs;
+ logic [6:0] target_id_mask0_wd;
+ logic target_id_mask0_we;
+ logic [6:0] target_id_address1_qs;
+ logic [6:0] target_id_address1_wd;
+ logic target_id_address1_we;
+ logic [6:0] target_id_mask1_qs;
+ logic [6:0] target_id_mask1_wd;
+ logic target_id_mask1_we;
+ logic [7:0] acqdata_abyte_qs;
+ logic acqdata_abyte_re;
+ logic [1:0] acqdata_signal_qs;
+ logic acqdata_signal_re;
+ logic [7:0] txdata_wd;
+ logic txdata_we;
// Register instances
// R[intr_state]: V(False)
@@ -507,6 +584,136 @@
);
+ // F[tx_empty]: 10:10
+ prim_subreg #(
+ .DW (1),
+ .SWACCESS("W1C"),
+ .RESVAL (1'h0)
+ ) u_intr_state_tx_empty (
+ .clk_i (clk_i ),
+ .rst_ni (rst_ni ),
+
+ // from register interface
+ .we (intr_state_tx_empty_we),
+ .wd (intr_state_tx_empty_wd),
+
+ // from internal hardware
+ .de (hw2reg.intr_state.tx_empty.de),
+ .d (hw2reg.intr_state.tx_empty.d ),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.intr_state.tx_empty.q ),
+
+ // to register interface (read)
+ .qs (intr_state_tx_empty_qs)
+ );
+
+
+ // F[tx_nonempty]: 11:11
+ prim_subreg #(
+ .DW (1),
+ .SWACCESS("W1C"),
+ .RESVAL (1'h0)
+ ) u_intr_state_tx_nonempty (
+ .clk_i (clk_i ),
+ .rst_ni (rst_ni ),
+
+ // from register interface
+ .we (intr_state_tx_nonempty_we),
+ .wd (intr_state_tx_nonempty_wd),
+
+ // from internal hardware
+ .de (hw2reg.intr_state.tx_nonempty.de),
+ .d (hw2reg.intr_state.tx_nonempty.d ),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.intr_state.tx_nonempty.q ),
+
+ // to register interface (read)
+ .qs (intr_state_tx_nonempty_qs)
+ );
+
+
+ // F[tx_overflow]: 12:12
+ prim_subreg #(
+ .DW (1),
+ .SWACCESS("W1C"),
+ .RESVAL (1'h0)
+ ) u_intr_state_tx_overflow (
+ .clk_i (clk_i ),
+ .rst_ni (rst_ni ),
+
+ // from register interface
+ .we (intr_state_tx_overflow_we),
+ .wd (intr_state_tx_overflow_wd),
+
+ // from internal hardware
+ .de (hw2reg.intr_state.tx_overflow.de),
+ .d (hw2reg.intr_state.tx_overflow.d ),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.intr_state.tx_overflow.q ),
+
+ // to register interface (read)
+ .qs (intr_state_tx_overflow_qs)
+ );
+
+
+ // F[acq_overflow]: 13:13
+ prim_subreg #(
+ .DW (1),
+ .SWACCESS("W1C"),
+ .RESVAL (1'h0)
+ ) u_intr_state_acq_overflow (
+ .clk_i (clk_i ),
+ .rst_ni (rst_ni ),
+
+ // from register interface
+ .we (intr_state_acq_overflow_we),
+ .wd (intr_state_acq_overflow_wd),
+
+ // from internal hardware
+ .de (hw2reg.intr_state.acq_overflow.de),
+ .d (hw2reg.intr_state.acq_overflow.d ),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.intr_state.acq_overflow.q ),
+
+ // to register interface (read)
+ .qs (intr_state_acq_overflow_qs)
+ );
+
+
+ // F[ack_stop]: 14:14
+ prim_subreg #(
+ .DW (1),
+ .SWACCESS("W1C"),
+ .RESVAL (1'h0)
+ ) u_intr_state_ack_stop (
+ .clk_i (clk_i ),
+ .rst_ni (rst_ni ),
+
+ // from register interface
+ .we (intr_state_ack_stop_we),
+ .wd (intr_state_ack_stop_wd),
+
+ // from internal hardware
+ .de (hw2reg.intr_state.ack_stop.de),
+ .d (hw2reg.intr_state.ack_stop.d ),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.intr_state.ack_stop.q ),
+
+ // to register interface (read)
+ .qs (intr_state_ack_stop_qs)
+ );
+
+
// R[intr_enable]: V(False)
// F[fmt_watermark]: 0:0
@@ -769,6 +976,136 @@
);
+ // F[tx_empty]: 10:10
+ prim_subreg #(
+ .DW (1),
+ .SWACCESS("RW"),
+ .RESVAL (1'h0)
+ ) u_intr_enable_tx_empty (
+ .clk_i (clk_i ),
+ .rst_ni (rst_ni ),
+
+ // from register interface
+ .we (intr_enable_tx_empty_we),
+ .wd (intr_enable_tx_empty_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0 ),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.intr_enable.tx_empty.q ),
+
+ // to register interface (read)
+ .qs (intr_enable_tx_empty_qs)
+ );
+
+
+ // F[tx_nonempty]: 11:11
+ prim_subreg #(
+ .DW (1),
+ .SWACCESS("RW"),
+ .RESVAL (1'h0)
+ ) u_intr_enable_tx_nonempty (
+ .clk_i (clk_i ),
+ .rst_ni (rst_ni ),
+
+ // from register interface
+ .we (intr_enable_tx_nonempty_we),
+ .wd (intr_enable_tx_nonempty_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0 ),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.intr_enable.tx_nonempty.q ),
+
+ // to register interface (read)
+ .qs (intr_enable_tx_nonempty_qs)
+ );
+
+
+ // F[tx_overflow]: 12:12
+ prim_subreg #(
+ .DW (1),
+ .SWACCESS("RW"),
+ .RESVAL (1'h0)
+ ) u_intr_enable_tx_overflow (
+ .clk_i (clk_i ),
+ .rst_ni (rst_ni ),
+
+ // from register interface
+ .we (intr_enable_tx_overflow_we),
+ .wd (intr_enable_tx_overflow_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0 ),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.intr_enable.tx_overflow.q ),
+
+ // to register interface (read)
+ .qs (intr_enable_tx_overflow_qs)
+ );
+
+
+ // F[acq_overflow]: 13:13
+ prim_subreg #(
+ .DW (1),
+ .SWACCESS("RW"),
+ .RESVAL (1'h0)
+ ) u_intr_enable_acq_overflow (
+ .clk_i (clk_i ),
+ .rst_ni (rst_ni ),
+
+ // from register interface
+ .we (intr_enable_acq_overflow_we),
+ .wd (intr_enable_acq_overflow_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0 ),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.intr_enable.acq_overflow.q ),
+
+ // to register interface (read)
+ .qs (intr_enable_acq_overflow_qs)
+ );
+
+
+ // F[ack_stop]: 14:14
+ prim_subreg #(
+ .DW (1),
+ .SWACCESS("RW"),
+ .RESVAL (1'h0)
+ ) u_intr_enable_ack_stop (
+ .clk_i (clk_i ),
+ .rst_ni (rst_ni ),
+
+ // from register interface
+ .we (intr_enable_ack_stop_we),
+ .wd (intr_enable_ack_stop_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0 ),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.intr_enable.ack_stop.q ),
+
+ // to register interface (read)
+ .qs (intr_enable_ack_stop_qs)
+ );
+
+
// R[intr_test]: V(True)
// F[fmt_watermark]: 0:0
@@ -921,19 +1258,95 @@
);
+ // F[tx_empty]: 10:10
+ prim_subreg_ext #(
+ .DW (1)
+ ) u_intr_test_tx_empty (
+ .re (1'b0),
+ .we (intr_test_tx_empty_we),
+ .wd (intr_test_tx_empty_wd),
+ .d ('0),
+ .qre (),
+ .qe (reg2hw.intr_test.tx_empty.qe),
+ .q (reg2hw.intr_test.tx_empty.q ),
+ .qs ()
+ );
+
+
+ // F[tx_nonempty]: 11:11
+ prim_subreg_ext #(
+ .DW (1)
+ ) u_intr_test_tx_nonempty (
+ .re (1'b0),
+ .we (intr_test_tx_nonempty_we),
+ .wd (intr_test_tx_nonempty_wd),
+ .d ('0),
+ .qre (),
+ .qe (reg2hw.intr_test.tx_nonempty.qe),
+ .q (reg2hw.intr_test.tx_nonempty.q ),
+ .qs ()
+ );
+
+
+ // F[tx_overflow]: 12:12
+ prim_subreg_ext #(
+ .DW (1)
+ ) u_intr_test_tx_overflow (
+ .re (1'b0),
+ .we (intr_test_tx_overflow_we),
+ .wd (intr_test_tx_overflow_wd),
+ .d ('0),
+ .qre (),
+ .qe (reg2hw.intr_test.tx_overflow.qe),
+ .q (reg2hw.intr_test.tx_overflow.q ),
+ .qs ()
+ );
+
+
+ // F[acq_overflow]: 13:13
+ prim_subreg_ext #(
+ .DW (1)
+ ) u_intr_test_acq_overflow (
+ .re (1'b0),
+ .we (intr_test_acq_overflow_we),
+ .wd (intr_test_acq_overflow_wd),
+ .d ('0),
+ .qre (),
+ .qe (reg2hw.intr_test.acq_overflow.qe),
+ .q (reg2hw.intr_test.acq_overflow.q ),
+ .qs ()
+ );
+
+
+ // F[ack_stop]: 14:14
+ prim_subreg_ext #(
+ .DW (1)
+ ) u_intr_test_ack_stop (
+ .re (1'b0),
+ .we (intr_test_ack_stop_we),
+ .wd (intr_test_ack_stop_wd),
+ .d ('0),
+ .qre (),
+ .qe (reg2hw.intr_test.ack_stop.qe),
+ .q (reg2hw.intr_test.ack_stop.q ),
+ .qs ()
+ );
+
+
// R[ctrl]: V(False)
+ // F[enablehost]: 0:0
prim_subreg #(
.DW (1),
.SWACCESS("RW"),
.RESVAL (1'h0)
- ) u_ctrl (
+ ) u_ctrl_enablehost (
.clk_i (clk_i ),
.rst_ni (rst_ni ),
// from register interface
- .we (ctrl_we),
- .wd (ctrl_wd),
+ .we (ctrl_enablehost_we),
+ .wd (ctrl_enablehost_wd),
// from internal hardware
.de (1'b0),
@@ -941,10 +1354,36 @@
// to internal hardware
.qe (),
- .q (reg2hw.ctrl.q ),
+ .q (reg2hw.ctrl.enablehost.q ),
// to register interface (read)
- .qs (ctrl_qs)
+ .qs (ctrl_enablehost_qs)
+ );
+
+
+ // F[enabletarget]: 1:1
+ prim_subreg #(
+ .DW (1),
+ .SWACCESS("RW"),
+ .RESVAL (1'h0)
+ ) u_ctrl_enabletarget (
+ .clk_i (clk_i ),
+ .rst_ni (rst_ni ),
+
+ // from register interface
+ .we (ctrl_enabletarget_we),
+ .wd (ctrl_enabletarget_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0 ),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.ctrl.enabletarget.q ),
+
+ // to register interface (read)
+ .qs (ctrl_enabletarget_qs)
);
@@ -1040,6 +1479,66 @@
);
+ // F[txfull]: 6:6
+ prim_subreg_ext #(
+ .DW (1)
+ ) u_status_txfull (
+ .re (status_txfull_re),
+ .we (1'b0),
+ .wd ('0),
+ .d (hw2reg.status.txfull.d),
+ .qre (),
+ .qe (),
+ .q (),
+ .qs (status_txfull_qs)
+ );
+
+
+ // F[acqfull]: 7:7
+ prim_subreg_ext #(
+ .DW (1)
+ ) u_status_acqfull (
+ .re (status_acqfull_re),
+ .we (1'b0),
+ .wd ('0),
+ .d (hw2reg.status.acqfull.d),
+ .qre (),
+ .qe (),
+ .q (),
+ .qs (status_acqfull_qs)
+ );
+
+
+ // F[txempty]: 8:8
+ prim_subreg_ext #(
+ .DW (1)
+ ) u_status_txempty (
+ .re (status_txempty_re),
+ .we (1'b0),
+ .wd ('0),
+ .d (hw2reg.status.txempty.d),
+ .qre (),
+ .qe (),
+ .q (),
+ .qs (status_txempty_qs)
+ );
+
+
+ // F[acqempty]: 9:9
+ prim_subreg_ext #(
+ .DW (1)
+ ) u_status_acqempty (
+ .re (status_acqempty_re),
+ .we (1'b0),
+ .wd ('0),
+ .d (hw2reg.status.acqempty.d),
+ .qre (),
+ .qe (),
+ .q (),
+ .qs (status_acqempty_qs)
+ );
+
+
// R[rdata]: V(True)
prim_subreg_ext #(
@@ -1312,6 +1811,56 @@
);
+ // F[acqrst]: 7:7
+ prim_subreg #(
+ .DW (1),
+ .SWACCESS("WO"),
+ .RESVAL (1'h0)
+ ) u_fifo_ctrl_acqrst (
+ .clk_i (clk_i ),
+ .rst_ni (rst_ni ),
+
+ // from register interface
+ .we (fifo_ctrl_acqrst_we),
+ .wd (fifo_ctrl_acqrst_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0 ),
+
+ // to internal hardware
+ .qe (reg2hw.fifo_ctrl.acqrst.qe),
+ .q (reg2hw.fifo_ctrl.acqrst.q ),
+
+ .qs ()
+ );
+
+
+ // F[txrst]: 8:8
+ prim_subreg #(
+ .DW (1),
+ .SWACCESS("WO"),
+ .RESVAL (1'h0)
+ ) u_fifo_ctrl_txrst (
+ .clk_i (clk_i ),
+ .rst_ni (rst_ni ),
+
+ // from register interface
+ .we (fifo_ctrl_txrst_we),
+ .wd (fifo_ctrl_txrst_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0 ),
+
+ // to internal hardware
+ .qe (reg2hw.fifo_ctrl.txrst.qe),
+ .q (reg2hw.fifo_ctrl.txrst.q ),
+
+ .qs ()
+ );
+
+
// R[fifo_status]: V(True)
// F[fmtlvl]: 5:0
@@ -1329,6 +1878,21 @@
);
+ // F[txlvl]: 13:8
+ prim_subreg_ext #(
+ .DW (6)
+ ) u_fifo_status_txlvl (
+ .re (fifo_status_txlvl_re),
+ .we (1'b0),
+ .wd ('0),
+ .d (hw2reg.fifo_status.txlvl.d),
+ .qre (),
+ .qe (),
+ .q (),
+ .qs (fifo_status_txlvl_qs)
+ );
+
+
// F[rxlvl]: 21:16
prim_subreg_ext #(
.DW (6)
@@ -1344,6 +1908,21 @@
);
+ // F[acqlvl]: 29:24
+ prim_subreg_ext #(
+ .DW (6)
+ ) u_fifo_status_acqlvl (
+ .re (fifo_status_acqlvl_re),
+ .we (1'b0),
+ .wd ('0),
+ .d (hw2reg.fifo_status.acqlvl.d),
+ .qre (),
+ .qe (),
+ .q (),
+ .qs (fifo_status_acqlvl_qs)
+ );
+
+
// R[ovrd]: V(False)
// F[txovrden]: 0:0
@@ -1780,9 +2359,173 @@
);
+ // R[target_id]: V(False)
+
+ // F[address0]: 6:0
+ prim_subreg #(
+ .DW (7),
+ .SWACCESS("RW"),
+ .RESVAL (7'h0)
+ ) u_target_id_address0 (
+ .clk_i (clk_i ),
+ .rst_ni (rst_ni ),
+
+ // from register interface
+ .we (target_id_address0_we),
+ .wd (target_id_address0_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0 ),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.target_id.address0.q ),
+
+ // to register interface (read)
+ .qs (target_id_address0_qs)
+ );
- logic [16:0] addr_hit;
+ // F[mask0]: 13:7
+ prim_subreg #(
+ .DW (7),
+ .SWACCESS("RW"),
+ .RESVAL (7'h0)
+ ) u_target_id_mask0 (
+ .clk_i (clk_i ),
+ .rst_ni (rst_ni ),
+
+ // from register interface
+ .we (target_id_mask0_we),
+ .wd (target_id_mask0_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0 ),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.target_id.mask0.q ),
+
+ // to register interface (read)
+ .qs (target_id_mask0_qs)
+ );
+
+
+ // F[address1]: 20:14
+ prim_subreg #(
+ .DW (7),
+ .SWACCESS("RW"),
+ .RESVAL (7'h0)
+ ) u_target_id_address1 (
+ .clk_i (clk_i ),
+ .rst_ni (rst_ni ),
+
+ // from register interface
+ .we (target_id_address1_we),
+ .wd (target_id_address1_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0 ),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.target_id.address1.q ),
+
+ // to register interface (read)
+ .qs (target_id_address1_qs)
+ );
+
+
+ // F[mask1]: 27:21
+ prim_subreg #(
+ .DW (7),
+ .SWACCESS("RW"),
+ .RESVAL (7'h0)
+ ) u_target_id_mask1 (
+ .clk_i (clk_i ),
+ .rst_ni (rst_ni ),
+
+ // from register interface
+ .we (target_id_mask1_we),
+ .wd (target_id_mask1_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0 ),
+
+ // to internal hardware
+ .qe (),
+ .q (reg2hw.target_id.mask1.q ),
+
+ // to register interface (read)
+ .qs (target_id_mask1_qs)
+ );
+
+
+ // R[acqdata]: V(True)
+
+ // F[abyte]: 7:0
+ prim_subreg_ext #(
+ .DW (8)
+ ) u_acqdata_abyte (
+ .re (acqdata_abyte_re),
+ .we (1'b0),
+ .wd ('0),
+ .d (hw2reg.acqdata.abyte.d),
+ .qre (reg2hw.acqdata.abyte.re),
+ .qe (),
+ .q (reg2hw.acqdata.abyte.q ),
+ .qs (acqdata_abyte_qs)
+ );
+
+
+ // F[signal]: 9:8
+ prim_subreg_ext #(
+ .DW (2)
+ ) u_acqdata_signal (
+ .re (acqdata_signal_re),
+ .we (1'b0),
+ .wd ('0),
+ .d (hw2reg.acqdata.signal.d),
+ .qre (reg2hw.acqdata.signal.re),
+ .qe (),
+ .q (reg2hw.acqdata.signal.q ),
+ .qs (acqdata_signal_qs)
+ );
+
+
+ // R[txdata]: V(False)
+
+ prim_subreg #(
+ .DW (8),
+ .SWACCESS("WO"),
+ .RESVAL (8'h0)
+ ) u_txdata (
+ .clk_i (clk_i ),
+ .rst_ni (rst_ni ),
+
+ // from register interface
+ .we (txdata_we),
+ .wd (txdata_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0 ),
+
+ // to internal hardware
+ .qe (reg2hw.txdata.qe),
+ .q (reg2hw.txdata.q ),
+
+ .qs ()
+ );
+
+
+
+
+ logic [19:0] addr_hit;
always_comb begin
addr_hit = '0;
addr_hit[ 0] = (reg_addr == I2C_INTR_STATE_OFFSET);
@@ -1802,6 +2545,9 @@
addr_hit[14] = (reg_addr == I2C_TIMING3_OFFSET);
addr_hit[15] = (reg_addr == I2C_TIMING4_OFFSET);
addr_hit[16] = (reg_addr == I2C_TIMEOUT_CTRL_OFFSET);
+ addr_hit[17] = (reg_addr == I2C_TARGET_ID_OFFSET);
+ addr_hit[18] = (reg_addr == I2C_ACQDATA_OFFSET);
+ addr_hit[19] = (reg_addr == I2C_TXDATA_OFFSET);
end
assign addrmiss = (reg_re || reg_we) ? ~|addr_hit : 1'b0 ;
@@ -1826,6 +2572,9 @@
if (addr_hit[14] && reg_we && (I2C_PERMIT[14] != (I2C_PERMIT[14] & reg_be))) wr_err = 1'b1 ;
if (addr_hit[15] && reg_we && (I2C_PERMIT[15] != (I2C_PERMIT[15] & reg_be))) wr_err = 1'b1 ;
if (addr_hit[16] && reg_we && (I2C_PERMIT[16] != (I2C_PERMIT[16] & reg_be))) wr_err = 1'b1 ;
+ if (addr_hit[17] && reg_we && (I2C_PERMIT[17] != (I2C_PERMIT[17] & reg_be))) wr_err = 1'b1 ;
+ if (addr_hit[18] && reg_we && (I2C_PERMIT[18] != (I2C_PERMIT[18] & reg_be))) wr_err = 1'b1 ;
+ if (addr_hit[19] && reg_we && (I2C_PERMIT[19] != (I2C_PERMIT[19] & reg_be))) wr_err = 1'b1 ;
end
assign intr_state_fmt_watermark_we = addr_hit[0] & reg_we & ~wr_err;
@@ -1858,6 +2607,21 @@
assign intr_state_trans_complete_we = addr_hit[0] & reg_we & ~wr_err;
assign intr_state_trans_complete_wd = reg_wdata[9];
+ assign intr_state_tx_empty_we = addr_hit[0] & reg_we & ~wr_err;
+ assign intr_state_tx_empty_wd = reg_wdata[10];
+
+ assign intr_state_tx_nonempty_we = addr_hit[0] & reg_we & ~wr_err;
+ assign intr_state_tx_nonempty_wd = reg_wdata[11];
+
+ assign intr_state_tx_overflow_we = addr_hit[0] & reg_we & ~wr_err;
+ assign intr_state_tx_overflow_wd = reg_wdata[12];
+
+ assign intr_state_acq_overflow_we = addr_hit[0] & reg_we & ~wr_err;
+ assign intr_state_acq_overflow_wd = reg_wdata[13];
+
+ assign intr_state_ack_stop_we = addr_hit[0] & reg_we & ~wr_err;
+ assign intr_state_ack_stop_wd = reg_wdata[14];
+
assign intr_enable_fmt_watermark_we = addr_hit[1] & reg_we & ~wr_err;
assign intr_enable_fmt_watermark_wd = reg_wdata[0];
@@ -1888,6 +2652,21 @@
assign intr_enable_trans_complete_we = addr_hit[1] & reg_we & ~wr_err;
assign intr_enable_trans_complete_wd = reg_wdata[9];
+ assign intr_enable_tx_empty_we = addr_hit[1] & reg_we & ~wr_err;
+ assign intr_enable_tx_empty_wd = reg_wdata[10];
+
+ assign intr_enable_tx_nonempty_we = addr_hit[1] & reg_we & ~wr_err;
+ assign intr_enable_tx_nonempty_wd = reg_wdata[11];
+
+ assign intr_enable_tx_overflow_we = addr_hit[1] & reg_we & ~wr_err;
+ assign intr_enable_tx_overflow_wd = reg_wdata[12];
+
+ assign intr_enable_acq_overflow_we = addr_hit[1] & reg_we & ~wr_err;
+ assign intr_enable_acq_overflow_wd = reg_wdata[13];
+
+ assign intr_enable_ack_stop_we = addr_hit[1] & reg_we & ~wr_err;
+ assign intr_enable_ack_stop_wd = reg_wdata[14];
+
assign intr_test_fmt_watermark_we = addr_hit[2] & reg_we & ~wr_err;
assign intr_test_fmt_watermark_wd = reg_wdata[0];
@@ -1918,8 +2697,26 @@
assign intr_test_trans_complete_we = addr_hit[2] & reg_we & ~wr_err;
assign intr_test_trans_complete_wd = reg_wdata[9];
- assign ctrl_we = addr_hit[3] & reg_we & ~wr_err;
- assign ctrl_wd = reg_wdata[0];
+ assign intr_test_tx_empty_we = addr_hit[2] & reg_we & ~wr_err;
+ assign intr_test_tx_empty_wd = reg_wdata[10];
+
+ assign intr_test_tx_nonempty_we = addr_hit[2] & reg_we & ~wr_err;
+ assign intr_test_tx_nonempty_wd = reg_wdata[11];
+
+ assign intr_test_tx_overflow_we = addr_hit[2] & reg_we & ~wr_err;
+ assign intr_test_tx_overflow_wd = reg_wdata[12];
+
+ assign intr_test_acq_overflow_we = addr_hit[2] & reg_we & ~wr_err;
+ assign intr_test_acq_overflow_wd = reg_wdata[13];
+
+ assign intr_test_ack_stop_we = addr_hit[2] & reg_we & ~wr_err;
+ assign intr_test_ack_stop_wd = reg_wdata[14];
+
+ assign ctrl_enablehost_we = addr_hit[3] & reg_we & ~wr_err;
+ assign ctrl_enablehost_wd = reg_wdata[0];
+
+ assign ctrl_enabletarget_we = addr_hit[3] & reg_we & ~wr_err;
+ assign ctrl_enabletarget_wd = reg_wdata[1];
assign status_fmtfull_re = addr_hit[4] && reg_re;
@@ -1933,6 +2730,14 @@
assign status_rxempty_re = addr_hit[4] && reg_re;
+ assign status_txfull_re = addr_hit[4] && reg_re;
+
+ assign status_acqfull_re = addr_hit[4] && reg_re;
+
+ assign status_txempty_re = addr_hit[4] && reg_re;
+
+ assign status_acqempty_re = addr_hit[4] && reg_re;
+
assign rdata_re = addr_hit[5] && reg_re;
assign fdata_fbyte_we = addr_hit[6] & reg_we & ~wr_err;
@@ -1965,10 +2770,20 @@
assign fifo_ctrl_fmtilvl_we = addr_hit[7] & reg_we & ~wr_err;
assign fifo_ctrl_fmtilvl_wd = reg_wdata[6:5];
+ assign fifo_ctrl_acqrst_we = addr_hit[7] & reg_we & ~wr_err;
+ assign fifo_ctrl_acqrst_wd = reg_wdata[7];
+
+ assign fifo_ctrl_txrst_we = addr_hit[7] & reg_we & ~wr_err;
+ assign fifo_ctrl_txrst_wd = reg_wdata[8];
+
assign fifo_status_fmtlvl_re = addr_hit[8] && reg_re;
+ assign fifo_status_txlvl_re = addr_hit[8] && reg_re;
+
assign fifo_status_rxlvl_re = addr_hit[8] && reg_re;
+ assign fifo_status_acqlvl_re = addr_hit[8] && reg_re;
+
assign ovrd_txovrden_we = addr_hit[9] & reg_we & ~wr_err;
assign ovrd_txovrden_wd = reg_wdata[0];
@@ -2018,6 +2833,25 @@
assign timeout_ctrl_en_we = addr_hit[16] & reg_we & ~wr_err;
assign timeout_ctrl_en_wd = reg_wdata[31];
+ assign target_id_address0_we = addr_hit[17] & reg_we & ~wr_err;
+ assign target_id_address0_wd = reg_wdata[6:0];
+
+ assign target_id_mask0_we = addr_hit[17] & reg_we & ~wr_err;
+ assign target_id_mask0_wd = reg_wdata[13:7];
+
+ assign target_id_address1_we = addr_hit[17] & reg_we & ~wr_err;
+ assign target_id_address1_wd = reg_wdata[20:14];
+
+ assign target_id_mask1_we = addr_hit[17] & reg_we & ~wr_err;
+ assign target_id_mask1_wd = reg_wdata[27:21];
+
+ assign acqdata_abyte_re = addr_hit[18] && reg_re;
+
+ assign acqdata_signal_re = addr_hit[18] && reg_re;
+
+ assign txdata_we = addr_hit[19] & reg_we & ~wr_err;
+ assign txdata_wd = reg_wdata[7:0];
+
// Read data return
always_comb begin
reg_rdata_next = '0;
@@ -2033,6 +2867,11 @@
reg_rdata_next[7] = intr_state_stretch_timeout_qs;
reg_rdata_next[8] = intr_state_sda_unstable_qs;
reg_rdata_next[9] = intr_state_trans_complete_qs;
+ reg_rdata_next[10] = intr_state_tx_empty_qs;
+ reg_rdata_next[11] = intr_state_tx_nonempty_qs;
+ reg_rdata_next[12] = intr_state_tx_overflow_qs;
+ reg_rdata_next[13] = intr_state_acq_overflow_qs;
+ reg_rdata_next[14] = intr_state_ack_stop_qs;
end
addr_hit[1]: begin
@@ -2046,6 +2885,11 @@
reg_rdata_next[7] = intr_enable_stretch_timeout_qs;
reg_rdata_next[8] = intr_enable_sda_unstable_qs;
reg_rdata_next[9] = intr_enable_trans_complete_qs;
+ reg_rdata_next[10] = intr_enable_tx_empty_qs;
+ reg_rdata_next[11] = intr_enable_tx_nonempty_qs;
+ reg_rdata_next[12] = intr_enable_tx_overflow_qs;
+ reg_rdata_next[13] = intr_enable_acq_overflow_qs;
+ reg_rdata_next[14] = intr_enable_ack_stop_qs;
end
addr_hit[2]: begin
@@ -2059,10 +2903,16 @@
reg_rdata_next[7] = '0;
reg_rdata_next[8] = '0;
reg_rdata_next[9] = '0;
+ reg_rdata_next[10] = '0;
+ reg_rdata_next[11] = '0;
+ reg_rdata_next[12] = '0;
+ reg_rdata_next[13] = '0;
+ reg_rdata_next[14] = '0;
end
addr_hit[3]: begin
- reg_rdata_next[0] = ctrl_qs;
+ reg_rdata_next[0] = ctrl_enablehost_qs;
+ reg_rdata_next[1] = ctrl_enabletarget_qs;
end
addr_hit[4]: begin
@@ -2072,6 +2922,10 @@
reg_rdata_next[3] = status_hostidle_qs;
reg_rdata_next[4] = status_targetidle_qs;
reg_rdata_next[5] = status_rxempty_qs;
+ reg_rdata_next[6] = status_txfull_qs;
+ reg_rdata_next[7] = status_acqfull_qs;
+ reg_rdata_next[8] = status_txempty_qs;
+ reg_rdata_next[9] = status_acqempty_qs;
end
addr_hit[5]: begin
@@ -2092,11 +2946,15 @@
reg_rdata_next[1] = '0;
reg_rdata_next[4:2] = fifo_ctrl_rxilvl_qs;
reg_rdata_next[6:5] = fifo_ctrl_fmtilvl_qs;
+ reg_rdata_next[7] = '0;
+ reg_rdata_next[8] = '0;
end
addr_hit[8]: begin
reg_rdata_next[5:0] = fifo_status_fmtlvl_qs;
+ reg_rdata_next[13:8] = fifo_status_txlvl_qs;
reg_rdata_next[21:16] = fifo_status_rxlvl_qs;
+ reg_rdata_next[29:24] = fifo_status_acqlvl_qs;
end
addr_hit[9]: begin
@@ -2140,6 +2998,22 @@
reg_rdata_next[31] = timeout_ctrl_en_qs;
end
+ addr_hit[17]: begin
+ reg_rdata_next[6:0] = target_id_address0_qs;
+ reg_rdata_next[13:7] = target_id_mask0_qs;
+ reg_rdata_next[20:14] = target_id_address1_qs;
+ reg_rdata_next[27:21] = target_id_mask1_qs;
+ end
+
+ addr_hit[18]: begin
+ reg_rdata_next[7:0] = acqdata_abyte_qs;
+ reg_rdata_next[9:8] = acqdata_signal_qs;
+ end
+
+ addr_hit[19]: begin
+ reg_rdata_next[7:0] = '0;
+ end
+
default: begin
reg_rdata_next = '1;
end
