[doc] Rename Hardware -> Development Stages
In advance of adding Device Interface Function (DIF) stage tracking to
the development stages, this change renames `doc/project/hw_stages.md`
to `doc/project/development_stages.md` and updates all the links that
reference it.
Signed-off-by: Sam Elliott <selliott@lowrisc.org>
diff --git a/doc/project/_index.md b/doc/project/_index.md
index 8985af8..008bda1 100644
--- a/doc/project/_index.md
+++ b/doc/project/_index.md
@@ -8,7 +8,7 @@
## Quality standards for open hardware IP
-In order to gauge the quality of the different IP that is in our repository, we define a series of [Hardware Development Stages]({{< relref "hw_stages" >}}) to track the designs.
+In order to gauge the quality of the different IP that is in our repository, we define a series of [Hardware Development Stages]({{< relref "development_stages" >}}) to track the designs.
The current status of different IP is reflected in the [Hardware Dashboard]({{< relref "hw" >}}).
The final state for developed IP is *Signed Off*, indicating that design and verification is complete, and the IP should be bug free.
To make it to that stage, a [Hardware Signoff Checklist]({{< relref "checklist.md" >}}) is used to confirm completion.
diff --git a/doc/project/checklist.md b/doc/project/checklist.md
index c5e4199..9625d3b 100644
--- a/doc/project/checklist.md
+++ b/doc/project/checklist.md
@@ -2,7 +2,7 @@
title: "Signoff Checklist"
---
-This document explains the recommended checklist items to review when transitioning from one [Hardware Stage]({{<relref "/doc/project/hw_stages.md" >}}) to another, for both design and verification stages.
+This document explains the recommended checklist items to review when transitioning from one [Hardware Stage]({{<relref "/doc/project/development_stages.md" >}}) to another, for both design and verification stages.
It is expected that the items in each stage (D1, V1, etc) are completed.
## D1
diff --git a/doc/project/hw_stages.md b/doc/project/development_stages.md
similarity index 99%
rename from doc/project/hw_stages.md
rename to doc/project/development_stages.md
index 93c6b18..8aa84da 100644
--- a/doc/project/hw_stages.md
+++ b/doc/project/development_stages.md
@@ -1,3 +1,7 @@
+---
+aliases: [/doc/project/hw_stages/]
+---
+
# OpenTitan Hardware Development Stages
## Document Goals
diff --git a/doc/ug/design.md b/doc/ug/design.md
index 1ab59f9..d6389d2 100644
--- a/doc/ug/design.md
+++ b/doc/ug/design.md
@@ -35,7 +35,7 @@
Designs within the OpenTitan project come in a variety of completion status levels.
Some designs are "tapeout ready" while others are still a work in progress.
Understanding the status of a design is important to gauge the confidence in its advertised feature set.
-To that end, we've designated a spectrum of design stages in the [OpenTitan Hardware Development Stages]({{< relref "doc/project/hw_stages.md" >}}) document.
+To that end, we've designated a spectrum of design stages in the [OpenTitan Hardware Development Stages]({{< relref "doc/project/development_stages.md" >}}) document.
This document defines the design stages and references where one can find the current status of each of the designs in the repository.
## Documentation
@@ -85,7 +85,7 @@
Note that all designs with enabled AscentLint targets will be run through the tool in eight-hour intervals and the results are published as part of the tool dashboards on the [hardware IP overview page](https://docs.opentitan.org/hw), enabling designers to close the lint errors and warnings even if they cannot run the sign-off tool locally.
-Goals for linting closure per design milestone are given in the [OpenTitan Development Stages]({{< relref "doc/project/hw_stages" >}}) document.
+Goals for linting closure per design milestone are given in the [OpenTitan Development Stages]({{< relref "doc/project/development_stages" >}}) document.
## Assertion Methodology
diff --git a/doc/ug/dv_methodology.md b/doc/ug/dv_methodology.md
index 3ce4e3b..3353f0e 100644
--- a/doc/ug/dv_methodology.md
+++ b/doc/ug/dv_methodology.md
@@ -33,7 +33,7 @@
Verification within the OpenTitan project comes in a variety of completion status levels.
Some designs are "tapeout ready" while others are still a work in progress.
Understanding the status of verification is important to gauge the confidence in the design's advertised feature set.
-To that end, we've designated a spectrum of design and verification stages in the [OpenTitan Hardware Development Stages]({{< relref "doc/project/hw_stages.md" >}}) document.
+To that end, we've designated a spectrum of design and verification stages in the [OpenTitan Hardware Development Stages]({{< relref "doc/project/development_stages.md" >}}) document.
It defines the verification stages and references where one can find the current verification status of each of the designs in the repository.
Splitting the effort in such a way enables the team to pace the development effort and allows the progress to be in lock-step with the design stages.
The list of tasks that are required to be completed to enable the effort to transition from one stage to the next is defined in the [checklists]({{< relref "doc/project/checklist" >}}) document.
@@ -44,7 +44,7 @@
DV effort needs to be well documented to not only provide a detailed description of what tests are being planned, but also how the overall effort is strategized and implemented.
The first is provided by the **testplan** document and the second, by the **DV plan** document.
-The [**project status**]({{< relref "doc/project/hw_stages.md#indicating-stages-and-making-transitions" >}}) document tracks to progression of the effort through the stages.
+The [**project status**]({{< relref "doc/project/development_stages.md#indicating-stages-and-making-transitions" >}}) document tracks to progression of the effort through the stages.
In addition to these documents, a nightly **regression dashboard** tabulating the test and coverage results will provide ability to track progress towards completion of the verification stages.
@@ -186,7 +186,7 @@
When progressing through the verification stages, there are key focus areas or testing activities that are perhaps common across all DUTs.
These are as follows.
-### Progressing towards [V1]({{< relref "doc/project/hw_stages#hardware-verification-stages" >}})
+### Progressing towards [V1]({{< relref "doc/project/development_stages#hardware-verification-stages" >}})
These set of tests (not exhaustive) provide the confidence that the design is ready for vertical integration.
@@ -203,7 +203,7 @@
The very first set of real tests validate the SW interface laid out using the regtool.
These prove that the SW interface is solid and all assumptions in CSRs in terms of field descriptions and their accessibility are correctly captured and there are no address decode bugs.
-### Progressing towards [V2]({{< relref "doc/project/hw_stages#hardware-verification-stages" >}})
+### Progressing towards [V2]({{< relref "doc/project/development_stages#hardware-verification-stages" >}})
Bulk of testing in this stage focus on functionally testing the DUT.
There however are certain categories of tests that may need additional attention.
@@ -250,7 +250,7 @@
The level of constraints are then slowly eased to allow deeper state space exploration, until all areas of the DUT are satisfactorily stressed.
Stress tests are ideal for bug hunting and closing coverage.
-### Progressing towards [V3]({{< relref "doc/project/hw_stages#hardware-verification-stages" >}})
+### Progressing towards [V3]({{< relref "doc/project/development_stages#hardware-verification-stages" >}})
The main focus of testing at this stage is to meet our [regression](#nightly) and [coverage](#coverage-collection) goals.
Apart from that, there are cleanup activities to resolve all pending TODO items in the DV code base and fix all compile and run time warnings (if any) thrown by the simulator tools.
@@ -492,7 +492,7 @@
The feedback in this review flows both ways - the language in the design specification could be made more precise, or missing items in both, the design specification as well as in the testplan could be identified and added.
This enables the development stage to progress smoothly.
-Subsequently, the intermediate transitions within the verification stages are reviewed within the GitHub pull-request made for updating the checklist and the [project status]({{< relref "doc/project/hw_stages.md#indicating-stages-and-making-transitions" >}}).
+Subsequently, the intermediate transitions within the verification stages are reviewed within the GitHub pull-request made for updating the checklist and the [project status]({{< relref "doc/project/development_stages.md#indicating-stages-and-making-transitions" >}}).
Finally, after the verification effort is complete, there is a final sign-off review to ensure all checklist items are completed satisfactorily without any major exceptions or open issues.
diff --git a/doc/ug/getting_started_design.md b/doc/ug/getting_started_design.md
index b8e8c46..e13bf5e 100644
--- a/doc/ug/getting_started_design.md
+++ b/doc/ug/getting_started_design.md
@@ -13,7 +13,7 @@
## Stages of a Design
-The life stages of a design within the OpenTitan are described in the [Hardware Development Stages]({{< relref "doc/project/hw_stages.md" >}}) document.
+The life stages of a design within the OpenTitan are described in the [Hardware Development Stages]({{< relref "doc/project/development_stages.md" >}}) document.
This separates the life of the design into three broad stages: Specification, In Development, and Signed off.
This document attempts to give guidance on how to get going with the first stage and have a smooth transition into the Development stage.
They are not hard and fast rules but methods we have seen work well in the project.
@@ -76,7 +76,7 @@
## Full Design
-As the design develops within the OpenTitan repository, it transitions into "D0", "D1", etc., [design stages]({{< relref "doc/project/hw_stages.md" >}}) and will be eventually plugged into the top level.
+As the design develops within the OpenTitan repository, it transitions into "D0", "D1", etc., [design stages]({{< relref "doc/project/development_stages.md" >}}) and will be eventually plugged into the top level.
Following the recommended best practices for digestible pull requests suggests that continuing to stage the design from the initial skeleton into the full featured design is a good way to make steady progress without over-burdening the reviewers.
## Top Level Inclusion
diff --git a/doc/ug/getting_started_dv.md b/doc/ug/getting_started_dv.md
index 724aaf5..0e23691 100644
--- a/doc/ug/getting_started_dv.md
+++ b/doc/ug/getting_started_dv.md
@@ -8,7 +8,7 @@
## Stages of DV
-The life stages of a design / DV effort within the OpenTitan are described in the [Hardware Development Stages]({{< relref "doc/project/hw_stages.md" >}}) document.
+The life stages of a design / DV effort within the OpenTitan are described in the [Hardware Development Stages]({{< relref "doc/project/development_stages.md" >}}) document.
It separates the life of DV into three broad stages: Initial Work, Under Test and Testing Complete.
This document attempts to give guidance on how to get going with the first stage and have a smooth transition into the Under Test stage.
They are not hard and fast rules but methods we have seen work well in the project.
@@ -88,7 +88,7 @@
## Full DV
-Running the sanity and CSR suite of tests while making progress toward reaching the [V1 stage]({{< relref "doc/project/hw_stages#hardware-verification-stages" >}}) should provide a good reference in terms of how to develop tests as outlined in the testplan and running and debugging them.
+Running the sanity and CSR suite of tests while making progress toward reaching the [V1 stage]({{< relref "doc/project/development_stages#hardware-verification-stages" >}}) should provide a good reference in terms of how to develop tests as outlined in the testplan and running and debugging them.
Please refer to the [checklist]({{< relref "doc/project/checklist" >}}) to understand the key requirements for progressing through the subsequent verification stages and final signoff.
The [UART DV](https://github.com/lowRISC/opentitan/tree/master/hw/ip/uart/dv) area can be used as a canonical example for making progress.
diff --git a/hw/_index.md b/hw/_index.md
index 9a44680..9f2135b 100644
--- a/hw/_index.md
+++ b/hw/_index.md
@@ -8,7 +8,7 @@
This includes DV simulations, FPV and lint, all of which are run with the `dvsim` tool which serves as the common frontend.
The [Comportable IPs](#comportable-ips) following it provides links to their design specifications and DV plans, and tracks their current stage of development.
-See the [Hardware Development Stages]({{< relref "/doc/project/hw_stages.md" >}}) for description of the hardware stages and how they are determined.
+See the [Hardware Development Stages]({{< relref "/doc/project/development_stages.md" >}}) for description of the hardware stages and how they are determined.
Next, we focus on all available [processor cores](#processor-cores) and provide links to their design specifications, DV plans and the DV simulation results.
diff --git a/hw/dv/doc/dv_plan_template.md b/hw/dv/doc/dv_plan_template.md
index 1e59979..0a636ba 100644
--- a/hw/dv/doc/dv_plan_template.md
+++ b/hw/dv/doc/dv_plan_template.md
@@ -20,7 +20,7 @@
## Current status
* [Design & verification stage]({{< relref "hw" >}})
- * [HW development stages]({{< relref "doc/project/hw_stages.md" >}})
+ * [HW development stages]({{< relref "doc/project/development_stages.md" >}})
* [Simulation results](https://reports.opentitan.org/hw/ip/foo/dv/latest/results.html)
## Design features
diff --git a/hw/ip/aes/doc/checklist.md b/hw/ip/aes/doc/checklist.md
index d49376a..66c6787 100644
--- a/hw/ip/aes/doc/checklist.md
+++ b/hw/ip/aes/doc/checklist.md
@@ -2,7 +2,7 @@
title: "AES Checklist"
---
-This checklist is for [Hardware Stage]({{< relref "/doc/project/hw_stages.md" >}}) transitions for the [AES peripheral.]({{<relref "hw/ip/aes/doc" >}})
+This checklist is for [Hardware Stage]({{< relref "/doc/project/development_stages.md" >}}) transitions for the [AES peripheral.]({{<relref "hw/ip/aes/doc" >}})
All checklist items refer to the content in the [Checklist.]({{< relref "/doc/project/checklist.md" >}})
## Design Checklist
diff --git a/hw/ip/aes/doc/dv_plan/index.md b/hw/ip/aes/doc/dv_plan/index.md
index 1fe7471..e8f0427 100644
--- a/hw/ip/aes/doc/dv_plan/index.md
+++ b/hw/ip/aes/doc/dv_plan/index.md
@@ -11,7 +11,7 @@
## Current status
* [Design & verification stage]({{< relref "hw" >}})
- * [HW development stages]({{< relref "doc/project/hw_stages.md" >}})
+ * [HW development stages]({{< relref "doc/project/development_stages.md" >}})
* [Simulation results](https://reports.opentitan.org/hw/ip/aes/dv/latest/results.html)
## Design features
diff --git a/hw/ip/alert_handler/doc/checklist.md b/hw/ip/alert_handler/doc/checklist.md
index aa14b74..41f8264 100644
--- a/hw/ip/alert_handler/doc/checklist.md
+++ b/hw/ip/alert_handler/doc/checklist.md
@@ -2,7 +2,7 @@
title: "Alert Handler Checklist"
---
-This checklist is for [Hardware Stage]({{< relref "/doc/project/hw_stages.md" >}}) transitions for the [Alert Handler peripheral.]({{< relref "./" >}})
+This checklist is for [Hardware Stage]({{< relref "/doc/project/development_stages.md" >}}) transitions for the [Alert Handler peripheral.]({{< relref "./" >}})
All checklist items refer to the content in the [Checklist.]({{< relref "/doc/project/checklist.md" >}})
## Design Checklist
diff --git a/hw/ip/alert_handler/doc/dv_plan/index.md b/hw/ip/alert_handler/doc/dv_plan/index.md
index d063539..b21c347 100644
--- a/hw/ip/alert_handler/doc/dv_plan/index.md
+++ b/hw/ip/alert_handler/doc/dv_plan/index.md
@@ -13,7 +13,7 @@
## Current status
* [Design & verification stage]({{< relref "hw" >}})
- * [HW development stages]({{< relref "doc/project/hw_stages" >}})
+ * [HW development stages]({{< relref "doc/project/development_stages" >}})
* [Simulation results](https://reports.opentitan.org/hw/ip/alert_handler/dv/latest/results.html)
## Design features
diff --git a/hw/ip/entropy_src/doc/checklist.md b/hw/ip/entropy_src/doc/checklist.md
index 1b9950b..eb7bfdd 100644
--- a/hw/ip/entropy_src/doc/checklist.md
+++ b/hw/ip/entropy_src/doc/checklist.md
@@ -2,7 +2,7 @@
title: "ENTROPY_SRC Checklist"
---
-This checklist is for [Hardware Stage]({{< relref "/doc/project/hw_stages.md" >}}) transitions for the [ENTROPY_SRC peripheral.]({{< relref "hw/ip/entropy_src/doc" >}})
+This checklist is for [Hardware Stage]({{< relref "/doc/project/development_stages.md" >}}) transitions for the [ENTROPY_SRC peripheral.]({{< relref "hw/ip/entropy_src/doc" >}})
All checklist items refer to the content in the [Checklist.]({{< relref "/doc/project/checklist.md" >}})
## Design Checklist
diff --git a/hw/ip/entropy_src/doc/dv_plan/index.md b/hw/ip/entropy_src/doc/dv_plan/index.md
index cf77ac2..58ae965 100644
--- a/hw/ip/entropy_src/doc/dv_plan/index.md
+++ b/hw/ip/entropy_src/doc/dv_plan/index.md
@@ -11,7 +11,7 @@
## Current status
* [Design & verification stage]({{< relref "hw" >}})
- * [HW development stages]({{< relref "doc/project/hw_stages" >}})
+ * [HW development stages]({{< relref "doc/project/development_stages" >}})
* [Simulation results](https://reports.opentitan.org/hw/ip/entropy_src/dv/latest/results.html)
## Design features
diff --git a/hw/ip/flash_ctrl/doc/checklist.md b/hw/ip/flash_ctrl/doc/checklist.md
index 73ef195..d953228 100644
--- a/hw/ip/flash_ctrl/doc/checklist.md
+++ b/hw/ip/flash_ctrl/doc/checklist.md
@@ -2,7 +2,7 @@
title: "FLASH_CTRL Checklist"
---
-This checklist is for [Hardware Stage]({{< relref "/doc/project/hw_stages.md" >}}) transitions for the [FLASH_CTRL peripheral.](../)
+This checklist is for [Hardware Stage]({{< relref "/doc/project/development_stages.md" >}}) transitions for the [FLASH_CTRL peripheral.](../)
All checklist items refer to the content in the [Checklist.]({{< relref "/doc/project/checklist.md" >}})
## Design Checklist
diff --git a/hw/ip/gpio/doc/checklist.md b/hw/ip/gpio/doc/checklist.md
index 0ca0eef..5e44a33 100644
--- a/hw/ip/gpio/doc/checklist.md
+++ b/hw/ip/gpio/doc/checklist.md
@@ -2,7 +2,7 @@
title: "GPIO Checklist"
---
-This checklist is for [Hardware Stage]({{<relref "/doc/project/hw_stages.md">}}) transitions for the [GPIO peripheral][GPIO Spec].
+This checklist is for [Hardware Stage]({{<relref "/doc/project/development_stages.md">}}) transitions for the [GPIO peripheral][GPIO Spec].
All checklist items refer to the content in the [Checklist.]({{<relref "/doc/project/checklist.md">}})
## Design Checklist
diff --git a/hw/ip/gpio/doc/dv_plan/index.md b/hw/ip/gpio/doc/dv_plan/index.md
index 5486ae8..1e76efe 100644
--- a/hw/ip/gpio/doc/dv_plan/index.md
+++ b/hw/ip/gpio/doc/dv_plan/index.md
@@ -11,7 +11,7 @@
## Current status
* [Design & verification stage]({{< relref "hw" >}})
- * [HW development stages]({{< relref "doc/project/hw_stages.md" >}})
+ * [HW development stages]({{< relref "doc/project/development_stages.md" >}})
* [Simulation results](https://reports.opentitan.org/hw/ip/gpio/dv/latest/results.html)
## Design features
diff --git a/hw/ip/hmac/doc/checklist.md b/hw/ip/hmac/doc/checklist.md
index d8360f6..195ac0b 100644
--- a/hw/ip/hmac/doc/checklist.md
+++ b/hw/ip/hmac/doc/checklist.md
@@ -2,7 +2,7 @@
title: "HMAC Checklist"
---
-This checklist is for [Hardware Stage]({{<relref "/doc/project/hw_stages.md" >}}) transitions for the [HMAC peripheral](../).
+This checklist is for [Hardware Stage]({{<relref "/doc/project/development_stages.md" >}}) transitions for the [HMAC peripheral](../).
All checklist items refer to the content in the [Checklist.]({{<relref "/doc/project/checklist.md" >}})
## Design Checklist
diff --git a/hw/ip/hmac/doc/dv_plan/index.md b/hw/ip/hmac/doc/dv_plan/index.md
index 371452a..f345230 100644
--- a/hw/ip/hmac/doc/dv_plan/index.md
+++ b/hw/ip/hmac/doc/dv_plan/index.md
@@ -11,7 +11,7 @@
## Current status
* [Design & verification stage]({{< relref "hw" >}})
- * [HW development stages]({{< relref "doc/project/hw_stages.md" >}})
+ * [HW development stages]({{< relref "doc/project/development_stages.md" >}})
* [Simulation results](https://reports.opentitan.org/hw/ip/hmac/dv/latest/results.html)
## Design features
diff --git a/hw/ip/i2c/doc/dv_plan/index.md b/hw/ip/i2c/doc/dv_plan/index.md
index 217ca7b..e36cdaa 100644
--- a/hw/ip/i2c/doc/dv_plan/index.md
+++ b/hw/ip/i2c/doc/dv_plan/index.md
@@ -11,7 +11,7 @@
## Current status
* [Design & verification stage]({{< relref "hw" >}})
- * [HW development stages]({{< relref "doc/project/hw_stages.md" >}})
+ * [HW development stages]({{< relref "doc/project/development_stages.md" >}})
* [Simulation results](https://reports.opentitan.org/hw/ip/i2c/dv/latest/results.html)
## Design features
diff --git a/hw/ip/padctrl/doc/checklist.md b/hw/ip/padctrl/doc/checklist.md
index 2568500..63fcfc6 100644
--- a/hw/ip/padctrl/doc/checklist.md
+++ b/hw/ip/padctrl/doc/checklist.md
@@ -2,7 +2,7 @@
title: "Padctrl Checklist"
---
-This checklist is for [Hardware Stage]({{< relref "/doc/project/hw_stages.md" >}}) transitions for the [Padctrl peripheral.]({{< relref "./" >}})
+This checklist is for [Hardware Stage]({{< relref "/doc/project/development_stages.md" >}}) transitions for the [Padctrl peripheral.]({{< relref "./" >}})
All checklist items refer to the content in the [Checklist.]({{< relref "/doc/project/checklist.md" >}})
## Design Checklist
diff --git a/hw/ip/pinmux/doc/checklist.md b/hw/ip/pinmux/doc/checklist.md
index bb9fa2b..c23e69b 100644
--- a/hw/ip/pinmux/doc/checklist.md
+++ b/hw/ip/pinmux/doc/checklist.md
@@ -2,7 +2,7 @@
title: "Pinmux Checklist"
---
-This checklist is for [Hardware Stage]({{< relref "/doc/project/hw_stages.md" >}}) transitions for the [Pinmux peripheral.]({{< relref "./" >}})
+This checklist is for [Hardware Stage]({{< relref "/doc/project/development_stages.md" >}}) transitions for the [Pinmux peripheral.]({{< relref "./" >}})
All checklist items refer to the content in the [Checklist.]({{< relref "/doc/project/checklist.md" >}})
## Design Checklist
diff --git a/hw/ip/pinmux/doc/dv_plan/index.md b/hw/ip/pinmux/doc/dv_plan/index.md
index f878b10..30241bb 100644
--- a/hw/ip/pinmux/doc/dv_plan/index.md
+++ b/hw/ip/pinmux/doc/dv_plan/index.md
@@ -12,7 +12,7 @@
## Current status
* [Design & verification stage]({{< relref "hw" >}})
- * [HW development stages]({{< relref "doc/project/hw_stages" >}})
+ * [HW development stages]({{< relref "doc/project/development_stages" >}})
* FPV dashboard (link TBD)
## Design features
diff --git a/hw/ip/rv_core_ibex/doc/checklist.md b/hw/ip/rv_core_ibex/doc/checklist.md
index 8a612fc..c42fe7d 100644
--- a/hw/ip/rv_core_ibex/doc/checklist.md
+++ b/hw/ip/rv_core_ibex/doc/checklist.md
@@ -5,7 +5,7 @@
This checklist is for [Hardware Stage][] transitions for the [Ibex Processor Core.](../)
All checklist items refer to the content in the [Checklist.]({{<relref "/doc/project/checklist.md">}})
-[Hardware Stage]: {{<relref "/doc/project/hw_stages.md" >}}
+[Hardware Stage]: {{<relref "/doc/project/development_stages.md" >}}
## Design Checklist
diff --git a/hw/ip/rv_plic/doc/checklist.md b/hw/ip/rv_plic/doc/checklist.md
index 5eb0d02..6c766fc 100644
--- a/hw/ip/rv_plic/doc/checklist.md
+++ b/hw/ip/rv_plic/doc/checklist.md
@@ -2,7 +2,7 @@
title: "RV_PLIC Checklist"
---
-This checklist is for [Hardware Stage]({{<relref "/doc/project/hw_stages.md" >}}) transitions for the [RV_PLIC peripheral](../).
+This checklist is for [Hardware Stage]({{<relref "/doc/project/development_stages.md" >}}) transitions for the [RV_PLIC peripheral](../).
All checklist items refer to the content in the [Checklist.]({{<relref "/doc/project/checklist.md" >}})
## Design Checklist
diff --git a/hw/ip/rv_plic/doc/dv_plan/index.md b/hw/ip/rv_plic/doc/dv_plan/index.md
index 66c44d8..c40b190 100644
--- a/hw/ip/rv_plic/doc/dv_plan/index.md
+++ b/hw/ip/rv_plic/doc/dv_plan/index.md
@@ -13,7 +13,7 @@
## Current status
* [Design & verification stage]({{< relref "hw" >}})
- * [HW development stages]({{< relref "doc/project/hw_stages" >}})
+ * [HW development stages]({{< relref "doc/project/development_stages" >}})
* FPV dashboard (link TBD)
## Design features
diff --git a/hw/ip/rv_timer/doc/checklist.md b/hw/ip/rv_timer/doc/checklist.md
index 963b4b2..9febad3 100644
--- a/hw/ip/rv_timer/doc/checklist.md
+++ b/hw/ip/rv_timer/doc/checklist.md
@@ -2,7 +2,7 @@
title: "RV_TIMER Checklist"
---
-This checklist is for [Hardware Stage]({{<relref "/doc/project/hw_stages.md" >}})
+This checklist is for [Hardware Stage]({{<relref "/doc/project/development_stages.md" >}})
transitions for the [rv_timer peripheral.](../) All checklist
items refer to the content in the [Checklist.]({{<relref "/doc/project/checklist.md" >}})
diff --git a/hw/ip/rv_timer/doc/dv_plan/index.md b/hw/ip/rv_timer/doc/dv_plan/index.md
index ab74282..64d522a 100644
--- a/hw/ip/rv_timer/doc/dv_plan/index.md
+++ b/hw/ip/rv_timer/doc/dv_plan/index.md
@@ -11,7 +11,7 @@
## Current status
* [Design & verification stage]({{< relref "hw" >}})
- * [HW development stages]({{< relref "doc/project/hw_stages.md" >}})
+ * [HW development stages]({{< relref "doc/project/development_stages.md" >}})
* [Simulation results](https://reports.opentitan.org/hw/ip/rv_timer/dv/latest/results.html)
## Design features
diff --git a/hw/ip/spi_device/doc/checklist.md b/hw/ip/spi_device/doc/checklist.md
index 1fdb9a0..ee09222 100644
--- a/hw/ip/spi_device/doc/checklist.md
+++ b/hw/ip/spi_device/doc/checklist.md
@@ -2,7 +2,7 @@
title: "SPI_DEVICE Checklist"
---
-This checklist is for [Hardware Stage]({{< relref "/doc/project/hw_stages.md" >}}) transitions for the [spi_device peripheral]({{< relref "./" >}}).
+This checklist is for [Hardware Stage]({{< relref "/doc/project/development_stages.md" >}}) transitions for the [spi_device peripheral]({{< relref "./" >}}).
All checklist items refer to the content in the [Checklist]({{< relref "/doc/project/checklist.md" >}}).
## Design Checklist
diff --git a/hw/ip/spi_device/doc/dv_plan/index.md b/hw/ip/spi_device/doc/dv_plan/index.md
index 54ddfb5..69d5e51 100644
--- a/hw/ip/spi_device/doc/dv_plan/index.md
+++ b/hw/ip/spi_device/doc/dv_plan/index.md
@@ -12,7 +12,7 @@
## Current status
* [Design & verification stage]({{< relref "hw" >}})
- * [HW development stages]({{< relref "doc/project/hw_stages.md" >}})
+ * [HW development stages]({{< relref "doc/project/development_stages.md" >}})
* [Simulation results](https://reports.opentitan.org/hw/ip/spi_device/dv/latest/results.html)
## Design features
diff --git a/hw/ip/tlul/doc/dv_plan/index.md b/hw/ip/tlul/doc/dv_plan/index.md
index b5fa640..a9ff865 100644
--- a/hw/ip/tlul/doc/dv_plan/index.md
+++ b/hw/ip/tlul/doc/dv_plan/index.md
@@ -12,7 +12,7 @@
## Current status
* [Design & verification stage]({{< relref "hw" >}})
- * [HW development stages]({{< relref "doc/project/hw_stages" >}})
+ * [HW development stages]({{< relref "doc/project/development_stages" >}})
* DV regression results dashboard (link TBD)
## Design features
diff --git a/hw/ip/uart/doc/checklist.md b/hw/ip/uart/doc/checklist.md
index e450d78..091a21a 100644
--- a/hw/ip/uart/doc/checklist.md
+++ b/hw/ip/uart/doc/checklist.md
@@ -5,7 +5,7 @@
This checklist is for [Hardware Stage][] transitions for the [UART peripheral.](../)
All checklist items refer to the content in the [Checklist.]({{<relref "/doc/project/checklist.md">}})
-[Hardware Stage]: {{<relref "/doc/project/hw_stages.md" >}}
+[Hardware Stage]: {{<relref "/doc/project/development_stages.md" >}}
## Design Checklist
diff --git a/hw/ip/uart/doc/dv_plan/index.md b/hw/ip/uart/doc/dv_plan/index.md
index 98b41d2..34de9e1 100644
--- a/hw/ip/uart/doc/dv_plan/index.md
+++ b/hw/ip/uart/doc/dv_plan/index.md
@@ -12,7 +12,7 @@
## Current status
* [Design & verification stage]({{< relref "hw" >}})
- * [HW development stages]({{< relref "doc/project/hw_stages.md" >}})
+ * [HW development stages]({{< relref "doc/project/development_stages.md" >}})
* [Simulation results](https://reports.opentitan.org/hw/ip/uart/dv/latest/results.html)
## Design features
diff --git a/hw/ip/usbdev/doc/dv_plan/index.md b/hw/ip/usbdev/doc/dv_plan/index.md
index dcd322c..2de62f7 100644
--- a/hw/ip/usbdev/doc/dv_plan/index.md
+++ b/hw/ip/usbdev/doc/dv_plan/index.md
@@ -13,7 +13,7 @@
## Current status
* [Design & verification stage]({{< relref "hw" >}})
- * [HW development stages]({{< relref "doc/project/hw_stages" >}})
+ * [HW development stages]({{< relref "doc/project/development_stages" >}})
* [Simulation results](https://reports.opentitan.org/hw/ip/usbdev/dv/latest/results.html)
## Design features
diff --git a/hw/top_earlgrey/ip/xbar/doc/checklist.md b/hw/top_earlgrey/ip/xbar/doc/checklist.md
index 6d843ed..45f3b67 100644
--- a/hw/top_earlgrey/ip/xbar/doc/checklist.md
+++ b/hw/top_earlgrey/ip/xbar/doc/checklist.md
@@ -2,7 +2,7 @@
title: "TL-UL Checklist"
---
-This checklist is for [Hardware Stage]({{< relref "/doc/project/hw_stages.md" >}}) transitions for the [TL-UL component.]({{<relref "/hw/ip/tlul/doc">}})
+This checklist is for [Hardware Stage]({{< relref "/doc/project/development_stages.md" >}}) transitions for the [TL-UL component.]({{<relref "/hw/ip/tlul/doc">}})
All checklist items refer to the content in the [Checklist]({{< relref "/doc/project/checklist.md" >}}).
## Design Checklist
diff --git a/site/docs/layouts/shortcodes/dashboard.html b/site/docs/layouts/shortcodes/dashboard.html
index 7aa01c9..06c19dd 100644
--- a/site/docs/layouts/shortcodes/dashboard.html
+++ b/site/docs/layouts/shortcodes/dashboard.html
@@ -3,8 +3,8 @@
<tr>
<th>Design Spec</th>
<th>DV Plan</th>
- <th><a href="{{ relref . "doc/project/hw_stages#versioning" }}">Version</a></th>
- <th><a href="{{ relref . "doc/project/hw_stages#life-stages" }}">Development Stage</a></th>
+ <th><a href="{{ relref . "doc/project/development_stages#versioning" }}">Version</a></th>
+ <th><a href="{{ relref . "doc/project/development_stages#life-stages" }}">Development Stage</a></th>
<th>Notes</th>
</tr>
</thead>
diff --git a/util/dvsim/testplanner/README.md b/util/dvsim/testplanner/README.md
index c663166..7c0f5f4 100644
--- a/util/dvsim/testplanner/README.md
+++ b/util/dvsim/testplanner/README.md
@@ -43,7 +43,7 @@
* **tests: list of actual written tests that maps to this planned test**
Testplan is written in the initial work stage of the verification
- [life-cycle]({{< relref "doc/project/hw_stages#hardware-verification-stages" >}}).
+ [life-cycle]({{< relref "doc/project/development_stages#hardware-verification-stages" >}}).
When the DV engineer gets to actually developing the test, it may not map 1:1 to
the planned test - it may be possible that an already written test that mapped
to another planned test also satisfies the current one; OR it may also be
diff --git a/util/uvmdvgen/checklist.md.tpl b/util/uvmdvgen/checklist.md.tpl
index d40e8ea..2a16f88 100644
--- a/util/uvmdvgen/checklist.md.tpl
+++ b/util/uvmdvgen/checklist.md.tpl
@@ -7,7 +7,7 @@
directory for a new design that transitions from L0 (Specification) to L1 (Development)
stage, and updated as needed. Once done, please remove this comment before checking it in.
-->
-This checklist is for [Hardware Stage]({{< relref "/doc/project/hw_stages.md" >}}) transitions for the [${name.upper()} peripheral.]({{< relref "hw/ip/${name}/doc" >}})
+This checklist is for [Hardware Stage]({{< relref "/doc/project/development_stages.md" >}}) transitions for the [${name.upper()} peripheral.]({{< relref "hw/ip/${name}/doc" >}})
All checklist items refer to the content in the [Checklist.]({{< relref "/doc/project/checklist.md" >}})
## Design Checklist
diff --git a/util/uvmdvgen/index.md.tpl b/util/uvmdvgen/index.md.tpl
index 8e48270..4880d04 100644
--- a/util/uvmdvgen/index.md.tpl
+++ b/util/uvmdvgen/index.md.tpl
@@ -20,7 +20,7 @@
${'##'} Current status
* [Design & verification stage]({{< relref "hw" >}})
- * [HW development stages]({{< relref "doc/project/hw_stages" >}})
+ * [HW development stages]({{< relref "doc/project/development_stages" >}})
* [Simulation results](https://reports.opentitan.org/hw/ip/${name}/dv/latest/results.html)
${'##'} Design features
