[topgen] Allow multiple device interfaces to connect to the crossbar
This looks like quite a big change, but lots of the changes are
auto-generated.
The main change to the data model is that an IpBlock can now contain
multiple RegBlock objects (one for each device interface). While we're
at it, we also remove the "Block" base class that nothing ever used:
we're Python, not Java: time to embrace sum types :-D
The other noticeable change is in how the xbar parsing logic works. If
you want multiple device interfaces for a block, you should create a
node for each in e.g. xbar_main.hjson. These should be named
"<inst_name>.<if_name>" for a named interface. Obviously, these nodes
also need adding to the connections list at the bottom.
There's a problem of aliasing, where the first register in each
interface will have address zero in <block>_ral_pkg.sv. For now, we're
"solving" this by adding the index of the device interface to the
address, shifted up by 28 bits. I'm not sure how best to do this at
the chip level, but it can probably be addressed in a follow-up.
The structure of most output files are unchanged. The only difference
is stuff that needs creating per device interface (such as the reg_top
modules and the FPV CSR files).
Signed-off-by: Rupert Swarbrick <rswarbrick@lowrisc.org>
diff --git a/util/topgen.py b/util/topgen.py
index 9b208da..88538f5 100755
--- a/util/topgen.py
+++ b/util/topgen.py
@@ -13,7 +13,7 @@
from copy import deepcopy
from io import StringIO
from pathlib import Path
-from typing import Dict, Tuple
+from typing import Dict, Optional, Tuple
import hjson
from mako import exceptions
@@ -773,22 +773,31 @@
gen_rtl.gen_rtl(IpBlock.from_path(str(hjson_path), []), str(genrtl_dir))
-def generate_top_ral(top, ip_objs, dv_base_prefix, out_path):
+def generate_top_ral(top: Dict[str, object],
+ ip_objs: Dict[str, object],
+ name_to_block: Dict[str, IpBlock],
+ dv_base_prefix: str,
+ out_path: str):
# construct top ral block
regwidth = int(top['datawidth'])
assert regwidth % 8 == 0
addrsep = regwidth // 8
- # Get sub-block base addresses and instance names from top cfg
- sub_blocks = {} # type: Dict[int, Tuple[str, IpBlock]]
- for block in ip_objs:
- block_lname = block.name.lower()
- for module in top["module"]:
- if block_lname == module["type"]:
- block_addr = int(module["base_addr"], 0)
- assert block_addr not in sub_blocks
- sub_blocks[block_addr] = (module["name"], block)
+ # Generate a map from instance name to the block that it instantiates,
+ # together with a map of interface addresses.
+ inst_to_block = {} # type: Dict[str, str]
+ if_addrs = {} # type: Dict[Tuple[str, Optional[str]], int],
+
+ for module in top['module']:
+ inst_name = module['name']
+ block_name = module['type']
+ block = name_to_block[block_name]
+
+ inst_to_block[inst_name] = block_name
+ for if_name in block.reg_blocks.keys():
+ if_addr = int(module["base_addrs"][if_name], 0)
+ if_addrs[(inst_name, if_name)] = if_addr
# Collect up the memories to add
mems = []
@@ -810,7 +819,7 @@
offset=int(item["base_addr"], 0),
swaccess=swaccess))
- chip = Top(regwidth, sub_blocks, mems)
+ chip = Top(regwidth, name_to_block, inst_to_block, if_addrs, mems)
# generate the top ral model with template
gen_dv.gen_ral(chip, dv_base_prefix, str(out_path))
@@ -965,7 +974,8 @@
generate_top_only(top_only_list, out_path, topname)
if pass_idx > 0 and args.top_ral:
- generate_top_ral(completecfg, ip_objs, args.dv_base_prefix, out_path)
+ generate_top_ral(completecfg, ip_objs, name_to_block,
+ args.dv_base_prefix, out_path)
sys.exit()
return completecfg, name_to_block
@@ -1178,7 +1188,7 @@
# The C / SV file needs some complex information, so we initialize this
# object to store it.
- c_helper = TopGenC(completecfg)
+ c_helper = TopGenC(completecfg, name_to_block)
# 'top_{topname}_pkg.sv.tpl' -> 'rtl/autogen/top_{topname}_pkg.sv'
render_template('top_%s_pkg.sv',
