[prim_sync_reqack] Disable reset checks by default, enable inside OTBN
This commit adds a new SV parameter to the prim_edn_req and
prim_sync_reqack(data) modules to only enable the reset checks if
explicitly enabled. For now, the checks are only enabled within OTBN.
The reason for doing this is that currently we expect quite a few test
failures based on this change. Once the reset domains have been
re-organized (see lowRISC/OpenTitan#15317) this commit can be reverted
and the checks can be enabled system wide without causing a large amount
of test failures.
Signed-off-by: Pirmin Vogel <vogelpi@lowrisc.org>
diff --git a/hw/ip/otbn/rtl/otbn.sv b/hw/ip/otbn/rtl/otbn.sv
index 108df26..3214b56 100644
--- a/hw/ip/otbn/rtl/otbn.sv
+++ b/hw/ip/otbn/rtl/otbn.sv
@@ -1017,6 +1017,7 @@
// internal entropy width of 256 bit.
prim_edn_req #(
+ .EnRstChks(1'b1),
.OutWidth(EdnDataWidth),
// SEC_CM: RND.BUS.CONSISTENCY
.RepCheck(1'b1)
@@ -1036,6 +1037,7 @@
);
prim_edn_req #(
+ .EnRstChks(1'b1),
.OutWidth(EdnDataWidth)
) u_prim_edn_urnd_req (
.clk_i,
diff --git a/hw/ip/otbn/rtl/otbn_scramble_ctrl.sv b/hw/ip/otbn/rtl/otbn_scramble_ctrl.sv
index 0b2e002..5d372b2 100644
--- a/hw/ip/otbn/rtl/otbn_scramble_ctrl.sv
+++ b/hw/ip/otbn/rtl/otbn_scramble_ctrl.sv
@@ -226,6 +226,7 @@
prim_sync_reqack_data #(
.Width($bits(otp_ctrl_pkg::otbn_otp_key_rsp_t)-1),
+ .EnRstChks(1'b1),
.DataSrc2Dst(1'b0)
) u_otp_key_req_sync (
.clk_src_i (clk_i),
diff --git a/hw/ip/prim/rtl/prim_edn_req.sv b/hw/ip/prim/rtl/prim_edn_req.sv
index a3cf988..ff12cd7 100644
--- a/hw/ip/prim/rtl/prim_edn_req.sv
+++ b/hw/ip/prim/rtl/prim_edn_req.sv
@@ -19,6 +19,8 @@
parameter int OutWidth = 32,
// Repetition check for incoming edn data
parameter bit RepCheck = 0,
+ // Disable reset-related assertion checks inside prim_sync_reqack primitives.
+ parameter bit EnRstChks = 0,
// EDN Request latency checker
//
@@ -56,6 +58,7 @@
localparam int SyncWidth = $bits({edn_i.edn_fips, edn_i.edn_bus});
prim_sync_reqack_data #(
.Width(SyncWidth),
+ .EnRstChks(EnRstChks),
.DataSrc2Dst(1'b0),
.DataReg(1'b0)
) u_prim_sync_reqack_data (
diff --git a/hw/ip/prim/rtl/prim_sync_reqack.sv b/hw/ip/prim/rtl/prim_sync_reqack.sv
index d58217f..8f4d9aa 100644
--- a/hw/ip/prim/rtl/prim_sync_reqack.sv
+++ b/hw/ip/prim/rtl/prim_sync_reqack.sv
@@ -25,7 +25,9 @@
`include "prim_assert.sv"
-module prim_sync_reqack (
+module prim_sync_reqack #(
+ parameter bit EnRstChks = 1'b0 // Enable reset-related assertion checks, disabled by default.
+) (
input clk_src_i, // REQ side, SRC domain
input rst_src_ni, // REQ side, SRC domain
input clk_dst_i, // ACK side, DST domain
@@ -194,12 +196,14 @@
`ASSERT(SyncReqAckAckNeedsReq, dst_ack_i |->
dst_req_o, clk_dst_i, !rst_src_ni || !rst_dst_ni)
- // Always reset both domains. Both resets need to be active at the same time.
- `ASSERT(SyncReqAckRstSrc, $fell(rst_src_ni) |->
- (##[0:$] !rst_dst_ni within !rst_src_ni [*1:$]),
- clk_src_i, 0)
- `ASSERT(SyncReqAckRstDst, $fell(rst_dst_ni) |->
- (##[0:$] !rst_src_ni within !rst_dst_ni [*1:$]),
- clk_dst_i, 0)
+ if (EnRstChks) begin : gen_assert_en_rst_chks
+ // Always reset both domains. Both resets need to be active at the same time.
+ `ASSERT(SyncReqAckRstSrc, $fell(rst_src_ni) |->
+ (##[0:$] !rst_dst_ni within !rst_src_ni [*1:$]),
+ clk_src_i, 0)
+ `ASSERT(SyncReqAckRstDst, $fell(rst_dst_ni) |->
+ (##[0:$] !rst_src_ni within !rst_dst_ni [*1:$]),
+ clk_dst_i, 0)
+ end
endmodule
diff --git a/hw/ip/prim/rtl/prim_sync_reqack_data.sv b/hw/ip/prim/rtl/prim_sync_reqack_data.sv
index d05d0f3..6950716 100644
--- a/hw/ip/prim/rtl/prim_sync_reqack_data.sv
+++ b/hw/ip/prim/rtl/prim_sync_reqack_data.sv
@@ -18,6 +18,8 @@
module prim_sync_reqack_data #(
parameter int unsigned Width = 1,
+ parameter bit EnRstChks = 1'b0, // Enable reset-related assertion checks, disabled by
+ // default.
parameter bit DataSrc2Dst = 1'b1, // Direction of data flow: 1'b1 = SRC to DST,
// 1'b0 = DST to SRC
parameter bit DataReg = 1'b0 // Enable optional register stage for data,
@@ -42,7 +44,9 @@
////////////////////////////////////
// REQ/ACK synchronizer primitive //
////////////////////////////////////
- prim_sync_reqack u_prim_sync_reqack (
+ prim_sync_reqack #(
+ .EnRstChks(EnRstChks)
+ ) u_prim_sync_reqack (
.clk_src_i,
.rst_src_ni,
.clk_dst_i,
