commit 1e87fe52bee1a27e19e74efde915126b51e71546
author Cindy Chen <chencindy@opentitan.org> Thu May 27 14:37:22 2021 -0700
committer cindychip <cindy.chen0316@gmail.com> Fri Jun 04 15:01:54 2021 -0700
tree 4ad1cb59fbdf131d627750284fba2a2591e15594
parent 794c8d3b0b54d796b84ca6cc2d2298c1780c9be8

[dv/edn_rst] Detach edn reset with dut reset

This PR drives edn reset separately from dut reset:

1. In `apply_reset`, add random delays for edn reset, so it does not
always asserted at the same time as dut reset.
2. Add a separate `apply_edn_reset` function to drive edn reset
separately from DUT reset.

Signed-off-by: Cindy Chen <chencindy@opentitan.org>

hw/dv/sv/cip_lib/cip_macros.svh

diff --git a/hw/dv/sv/cip_lib/cip_macros.svh b/hw/dv/sv/cip_lib/cip_macros.svh
index 6a45cdd..f9918b7 100644
--- a/hw/dv/sv/cip_lib/cip_macros.svh
+++ b/hw/dv/sv/cip_lib/cip_macros.svh
@@ -29,13 +29,13 @@
 // TODO, tie core reset with EDN reset for now
 `ifndef DV_EDN_IF_CONNECT
 `define DV_EDN_IF_CONNECT \
-  wire edn_rst_n = rst_n; \
+  wire edn_rst_n; \
   wire edn_clk; \
   clk_rst_if edn_clk_rst_if(.clk(edn_clk), .rst_n(edn_rst_n)); \
   push_pull_if #(.DeviceDataWidth(cip_base_pkg::EDN_DATA_WIDTH)) edn_if(.clk(edn_clk), \
                                                                         .rst_n(edn_rst_n)); \
   initial begin \
-    edn_clk_rst_if.set_active(.drive_rst_n_val(0)); \
+    edn_clk_rst_if.set_active(); \
     uvm_config_db#(virtual clk_rst_if)::set(null, "*.env", "edn_clk_rst_vif", edn_clk_rst_if); \
     uvm_config_db#(virtual push_pull_if#(.DeviceDataWidth(cip_base_pkg::EDN_DATA_WIDTH)))::set \
                    (null, "*env.m_edn_pull_agent*", "vif", edn_if); \

hw/dv/sv/cip_lib/seq_lib/cip_base_vseq.sv

diff --git a/hw/dv/sv/cip_lib/seq_lib/cip_base_vseq.sv b/hw/dv/sv/cip_lib/seq_lib/cip_base_vseq.sv
index d06a80a..253ab39 100644
--- a/hw/dv/sv/cip_lib/seq_lib/cip_base_vseq.sv
+++ b/hw/dv/sv/cip_lib/seq_lib/cip_base_vseq.sv
@@ -110,6 +110,38 @@
     if (do_clear_all_interrupts) clear_all_interrupts();
   endtask
 
+  virtual task apply_reset(string kind = "HARD");
+    if (kind == "HARD") begin
+      // If DUT is connected to `edn_rst`, assert resets with random delays
+      if (cfg.has_edn) begin
+        fork
+          begin : isolation_fork
+            fork
+              apply_edn_reset(kind);
+              super.apply_reset(kind);
+            join_any
+            disable fork;
+          end
+        join
+
+        // Deassert resets at the same time to avoid undriven outputs.
+        cfg.edn_clk_rst_vif.drive_rst_pin(1);
+        if (cfg.clk_rst_vifs.size > 0) begin
+          foreach (cfg.clk_rst_vifs[i]) cfg.clk_rst_vifs[i].drive_rst_pin(1);
+        end else begin
+          cfg.clk_rst_vif.drive_rst_pin(1);
+        end
+
+      end else begin
+        super.apply_reset(kind);
+      end
+    end
+  endtask
+
+  virtual task apply_edn_reset(string kind = "HARD");
+    if (cfg.has_edn && kind == "HARD") cfg.edn_clk_rst_vif.apply_reset();
+  endtask
+
   // tl_access task: does a single BUS_DW-bit write or read transaction to the specified address
   // note that this task does not update ral model; optionally also checks for error response
   // TODO: randomize size, addr here based on given addr range, data, and mask, eventually can be