[SPI/DV] Regression Failure Fixes And Testplan Update
- Fixed regression failures
- Testplan update for unmapped tests
Signed-off-by: Viswanadha Bazawada <viswanadha.bazawada@ensilica.com>
diff --git a/hw/ip/spi_host/data/spi_host_testplan.hjson b/hw/ip/spi_host/data/spi_host_testplan.hjson
index 39b252d..5c12f29 100644
--- a/hw/ip/spi_host/data/spi_host_testplan.hjson
+++ b/hw/ip/spi_host/data/spi_host_testplan.hjson
@@ -6,6 +6,7 @@
import_testplans: ["hw/dv/tools/dvsim/testplans/csr_testplan.hjson",
"hw/dv/tools/dvsim/testplans/alert_test_testplan.hjson",
"hw/dv/tools/dvsim/testplans/intr_test_testplan.hjson",
+ "hw/dv/tools/dvsim/testplans/mem_testplan.hjson",
"hw/dv/tools/dvsim/testplans/stress_all_with_reset_testplan.hjson",
"hw/dv/tools/dvsim/testplans/tl_device_access_types_testplan.hjson",
"spi_host_sec_cm_testplan.hjson"],
@@ -201,6 +202,35 @@
tests: ["spi_host_stress_all"]
}
{
+ name: stall
+ desc: '''
+ Stimulus:
+ - Ongoing transaction has stalled due to lack of available space in the RX FIFO
+ and continues when RX fifo is cleared
+ - Ongoing transaction has stalled due to lack of data in the TX FIFO
+ and continues when data is provided in TX FIFO
+
+ Checking:
+ - Ensure Rxstall occurs and recovers
+ - Ensure Txstall occurs and recovers
+ '''
+ milestone: V2
+ tests: ["spi_host_status_stall"]
+ }
+ {
+ name: Idlecsbactive
+ desc: '''
+ Stimulus:
+ - Pause next segment availability and idly wait for next command
+
+ Checking:
+ - Ensure transactions goes through even with a segment pause and idle wait
+ in the state IdleCsbActive
+ '''
+ milestone: V2
+ tests: ["spi_host_idlecsbactive"]
+ }
+ {
name: winbond
desc: '''
Replace SPI agent with the Winbond Flash model
diff --git a/hw/ip/spi_host/dv/env/seq_lib/spi_host_event_vseq.sv b/hw/ip/spi_host/dv/env/seq_lib/spi_host_event_vseq.sv
index ccc3a91..96fac30 100644
--- a/hw/ip/spi_host/dv/env/seq_lib/spi_host_event_vseq.sv
+++ b/hw/ip/spi_host/dv/env/seq_lib/spi_host_event_vseq.sv
@@ -43,9 +43,9 @@
csr_rd(.ptr(ral.status.txqd), .value(txqd));
if (txqd < spi_host_ctrl_reg.tx_watermark) begin
check_event(ral.status.txwm, 1);
+ read_rx_fifo();
end
end
- read_rx_fifo();
check_event(ral.status.txempty, 1);
cfg.clk_rst_vif.wait_clks(100);
diff --git a/hw/ip/spi_host/dv/env/seq_lib/spi_host_idlecsbactive_vseq.sv b/hw/ip/spi_host/dv/env/seq_lib/spi_host_idlecsbactive_vseq.sv
index 1eae987..1f53c45 100644
--- a/hw/ip/spi_host/dv/env/seq_lib/spi_host_idlecsbactive_vseq.sv
+++ b/hw/ip/spi_host/dv/env/seq_lib/spi_host_idlecsbactive_vseq.sv
@@ -73,4 +73,9 @@
end
endtask
+ virtual task generate_transaction();
+ transaction_init();
+ `DV_CHECK_RANDOMIZE_WITH_FATAL(transaction, num_segments == 4; cmd == ReadStd;)
+ endtask
+
endclass : spi_host_idlecsbactive_vseq
diff --git a/hw/ip/spi_host/dv/env/seq_lib/spi_host_status_stall_vseq.sv b/hw/ip/spi_host/dv/env/seq_lib/spi_host_status_stall_vseq.sv
index fbca430..fed112b 100644
--- a/hw/ip/spi_host/dv/env/seq_lib/spi_host_status_stall_vseq.sv
+++ b/hw/ip/spi_host/dv/env/seq_lib/spi_host_status_stall_vseq.sv
@@ -16,6 +16,7 @@
virtual task body();
spi_host_command_t command_snd;
spi_segment_item segment_snd;
+ bit [7:0] read_q[$];
begin : isolation_fork
fork
@@ -38,7 +39,9 @@
end : isolation_fork
csr_spinwait(.ptr(ral.status.rxfull), .exp_data(1'b1));
csr_spinwait(.ptr(ral.status.rxstall), .exp_data(1'b1));
- read_rx_fifo();
+ for (int i = 0; i < SPI_HOST_RX_DEPTH; i++) begin
+ access_data_fifo(read_q, RxFifo);
+ end
// send transaction to check tx stall
cfg.tx_stall_check = 1'b1;
wr_trans();
