| commit | 1def47b2507b73b66d045695c03946e5349f738d | [log] [tgz] |
|---|---|---|
| author | Rupert Swarbrick <rswarbrick@lowrisc.org> | Fri Apr 09 10:07:55 2021 +0100 |
| committer | Rupert Swarbrick <rswarbrick@gmail.com> | Mon Apr 12 07:57:43 2021 +0100 |
| tree | ac400f20063498fae8ed383aec8ca9cd3abe7534 | |
| parent | dc054518a493985f2e0884ba9bacd6de2acea491 [diff] |
[keymgr] Define an intermediate signal for setting cfg_regwen This avoids an UNOPTFLAT warning from Verilator, caused because Verilator doesn't automatically split the hw2reg structure when topologically sorting the processes that read to and write from it. Another way to address this is to use a "split_var" Verilator-specific hint, but I think the code is also probably clearer for humans when rewritten this way. Signed-off-by: Rupert Swarbrick <rswarbrick@lowrisc.org>
OpenTitan is an open source silicon Root of Trust (RoT) project. OpenTitan will make the silicon RoT design and implementation more transparent, trustworthy, and secure for enterprises, platform providers, and chip manufacturers. OpenTitan is administered by lowRISC CIC as a collaborative project to produce high quality, open IP for instantiation as a full-featured product. See the OpenTitan site and OpenTitan docs for more information about the project.
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