[top] Remove NexysVideo pinout configuration and files
This partially addresses #12221
Signed-off-by: Michael Schaffner <msf@opentitan.org>
diff --git a/hw/top_earlgrey/chip_earlgrey_nexysvideo.core b/hw/top_earlgrey/chip_earlgrey_nexysvideo.core
deleted file mode 100644
index ae620e0..0000000
--- a/hw/top_earlgrey/chip_earlgrey_nexysvideo.core
+++ /dev/null
@@ -1,87 +0,0 @@
-CAPI=2:
-# Copyright lowRISC contributors.
-# Licensed under the Apache License, Version 2.0, see LICENSE for details.
-# SPDX-License-Identifier: Apache-2.0
-name: "lowrisc:systems:chip_earlgrey_nexysvideo:0.1"
-description: "Earl Grey toplevel for the Nexys Video board"
-filesets:
- files_rtl_nexysvideo:
- depend:
- - lowrisc:systems:top_earlgrey:0.1
- - lowrisc:systems:top_earlgrey_pkg
- - lowrisc:systems:padring
- - lowrisc:systems:ast
- - lowrisc:tool:chip_earlgrey_nexysvideo_size_check
- files:
- - rtl/clkgen_xil7series.sv
- - rtl/usr_access_xil7series.sv
- - rtl/autogen/chip_earlgrey_nexysvideo.sv
- file_type: systemVerilogSource
-
- files_constraints:
- files:
- - data/clocks.xdc
- - data/pins_nexysvideo.xdc
- file_type: xdc
-
- files_tcl:
- files:
- - util/vivado_setup_hooks.tcl: { file_type: tclSource }
- # File copied by fusesoc into the workroot (the file containing the
- # .eda.yml file), and referenced from vivado_setup_hooks.tcl
- - util/vivado_hook_synth_design_pre.tcl: { file_type: user, copyto: vivado_hook_synth_design_pre.tcl }
- - util/vivado_hook_write_bitstream_pre.tcl: { file_type: user, copyto: vivado_hook_write_bitstream_pre.tcl }
- - util/vivado_hook_opt_design_post.tcl: { file_type: user, copyto: vivado_hook_opt_design_post.tcl }
-
-parameters:
- # XXX: This parameter needs to be absolute, or relative to the *.runs/synth_1
- # directory. It's best to pass it as absolute path when invoking fusesoc, e.g.
- # --BootRomInitFile=$PWD/build-bin/sw/device/lib/testing/test_rom/test_rom_fpga_nexysvideo.scr.39.vmem
- # XXX: The VMEM file should be added to the sources of the Vivado project to
- # make the Vivado dependency tracking work. However this requires changes to
- # fusesoc first.
- BootRomInitFile:
- datatype: str
- description: Scrambled boot ROM initialization file in 40 bit vmem hex format
- default: "../../../../../build-bin/sw/device/lib/testing/test_rom/test_rom_fpga_nexysvideo.scr.39.vmem"
- paramtype: vlogparam
- OtpCtrlMemInitFile:
- datatype: str
- description: OTP initialization file in vmem hex format
- default: "../../../../../build-bin/sw/device/otp_img/otp_img_fpga_nexysvideo.vmem"
- paramtype: vlogparam
- # For value definition, please see ip/prim/rtl/prim_pkg.sv
- PRIM_DEFAULT_IMPL:
- datatype: str
- paramtype: vlogdefine
- description: Primitives implementation to use, e.g. "prim_pkg::ImplGeneric".
-
-targets:
- default: &default_target
- filesets:
- - files_rtl_nexysvideo
- toplevel: chip_earlgrey_nexysvideo
-
- synth:
- default_tool: vivado
- filesets:
- - files_rtl_nexysvideo
- - files_constraints
- - files_tcl
- toplevel: chip_earlgrey_nexysvideo
- parameters:
- - BootRomInitFile
- - OtpCtrlMemInitFile
- - PRIM_DEFAULT_IMPL=prim_pkg::ImplXilinx
- tools:
- vivado:
- part: "xc7a200tsbg484-1" # Nexys Video
-
- lint:
- <<: *default_target
- default_tool: verilator
- tools:
- verilator:
- mode: lint-only
- verilator_options:
- - "-Wall"
diff --git a/hw/top_earlgrey/data/autogen/top_earlgrey.gen.hjson b/hw/top_earlgrey/data/autogen/top_earlgrey.gen.hjson
index af26fbc..0453ecb 100644
--- a/hw/top_earlgrey/data/autogen/top_earlgrey.gen.hjson
+++ b/hw/top_earlgrey/data/autogen/top_earlgrey.gen.hjson
@@ -12465,188 +12465,6 @@
]
}
}
- {
- name: nexysvideo
- pinout:
- {
- remove_ports: []
- remove_pads:
- [
- CC1
- CC2
- SPI_DEV_D2
- SPI_DEV_D3
- SPI_HOST_CLK
- SPI_HOST_CS_L
- SPI_HOST_D0
- SPI_HOST_D1
- SPI_HOST_D2
- SPI_HOST_D3
- FLASH_TEST_VOLT
- OTP_EXT_VOLT
- FLASH_TEST_MODE0
- FLASH_TEST_MODE1
- IOB10
- IOB11
- IOB12
- IOC0
- IOC1
- IOC12
- IOR2
- IOR3
- IOR4
- IOR5
- IOR6
- IOR7
- IOR8
- IOR9
- IOR10
- IOR11
- IOR12
- IOR13
- ]
- add_pads:
- [
- {
- name: IO_CLK
- type: InputStd
- bank: VCC
- connection: manual
- desc: Extra clock input for FPGA target
- }
- {
- name: IO_JSRST_N
- type: InputStd
- bank: VCC
- connection: manual
- desc: Dedicated JTAG system reset input
- }
- {
- name: IO_USB_DNPULLUP0
- type: BidirStd
- bank: VCC
- connection: manual
- desc: Manual USB signal for FPGA target
- }
- {
- name: IO_USB_DPPULLUP0
- type: BidirStd
- bank: VCC
- connection: manual
- desc: Manual USB signal for FPGA target
- }
- {
- name: IO_UPHY_DP_TX
- type: BidirStd
- bank: VCC
- connection: manual
- desc: Manual USB UPHY signal for FPGA target
- }
- {
- name: IO_UPHY_DN_TX
- type: BidirStd
- bank: VCC
- connection: manual
- desc: Manual USB UPHY signal for FPGA target
- }
- {
- name: IO_UPHY_DP_RX
- type: BidirStd
- bank: VCC
- connection: manual
- desc: Manual USB UPHY signal for FPGA target
- }
- {
- name: IO_UPHY_DN_RX
- type: BidirStd
- bank: VCC
- connection: manual
- desc: Manual USB UPHY signal for FPGA target
- }
- {
- name: IO_UPHY_D_RX
- type: BidirStd
- bank: VCC
- connection: manual
- desc: Manual USB UPHY signal for FPGA target
- }
- {
- name: IO_UPHY_OE_N
- type: BidirStd
- bank: VCC
- connection: manual
- desc: Manual USB UPHY signal for FPGA target
- }
- {
- name: IO_UPHY_DPPULLUP
- type: BidirStd
- bank: VCC
- connection: manual
- desc: Manual USB UPHY signal for FPGA target
- }
- ]
- }
- pinmux:
- {
- special_signals:
- [
- {
- name: tap0
- pad: IOC0
- desc: TAP strap signal, maps to a stubbed-off MIO.
- idx: 22
- }
- {
- name: tap1
- pad: IOB7
- desc: TAP strap signal, maps to MIO pad 16.
- idx: 16
- }
- {
- name: dft0
- pad: IOC1
- desc: DFT strap signal, maps to a stubbed-off MIO.
- idx: 23
- }
- {
- name: dft1
- pad: IOC12
- desc: DFT strap signal, maps to a stubbed-off MIO.
- idx: 34
- }
- {
- name: tck
- pad: SPI_DEV_CLK
- desc: JTAG tck signal, overlaid on SPI_DEV.
- idx: 59
- }
- {
- name: tms
- pad: SPI_DEV_CS_L
- desc: JTAG tms signal, overlaid on SPI_DEV.
- idx: 60
- }
- {
- name: trst_n
- pad: IOB9
- desc: JTAG trst_n signal, maps to MIO pad 18.
- idx: 18
- }
- {
- name: tdi
- pad: SPI_DEV_D0
- desc: JTAG tdi signal, overlaid on SPI_DEV.
- idx: 53
- }
- {
- name: tdo
- pad: SPI_DEV_D1
- desc: JTAG tdo signal, overlaid on SPI_DEV.
- idx: 54
- }
- ]
- }
- }
]
exported_clks: {}
wakeups:
diff --git a/hw/top_earlgrey/data/pins_nexysvideo.xdc b/hw/top_earlgrey/data/pins_nexysvideo.xdc
deleted file mode 100644
index 4cfece2..0000000
--- a/hw/top_earlgrey/data/pins_nexysvideo.xdc
+++ /dev/null
@@ -1,355 +0,0 @@
-# This file has been prepared by Digilent and edited for use in this project.
-# Upstream source:
-# https://github.com/Digilent/digilent-xdc/blob/master/Nexys-Video-Master.xdc
-
-## Clock Signal
-set_property -dict { PACKAGE_PIN R4 IOSTANDARD LVCMOS33 } [get_ports { IO_CLK }]; #IO_L13P_T2_MRCC_34 Sch=sysclk
-create_clock -add -name sys_clk_pin -period 10.00 -waveform {0 5} [get_ports IO_CLK]
-
-## Clock constraints
-## set via clocks.xdc
-
-## Preserve prim_prince modules and setup multi-cycle paths
-## These are no longer required, but kept here as a reference
-## set_property KEEP_HIERARCHY TRUE [get_cells top_earlgrey/u_flash_eflash/gen_flash_banks[*].i_core/u_scramble/u_cipher]
-## set_multicycle_path -setup 2 -through [get_pins -of_objects [get_cells top_earlgrey/u_flash_eflash/gen_flash_banks[*].i_core/u_scramble/u_cipher]]
-## set_multicycle_path -hold 1 -through [get_pins -of_objects [get_cells top_earlgrey/u_flash_eflash/gen_flash_banks[*].i_core/u_scramble/u_cipher]]
-
-#set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets IO_SDCK_IBUF]; # SDCK clock to be ignored
-
-## FMC Transceiver clocks (Must be set to value provided by Mezzanine card, currently set to 156.25 MHz)
-## Note: This clock is attached to a MGTREFCLK pin
-#set_property -dict { PACKAGE_PIN E6 } [get_ports { GTP_CLK_N }];
-#set_property -dict { PACKAGE_PIN F6 } [get_ports { GTP_CLK_P }];
-#create_clock -add -name gtpclk0_pin -period 6.400 -waveform {0 3.200} [get_ports {GTP_CLK_P}];
-#set_property -dict { PACKAGE_PIN E10 } [get_ports { FMC_MGT_CLK_N }];
-#set_property -dict { PACKAGE_PIN F10 } [get_ports { FMC_MGT_CLK_P }];
-#create_clock -add -name mgtclk1_pin -period 6.400 -waveform {0 3.200} [get_ports {FMC_MGT_CLK_P}];
-
-
-## LEDs
-set_property -dict { PACKAGE_PIN T14 IOSTANDARD LVCMOS25 } [get_ports { IOA8 }]; #IO_L15P_T2_DQS_13 Sch=led[0]
-set_property -dict { PACKAGE_PIN T15 IOSTANDARD LVCMOS25 } [get_ports { IOB0 }]; #IO_L15N_T2_DQS_13 Sch=led[1]
-set_property -dict { PACKAGE_PIN T16 IOSTANDARD LVCMOS25 } [get_ports { IOB1 }]; #IO_L17P_T2_13 Sch=led[2]
-set_property -dict { PACKAGE_PIN U16 IOSTANDARD LVCMOS25 } [get_ports { IOB2 }]; #IO_L17N_T2_13 Sch=led[3]
-set_property -dict { PACKAGE_PIN V15 IOSTANDARD LVCMOS25 } [get_ports { IOB3 }]; #IO_L14N_T2_SRCC_13 Sch=led[4]
-set_property -dict { PACKAGE_PIN W16 IOSTANDARD LVCMOS25 } [get_ports { IOB4 }]; #IO_L16N_T2_13 Sch=led[5]
-set_property -dict { PACKAGE_PIN W15 IOSTANDARD LVCMOS25 } [get_ports { IOB5 }]; #IO_L16P_T2_13 Sch=led[6]
-set_property -dict { PACKAGE_PIN Y13 IOSTANDARD LVCMOS25 } [get_ports { IOB6 }]; #IO_L5P_T0_13 Sch=led[7]
-
-
-## Buttons
-#set_property -dict { PACKAGE_PIN B22 IOSTANDARD LVCMOS12 } [get_ports { btnc }]; #IO_L20N_T3_16 Sch=btnc
-#set_property -dict { PACKAGE_PIN D22 IOSTANDARD LVCMOS12 } [get_ports { btnd }]; #IO_L22N_T3_16 Sch=btnd
-#set_property -dict { PACKAGE_PIN C22 IOSTANDARD LVCMOS12 } [get_ports { btnl }]; #IO_L20P_T3_16 Sch=btnl
-#set_property -dict { PACKAGE_PIN D14 IOSTANDARD LVCMOS12 } [get_ports { btnr }]; #IO_L6P_T0_16 Sch=btnr
-#set_property -dict { PACKAGE_PIN F15 IOSTANDARD LVCMOS12 } [get_ports { btnu }]; #IO_0_16 Sch=btnu
-set_property -dict { PACKAGE_PIN G4 IOSTANDARD LVCMOS15 } [get_ports { POR_N }]; #IO_L12N_T1_MRCC_35 Sch=cpu_resetn
-
-
-## Switches
-set_property -dict { PACKAGE_PIN E22 IOSTANDARD LVCMOS12 } [get_ports { IOA0 }]; #IO_L22P_T3_16 Sch=sw[0]
-set_property -dict { PACKAGE_PIN F21 IOSTANDARD LVCMOS12 } [get_ports { IOA1 }]; #IO_25_16 Sch=sw[1]
-set_property -dict { PACKAGE_PIN G21 IOSTANDARD LVCMOS12 } [get_ports { IOA2 }]; #IO_L24P_T3_16 Sch=sw[2]
-set_property -dict { PACKAGE_PIN G22 IOSTANDARD LVCMOS12 } [get_ports { IOA3 }]; #IO_L24N_T3_16 Sch=sw[3]
-set_property -dict { PACKAGE_PIN H17 IOSTANDARD LVCMOS12 } [get_ports { IOA4 }]; #IO_L6P_T0_15 Sch=sw[4]
-set_property -dict { PACKAGE_PIN J16 IOSTANDARD LVCMOS12 } [get_ports { IOA5 }]; #IO_0_15 Sch=sw[5]
-set_property -dict { PACKAGE_PIN K13 IOSTANDARD LVCMOS12 } [get_ports { IOA6 }]; #IO_L19P_T3_A22_15 Sch=sw[6]
-set_property -dict { PACKAGE_PIN M17 IOSTANDARD LVCMOS12 } [get_ports { IOA7 }]; #IO_25_15 Sch=sw[7]
-
-
-## OLED Display
-#set_property -dict { PACKAGE_PIN W22 IOSTANDARD LVCMOS33 } [get_ports { oled_dc }]; #IO_L7N_T1_D10_14 Sch=oled_dc
-#set_property -dict { PACKAGE_PIN U21 IOSTANDARD LVCMOS33 } [get_ports { oled_res }]; #IO_L4N_T0_D05_14 Sch=oled_res
-#set_property -dict { PACKAGE_PIN W21 IOSTANDARD LVCMOS33 } [get_ports { oled_sclk }]; #IO_L7P_T1_D09_14 Sch=oled_sclk
-#set_property -dict { PACKAGE_PIN Y22 IOSTANDARD LVCMOS33 } [get_ports { oled_sdin }]; #IO_L9N_T1_DQS_D13_14 Sch=oled_sdin
-#set_property -dict { PACKAGE_PIN P20 IOSTANDARD LVCMOS33 } [get_ports { oled_vbat }]; #IO_0_14 Sch=oled_vbat
-#set_property -dict { PACKAGE_PIN V22 IOSTANDARD LVCMOS33 } [get_ports { oled_vdd }]; #IO_L3N_T0_DQS_EMCCLK_14 Sch=oled_vdd
-
-
-## HDMI in
-#set_property -dict { PACKAGE_PIN AA5 IOSTANDARD LVCMOS33 } [get_ports { hdmi_rx_cec }]; #IO_L10P_T1_34 Sch=hdmi_rx_cec
-#set_property -dict { PACKAGE_PIN W4 IOSTANDARD TMDS_33 } [get_ports { hdmi_rx_clk_n }]; #IO_L12N_T1_MRCC_34 Sch=hdmi_rx_clk_n
-#set_property -dict { PACKAGE_PIN V4 IOSTANDARD TMDS_33 } [get_ports { hdmi_rx_clk_p }]; #IO_L12P_T1_MRCC_34 Sch=hdmi_rx_clk_p
-#set_property -dict { PACKAGE_PIN AB12 IOSTANDARD LVCMOS25 } [get_ports { hdmi_rx_hpa }]; #IO_L7N_T1_13 Sch=hdmi_rx_hpa
-#set_property -dict { PACKAGE_PIN Y4 IOSTANDARD LVCMOS33 } [get_ports { hdmi_rx_scl }]; #IO_L11P_T1_SRCC_34 Sch=hdmi_rx_scl
-#set_property -dict { PACKAGE_PIN AB5 IOSTANDARD LVCMOS33 } [get_ports { hdmi_rx_sda }]; #IO_L10N_T1_34 Sch=hdmi_rx_sda
-#set_property -dict { PACKAGE_PIN R3 IOSTANDARD LVCMOS33 } [get_ports { hdmi_rx_txen }]; #IO_L3P_T0_DQS_34 Sch=hdmi_rx_txen
-#set_property -dict { PACKAGE_PIN AA3 IOSTANDARD TMDS_33 } [get_ports { hdmi_rx_n[0] }]; #IO_L9N_T1_DQS_34 Sch=hdmi_rx_n[0]
-#set_property -dict { PACKAGE_PIN Y3 IOSTANDARD TMDS_33 } [get_ports { hdmi_rx_p[0] }]; #IO_L9P_T1_DQS_34 Sch=hdmi_rx_p[0]
-#set_property -dict { PACKAGE_PIN Y2 IOSTANDARD TMDS_33 } [get_ports { hdmi_rx_n[1] }]; #IO_L4N_T0_34 Sch=hdmi_rx_n[1]
-#set_property -dict { PACKAGE_PIN W2 IOSTANDARD TMDS_33 } [get_ports { hdmi_rx_p[1] }]; #IO_L4P_T0_34 Sch=hdmi_rx_p[1]
-#set_property -dict { PACKAGE_PIN V2 IOSTANDARD TMDS_33 } [get_ports { hdmi_rx_n[2] }]; #IO_L2N_T0_34 Sch=hdmi_rx_n[2]
-#set_property -dict { PACKAGE_PIN U2 IOSTANDARD TMDS_33 } [get_ports { hdmi_rx_p[2] }]; #IO_L2P_T0_34 Sch=hdmi_rx_p[2]
-
-
-## HDMI out
-#set_property -dict { PACKAGE_PIN AA4 IOSTANDARD LVCMOS33 } [get_ports { hdmi_tx_cec }]; #IO_L11N_T1_SRCC_34 Sch=hdmi_tx_cec
-#set_property -dict { PACKAGE_PIN U1 IOSTANDARD TMDS_33 } [get_ports { hdmi_tx_clk_n }]; #IO_L1N_T0_34 Sch=hdmi_tx_clk_n
-#set_property -dict { PACKAGE_PIN T1 IOSTANDARD TMDS_33 } [get_ports { hdmi_tx_clk_p }]; #IO_L1P_T0_34 Sch=hdmi_tx_clk_p
-#set_property -dict { PACKAGE_PIN AB13 IOSTANDARD LVCMOS25 } [get_ports { hdmi_tx_hpd }]; #IO_L3N_T0_DQS_13 Sch=hdmi_tx_hpd
-#set_property -dict { PACKAGE_PIN U3 IOSTANDARD LVCMOS33 } [get_ports { hdmi_tx_rscl }]; #IO_L6P_T0_34 Sch=hdmi_tx_rscl
-#set_property -dict { PACKAGE_PIN V3 IOSTANDARD LVCMOS33 } [get_ports { hdmi_tx_rsda }]; #IO_L6N_T0_VREF_34 Sch=hdmi_tx_rsda
-#set_property -dict { PACKAGE_PIN Y1 IOSTANDARD TMDS_33 } [get_ports { hdmi_tx_n[0] }]; #IO_L5N_T0_34 Sch=hdmi_tx_n[0]
-#set_property -dict { PACKAGE_PIN W1 IOSTANDARD TMDS_33 } [get_ports { hdmi_tx_p[0] }]; #IO_L5P_T0_34 Sch=hdmi_tx_p[0]
-#set_property -dict { PACKAGE_PIN AB1 IOSTANDARD TMDS_33 } [get_ports { hdmi_tx_n[1] }]; #IO_L7N_T1_34 Sch=hdmi_tx_n[1]
-#set_property -dict { PACKAGE_PIN AA1 IOSTANDARD TMDS_33 } [get_ports { hdmi_tx_p[1] }]; #IO_L7P_T1_34 Sch=hdmi_tx_p[1]
-#set_property -dict { PACKAGE_PIN AB2 IOSTANDARD TMDS_33 } [get_ports { hdmi_tx_n[2] }]; #IO_L8N_T1_34 Sch=hdmi_tx_n[2]
-#set_property -dict { PACKAGE_PIN AB3 IOSTANDARD TMDS_33 } [get_ports { hdmi_tx_p[2] }]; #IO_L8P_T1_34 Sch=hdmi_tx_p[2]
-
-
-## Display Port
-#set_property -dict { PACKAGE_PIN AB10 IOSTANDARD TMDS_33 } [get_ports { dp_tx_aux_n }]; #IO_L8N_T1_13 Sch=dp_tx_aux_n
-#set_property -dict { PACKAGE_PIN AA11 IOSTANDARD TMDS_33 } [get_ports { dp_tx_aux_n }]; #IO_L9N_T1_DQS_13 Sch=dp_tx_aux_n
-#set_property -dict { PACKAGE_PIN AA9 IOSTANDARD TMDS_33 } [get_ports { dp_tx_aux_p }]; #IO_L8P_T1_13 Sch=dp_tx_aux_p
-#set_property -dict { PACKAGE_PIN AA10 IOSTANDARD TMDS_33 } [get_ports { dp_tx_aux_p }]; #IO_L9P_T1_DQS_13 Sch=dp_tx_aux_p
-#set_property -dict { PACKAGE_PIN N15 IOSTANDARD LVCMOS33 } [get_ports { dp_tx_hpd }]; #IO_25_14 Sch=dp_tx_hpd
-
-
-## Audio Codec
-#set_property -dict { PACKAGE_PIN T4 IOSTANDARD LVCMOS33 } [get_ports { ac_adc_sdata }]; #IO_L13N_T2_MRCC_34 Sch=ac_adc_sdata
-#set_property -dict { PACKAGE_PIN T5 IOSTANDARD LVCMOS33 } [get_ports { ac_bclk }]; #IO_L14P_T2_SRCC_34 Sch=ac_bclk
-#set_property -dict { PACKAGE_PIN W6 IOSTANDARD LVCMOS33 } [get_ports { ac_dac_sdata }]; #IO_L15P_T2_DQS_34 Sch=ac_dac_sdata
-#set_property -dict { PACKAGE_PIN U5 IOSTANDARD LVCMOS33 } [get_ports { ac_lrclk }]; #IO_L14N_T2_SRCC_34 Sch=ac_lrclk
-#set_property -dict { PACKAGE_PIN U6 IOSTANDARD LVCMOS33 } [get_ports { ac_mclk }]; #IO_L16P_T2_34 Sch=ac_mclk
-
-
-## Pmod header JA
-set_property -dict { PACKAGE_PIN AB22 IOSTANDARD LVCMOS33 } [get_ports { IOC2 }]; #IO_L10N_T1_D15_14 Sch=ja[1]
-set_property -dict { PACKAGE_PIN AB18 IOSTANDARD LVCMOS33 } [get_ports { IOC5 }]; #IO_L17N_T2_A13_D29_14 Sch=ja[4]
-set_property -dict { PACKAGE_PIN Y21 IOSTANDARD LVCMOS33 } [get_ports { IOC6 }]; #IO_L9P_T1_DQS_14 Sch=ja[7]
-set_property -dict { PACKAGE_PIN AA21 IOSTANDARD LVCMOS33 } [get_ports { IOC7 }]; #IO_L8N_T1_D12_14 Sch=ja[8]
-set_property -dict { PACKAGE_PIN AA20 IOSTANDARD LVCMOS33 } [get_ports { IOC8 }]; #IO_L8P_T1_D11_14 Sch=ja[9]
-set_property -dict { PACKAGE_PIN AA18 IOSTANDARD LVCMOS33 } [get_ports { IOC9 }]; #IO_L17P_T2_A14_D30_14 Sch=ja[10]
-set_property -dict { PACKAGE_PIN AB21 IOSTANDARD LVCMOS33 } [get_ports { IOC10 }]; #IO_L10P_T1_D14_14 Sch=ja[2]
-set_property -dict { PACKAGE_PIN AB20 IOSTANDARD LVCMOS33 } [get_ports { IOC11 }]; #IO_L15N_T2_DQS_DOUT_CSO_B_14 Sch=ja[3]
-
-
-## Pmod header JB
-set_property -dict { PACKAGE_PIN V9 IOSTANDARD LVCMOS33 DRIVE 8 SLEW FAST } [get_ports { USB_P }]; #IO_L21P_T3_DQS_34 Sch=jb_p[1]
-set_property -dict { PACKAGE_PIN V8 IOSTANDARD LVCMOS33 DRIVE 8 SLEW FAST } [get_ports { USB_N }]; #IO_L21N_T3_DQS_34 Sch=jb_n[1]
-set_property -dict { PACKAGE_PIN V7 IOSTANDARD LVCMOS33 } [get_ports { IO_USB_DPPULLUP0 }]; #IO_L19P_T3_34 Sch=jb_p[2]
-set_property -dict { PACKAGE_PIN W7 IOSTANDARD LVCMOS33 } [get_ports { IOR1 }]; #IO_L19N_T3_VREF_34 Sch=jb_n[2]
-set_property -dict { PACKAGE_PIN Y8 IOSTANDARD LVCMOS33 } [get_ports { IO_USB_DNPULLUP0 }]; #IO_L23P_T3_34 Sch=jb_p[4]
-
-## Pmod header JB UNUSED pins (used for testing 2 USB interfaces)
-#set_property -dict { PACKAGE_PIN W9 IOSTANDARD LVCMOS33 DRIVE 8 SLEW FAST } [get_ports { IO_USB_DP1 }]; #IO_L24P_T3_34 Sch=jb_p[3]
-#set_property -dict { PACKAGE_PIN Y9 IOSTANDARD LVCMOS33 DRIVE 8 SLEW FAST } [get_ports { IO_USB_DN1 }]; #IO_L24N_T3_34 Sch=jb_n[3]
-#set_property -dict { PACKAGE_PIN Y7 IOSTANDARD LVCMOS33 } [get_ports { IO_USB_SENSE1 }]; #IO_L23N_T3_34 Sch=jb_n[4]
-
-## Pmod header JC -- When used for SPI
-#set_property -dict { PACKAGE_PIN Y6 IOSTANDARD LVCMOS33 } [get_ports { IO_SDCK }]; #IO_L18P_T2_34 Sch=jc_p[1]
-#set_property -dict { PACKAGE_PIN AA6 IOSTANDARD LVCMOS33 } [get_ports { IO_SDCSB }]; #IO_L18N_T2_34 Sch=jc_n[1]
-#set_property -dict { PACKAGE_PIN AA8 IOSTANDARD LVCMOS33 } [get_ports { IO_SDSDI }]; #IO_L22P_T3_34 Sch=jc_p[2]
-#set_property -dict { PACKAGE_PIN AB8 IOSTANDARD LVCMOS33 } [get_ports { IO_SDSDO }]; #IO_L22N_T3_34 Sch=jc_n[2]
-
-## Pmod header JC -- When used for TI TUSB1106 USB PHY usbdev testing
-set_property -dict { PACKAGE_PIN Y6 IOSTANDARD LVCMOS33 } [get_ports { IO_UPHY_DP_TX }]; #IO_L18P_T2_34 Sch=jc_p[1]
-set_property -dict { PACKAGE_PIN AA6 IOSTANDARD LVCMOS33 } [get_ports { IO_UPHY_DN_TX }]; #IO_L18N_T2_34 Sch=jc_n[1]
-set_property -dict { PACKAGE_PIN AA8 IOSTANDARD LVCMOS33 } [get_ports { IO_UPHY_DP_RX }]; #IO_L22P_T3_34 Sch=jc_p[2]
-set_property -dict { PACKAGE_PIN AB8 IOSTANDARD LVCMOS33 } [get_ports { IO_UPHY_DN_RX }]; #IO_L22N_T3_34 Sch=jc_n[2]
-set_property -dict { PACKAGE_PIN R6 IOSTANDARD LVCMOS33 } [get_ports { IO_UPHY_DPPULLUP }]; #IO_L17P_T2_34 Sch=jc_p[3]
-set_property -dict { PACKAGE_PIN T6 IOSTANDARD LVCMOS33 } [get_ports { IOR0 }]; #IO_L17N_T2_34 Sch=jc_n[3]
-set_property -dict { PACKAGE_PIN AB7 IOSTANDARD LVCMOS33 } [get_ports { IO_UPHY_OE_N }]; #IO_L20P_T3_34 Sch=jc_p[4]
-set_property -dict { PACKAGE_PIN AB6 IOSTANDARD LVCMOS33 } [get_ports { IO_UPHY_D_RX }]; #IO_L20N_T3_34 Sch=jc_n[4]
-
-## USB input delay to accommodate T_FST (full-speed transition time) and the
-## PHY's sampling logic. The PHY expects to only see up to one transient / fake
-## SE0. The phase relationship with the PHY's sampling clock is arbitrary, but
-## for simplicity, constrain the maximum path delay to something smaller than
-## `T_sample - T_FST(max)` to help keep the P/N skew from slipping beyond one
-## sample period.
-set clks_48_unbuf [get_clocks -of_objects [get_pin clkgen/pll/CLKOUT1]]
-set_input_delay -clock ${clks_48_unbuf} -min 3 [get_ports {IO_UPHY_DP_RX IO_UPHY_DN_RX IO_UPHY_D_RX}]
-set_input_delay -clock ${clks_48_unbuf} -add_delay -max 17 [get_ports {IO_UPHY_DP_RX IO_UPHY_DN_RX IO_UPHY_D_RX}]
-
-## USB output max skew constraint
-## Use the output-enable as a "clock" and time the P/N relative to it. Keep the skew within T_FST.
-set usb_embed_out_clk [create_generated_clock -name usb_embed_out_clk -source [get_pin clkgen/pll/CLKOUT1] -multiply_by 1 [get_ports IO_UPHY_OE_N]]
-set_false_path -from [get_clocks -include_generated_clocks clk_io_div4] -to ${usb_embed_out_clk}
-set_output_delay -min -clock ${usb_embed_out_clk} 7 [get_ports {IO_UPHY_DP_TX IO_UPHY_DN_TX}]
-set_output_delay -max -clock ${usb_embed_out_clk} 14 [get_ports {IO_UPHY_DP_TX IO_UPHY_DN_TX}] -add_delay
-
-## Pmod header JC -- Default
-#set_property -dict { PACKAGE_PIN Y6 IOSTANDARD LVCMOS33 } [get_ports { IO_OBS }]; #IO_L18P_T2_34 Sch=jc_p[1]
-#set_property -dict { PACKAGE_PIN AA6 IOSTANDARD LVCMOS33 } [get_ports { jc[1] }]; #IO_L18N_T2_34 Sch=jc_n[1]
-#set_property -dict { PACKAGE_PIN AA8 IOSTANDARD LVCMOS33 } [get_ports { jc[2] }]; #IO_L22P_T3_34 Sch=jc_p[2]
-#set_property -dict { PACKAGE_PIN AB8 IOSTANDARD LVCMOS33 } [get_ports { jc[3] }]; #IO_L22N_T3_34 Sch=jc_n[2]
-#set_property -dict { PACKAGE_PIN R6 IOSTANDARD LVCMOS33 } [get_ports { jc[4] }]; #IO_L17P_T2_34 Sch=jc_p[3]
-#set_property -dict { PACKAGE_PIN T6 IOSTANDARD LVCMOS33 } [get_ports { jc[5] }]; #IO_L17N_T2_34 Sch=jc_n[3]
-#set_property -dict { PACKAGE_PIN AB7 IOSTANDARD LVCMOS33 } [get_ports { jc[6] }]; #IO_L20P_T3_34 Sch=jc_p[4]
-#set_property -dict { PACKAGE_PIN AB6 IOSTANDARD LVCMOS33 } [get_ports { jc[7] }]; #IO_L20N_T3_34 Sch=jc_n[4]
-
-
-## XADC Header
-#set_property -dict { PACKAGE_PIN J14 IOSTANDARD LVCMOS33 } [get_ports { xa_p[0] }]; #IO_L3P_T0_DQS_AD1P_15 Sch=xa_p[1]
-#set_property -dict { PACKAGE_PIN H14 IOSTANDARD LVCMOS33 } [get_ports { xa_n[0] }]; #IO_L3N_T0_DQS_AD1N_15 Sch=xa_n[1]
-#set_property -dict { PACKAGE_PIN H13 IOSTANDARD LVCMOS33 } [get_ports { xa_p[1] }]; #IO_L1P_T0_AD0P_15 Sch=xa_p[2]
-#set_property -dict { PACKAGE_PIN G13 IOSTANDARD LVCMOS33 } [get_ports { xa_n[1] }]; #IO_L1N_T0_AD0N_15 Sch=xa_n[2]
-#set_property -dict { PACKAGE_PIN G15 IOSTANDARD LVCMOS33 } [get_ports { xa_p[2] }]; #IO_L2P_T0_AD8P_15 Sch=xa_p[3]
-#set_property -dict { PACKAGE_PIN G16 IOSTANDARD LVCMOS33 } [get_ports { xa_n[2] }]; #IO_L2N_T0_AD8N_15 Sch=xa_n[3]
-#set_property -dict { PACKAGE_PIN J15 IOSTANDARD LVCMOS33 } [get_ports { xa_p[3] }]; #IO_L5P_T0_AD9P_15 Sch=xa_p[4]
-#set_property -dict { PACKAGE_PIN H15 IOSTANDARD LVCMOS33 } [get_ports { xa_n[3] }]; #IO_L5N_T0_AD9N_15 Sch=xa_n[4]
-
-
-## UART
-set_property -dict { PACKAGE_PIN AA19 IOSTANDARD LVCMOS33 } [get_ports { IOC4 }]; #IO_L15P_T2_DQS_RDWR_B_14 Sch=uart_rx_out
-set_property -dict { PACKAGE_PIN V18 IOSTANDARD LVCMOS33 } [get_ports { IOC3 }]; #IO_L14P_T2_SRCC_14 Sch=uart_tx_in
-
-
-## Ethernet
-#set_property -dict { PACKAGE_PIN Y14 IOSTANDARD LVCMOS25 } [get_ports { eth_int_b }]; #IO_L6N_T0_VREF_13 Sch=eth_int_b
-#set_property -dict { PACKAGE_PIN AA16 IOSTANDARD LVCMOS25 } [get_ports { eth_mdc }]; #IO_L1N_T0_13 Sch=eth_mdc
-#set_property -dict { PACKAGE_PIN Y16 IOSTANDARD LVCMOS25 } [get_ports { eth_mdio }]; #IO_L1P_T0_13 Sch=eth_mdio
-#set_property -dict { PACKAGE_PIN W14 IOSTANDARD LVCMOS25 } [get_ports { eth_pme_b }]; #IO_L6P_T0_13 Sch=eth_pme_b
-#set_property -dict { PACKAGE_PIN U7 IOSTANDARD LVCMOS33 } [get_ports { eth_rst_b }]; #IO_25_34 Sch=eth_rst_b
-#set_property -dict { PACKAGE_PIN V13 IOSTANDARD LVCMOS25 } [get_ports { eth_rxck }]; #IO_L13P_T2_MRCC_13 Sch=eth_rxck
-#set_property -dict { PACKAGE_PIN W10 IOSTANDARD LVCMOS25 } [get_ports { eth_rxctl }]; #IO_L10N_T1_13 Sch=eth_rxctl
-#set_property -dict { PACKAGE_PIN AB16 IOSTANDARD LVCMOS25 } [get_ports { eth_rxd[0] }]; #IO_L2P_T0_13 Sch=eth_rxd[0]
-#set_property -dict { PACKAGE_PIN AA15 IOSTANDARD LVCMOS25 } [get_ports { eth_rxd[1] }]; #IO_L4P_T0_13 Sch=eth_rxd[1]
-#set_property -dict { PACKAGE_PIN AB15 IOSTANDARD LVCMOS25 } [get_ports { eth_rxd[2] }]; #IO_L4N_T0_13 Sch=eth_rxd[2]
-#set_property -dict { PACKAGE_PIN AB11 IOSTANDARD LVCMOS25 } [get_ports { eth_rxd[3] }]; #IO_L7P_T1_13 Sch=eth_rxd[3]
-#set_property -dict { PACKAGE_PIN AA14 IOSTANDARD LVCMOS25 } [get_ports { eth_txck }]; #IO_L5N_T0_13 Sch=eth_txck
-#set_property -dict { PACKAGE_PIN V10 IOSTANDARD LVCMOS25 } [get_ports { eth_txctl }]; #IO_L10P_T1_13 Sch=eth_txctl
-#set_property -dict { PACKAGE_PIN Y12 IOSTANDARD LVCMOS25 } [get_ports { eth_txd[0] }]; #IO_L11N_T1_SRCC_13 Sch=eth_txd[0]
-#set_property -dict { PACKAGE_PIN W12 IOSTANDARD LVCMOS25 } [get_ports { eth_txd[1] }]; #IO_L12N_T1_MRCC_13 Sch=eth_txd[1]
-#set_property -dict { PACKAGE_PIN W11 IOSTANDARD LVCMOS25 } [get_ports { eth_txd[2] }]; #IO_L12P_T1_MRCC_13 Sch=eth_txd[2]
-#set_property -dict { PACKAGE_PIN Y11 IOSTANDARD LVCMOS25 } [get_ports { eth_txd[3] }]; #IO_L11P_T1_SRCC_13 Sch=eth_txd[3]
-
-
-## Fan PWM
-#set_property -dict { PACKAGE_PIN U15 IOSTANDARD LVCMOS25 } [get_ports { fan_pwm }]; #IO_L14P_T2_SRCC_13 Sch=fan_pwm
-
-
-## DPTI/DSPI
-#set_property -dict { PACKAGE_PIN Y18 IOSTANDARD LVCMOS33 } [get_ports { prog_clko }]; #IO_L13P_T2_MRCC_14 Sch=prog_clko
-set_property -dict { PACKAGE_PIN U20 IOSTANDARD LVCMOS33 } [get_ports { SPI_DEV_CLK }]; #IO_L11P_T1_SRCC_14 Sch=prog_d0/sck
-set_property -dict { PACKAGE_PIN P14 IOSTANDARD LVCMOS33 } [get_ports { SPI_DEV_D0 }]; #IO_L19P_T3_A10_D26_14 Sch=prog_d1/sdi
-set_property -dict { PACKAGE_PIN P15 IOSTANDARD LVCMOS33 } [get_ports { SPI_DEV_D1 }]; #IO_L22P_T3_A05_D21_14 Sch=prog_d2/sdo
-set_property -dict { PACKAGE_PIN U17 IOSTANDARD LVCMOS33 } [get_ports { SPI_DEV_CS_L }]; #IO_L18P_T2_A12_D28_14 Sch=prog_d3/ss
-set_property -dict { PACKAGE_PIN R17 IOSTANDARD LVCMOS33 } [get_ports { IOB9 }]; #IO_L24N_T3_A00_D16_14 Sch=prog_d[4]
-set_property -dict { PACKAGE_PIN P16 IOSTANDARD LVCMOS33 PULLTYPE PULLUP } [get_ports { IO_JSRST_N }]; #IO_L24P_T3_A01_D17_14 Sch=prog_d[5]
-set_property -dict { PACKAGE_PIN R18 IOSTANDARD LVCMOS33 PULLTYPE PULLDOWN } [get_ports { IOB7 }]; #IO_L20P_T3_A08_D24_14 Sch=prog_d[6]
-set_property -dict { PACKAGE_PIN N14 IOSTANDARD LVCMOS33 PULLTYPE PULLDOWN } [get_ports { IOB8 }]; #IO_L23N_T3_A02_D18_14 Sch=prog_d[7]
-#set_property -dict { PACKAGE_PIN V17 IOSTANDARD LVCMOS33 } [get_ports { prog_oen }]; #IO_L16P_T2_CSI_B_14 Sch=prog_oen
-#set_property -dict { PACKAGE_PIN P19 IOSTANDARD LVCMOS33 } [get_ports { prog_rdn }]; #IO_L5P_T0_D06_14 Sch=prog_rdn
-#set_property -dict { PACKAGE_PIN N17 IOSTANDARD LVCMOS33 } [get_ports { prog_rxen }]; #IO_L21P_T3_DQS_14 Sch=prog_rxen
-#set_property -dict { PACKAGE_PIN P17 IOSTANDARD LVCMOS33 } [get_ports { prog_siwun }]; #IO_L21N_T3_DQS_A06_D22_14 Sch=prog_siwun
-#set_property -dict { PACKAGE_PIN R14 IOSTANDARD LVCMOS33 } [get_ports { prog_spien }]; #IO_L19N_T3_A09_D25_VREF_14 Sch=prog_spien
-#set_property -dict { PACKAGE_PIN Y19 IOSTANDARD LVCMOS33 } [get_ports { prog_txen }]; #IO_L13N_T2_MRCC_14 Sch=prog_txen
-#set_property -dict { PACKAGE_PIN R19 IOSTANDARD LVCMOS33 } [get_ports { prog_wrn }]; #IO_L5N_T0_D07_14 Sch=prog_wrn
-
-
-## HID port
-#set_property -dict { PACKAGE_PIN W17 IOSTANDARD LVCMOS33 PULLUP true } [get_ports { ps2_clk }]; #IO_L16N_T2_A15_D31_14 Sch=ps2_clk
-#set_property -dict { PACKAGE_PIN N13 IOSTANDARD LVCMOS33 PULLUP true } [get_ports { ps2_data }]; #IO_L23P_T3_A03_D19_14 Sch=ps2_data
-
-
-## QSPI
-#set_property -dict { PACKAGE_PIN T19 IOSTANDARD LVCMOS33 } [get_ports { qspi_cs }]; #IO_L6P_T0_FCS_B_14 Sch=qspi_cs
-#set_property -dict { PACKAGE_PIN P22 IOSTANDARD LVCMOS33 } [get_ports { qspi_dq[0] }]; #IO_L1P_T0_D00_SDI_14 Sch=qspi_dq[0]
-#set_property -dict { PACKAGE_PIN R22 IOSTANDARD LVCMOS33 } [get_ports { qspi_dq[1] }]; #IO_L1N_T0_D01_DIN_14 Sch=qspi_dq[1]
-#set_property -dict { PACKAGE_PIN P21 IOSTANDARD LVCMOS33 } [get_ports { qspi_dq[2] }]; #IO_L2P_T0_D02_14 Sch=qspi_dq[2]
-#set_property -dict { PACKAGE_PIN R21 IOSTANDARD LVCMOS33 } [get_ports { qspi_dq[3] }]; #IO_L2N_T0_D03_14 Sch=qspi_dq[3]
-
-
-## SD card
-#set_property -dict { PACKAGE_PIN W19 IOSTANDARD LVCMOS33 } [get_ports { sd_cclk }]; #IO_L12P_T1_MRCC_14 Sch=sd_cclk
-#set_property -dict { PACKAGE_PIN T18 IOSTANDARD LVCMOS33 } [get_ports { sd_cd }]; #IO_L20N_T3_A07_D23_14 Sch=sd_cd
-#set_property -dict { PACKAGE_PIN W20 IOSTANDARD LVCMOS33 } [get_ports { sd_cmd }]; #IO_L12N_T1_MRCC_14 Sch=sd_cmd
-#set_property -dict { PACKAGE_PIN V19 IOSTANDARD LVCMOS33 } [get_ports { sd_d[0] }]; #IO_L14N_T2_SRCC_14 Sch=sd_d[0]
-#set_property -dict { PACKAGE_PIN T21 IOSTANDARD LVCMOS33 } [get_ports { sd_d[1] }]; #IO_L4P_T0_D04_14 Sch=sd_d[1]
-#set_property -dict { PACKAGE_PIN T20 IOSTANDARD LVCMOS33 } [get_ports { sd_d[2] }]; #IO_L6N_T0_D08_VREF_14 Sch=sd_d[2]
-#set_property -dict { PACKAGE_PIN U18 IOSTANDARD LVCMOS33 } [get_ports { sd_d[3] }]; #IO_L18N_T2_A11_D27_14 Sch=sd_d[3]
-#set_property -dict { PACKAGE_PIN V20 IOSTANDARD LVCMOS33 } [get_ports { sd_reset }]; #IO_L11N_T1_SRCC_14 Sch=sd_reset
-
-
-## I2C
-#set_property -dict { PACKAGE_PIN W5 IOSTANDARD LVCMOS33 } [get_ports { scl }]; #IO_L15N_T2_DQS_34 Sch=scl
-#set_property -dict { PACKAGE_PIN V5 IOSTANDARD LVCMOS33 } [get_ports { sda }]; #IO_L16N_T2_34 Sch=sda
-
-
-## Voltage Adjust
-#set_property -dict { PACKAGE_PIN AA13 IOSTANDARD LVCMOS25 } [get_ports { set_vadj[0] }]; #IO_L3P_T0_DQS_13 Sch=set_vadj[0]
-#set_property -dict { PACKAGE_PIN AB17 IOSTANDARD LVCMOS25 } [get_ports { set_vadj[1] }]; #IO_L2N_T0_13 Sch=set_vadj[1]
-#set_property -dict { PACKAGE_PIN V14 IOSTANDARD LVCMOS25 } [get_ports { vadj_en }]; #IO_L13N_T2_MRCC_13 Sch=vadj_en
-
-
-## FMC
-#set_property -dict { PACKAGE_PIN H19 IOSTANDARD LVCMOS12 } [get_ports { fmc_clk0_m2c_n }]; #IO_L12N_T1_MRCC_15 Sch=fmc_clk0_m2c_n
-#set_property -dict { PACKAGE_PIN J19 IOSTANDARD LVCMOS12 } [get_ports { fmc_clk0_m2c_p }]; #IO_L12P_T1_MRCC_15 Sch=fmc_clk0_m2c_p
-#set_property -dict { PACKAGE_PIN C19 IOSTANDARD LVCMOS12 } [get_ports { fmc_clk1_m2c_n }]; #IO_L13N_T2_MRCC_16 Sch=fmc_clk1_m2c_n
-#set_property -dict { PACKAGE_PIN C18 IOSTANDARD LVCMOS12 } [get_ports { fmc_clk1_m2c_p }]; #IO_L13P_T2_MRCC_16 Sch=fmc_clk1_m2c_p
-#set_property -dict { PACKAGE_PIN K19 IOSTANDARD LVCMOS12 } [get_ports { fmc_la00_cc_n }]; #IO_L13N_T2_MRCC_15 Sch=fmc_la00_cc_n
-#set_property -dict { PACKAGE_PIN K18 IOSTANDARD LVCMOS12 } [get_ports { fmc_la00_cc_p }]; #IO_L13P_T2_MRCC_15 Sch=fmc_la00_cc_p
-#set_property -dict { PACKAGE_PIN J21 IOSTANDARD LVCMOS12 } [get_ports { fmc_la01_cc_n }]; #IO_L11N_T1_SRCC_15 Sch=fmc_la01_cc_n
-#set_property -dict { PACKAGE_PIN J20 IOSTANDARD LVCMOS12 } [get_ports { fmc_la01_cc_p }]; #IO_L11P_T1_SRCC_15 Sch=fmc_la01_cc_p
-#set_property -dict { PACKAGE_PIN L18 IOSTANDARD LVCMOS12 } [get_ports { fmc_la_n[02] }]; #IO_L16N_T2_A27_15 Sch=fmc_la_n[02]
-#set_property -dict { PACKAGE_PIN M18 IOSTANDARD LVCMOS12 } [get_ports { fmc_la_p[02] }]; #IO_L16P_T2_A28_15 Sch=fmc_la_p[02]
-#set_property -dict { PACKAGE_PIN N19 IOSTANDARD LVCMOS12 } [get_ports { fmc_la_n[03] }]; #IO_L17N_T2_A25_15 Sch=fmc_la_n[03]
-#set_property -dict { PACKAGE_PIN N18 IOSTANDARD LVCMOS12 } [get_ports { fmc_la_p[03] }]; #IO_L17P_T2_A26_15 Sch=fmc_la_p[03]
-#set_property -dict { PACKAGE_PIN M20 IOSTANDARD LVCMOS12 } [get_ports { fmc_la_n[04] }]; #IO_L18N_T2_A23_15 Sch=fmc_la_n[04]
-#set_property -dict { PACKAGE_PIN N20 IOSTANDARD LVCMOS12 } [get_ports { fmc_la_p[04] }]; #IO_L18P_T2_A24_15 Sch=fmc_la_p[04]
-#set_property -dict { PACKAGE_PIN L21 IOSTANDARD LVCMOS12 } [get_ports { fmc_la_n[05] }]; #IO_L10N_T1_AD11N_15 Sch=fmc_la_n[05]
-#set_property -dict { PACKAGE_PIN M21 IOSTANDARD LVCMOS12 } [get_ports { fmc_la_p[05] }]; #IO_L10P_T1_AD11P_15 Sch=fmc_la_p[05]
-#set_property -dict { PACKAGE_PIN M22 IOSTANDARD LVCMOS12 } [get_ports { fmc_la_n[06] }]; #IO_L15N_T2_DQS_ADV_B_15 Sch=fmc_la_n[06]
-#set_property -dict { PACKAGE_PIN N22 IOSTANDARD LVCMOS12 } [get_ports { fmc_la_p[06] }]; #IO_L15P_T2_DQS_15 Sch=fmc_la_p[06]
-#set_property -dict { PACKAGE_PIN L13 IOSTANDARD LVCMOS12 } [get_ports { fmc_la_n[07] }]; #IO_L20N_T3_A19_15 Sch=fmc_la_n[07]
-#set_property -dict { PACKAGE_PIN M13 IOSTANDARD LVCMOS12 } [get_ports { fmc_la_p[07] }]; #IO_L20P_T3_A20_15 Sch=fmc_la_p[07]
-#set_property -dict { PACKAGE_PIN M16 IOSTANDARD LVCMOS12 } [get_ports { fmc_la_n[08] }]; #IO_L24N_T3_RS0_15 Sch=fmc_la_n[08]
-#set_property -dict { PACKAGE_PIN M15 IOSTANDARD LVCMOS12 } [get_ports { fmc_la_p[08] }]; #IO_L24P_T3_RS1_15 Sch=fmc_la_p[08]
-#set_property -dict { PACKAGE_PIN G20 IOSTANDARD LVCMOS12 } [get_ports { fmc_la_n[09] }]; #IO_L8N_T1_AD10N_15 Sch=fmc_la_n[09]
-#set_property -dict { PACKAGE_PIN H20 IOSTANDARD LVCMOS12 } [get_ports { fmc_la_p[09] }]; #IO_L8P_T1_AD10P_15 Sch=fmc_la_p[09]
-#set_property -dict { PACKAGE_PIN K22 IOSTANDARD LVCMOS12 } [get_ports { fmc_la_n[10] }]; #IO_L9N_T1_DQS_AD3N_15 Sch=fmc_la_n[10]
-#set_property -dict { PACKAGE_PIN K21 IOSTANDARD LVCMOS12 } [get_ports { fmc_la_p[10] }]; #IO_L9P_T1_DQS_AD3P_15 Sch=fmc_la_p[10]
-#set_property -dict { PACKAGE_PIN L15 IOSTANDARD LVCMOS12 } [get_ports { fmc_la_n[11] }]; #IO_L22N_T3_A16_15 Sch=fmc_la_n[11]
-#set_property -dict { PACKAGE_PIN L14 IOSTANDARD LVCMOS12 } [get_ports { fmc_la_p[11] }]; #IO_L22P_T3_A17_15 Sch=fmc_la_p[11]
-#set_property -dict { PACKAGE_PIN L20 IOSTANDARD LVCMOS12 } [get_ports { fmc_la_n[12] }]; #IO_L14N_T2_SRCC_15 Sch=fmc_la_n[12]
-#set_property -dict { PACKAGE_PIN L19 IOSTANDARD LVCMOS12 } [get_ports { fmc_la_p[12] }]; #IO_L14P_T2_SRCC_15 Sch=fmc_la_p[12]
-#set_property -dict { PACKAGE_PIN J17 IOSTANDARD LVCMOS12 } [get_ports { fmc_la_n[13] }]; #IO_L21N_T3_DQS_A18_15 Sch=fmc_la_n[13]
-#set_property -dict { PACKAGE_PIN K17 IOSTANDARD LVCMOS12 } [get_ports { fmc_la_p[13] }]; #IO_L21P_T3_DQS_15 Sch=fmc_la_p[13]
-#set_property -dict { PACKAGE_PIN H22 IOSTANDARD LVCMOS12 } [get_ports { fmc_la_n[14] }]; #IO_L7N_T1_AD2N_15 Sch=fmc_la_n[14]
-#set_property -dict { PACKAGE_PIN J22 IOSTANDARD LVCMOS12 } [get_ports { fmc_la_p[14] }]; #IO_L7P_T1_AD2P_15 Sch=fmc_la_p[14]
-#set_property -dict { PACKAGE_PIN K16 IOSTANDARD LVCMOS12 } [get_ports { fmc_la_n[15] }]; #IO_L23N_T3_FWE_B_15 Sch=fmc_la_n[15]
-#set_property -dict { PACKAGE_PIN L16 IOSTANDARD LVCMOS12 } [get_ports { fmc_la_p[15] }]; #IO_L23P_T3_FOE_B_15 Sch=fmc_la_p[15]
-#set_property -dict { PACKAGE_PIN G18 IOSTANDARD LVCMOS12 } [get_ports { fmc_la_n[16] }]; #IO_L4N_T0_15 Sch=fmc_la_n[16]
-#set_property -dict { PACKAGE_PIN G17 IOSTANDARD LVCMOS12 } [get_ports { fmc_la_p[16] }]; #IO_L4P_T0_15 Sch=fmc_la_p[16]
-#set_property -dict { PACKAGE_PIN B18 IOSTANDARD LVCMOS12 } [get_ports { fmc_la17_cc_n }]; #IO_L11N_T1_SRCC_16 Sch=fmc_la17_cc_n
-#set_property -dict { PACKAGE_PIN B17 IOSTANDARD LVCMOS12 } [get_ports { fmc_la17_cc_p }]; #IO_L11P_T1_SRCC_16 Sch=fmc_la17_cc_p
-#set_property -dict { PACKAGE_PIN C17 IOSTANDARD LVCMOS12 } [get_ports { fmc_la18_cc_n }]; #IO_L12N_T1_MRCC_16 Sch=fmc_la18_cc_n
-#set_property -dict { PACKAGE_PIN D17 IOSTANDARD LVCMOS12 } [get_ports { fmc_la18_cc_p }]; #IO_L12P_T1_MRCC_16 Sch=fmc_la18_cc_p
-#set_property -dict { PACKAGE_PIN A19 IOSTANDARD LVCMOS12 } [get_ports { fmc_la_n[19] }]; #IO_L17N_T2_16 Sch=fmc_la_n[19]
-#set_property -dict { PACKAGE_PIN A18 IOSTANDARD LVCMOS12 } [get_ports { fmc_la_p[19] }]; #IO_L17P_T2_16 Sch=fmc_la_p[19]
-#set_property -dict { PACKAGE_PIN F20 IOSTANDARD LVCMOS12 } [get_ports { fmc_la_n[20] }]; #IO_L18N_T2_16 Sch=fmc_la_n[20]
-#set_property -dict { PACKAGE_PIN F19 IOSTANDARD LVCMOS12 } [get_ports { fmc_la_p[20] }]; #IO_L18P_T2_16 Sch=fmc_la_p[20]
-#set_property -dict { PACKAGE_PIN D19 IOSTANDARD LVCMOS12 } [get_ports { fmc_la_n[21] }]; #IO_L14N_T2_SRCC_16 Sch=fmc_la_n[21]
-#set_property -dict { PACKAGE_PIN E19 IOSTANDARD LVCMOS12 } [get_ports { fmc_la_p[21] }]; #IO_L14P_T2_SRCC_16 Sch=fmc_la_p[21]
-#set_property -dict { PACKAGE_PIN D21 IOSTANDARD LVCMOS12 } [get_ports { fmc_la_n[22] }]; #IO_L23N_T3_16 Sch=fmc_la_n[22]
-#set_property -dict { PACKAGE_PIN E21 IOSTANDARD LVCMOS12 } [get_ports { fmc_la_p[22] }]; #IO_L23P_T3_16 Sch=fmc_la_p[22]
-#set_property -dict { PACKAGE_PIN A21 IOSTANDARD LVCMOS12 } [get_ports { fmc_la_n[23] }]; #IO_L21N_T3_DQS_16 Sch=fmc_la_n[23]
-#set_property -dict { PACKAGE_PIN B21 IOSTANDARD LVCMOS12 } [get_ports { fmc_la_p[23] }]; #IO_L21P_T3_DQS_16 Sch=fmc_la_p[23]
-#set_property -dict { PACKAGE_PIN B16 IOSTANDARD LVCMOS12 } [get_ports { fmc_la_n[24] }]; #IO_L7N_T1_16 Sch=fmc_la_n[24]
-#set_property -dict { PACKAGE_PIN B15 IOSTANDARD LVCMOS12 } [get_ports { fmc_la_p[24] }]; #IO_L7P_T1_16 Sch=fmc_la_p[24]
-#set_property -dict { PACKAGE_PIN E17 IOSTANDARD LVCMOS12 } [get_ports { fmc_la_n[25] }]; #IO_L2N_T0_16 Sch=fmc_la_n[25]
-#set_property -dict { PACKAGE_PIN F16 IOSTANDARD LVCMOS12 } [get_ports { fmc_la_p[25] }]; #IO_L2P_T0_16 Sch=fmc_la_p[25]
-#set_property -dict { PACKAGE_PIN E18 IOSTANDARD LVCMOS12 } [get_ports { fmc_la_n[26] }]; #IO_L15N_T2_DQS_16 Sch=fmc_la_n[26]
-#set_property -dict { PACKAGE_PIN F18 IOSTANDARD LVCMOS12 } [get_ports { fmc_la_p[26] }]; #IO_L15P_T2_DQS_16 Sch=fmc_la_p[26]
-#set_property -dict { PACKAGE_PIN A20 IOSTANDARD LVCMOS12 } [get_ports { fmc_la_n[27] }]; #IO_L16N_T2_16 Sch=fmc_la_n[27]
-#set_property -dict { PACKAGE_PIN B20 IOSTANDARD LVCMOS12 } [get_ports { fmc_la_p[27] }]; #IO_L16P_T2_16 Sch=fmc_la_p[27]
-#set_property -dict { PACKAGE_PIN B13 IOSTANDARD LVCMOS12 } [get_ports { fmc_la_n[28] }]; #IO_L8N_T1_16 Sch=fmc_la_n[28]
-#set_property -dict { PACKAGE_PIN C13 IOSTANDARD LVCMOS12 } [get_ports { fmc_la_p[28] }]; #IO_L8P_T1_16 Sch=fmc_la_p[28]
-#set_property -dict { PACKAGE_PIN C15 IOSTANDARD LVCMOS12 } [get_ports { fmc_la_n[29] }]; #IO_L3N_T0_DQS_16 Sch=fmc_la_n[29]
-#set_property -dict { PACKAGE_PIN C14 IOSTANDARD LVCMOS12 } [get_ports { fmc_la_p[29] }]; #IO_L3P_T0_DQS_16 Sch=fmc_la_p[29]
-#set_property -dict { PACKAGE_PIN A14 IOSTANDARD LVCMOS12 } [get_ports { fmc_la_n[30] }]; #IO_L10N_T1_16 Sch=fmc_la_n[30]
-#set_property -dict { PACKAGE_PIN A13 IOSTANDARD LVCMOS12 } [get_ports { fmc_la_p[30] }]; #IO_L10P_T1_16 Sch=fmc_la_p[30]
-#set_property -dict { PACKAGE_PIN E14 IOSTANDARD LVCMOS12 } [get_ports { fmc_la_n[31] }]; #IO_L4N_T0_16 Sch=fmc_la_n[31]
-#set_property -dict { PACKAGE_PIN E13 IOSTANDARD LVCMOS12 } [get_ports { fmc_la_p[31] }]; #IO_L4P_T0_16 Sch=fmc_la_p[31]
-#set_property -dict { PACKAGE_PIN A16 IOSTANDARD LVCMOS12 } [get_ports { fmc_la_n[32] }]; #IO_L9N_T1_DQS_16 Sch=fmc_la_n[32]
-#set_property -dict { PACKAGE_PIN A15 IOSTANDARD LVCMOS12 } [get_ports { fmc_la_p[32] }]; #IO_L9P_T1_DQS_16 Sch=fmc_la_p[32]
-#set_property -dict { PACKAGE_PIN F14 IOSTANDARD LVCMOS12 } [get_ports { fmc_la_n[33] }]; #IO_L1N_T0_16 Sch=fmc_la_n[33]
-#set_property -dict { PACKAGE_PIN F13 IOSTANDARD LVCMOS12 } [get_ports { fmc_la_p[33] }]; #IO_L1P_T0_16 Sch=fmc_la_p[33]
-
-
-## Configuration options, can be used for all designs
-set_property CONFIG_VOLTAGE 3.3 [current_design]
-set_property CFGBVS VCCO [current_design]
diff --git a/hw/top_earlgrey/data/top_earlgrey.hjson b/hw/top_earlgrey/data/top_earlgrey.hjson
index 18d0694..b1592dd 100644
--- a/hw/top_earlgrey/data/top_earlgrey.hjson
+++ b/hw/top_earlgrey/data/top_earlgrey.hjson
@@ -1418,54 +1418,5 @@
],
}
}
- { name: 'nexysvideo',
-
- pinout: {
- remove_ports: [],
- remove_pads: [
- 'CC1', 'CC2',
- 'SPI_DEV_D2', 'SPI_DEV_D3'
- 'SPI_HOST_CLK', 'SPI_HOST_CS_L',
- 'SPI_HOST_D0', 'SPI_HOST_D1', 'SPI_HOST_D2', 'SPI_HOST_D3',
- 'FLASH_TEST_VOLT', 'OTP_EXT_VOLT'
- 'FLASH_TEST_MODE0', 'FLASH_TEST_MODE1',
- 'IOB10', 'IOB11', 'IOB12',
- 'IOC0', 'IOC1', 'IOC12',
- 'IOR2', 'IOR3', 'IOR4', 'IOR5', 'IOR6', 'IOR7', 'IOR8', 'IOR9', 'IOR10', 'IOR11', 'IOR12', 'IOR13'
- ],
-
- add_pads: [
- // Additional infrastructure pads
- { name: 'IO_CLK', type: 'InputStd', bank: 'VCC', connection: 'manual', desc: 'Extra clock input for FPGA target'}
- { name: 'IO_JSRST_N', type: 'InputStd', bank: 'VCC', connection: 'manual', desc: 'Dedicated JTAG system reset input'}
- // Custom USB pads
- { name: 'IO_USB_DNPULLUP0', type: 'BidirStd', bank: 'VCC', connection: 'manual', desc: 'Manual USB signal for FPGA target'}
- { name: 'IO_USB_DPPULLUP0', type: 'BidirStd', bank: 'VCC', connection: 'manual', desc: 'Manual USB signal for FPGA target'}
- { name: 'IO_UPHY_DP_TX', type: 'BidirStd', bank: 'VCC', connection: 'manual', desc: 'Manual USB UPHY signal for FPGA target'}
- { name: 'IO_UPHY_DN_TX', type: 'BidirStd', bank: 'VCC', connection: 'manual', desc: 'Manual USB UPHY signal for FPGA target'}
- { name: 'IO_UPHY_DP_RX', type: 'BidirStd', bank: 'VCC', connection: 'manual', desc: 'Manual USB UPHY signal for FPGA target'}
- { name: 'IO_UPHY_DN_RX', type: 'BidirStd', bank: 'VCC', connection: 'manual', desc: 'Manual USB UPHY signal for FPGA target'}
- { name: 'IO_UPHY_D_RX', type: 'BidirStd', bank: 'VCC', connection: 'manual', desc: 'Manual USB UPHY signal for FPGA target'}
- { name: 'IO_UPHY_OE_N', type: 'BidirStd', bank: 'VCC', connection: 'manual', desc: 'Manual USB UPHY signal for FPGA target'}
- { name: 'IO_UPHY_DPPULLUP', type: 'BidirStd', bank: 'VCC', connection: 'manual', desc: 'Manual USB UPHY signal for FPGA target'}
- ],
- },
-
- pinmux: {
- special_signals: [
- // Straps
- { name: 'tap0', pad: 'IOC0' , desc: 'TAP strap signal, maps to a stubbed-off MIO.' },
- { name: 'tap1', pad: 'IOB7', desc: 'TAP strap signal, maps to MIO pad 16.' },
- { name: 'dft0', pad: 'IOC1' , desc: 'DFT strap signal, maps to a stubbed-off MIO.' },
- { name: 'dft1', pad: 'IOC12', desc: 'DFT strap signal, maps to a stubbed-off MIO.' },
- // JTAG
- { name: 'tck', pad: 'SPI_DEV_CLK' , desc: 'JTAG tck signal, overlaid on SPI_DEV.' },
- { name: 'tms', pad: 'SPI_DEV_CS_L', desc: 'JTAG tms signal, overlaid on SPI_DEV.' },
- { name: 'trst_n', pad: 'IOB9' , desc: 'JTAG trst_n signal, maps to MIO pad 18.' },
- { name: 'tdi', pad: 'SPI_DEV_D0' , desc: 'JTAG tdi signal, overlaid on SPI_DEV.' },
- { name: 'tdo', pad: 'SPI_DEV_D1' , desc: 'JTAG tdo signal, overlaid on SPI_DEV.' },
- ],
- }
- }
]
}
diff --git a/hw/top_earlgrey/ip/pinmux/doc/autogen/targets.md b/hw/top_earlgrey/ip/pinmux/doc/autogen/targets.md
index d7fbc78..d6a7ff0 100644
--- a/hw/top_earlgrey/ip/pinmux/doc/autogen/targets.md
+++ b/hw/top_earlgrey/ip/pinmux/doc/autogen/targets.md
@@ -5,8 +5,7 @@
-->
-| Target Name | #IO Banks | #Muxed Pads | #Direct Pads | #Manual Pads | #Total Pads | Pinout / Pinmux Tables |
-|:-------------:|:-----------:|:-------------:|:--------------:|:--------------:|:-------------:|:----------------------------------------------------------------------------------------:|
-| ASIC | 4 | 47 | 14 | 10 | 71 | [Pinout Table](../../../top_earlgrey/ip/pinmux/doc/autogen/pinout_asic/index.html) |
-| CW310 | 4 | 30 | 10 | 14 | 54 | [Pinout Table](../../../top_earlgrey/ip/pinmux/doc/autogen/pinout_cw310/index.html) |
-| NEXYSVIDEO | 4 | 31 | 4 | 14 | 49 | [Pinout Table](../../../top_earlgrey/ip/pinmux/doc/autogen/pinout_nexysvideo/index.html) |
\ No newline at end of file
+| Target Name | #IO Banks | #Muxed Pads | #Direct Pads | #Manual Pads | #Total Pads | Pinout / Pinmux Tables |
+|:-------------:|:-----------:|:-------------:|:--------------:|:--------------:|:-------------:|:-----------------------------------------------------------------------------------:|
+| ASIC | 4 | 47 | 14 | 10 | 71 | [Pinout Table](../../../top_earlgrey/ip/pinmux/doc/autogen/pinout_asic/index.html) |
+| CW310 | 4 | 30 | 10 | 14 | 54 | [Pinout Table](../../../top_earlgrey/ip/pinmux/doc/autogen/pinout_cw310/index.html) |
diff --git a/hw/top_earlgrey/rtl/autogen/chip_earlgrey_nexysvideo.sv b/hw/top_earlgrey/rtl/autogen/chip_earlgrey_nexysvideo.sv
deleted file mode 100644
index 40f3357..0000000
--- a/hw/top_earlgrey/rtl/autogen/chip_earlgrey_nexysvideo.sv
+++ /dev/null
@@ -1,1080 +0,0 @@
-// Copyright lowRISC contributors.
-// Licensed under the Apache License, Version 2.0, see LICENSE for details.
-// SPDX-License-Identifier: Apache-2.0
-//
-// ------------------- W A R N I N G: A U T O - G E N E R A T E D C O D E !! -------------------//
-// PLEASE DO NOT HAND-EDIT THIS FILE. IT HAS BEEN AUTO-GENERATED WITH THE FOLLOWING COMMAND:
-//
-// util/topgen.py -t hw/top_earlgrey/data/top_earlgrey.hjson \
-// -o hw/top_earlgrey/ \
-// --rnd_cnst_seed 4881560218908238235
-
-module chip_earlgrey_nexysvideo #(
- // Path to a VMEM file containing the contents of the boot ROM, which will be
- // baked into the FPGA bitstream.
- parameter BootRomInitFile = "test_rom_fpga_nexysvideo.32.vmem",
- // Path to a VMEM file containing the contents of the emulated OTP, which will be
- // baked into the FPGA bitstream.
- parameter OtpCtrlMemInitFile = "otp_img_fpga_nexysvideo.vmem"
-) (
- // Dedicated Pads
- inout POR_N, // Manual Pad
- inout USB_P, // Manual Pad
- inout USB_N, // Manual Pad
- inout SPI_DEV_D0, // Dedicated Pad for spi_device_sd
- inout SPI_DEV_D1, // Dedicated Pad for spi_device_sd
- inout SPI_DEV_CLK, // Dedicated Pad for spi_device_sck
- inout SPI_DEV_CS_L, // Dedicated Pad for spi_device_csb
- inout IO_CLK, // Manual Pad
- inout IO_JSRST_N, // Manual Pad
- inout IO_USB_DNPULLUP0, // Manual Pad
- inout IO_USB_DPPULLUP0, // Manual Pad
- inout IO_UPHY_DP_TX, // Manual Pad
- inout IO_UPHY_DN_TX, // Manual Pad
- inout IO_UPHY_DP_RX, // Manual Pad
- inout IO_UPHY_DN_RX, // Manual Pad
- inout IO_UPHY_D_RX, // Manual Pad
- inout IO_UPHY_OE_N, // Manual Pad
- inout IO_UPHY_DPPULLUP, // Manual Pad
-
- // Muxed Pads
- inout IOA0, // MIO Pad 0
- inout IOA1, // MIO Pad 1
- inout IOA2, // MIO Pad 2
- inout IOA3, // MIO Pad 3
- inout IOA4, // MIO Pad 4
- inout IOA5, // MIO Pad 5
- inout IOA6, // MIO Pad 6
- inout IOA7, // MIO Pad 7
- inout IOA8, // MIO Pad 8
- inout IOB0, // MIO Pad 9
- inout IOB1, // MIO Pad 10
- inout IOB2, // MIO Pad 11
- inout IOB3, // MIO Pad 12
- inout IOB4, // MIO Pad 13
- inout IOB5, // MIO Pad 14
- inout IOB6, // MIO Pad 15
- inout IOB7, // MIO Pad 16
- inout IOB8, // MIO Pad 17
- inout IOB9, // MIO Pad 18
- inout IOC2, // MIO Pad 24
- inout IOC3, // MIO Pad 25
- inout IOC4, // MIO Pad 26
- inout IOC5, // MIO Pad 27
- inout IOC6, // MIO Pad 28
- inout IOC7, // MIO Pad 29
- inout IOC8, // MIO Pad 30
- inout IOC9, // MIO Pad 31
- inout IOC10, // MIO Pad 32
- inout IOC11, // MIO Pad 33
- inout IOR0, // MIO Pad 35
- inout IOR1 // MIO Pad 36
-);
-
- import top_earlgrey_pkg::*;
- import prim_pad_wrapper_pkg::*;
-
- ////////////////////////////
- // Special Signal Indices //
- ////////////////////////////
-
- localparam int Tap0PadIdx = 22;
- localparam int Tap1PadIdx = 16;
- localparam int Dft0PadIdx = 23;
- localparam int Dft1PadIdx = 34;
- localparam int TckPadIdx = 59;
- localparam int TmsPadIdx = 60;
- localparam int TrstNPadIdx = 18;
- localparam int TdiPadIdx = 53;
- localparam int TdoPadIdx = 54;
-
- // DFT and Debug signal positions in the pinout.
- localparam pinmux_pkg::target_cfg_t PinmuxTargetCfg = '{
- tck_idx: TckPadIdx,
- tms_idx: TmsPadIdx,
- trst_idx: TrstNPadIdx,
- tdi_idx: TdiPadIdx,
- tdo_idx: TdoPadIdx,
- tap_strap0_idx: Tap0PadIdx,
- tap_strap1_idx: Tap1PadIdx,
- dft_strap0_idx: Dft0PadIdx,
- dft_strap1_idx: Dft1PadIdx,
- // TODO: check whether there is a better way to pass these USB-specific params
- usb_dp_idx: DioUsbdevUsbDp,
- usb_dn_idx: DioUsbdevUsbDn,
- usb_sense_idx: MioInUsbdevSense,
- // Pad types for attribute WARL behavior
- dio_pad_type: {
- BidirStd, // DIO spi_host0_csb
- BidirStd, // DIO spi_host0_sck
- InputStd, // DIO spi_device_csb
- InputStd, // DIO spi_device_sck
- BidirOd, // DIO sysrst_ctrl_aon_flash_wp_l
- BidirOd, // DIO sysrst_ctrl_aon_ec_rst_l
- BidirStd, // DIO spi_device_sd
- BidirStd, // DIO spi_device_sd
- BidirStd, // DIO spi_device_sd
- BidirStd, // DIO spi_device_sd
- BidirStd, // DIO spi_host0_sd
- BidirStd, // DIO spi_host0_sd
- BidirStd, // DIO spi_host0_sd
- BidirStd, // DIO spi_host0_sd
- BidirStd, // DIO usbdev_usb_dn
- BidirStd // DIO usbdev_usb_dp
- },
- mio_pad_type: {
- BidirOd, // MIO Pad 46
- BidirOd, // MIO Pad 45
- BidirOd, // MIO Pad 44
- BidirOd, // MIO Pad 43
- BidirStd, // MIO Pad 42
- BidirStd, // MIO Pad 41
- BidirStd, // MIO Pad 40
- BidirStd, // MIO Pad 39
- BidirStd, // MIO Pad 38
- BidirStd, // MIO Pad 37
- BidirStd, // MIO Pad 36
- BidirStd, // MIO Pad 35
- BidirOd, // MIO Pad 34
- BidirOd, // MIO Pad 33
- BidirOd, // MIO Pad 32
- BidirStd, // MIO Pad 31
- BidirStd, // MIO Pad 30
- BidirStd, // MIO Pad 29
- BidirStd, // MIO Pad 28
- BidirStd, // MIO Pad 27
- BidirStd, // MIO Pad 26
- BidirStd, // MIO Pad 25
- BidirStd, // MIO Pad 24
- BidirStd, // MIO Pad 23
- BidirStd, // MIO Pad 22
- BidirOd, // MIO Pad 21
- BidirOd, // MIO Pad 20
- BidirOd, // MIO Pad 19
- BidirOd, // MIO Pad 18
- BidirStd, // MIO Pad 17
- BidirStd, // MIO Pad 16
- BidirStd, // MIO Pad 15
- BidirStd, // MIO Pad 14
- BidirStd, // MIO Pad 13
- BidirStd, // MIO Pad 12
- BidirStd, // MIO Pad 11
- BidirStd, // MIO Pad 10
- BidirStd, // MIO Pad 9
- BidirOd, // MIO Pad 8
- BidirOd, // MIO Pad 7
- BidirOd, // MIO Pad 6
- BidirStd, // MIO Pad 5
- BidirStd, // MIO Pad 4
- BidirStd, // MIO Pad 3
- BidirStd, // MIO Pad 2
- BidirStd, // MIO Pad 1
- BidirStd // MIO Pad 0
- }
- };
-
- ////////////////////////
- // Signal definitions //
- ////////////////////////
-
-
- pad_attr_t [pinmux_reg_pkg::NMioPads-1:0] mio_attr;
- pad_attr_t [pinmux_reg_pkg::NDioPads-1:0] dio_attr;
- logic [pinmux_reg_pkg::NMioPads-1:0] mio_out;
- logic [pinmux_reg_pkg::NMioPads-1:0] mio_oe;
- logic [pinmux_reg_pkg::NMioPads-1:0] mio_in;
- logic [pinmux_reg_pkg::NMioPads-1:0] mio_in_raw;
- logic [pinmux_reg_pkg::NDioPads-1:0] dio_out;
- logic [pinmux_reg_pkg::NDioPads-1:0] dio_oe;
- logic [pinmux_reg_pkg::NDioPads-1:0] dio_in;
-
- logic unused_mio_in_raw;
- assign unused_mio_in_raw = ^mio_in_raw;
-
- // Manual pads
- logic manual_in_por_n, manual_out_por_n, manual_oe_por_n;
- logic manual_in_usb_p, manual_out_usb_p, manual_oe_usb_p;
- logic manual_in_usb_n, manual_out_usb_n, manual_oe_usb_n;
- logic manual_in_io_clk, manual_out_io_clk, manual_oe_io_clk;
- logic manual_in_io_jsrst_n, manual_out_io_jsrst_n, manual_oe_io_jsrst_n;
- logic manual_in_io_usb_dnpullup0, manual_out_io_usb_dnpullup0, manual_oe_io_usb_dnpullup0;
- logic manual_in_io_usb_dppullup0, manual_out_io_usb_dppullup0, manual_oe_io_usb_dppullup0;
- logic manual_in_io_uphy_dp_tx, manual_out_io_uphy_dp_tx, manual_oe_io_uphy_dp_tx;
- logic manual_in_io_uphy_dn_tx, manual_out_io_uphy_dn_tx, manual_oe_io_uphy_dn_tx;
- logic manual_in_io_uphy_dp_rx, manual_out_io_uphy_dp_rx, manual_oe_io_uphy_dp_rx;
- logic manual_in_io_uphy_dn_rx, manual_out_io_uphy_dn_rx, manual_oe_io_uphy_dn_rx;
- logic manual_in_io_uphy_d_rx, manual_out_io_uphy_d_rx, manual_oe_io_uphy_d_rx;
- logic manual_in_io_uphy_oe_n, manual_out_io_uphy_oe_n, manual_oe_io_uphy_oe_n;
- logic manual_in_io_uphy_dppullup, manual_out_io_uphy_dppullup, manual_oe_io_uphy_dppullup;
-
- pad_attr_t manual_attr_por_n;
- pad_attr_t manual_attr_usb_p;
- pad_attr_t manual_attr_usb_n;
- pad_attr_t manual_attr_io_clk;
- pad_attr_t manual_attr_io_jsrst_n;
- pad_attr_t manual_attr_io_usb_dnpullup0;
- pad_attr_t manual_attr_io_usb_dppullup0;
- pad_attr_t manual_attr_io_uphy_dp_tx;
- pad_attr_t manual_attr_io_uphy_dn_tx;
- pad_attr_t manual_attr_io_uphy_dp_rx;
- pad_attr_t manual_attr_io_uphy_dn_rx;
- pad_attr_t manual_attr_io_uphy_d_rx;
- pad_attr_t manual_attr_io_uphy_oe_n;
- pad_attr_t manual_attr_io_uphy_dppullup;
-
- /////////////////////////
- // Stubbed pad tie-off //
- /////////////////////////
-
- // Only signals going to non-custom pads need to be tied off.
- logic [69:0] unused_sig;
- assign dio_in[DioSpiHost0Sd0] = 1'b0;
- assign unused_sig[9] = dio_out[DioSpiHost0Sd0] ^ dio_oe[DioSpiHost0Sd0];
- assign dio_in[DioSpiHost0Sd1] = 1'b0;
- assign unused_sig[10] = dio_out[DioSpiHost0Sd1] ^ dio_oe[DioSpiHost0Sd1];
- assign dio_in[DioSpiHost0Sd2] = 1'b0;
- assign unused_sig[11] = dio_out[DioSpiHost0Sd2] ^ dio_oe[DioSpiHost0Sd2];
- assign dio_in[DioSpiHost0Sd3] = 1'b0;
- assign unused_sig[12] = dio_out[DioSpiHost0Sd3] ^ dio_oe[DioSpiHost0Sd3];
- assign dio_in[DioSpiHost0Sck] = 1'b0;
- assign unused_sig[13] = dio_out[DioSpiHost0Sck] ^ dio_oe[DioSpiHost0Sck];
- assign dio_in[DioSpiHost0Csb] = 1'b0;
- assign unused_sig[14] = dio_out[DioSpiHost0Csb] ^ dio_oe[DioSpiHost0Csb];
- assign dio_in[DioSpiDeviceSd2] = 1'b0;
- assign unused_sig[17] = dio_out[DioSpiDeviceSd2] ^ dio_oe[DioSpiDeviceSd2];
- assign dio_in[DioSpiDeviceSd3] = 1'b0;
- assign unused_sig[18] = dio_out[DioSpiDeviceSd3] ^ dio_oe[DioSpiDeviceSd3];
- assign mio_in[19] = 1'b0;
- assign mio_in_raw[19] = 1'b0;
- assign unused_sig[40] = mio_out[19] ^ mio_oe[19];
- assign mio_in[20] = 1'b0;
- assign mio_in_raw[20] = 1'b0;
- assign unused_sig[41] = mio_out[20] ^ mio_oe[20];
- assign mio_in[21] = 1'b0;
- assign mio_in_raw[21] = 1'b0;
- assign unused_sig[42] = mio_out[21] ^ mio_oe[21];
- assign mio_in[22] = 1'b0;
- assign mio_in_raw[22] = 1'b0;
- assign unused_sig[43] = mio_out[22] ^ mio_oe[22];
- assign mio_in[23] = 1'b0;
- assign mio_in_raw[23] = 1'b0;
- assign unused_sig[44] = mio_out[23] ^ mio_oe[23];
- assign mio_in[34] = 1'b0;
- assign mio_in_raw[34] = 1'b0;
- assign unused_sig[55] = mio_out[34] ^ mio_oe[34];
- assign mio_in[37] = 1'b0;
- assign mio_in_raw[37] = 1'b0;
- assign unused_sig[58] = mio_out[37] ^ mio_oe[37];
- assign mio_in[38] = 1'b0;
- assign mio_in_raw[38] = 1'b0;
- assign unused_sig[59] = mio_out[38] ^ mio_oe[38];
- assign mio_in[39] = 1'b0;
- assign mio_in_raw[39] = 1'b0;
- assign unused_sig[60] = mio_out[39] ^ mio_oe[39];
- assign mio_in[40] = 1'b0;
- assign mio_in_raw[40] = 1'b0;
- assign unused_sig[61] = mio_out[40] ^ mio_oe[40];
- assign mio_in[41] = 1'b0;
- assign mio_in_raw[41] = 1'b0;
- assign unused_sig[62] = mio_out[41] ^ mio_oe[41];
- assign mio_in[42] = 1'b0;
- assign mio_in_raw[42] = 1'b0;
- assign unused_sig[63] = mio_out[42] ^ mio_oe[42];
- assign dio_in[DioSysrstCtrlAonEcRstL] = 1'b0;
- assign unused_sig[64] = dio_out[DioSysrstCtrlAonEcRstL] ^ dio_oe[DioSysrstCtrlAonEcRstL];
- assign dio_in[DioSysrstCtrlAonFlashWpL] = 1'b0;
- assign unused_sig[65] = dio_out[DioSysrstCtrlAonFlashWpL] ^ dio_oe[DioSysrstCtrlAonFlashWpL];
- assign mio_in[43] = 1'b0;
- assign mio_in_raw[43] = 1'b0;
- assign unused_sig[66] = mio_out[43] ^ mio_oe[43];
- assign mio_in[44] = 1'b0;
- assign mio_in_raw[44] = 1'b0;
- assign unused_sig[67] = mio_out[44] ^ mio_oe[44];
- assign mio_in[45] = 1'b0;
- assign mio_in_raw[45] = 1'b0;
- assign unused_sig[68] = mio_out[45] ^ mio_oe[45];
- assign mio_in[46] = 1'b0;
- assign mio_in_raw[46] = 1'b0;
- assign unused_sig[69] = mio_out[46] ^ mio_oe[46];
-
- //////////////////////
- // Padring Instance //
- //////////////////////
-
- ast_pkg::ast_clks_t ast_base_clks;
-
-
- padring #(
- // Padring specific counts may differ from pinmux config due
- // to custom, stubbed or added pads.
- .NDioPads(18),
- .NMioPads(31),
- .DioPadType ({
- BidirStd, // IO_UPHY_DPPULLUP
- BidirStd, // IO_UPHY_OE_N
- BidirStd, // IO_UPHY_D_RX
- BidirStd, // IO_UPHY_DN_RX
- BidirStd, // IO_UPHY_DP_RX
- BidirStd, // IO_UPHY_DN_TX
- BidirStd, // IO_UPHY_DP_TX
- BidirStd, // IO_USB_DPPULLUP0
- BidirStd, // IO_USB_DNPULLUP0
- InputStd, // IO_JSRST_N
- InputStd, // IO_CLK
- InputStd, // SPI_DEV_CS_L
- InputStd, // SPI_DEV_CLK
- BidirStd, // SPI_DEV_D1
- BidirStd, // SPI_DEV_D0
- DualBidirTol, // USB_N
- DualBidirTol, // USB_P
- InputStd // POR_N
- }),
- .MioPadType ({
- BidirStd, // IOR1
- BidirStd, // IOR0
- BidirOd, // IOC11
- BidirOd, // IOC10
- BidirStd, // IOC9
- BidirStd, // IOC8
- BidirStd, // IOC7
- BidirStd, // IOC6
- BidirStd, // IOC5
- BidirStd, // IOC4
- BidirStd, // IOC3
- BidirStd, // IOC2
- BidirOd, // IOB9
- BidirStd, // IOB8
- BidirStd, // IOB7
- BidirStd, // IOB6
- BidirStd, // IOB5
- BidirStd, // IOB4
- BidirStd, // IOB3
- BidirStd, // IOB2
- BidirStd, // IOB1
- BidirStd, // IOB0
- BidirOd, // IOA8
- BidirOd, // IOA7
- BidirOd, // IOA6
- BidirStd, // IOA5
- BidirStd, // IOA4
- BidirStd, // IOA3
- BidirStd, // IOA2
- BidirStd, // IOA1
- BidirStd // IOA0
- })
- ) u_padring (
- // This is only used for scan and DFT purposes
- .clk_scan_i ( 1'b0 ),
- .scanmode_i ( prim_mubi_pkg::MuBi4False ),
- .dio_in_raw_o ( ),
- // Chip IOs
- .dio_pad_io ({
- IO_UPHY_DPPULLUP,
- IO_UPHY_OE_N,
- IO_UPHY_D_RX,
- IO_UPHY_DN_RX,
- IO_UPHY_DP_RX,
- IO_UPHY_DN_TX,
- IO_UPHY_DP_TX,
- IO_USB_DPPULLUP0,
- IO_USB_DNPULLUP0,
- IO_JSRST_N,
- IO_CLK,
- SPI_DEV_CS_L,
- SPI_DEV_CLK,
- SPI_DEV_D1,
- SPI_DEV_D0,
- USB_N,
- USB_P,
- POR_N
- }),
-
- .mio_pad_io ({
- IOR1,
- IOR0,
- IOC11,
- IOC10,
- IOC9,
- IOC8,
- IOC7,
- IOC6,
- IOC5,
- IOC4,
- IOC3,
- IOC2,
- IOB9,
- IOB8,
- IOB7,
- IOB6,
- IOB5,
- IOB4,
- IOB3,
- IOB2,
- IOB1,
- IOB0,
- IOA8,
- IOA7,
- IOA6,
- IOA5,
- IOA4,
- IOA3,
- IOA2,
- IOA1,
- IOA0
- }),
-
- // Core-facing
- .dio_in_o ({
- manual_in_io_uphy_dppullup,
- manual_in_io_uphy_oe_n,
- manual_in_io_uphy_d_rx,
- manual_in_io_uphy_dn_rx,
- manual_in_io_uphy_dp_rx,
- manual_in_io_uphy_dn_tx,
- manual_in_io_uphy_dp_tx,
- manual_in_io_usb_dppullup0,
- manual_in_io_usb_dnpullup0,
- manual_in_io_jsrst_n,
- manual_in_io_clk,
- dio_in[DioSpiDeviceCsb],
- dio_in[DioSpiDeviceSck],
- dio_in[DioSpiDeviceSd1],
- dio_in[DioSpiDeviceSd0],
- manual_in_usb_n,
- manual_in_usb_p,
- manual_in_por_n
- }),
- .dio_out_i ({
- manual_out_io_uphy_dppullup,
- manual_out_io_uphy_oe_n,
- manual_out_io_uphy_d_rx,
- manual_out_io_uphy_dn_rx,
- manual_out_io_uphy_dp_rx,
- manual_out_io_uphy_dn_tx,
- manual_out_io_uphy_dp_tx,
- manual_out_io_usb_dppullup0,
- manual_out_io_usb_dnpullup0,
- manual_out_io_jsrst_n,
- manual_out_io_clk,
- dio_out[DioSpiDeviceCsb],
- dio_out[DioSpiDeviceSck],
- dio_out[DioSpiDeviceSd1],
- dio_out[DioSpiDeviceSd0],
- manual_out_usb_n,
- manual_out_usb_p,
- manual_out_por_n
- }),
- .dio_oe_i ({
- manual_oe_io_uphy_dppullup,
- manual_oe_io_uphy_oe_n,
- manual_oe_io_uphy_d_rx,
- manual_oe_io_uphy_dn_rx,
- manual_oe_io_uphy_dp_rx,
- manual_oe_io_uphy_dn_tx,
- manual_oe_io_uphy_dp_tx,
- manual_oe_io_usb_dppullup0,
- manual_oe_io_usb_dnpullup0,
- manual_oe_io_jsrst_n,
- manual_oe_io_clk,
- dio_oe[DioSpiDeviceCsb],
- dio_oe[DioSpiDeviceSck],
- dio_oe[DioSpiDeviceSd1],
- dio_oe[DioSpiDeviceSd0],
- manual_oe_usb_n,
- manual_oe_usb_p,
- manual_oe_por_n
- }),
- .dio_attr_i ({
- manual_attr_io_uphy_dppullup,
- manual_attr_io_uphy_oe_n,
- manual_attr_io_uphy_d_rx,
- manual_attr_io_uphy_dn_rx,
- manual_attr_io_uphy_dp_rx,
- manual_attr_io_uphy_dn_tx,
- manual_attr_io_uphy_dp_tx,
- manual_attr_io_usb_dppullup0,
- manual_attr_io_usb_dnpullup0,
- manual_attr_io_jsrst_n,
- manual_attr_io_clk,
- dio_attr[DioSpiDeviceCsb],
- dio_attr[DioSpiDeviceSck],
- dio_attr[DioSpiDeviceSd1],
- dio_attr[DioSpiDeviceSd0],
- manual_attr_usb_n,
- manual_attr_usb_p,
- manual_attr_por_n
- }),
-
- .mio_in_o ({
- mio_in[36:35],
- mio_in[33:24],
- mio_in[18:0]
- }),
- .mio_out_i ({
- mio_out[36:35],
- mio_out[33:24],
- mio_out[18:0]
- }),
- .mio_oe_i ({
- mio_oe[36:35],
- mio_oe[33:24],
- mio_oe[18:0]
- }),
- .mio_attr_i ({
- mio_attr[36:35],
- mio_attr[33:24],
- mio_attr[18:0]
- }),
- .mio_in_raw_o ({
- mio_in_raw[36:35],
- mio_in_raw[33:24],
- mio_in_raw[18:0]
- })
- );
-
-
-
-
- /////////////////////
- // USB Overlay Mux //
- /////////////////////
-
- // TODO: generalize this USB mux code and align with other tops.
-
- // Software can enable the pinflip feature inside usbdev.
- // The example hello_usbdev does this based on GPIO0 (a switch on the board)
- //
- // Here, we use the state of the DN pullup to effectively undo the
- // swapping such that the PCB always sees the unflipped D+/D-. We
- // could do the same inside the .xdc file but then two FPGA
- // bitstreams would be needed for testing.
- //
- // dio_in/out/oe map is: PADS <- _padring <- JTAG mux -> _umux -> USB mux -> _core
-
- // Split out for differential PHY testing
-
- // Outputs always drive and just copy the value
- // Let them go to the normal place too because it won't do any harm
- // and it simplifies the changes needed
- logic usb_dp_pullup_en;
- logic usb_dn_pullup_en;
- logic usb_rx_d;
- logic usb_tx_d;
- logic usb_tx_se0;
- logic usb_tx_use_d_se0;
- logic usb_suspend;
- logic usb_rx_enable;
-
- // The value for IO_USB_DNPULLUP0 is used to decide whether we need to undo the swapping.
- logic undo_swap;
- assign undo_swap = usb_dn_pullup_en;
-
- // GPIO[2] = Switch 2 on board is used to select using the UPHY
- // Keep GPIO[1] for selecting differential in sw
- logic use_uphy;
- assign use_uphy = mio_in[MioPadIoa2];
-
- // DioUsbdevUsbDn
- assign manual_attr_usb_n = '0;
- assign manual_attr_io_uphy_dn_tx = '0;
-
- assign manual_out_io_uphy_dn_tx = manual_out_usb_n;
- assign manual_out_usb_n = undo_swap ? dio_out[DioUsbdevUsbDp] :
- dio_out[DioUsbdevUsbDn];
-
- assign manual_oe_io_uphy_dn_tx = manual_oe_usb_n;
- assign manual_oe_usb_n = undo_swap ? dio_oe[DioUsbdevUsbDp] :
- dio_oe[DioUsbdevUsbDn];
-
- assign dio_in[DioUsbdevUsbDn] = use_uphy ?
- (undo_swap ? manual_in_io_uphy_dp_rx :
- manual_in_io_uphy_dn_rx) :
- (undo_swap ? manual_in_usb_p :
- manual_in_usb_n);
- // DioUsbdevUsbDp
- assign manual_attr_usb_p = '0;
- assign manual_attr_io_uphy_dp_tx = '0;
-
- assign manual_out_io_uphy_dp_tx = manual_out_usb_p;
- assign manual_out_usb_p = undo_swap ? dio_out[DioUsbdevUsbDn] :
- dio_out[DioUsbdevUsbDp];
-
- assign manual_oe_io_uphy_dp_tx = manual_oe_usb_p;
- assign manual_oe_usb_p = undo_swap ? dio_oe[DioUsbdevUsbDn] :
- dio_oe[DioUsbdevUsbDp];
- assign dio_in[DioUsbdevUsbDp] = use_uphy ?
- (undo_swap ? manual_in_io_uphy_dn_rx :
- manual_in_io_uphy_dp_rx) :
- (undo_swap ? manual_in_usb_n :
- manual_in_usb_p);
- // UsbdevD
- // This is not connected at the moment
- logic unused_out_usb_d;
- assign unused_out_usb_d = usb_tx_d;
- assign usb_rx_d = use_uphy ?
- (undo_swap ? ~manual_in_io_uphy_d_rx :
- manual_in_io_uphy_d_rx) :
- // This is not connected at the moment
- (undo_swap ? 1'b1 : 1'b0);
- assign manual_out_io_uphy_d_rx = 1'b0;
- assign manual_oe_io_uphy_d_rx = 1'b0;
-
- // UsbdevDnPullup
- assign manual_attr_io_usb_dnpullup0 = '0;
- assign manual_out_io_usb_dnpullup0 = usb_dn_pullup_en;
- assign manual_oe_io_usb_dnpullup0 = undo_swap ? usb_dp_pullup_en : usb_dn_pullup_en;
-
- // DioUsbdevDpPullup
- assign manual_attr_io_usb_dppullup0 = '0;
- assign manual_out_io_usb_dppullup0 = usb_dp_pullup_en;
- assign manual_oe_io_usb_dppullup0 = undo_swap ? usb_dn_pullup_en : usb_dp_pullup_en;
-
- // Additional outputs for uphy
- assign manual_oe_io_uphy_dppullup = 1'b1;
- assign manual_out_io_uphy_dppullup = manual_out_io_usb_dppullup0 &
- manual_oe_io_usb_dppullup0;
-
- logic unused_in_io_uphy_dppullup;
- assign unused_in_io_uphy_dppullup = manual_in_io_uphy_dppullup;
-
- assign manual_oe_io_uphy_oe_n = 1'b1;
- assign manual_out_io_uphy_oe_n = ~manual_oe_usb_p;
-
- logic unused_in_io_uphy_oe_n;
- assign unused_in_io_uphy_oe_n = manual_in_io_uphy_oe_n;
-
-
-
- //////////////////////////////////
- // AST - Common for all targets //
- //////////////////////////////////
-
- // pwrmgr interface
- pwrmgr_pkg::pwr_ast_req_t base_ast_pwr;
- pwrmgr_pkg::pwr_ast_rsp_t ast_base_pwr;
-
- // assorted ast status
- ast_pkg::ast_pwst_t ast_pwst;
- ast_pkg::ast_pwst_t ast_pwst_h;
-
- // TLUL interface
- tlul_pkg::tl_h2d_t base_ast_bus;
- tlul_pkg::tl_d2h_t ast_base_bus;
-
- // synchronization clocks / rests
- clkmgr_pkg::clkmgr_out_t clkmgr_aon_clocks;
- rstmgr_pkg::rstmgr_out_t rstmgr_aon_resets;
-
- // external clock
- logic ext_clk;
-
- // monitored clock
- logic sck_monitor;
-
- // observe interface
- logic [7:0] fla_obs;
- logic [7:0] otp_obs;
- ast_pkg::ast_obs_ctrl_t obs_ctrl;
-
- // otp power sequence
- otp_ctrl_pkg::otp_ast_req_t otp_ctrl_otp_ast_pwr_seq;
- otp_ctrl_pkg::otp_ast_rsp_t otp_ctrl_otp_ast_pwr_seq_h;
-
- logic usb_ref_pulse;
- logic usb_ref_val;
-
- // adc
- ast_pkg::adc_ast_req_t adc_req;
- ast_pkg::adc_ast_rsp_t adc_rsp;
-
- // entropy source interface
- // The entropy source pacakge definition should eventually be moved to es
- entropy_src_pkg::entropy_src_rng_req_t es_rng_req;
- entropy_src_pkg::entropy_src_rng_rsp_t es_rng_rsp;
- logic es_rng_fips;
-
- // entropy distribution network
- edn_pkg::edn_req_t ast_edn_edn_req;
- edn_pkg::edn_rsp_t ast_edn_edn_rsp;
-
- // alerts interface
- ast_pkg::ast_alert_rsp_t ast_alert_rsp;
- ast_pkg::ast_alert_req_t ast_alert_req;
-
- // Flash connections
- prim_mubi_pkg::mubi4_t flash_bist_enable;
- logic flash_power_down_h;
- logic flash_power_ready_h;
-
- // clock bypass req/ack
- prim_mubi_pkg::mubi4_t io_clk_byp_req;
- prim_mubi_pkg::mubi4_t io_clk_byp_ack;
- prim_mubi_pkg::mubi4_t all_clk_byp_req;
- prim_mubi_pkg::mubi4_t all_clk_byp_ack;
- prim_mubi_pkg::mubi4_t hi_speed_sel;
- prim_mubi_pkg::mubi4_t div_step_down_req;
-
- // DFT connections
- logic scan_en;
- lc_ctrl_pkg::lc_tx_t dft_en;
- pinmux_pkg::dft_strap_test_req_t dft_strap_test;
-
- // Debug connections
- logic [ast_pkg::Ast2PadOutWidth-1:0] ast2pinmux;
- logic [ast_pkg::Pad2AstInWidth-1:0] pad2ast;
-
- // Jitter enable
- prim_mubi_pkg::mubi4_t jen;
-
- // reset domain connections
- import rstmgr_pkg::PowerDomains;
- import rstmgr_pkg::DomainAonSel;
- import rstmgr_pkg::Domain0Sel;
-
- // Memory configuration connections
- ast_pkg::spm_rm_t ast_ram_1p_cfg;
- ast_pkg::spm_rm_t ast_rf_cfg;
- ast_pkg::spm_rm_t ast_rom_cfg;
- ast_pkg::dpm_rm_t ast_ram_2p_fcfg;
- ast_pkg::dpm_rm_t ast_ram_2p_lcfg;
-
- prim_ram_1p_pkg::ram_1p_cfg_t ram_1p_cfg;
- prim_ram_2p_pkg::ram_2p_cfg_t ram_2p_cfg;
- prim_rom_pkg::rom_cfg_t rom_cfg;
-
- // conversion from ast structure to memory centric structures
- assign ram_1p_cfg = '{
- ram_cfg: '{
- cfg_en: ast_ram_1p_cfg.marg_en,
- cfg: ast_ram_1p_cfg.marg
- },
- rf_cfg: '{
- cfg_en: ast_rf_cfg.marg_en,
- cfg: ast_rf_cfg.marg
- }
- };
-
- assign ram_2p_cfg = '{
- a_ram_fcfg: '{
- cfg_en: ast_ram_2p_fcfg.marg_en_a,
- cfg: ast_ram_2p_fcfg.marg_a
- },
- a_ram_lcfg: '{
- cfg_en: ast_ram_2p_lcfg.marg_en_a,
- cfg: ast_ram_2p_lcfg.marg_a
- },
- b_ram_fcfg: '{
- cfg_en: ast_ram_2p_fcfg.marg_en_b,
- cfg: ast_ram_2p_fcfg.marg_b
- },
- b_ram_lcfg: '{
- cfg_en: ast_ram_2p_lcfg.marg_en_b,
- cfg: ast_ram_2p_lcfg.marg_b
- }
- };
-
- assign rom_cfg = '{
- cfg_en: ast_rom_cfg.marg_en,
- cfg: ast_rom_cfg.marg
- };
-
-
- //////////////////////////////////
- // AST - Custom for targets //
- //////////////////////////////////
-
-
- // TODO: Hook this up when FPGA pads are updated
- assign ext_clk = '0;
- assign pad2ast = '0;
-
- assign ast_base_pwr.main_pok = base_ast_pwr.main_pd_n;
-
- logic clk_main, clk_usb_48mhz, clk_aon, rst_n;
- clkgen_xil7series # (
- .AddClkBuf(0)
- ) clkgen (
- .clk_i(manual_in_io_clk),
- .rst_ni(manual_in_por_n),
- .jtag_srst_ni(manual_in_io_jsrst_n),
- .clk_main_o(clk_main),
- .clk_48MHz_o(clk_usb_48mhz),
- .clk_aon_o(clk_aon),
- .rst_no(rst_n)
- );
-
- logic [31:0] fpga_info;
- usr_access_xil7series u_info (
- .info_o(fpga_info)
- );
-
- ast_pkg::clks_osc_byp_t clks_osc_byp;
- assign clks_osc_byp = '{
- usb: clk_usb_48mhz,
- sys: clk_main,
- io: clk_main,
- aon: clk_aon
- };
-
-
- ast #(
- .EntropyStreams(ast_pkg::EntropyStreams),
- .AdcChannels(ast_pkg::AdcChannels),
- .AdcDataWidth(ast_pkg::AdcDataWidth),
- .UsbCalibWidth(ast_pkg::UsbCalibWidth),
- .Ast2PadOutWidth(ast_pkg::Ast2PadOutWidth),
- .Pad2AstInWidth(ast_pkg::Pad2AstInWidth)
- ) u_ast (
- // external POR
- .por_ni ( rst_n ),
-
- // USB IO Pull-up Calibration Setting
- .usb_io_pu_cal_o ( ),
-
- // clocks' oschillator bypass for FPGA
- .clk_osc_byp_i ( clks_osc_byp ),
-
- // adc
- .adc_a0_ai ( '0 ),
- .adc_a1_ai ( '0 ),
-
- // Direct short to PAD
- .ast2pad_t0_ao ( ),
- .ast2pad_t1_ao ( ),
-
- // clocks and resets supplied for detection
- .sns_clks_i ( clkmgr_aon_clocks ),
- .sns_rsts_i ( rstmgr_aon_resets ),
- .sns_spi_ext_clk_i ( sck_monitor ),
- // tlul
- .tl_i ( base_ast_bus ),
- .tl_o ( ast_base_bus ),
- // init done indication
- .ast_init_done_o ( ast_init_done ),
- // buffered clocks & resets
- .clk_ast_tlul_i (clkmgr_aon_clocks.clk_io_div4_secure),
- .clk_ast_adc_i (clkmgr_aon_clocks.clk_aon_secure),
- .clk_ast_alert_i (clkmgr_aon_clocks.clk_io_div4_secure),
- .clk_ast_es_i (clkmgr_aon_clocks.clk_main_secure),
- .clk_ast_rng_i (clkmgr_aon_clocks.clk_main_secure),
- .clk_ast_usb_i (clkmgr_aon_clocks.clk_usb_secure),
- .rst_ast_tlul_ni (rstmgr_aon_resets.rst_lc_io_div4_n[rstmgr_pkg::Domain0Sel]),
- .rst_ast_adc_ni (rstmgr_aon_resets.rst_sys_aon_n[rstmgr_pkg::DomainAonSel]),
- .rst_ast_alert_ni (rstmgr_aon_resets.rst_lc_io_div4_n[rstmgr_pkg::Domain0Sel]),
- .rst_ast_es_ni (rstmgr_aon_resets.rst_sys_n[rstmgr_pkg::Domain0Sel]),
- .rst_ast_rng_ni (rstmgr_aon_resets.rst_sys_n[rstmgr_pkg::Domain0Sel]),
- .rst_ast_usb_ni (rstmgr_aon_resets.rst_usbif_n[rstmgr_pkg::Domain0Sel]),
- .clk_ast_ext_i ( ext_clk ),
-
- // pok test for FPGA
- .vcc_supp_i ( 1'b1 ),
- .vcaon_supp_i ( 1'b1 ),
- .vcmain_supp_i ( 1'b1 ),
- .vioa_supp_i ( 1'b1 ),
- .viob_supp_i ( 1'b1 ),
- // pok
- .ast_pwst_o ( ast_pwst ),
- .ast_pwst_h_o ( ast_pwst_h ),
- // main regulator
- .main_env_iso_en_i ( base_ast_pwr.pwr_clamp_env ),
- .main_pd_ni ( base_ast_pwr.main_pd_n ),
- // pdm control (flash)/otp
- .flash_power_down_h_o ( flash_power_down_h ),
- .flash_power_ready_h_o ( flash_power_ready_h ),
- .otp_power_seq_i ( otp_ctrl_otp_ast_pwr_seq ),
- .otp_power_seq_h_o ( otp_ctrl_otp_ast_pwr_seq_h ),
- // system source clock
- .clk_src_sys_en_i ( base_ast_pwr.core_clk_en ),
- // need to add function in clkmgr
- .clk_src_sys_jen_i ( jen ),
- .clk_src_sys_o ( ast_base_clks.clk_sys ),
- .clk_src_sys_val_o ( ast_base_pwr.core_clk_val ),
- // aon source clock
- .clk_src_aon_o ( ast_base_clks.clk_aon ),
- .clk_src_aon_val_o ( ast_base_pwr.slow_clk_val ),
- // io source clock
- .clk_src_io_en_i ( base_ast_pwr.io_clk_en ),
- .clk_src_io_o ( ast_base_clks.clk_io ),
- .clk_src_io_val_o ( ast_base_pwr.io_clk_val ),
- .clk_src_io_48m_o ( div_step_down_req ),
- // usb source clock
- .usb_ref_pulse_i ( usb_ref_pulse ),
- .usb_ref_val_i ( usb_ref_val ),
- .clk_src_usb_en_i ( base_ast_pwr.usb_clk_en ),
- .clk_src_usb_o ( ast_base_clks.clk_usb ),
- .clk_src_usb_val_o ( ast_base_pwr.usb_clk_val ),
- // adc
- .adc_pd_i ( adc_req.pd ),
- .adc_chnsel_i ( adc_req.channel_sel ),
- .adc_d_o ( adc_rsp.data ),
- .adc_d_val_o ( adc_rsp.data_valid ),
- // rng
- .rng_en_i ( es_rng_req.rng_enable ),
- .rng_fips_i ( es_rng_fips ),
- .rng_val_o ( es_rng_rsp.rng_valid ),
- .rng_b_o ( es_rng_rsp.rng_b ),
- // entropy
- .entropy_rsp_i ( ast_edn_edn_rsp ),
- .entropy_req_o ( ast_edn_edn_req ),
- // alerts
- .fla_alert_src_i ( flash_alert ),
- .otp_alert_src_i ( otp_alert ),
- .alert_rsp_i ( ast_alert_rsp ),
- .alert_req_o ( ast_alert_req ),
- // dft
- .dft_strap_test_i ( dft_strap_test ),
- .lc_dft_en_i ( dft_en ),
- .fla_obs_i ( fla_obs ),
- .otp_obs_i ( otp_obs ),
- .otm_obs_i ( '0 ),
- .usb_obs_i ( usb_diff_rx_obs ),
- .obs_ctrl_o ( obs_ctrl ),
- // pinmux related
- .padmux2ast_i ( pad2ast ),
- .ast2padmux_o ( ast2pinmux ),
- .ext_freq_is_96m_i ( hi_speed_sel ),
- .all_clk_byp_req_i ( all_clk_byp_req ),
- .all_clk_byp_ack_o ( all_clk_byp_ack ),
- .io_clk_byp_req_i ( io_clk_byp_req ),
- .io_clk_byp_ack_o ( io_clk_byp_ack ),
- .flash_bist_en_o ( flash_bist_enable ),
- // Memory configuration connections
- .dpram_rmf_o ( ast_ram_2p_fcfg ),
- .dpram_rml_o ( ast_ram_2p_lcfg ),
- .spram_rm_o ( ast_ram_1p_cfg ),
- .sprgf_rm_o ( ast_rf_cfg ),
- .sprom_rm_o ( ast_rom_cfg ),
- // scan
- .dft_scan_md_o ( scanmode ),
- .scan_shift_en_o ( scan_en ),
- .scan_reset_no ( scan_rst_n )
- );
-
-
-
-
- //////////////////
- // PLL for FPGA //
- //////////////////
-
- assign manual_out_io_clk = 1'b0;
- assign manual_oe_io_clk = 1'b0;
- assign manual_out_por_n = 1'b0;
- assign manual_oe_por_n = 1'b0;
- assign manual_out_io_jsrst_n = 1'b0;
- assign manual_oe_io_jsrst_n = 1'b0;
-
-
- //////////////////////
- // Top-level design //
- //////////////////////
-
- // the rst_ni pin only goes to AST
- // the rest of the logic generates reset based on the 'pok' signal.
- // for verilator purposes, make these two the same.
- prim_mubi_pkg::mubi4_t lc_clk_bypass; // TODO Tim
-
-// TODO: align this with ASIC version to minimize the duplication.
-// Also need to add AST simulation and FPGA emulation models for things like entropy source -
-// otherwise Verilator / FPGA will hang.
- top_earlgrey #(
- .SecAesMasking(1'b0),
- .SecAesSBoxImpl(aes_pkg::SBoxImplLut),
- .KmacEnMasking(1'b0),
- .KeymgrKmacEnMasking(0),
- .SecAesStartTriggerDelay(0),
- .SecAesAllowForcingMasks(1'b0),
- .SecAesSkipPRNGReseeding(1'b0),
- .EntropySrcStub(1'b1),
- .CsrngSBoxImpl(aes_pkg::SBoxImplLut),
- .OtbnRegFile(otbn_pkg::RegFileFPGA),
- .OtbnStub(1'b1),
- .OtpCtrlMemInitFile(OtpCtrlMemInitFile),
- .RomCtrlBootRomInitFile(BootRomInitFile),
- .RvCoreIbexRegFile(ibex_pkg::RegFileFPGA),
- .RvCoreIbexPipeLine(1),
- .RvCoreIbexSecureIbex(0),
- .SramCtrlRetAonInstrExec(0),
- .SramCtrlMainInstrExec(1),
- .PinmuxAonTargetCfg(PinmuxTargetCfg)
- ) top_earlgrey (
- .por_n_i ( {rst_n, rst_n} ),
- .clk_main_i ( ast_base_clks.clk_sys ),
- .clk_io_i ( ast_base_clks.clk_io ),
- .clk_usb_i ( ast_base_clks.clk_usb ),
- .clk_aon_i ( ast_base_clks.clk_aon ),
- .clks_ast_o ( clkmgr_aon_clocks ),
- .clk_main_jitter_en_o ( jen ),
- .rsts_ast_o ( rstmgr_aon_resets ),
- .sck_monitor_o ( sck_monitor ),
- .pwrmgr_ast_req_o ( base_ast_pwr ),
- .pwrmgr_ast_rsp_i ( ast_base_pwr ),
- .usb_dp_pullup_en_o ( usb_dp_pullup_en ),
- .usb_dn_pullup_en_o ( usb_dn_pullup_en ),
- .usbdev_usb_rx_d_i ( usb_rx_d ),
- .usbdev_usb_tx_d_o ( usb_tx_d ),
- .usbdev_usb_tx_se0_o ( usb_tx_se0 ),
- .usbdev_usb_tx_use_d_se0_o ( usb_tx_use_d_se0 ),
- .usbdev_usb_suspend_o ( usb_suspend ),
- .usbdev_usb_rx_enable_o ( usb_rx_enable ),
- .usbdev_usb_ref_val_o ( usb_ref_val ),
- .usbdev_usb_ref_pulse_o ( usb_ref_pulse ),
- .ast_edn_req_i ( ast_edn_edn_req ),
- .ast_edn_rsp_o ( ast_edn_edn_rsp ),
- .obs_ctrl_i ( obs_ctrl ),
- .flash_bist_enable_i ( flash_bist_enable ),
- .flash_power_down_h_i ( 1'b0 ),
- .flash_power_ready_h_i ( 1'b1 ),
- .flash_obs_o ( flash_obs ),
- .io_clk_byp_req_o ( io_clk_byp_req ),
- .io_clk_byp_ack_i ( io_clk_byp_ack ),
- .all_clk_byp_req_o ( all_clk_byp_req ),
- .all_clk_byp_ack_i ( all_clk_byp_ack ),
- .hi_speed_sel_o ( hi_speed_sel ),
- .div_step_down_req_i ( div_step_down_req ),
- .fpga_info_i ( fpga_info ),
- .ast_tl_req_o ( base_ast_bus ),
- .ast_tl_rsp_i ( ast_base_bus ),
- .adc_req_o ( adc_req ),
- .adc_rsp_i ( adc_rsp ),
- .otp_ctrl_otp_ast_pwr_seq_o ( otp_ctrl_otp_ast_pwr_seq ),
- .otp_ctrl_otp_ast_pwr_seq_h_i ( otp_ctrl_otp_ast_pwr_seq_h ),
- .otp_alert_o ( otp_alert ),
- .otp_obs_o ( otp_obs ),
- .sensor_ctrl_ast_alert_req_i ( ast_alert_req ),
- .sensor_ctrl_ast_alert_rsp_o ( ast_alert_rsp ),
- .sensor_ctrl_ast_status_i ( ast_pwst.io_pok ),
- .es_rng_req_o ( es_rng_req ),
- .es_rng_rsp_i ( es_rng_rsp ),
- .es_rng_fips_o ( es_rng_fips ),
- .ast2pinmux_i ( ast2pinmux ),
- .ast_init_done_i ( ast_init_done ),
-
- // Multiplexed I/O
- .mio_in_i ( mio_in ),
- .mio_out_o ( mio_out ),
- .mio_oe_o ( mio_oe ),
-
- // Dedicated I/O
- .dio_in_i ( dio_in ),
- .dio_out_o ( dio_out ),
- .dio_oe_o ( dio_oe ),
-
- // Pad attributes
- .mio_attr_o ( mio_attr ),
- .dio_attr_o ( dio_attr ),
-
- // Memory attributes
- .ram_1p_cfg_i ( '0 ),
- .ram_2p_cfg_i ( '0 ),
- .rom_cfg_i ( '0 ),
-
- // DFT signals
- .dft_hold_tap_sel_i ( '0 ),
- .scan_rst_ni ( 1'b1 ),
- .scan_en_i ( 1'b0 ),
- .scanmode_i ( prim_mubi_pkg::MuBi4False )
- );
-
-
-endmodule : chip_earlgrey_nexysvideo
diff --git a/util/topgen/gen_top_docs.py b/util/topgen/gen_top_docs.py
index d311365..3749ea9 100644
--- a/util/topgen/gen_top_docs.py
+++ b/util/topgen/gen_top_docs.py
@@ -198,7 +198,7 @@
headers="firstrow",
tablefmt="pipe",
colalign=colalign)
- summary_table = TABLE_HEADER + gencmd + "-->\n\n" + summary_table
+ summary_table = TABLE_HEADER + gencmd + "-->\n\n" + summary_table + "\n"
target_table_path = doc_path / "targets.md"
with open(target_table_path, 'w') as target_outfile:
