[util] Add optional fields to reggen, topgen
Add missing fields to the validation code.
Signed-off-by: Eunchan Kim <eunchan@opentitan.org>
diff --git a/util/reggen/validate.py b/util/reggen/validate.py
index ee01f93..7cf4a3f 100644
--- a/util/reggen/validate.py
+++ b/util/reggen/validate.py
@@ -306,6 +306,7 @@
'available_output_list': ['lnw', "list of available peripheral outputs"],
'available_inout_list': ['lnw', "list of available peripheral inouts"],
'interrupt_list': ['lnw', "list of peripheral interrupts"],
+ 'inter_signal_list': ['l', "list of inter-module signals"],
'no_auto_intr_regs': [
's', "Set to true to suppress automatic "
"generation of interrupt registers. "
diff --git a/util/topgen/validate.py b/util/topgen/validate.py
index b18d46c..f29fa76 100644
--- a/util/topgen/validate.py
+++ b/util/topgen/validate.py
@@ -50,9 +50,9 @@
}
top_optional = {
- 'interrupt_modules': ['l', 'list of the modules that connects to rv_plic'],
+ 'interrupt_module': ['l', 'list of the modules that connects to rv_plic'],
'interrupt': ['lnw', 'interrupts (generated)'],
- 'alert_modules':
+ 'alert_module':
['l', 'list of the modules that connects to alert_handler'],
'alert': ['lnw', 'alerts (generated)'],
'alert_async': ['l', 'async alerts (generated)'],
@@ -60,6 +60,8 @@
'padctrl':
['g', 'PADS instantiation, if doesn\'t exist, tool creates direct output'],
'inter_module': ['g', 'define the signal connections between the modules'],
+ 'num_cores': ['pn', "number of computing units"],
+ 'datawidth': ['pn', "default data width"],
}
top_added = {}
