[sysrst_ctrl/lint] Import common lint waivers for comportable IPs
Signed-off-by: Michael Schaffner <msf@google.com>
diff --git a/hw/ip/adc_ctrl/adc_ctrl.core b/hw/ip/adc_ctrl/adc_ctrl.core
index 8997118..be30f55 100644
--- a/hw/ip/adc_ctrl/adc_ctrl.core
+++ b/hw/ip/adc_ctrl/adc_ctrl.core
@@ -20,10 +20,22 @@
- rtl/adc_ctrl.sv
file_type: systemVerilogSource
+ files_verilator_waiver:
+ depend:
+ # common waivers
+ - lowrisc:lint:common
+ - lowrisc:lint:comportable
+ files:
+ # - lint/adc_ctrl.vlt
+ file_type: vlt
+
files_ascentlint_waiver:
depend:
# common waivers
- lowrisc:lint:common
+ - lowrisc:lint:comportable
+ files:
+ # - lint/adc_ctrl.waiver
file_type: waiver
files_veriblelint_waiver:
@@ -40,7 +52,9 @@
targets:
default: &default_target
filesets:
+ - tool_verilator ? (files_verilator_waiver)
- tool_ascentlint ? (files_ascentlint_waiver)
+ - tool_veriblelint ? (files_veriblelint_waiver)
- files_rtl
toplevel: adc_ctrl
diff --git a/hw/ip/adc_ctrl/rtl/adc_ctrl_core.sv b/hw/ip/adc_ctrl/rtl/adc_ctrl_core.sv
index 198b21e..dc1508e 100644
--- a/hw/ip/adc_ctrl/rtl/adc_ctrl_core.sv
+++ b/hw/ip/adc_ctrl/rtl/adc_ctrl_core.sv
@@ -80,7 +80,8 @@
logic [NumAdcFilter-1:0] chn0_match, chn1_match, adc_ctrl_match;
logic [NumAdcFilter-1:0] adc_ctrl_match_pulse;
- logic adc_ctrl_done, oneshot_done;//write enable for the ADC sample when the interrupt is triggered
+ //write enable for the ADC sample when the interrupt is triggered
+ logic adc_ctrl_done, oneshot_done;
logic cfg_adc_ctrl_done, cfg_oneshot_done;
//CFG clock domain synchronized write enable when interrupt is triggered
logic cfg_chn_val_intr_we;//Either oneshot_done or adc_ctrl_done
diff --git a/hw/ip/sysrst_ctrl/rtl/sysrst_ctrl_combo.sv b/hw/ip/sysrst_ctrl/rtl/sysrst_ctrl_combo.sv
index 0070f33..2eeb799 100644
--- a/hw/ip/sysrst_ctrl/rtl/sysrst_ctrl_combo.sv
+++ b/hw/ip/sysrst_ctrl/rtl/sysrst_ctrl_combo.sv
@@ -381,7 +381,10 @@
assign combo_intr_status_o.combo3_h2l.de = combo3_h2l_intr;
- assign sysrst_ctrl_combo_intr = combo0_h2l_intr | combo1_h2l_intr | combo2_h2l_intr | combo3_h2l_intr;
+ assign sysrst_ctrl_combo_intr = combo0_h2l_intr |
+ combo1_h2l_intr |
+ combo2_h2l_intr |
+ combo3_h2l_intr;
//To write into interrupt status register
assign combo_intr_status_o.combo0_h2l.d = 1'b1;
diff --git a/hw/ip/sysrst_ctrl/sysrst_ctrl.core b/hw/ip/sysrst_ctrl/sysrst_ctrl.core
index aa468a1..2032b82 100644
--- a/hw/ip/sysrst_ctrl/sysrst_ctrl.core
+++ b/hw/ip/sysrst_ctrl/sysrst_ctrl.core
@@ -27,17 +27,23 @@
- rtl/sysrst_ctrl.sv
file_type: systemVerilogSource
- files_ascentlint_waiver:
- depend:
- # common waivers
- - lowrisc:lint:common
- file_type: waiver
-
- files_veriblelint_waiver:
+ files_verilator_waiver:
depend:
# common waivers
- lowrisc:lint:common
- lowrisc:lint:comportable
+ files:
+ # - lint/sysrst_ctrl.vlt
+ file_type: vlt
+
+ files_ascentlint_waiver:
+ depend:
+ # common waivers
+ - lowrisc:lint:common
+ - lowrisc:lint:comportable
+ files:
+ # - lint/sysrst_ctrl.waiver
+ file_type: waiver
parameters:
SYNTHESIS:
@@ -47,7 +53,8 @@
targets:
default: &default_target
filesets:
- - tool_ascentlint ? (files_ascentlint_waiver)
+ - tool_verilator ? (files_verilator_waiver)
+ - tool_ascentlint ? (files_ascentlint_waiver)
- files_rtl
toplevel: sysrst_ctrl
