[dv/flash_ctrl] Add shadow_reg tests
This PR adds the auto generated shadow reg tests for flash_ctrl.
Signed-off-by: Cindy Chen <chencindy@opentitan.org>
diff --git a/hw/ip/flash_ctrl/data/flash_ctrl_testplan.hjson b/hw/ip/flash_ctrl/data/flash_ctrl_testplan.hjson
index 2571b4c..18f7506 100644
--- a/hw/ip/flash_ctrl/data/flash_ctrl_testplan.hjson
+++ b/hw/ip/flash_ctrl/data/flash_ctrl_testplan.hjson
@@ -8,6 +8,7 @@
"hw/dv/tools/dvsim/testplans/mem_testplan.hjson",
"hw/dv/tools/dvsim/testplans/alert_test_testplan.hjson",
"hw/dv/tools/dvsim/testplans/intr_test_testplan.hjson",
+ "hw/dv/tools/dvsim/testplans/shadow_reg_errors_testplan.hjson",
"hw/dv/tools/dvsim/testplans/tl_device_access_types_testplan.hjson",
"hw/dv/tools/dvsim/testplans/stress_all_with_reset_testplan.hjson"]
testpoints: [
diff --git a/hw/ip/flash_ctrl/dv/env/flash_ctrl_env_cfg.sv b/hw/ip/flash_ctrl/dv/env/flash_ctrl_env_cfg.sv
index 5a5861c..810be0a 100644
--- a/hw/ip/flash_ctrl/dv/env/flash_ctrl_env_cfg.sv
+++ b/hw/ip/flash_ctrl/dv/env/flash_ctrl_env_cfg.sv
@@ -26,8 +26,13 @@
virtual function void initialize(bit [TL_AW-1:0] csr_base_addr = '1);
list_of_alerts = flash_ctrl_env_pkg::LIST_OF_ALERTS;
+ has_shadowed_regs = 1;
tl_intg_alert_name = "fatal_intg_err";
super.initialize(csr_base_addr);
+
+ shadow_update_err_status_fields[ral.err_code.update_err] = 1;
+ shadow_storage_err_status_fields[ral.fault_status.storage_err] = 1;
+
// create tl agent config obj
m_eflash_tl_agent_cfg = tl_agent_cfg::type_id::create("m_eflash_tl_agent_cfg");
m_eflash_tl_agent_cfg.if_mode = dv_utils_pkg::Host;
diff --git a/hw/ip/flash_ctrl/dv/flash_ctrl_sim_cfg.hjson b/hw/ip/flash_ctrl/dv/flash_ctrl_sim_cfg.hjson
index 20b0fdd..59cd0bf 100644
--- a/hw/ip/flash_ctrl/dv/flash_ctrl_sim_cfg.hjson
+++ b/hw/ip/flash_ctrl/dv/flash_ctrl_sim_cfg.hjson
@@ -30,6 +30,7 @@
"{proj_root}/hw/dv/tools/dvsim/tests/mem_tests.hjson",
"{proj_root}/hw/dv/tools/dvsim/tests/alert_test.hjson",
"{proj_root}/hw/dv/tools/dvsim/tests/intr_test.hjson",
+ "{proj_root}/hw/dv/tools/dvsim/tests/shadow_reg_errors_tests.hjson",
"{proj_root}/hw/dv/tools/dvsim/tests/tl_access_tests.hjson",
"{proj_root}/hw/dv/tools/dvsim/tests/stress_tests.hjson"],
diff --git a/hw/ip/flash_ctrl/dv/tb/tb.sv b/hw/ip/flash_ctrl/dv/tb/tb.sv
index 2be5ef8..0b7bf10 100644
--- a/hw/ip/flash_ctrl/dv/tb/tb.sv
+++ b/hw/ip/flash_ctrl/dv/tb/tb.sv
@@ -16,7 +16,7 @@
`include "uvm_macros.svh"
`include "dv_macros.svh"
- wire clk, rst_n;
+ wire clk, rst_n, rst_shadowed_n;
wire devmode;
wire intr_prog_empty;
wire intr_prog_lvl;
@@ -28,6 +28,7 @@
// interfaces
clk_rst_if clk_rst_if(.clk(clk), .rst_n(rst_n));
+ rst_shadowed_if rst_shadowed_if(.rst_n(rst_n), .rst_shadowed_n(rst_shadowed_n));
pins_if #(NUM_MAX_INTERRUPTS) intr_if(interrupts);
pins_if #(1) devmode_if(devmode);
tl_if tl_if(.clk(clk), .rst_n(rst_n));
@@ -46,11 +47,11 @@
// dut
flash_ctrl dut (
- .clk_i (clk ),
- .rst_ni (rst_n ),
- .rst_shadowed_ni(rst_n),
- .clk_otp_i (clk ),
- .rst_otp_ni (rst_n ),
+ .clk_i (clk ),
+ .rst_ni (rst_n ),
+ .rst_shadowed_ni (rst_shadowed_n),
+ .clk_otp_i (clk ),
+ .rst_otp_ni (rst_n ),
// various tlul interfaces
.core_tl_i (tl_if.h2d),
@@ -206,6 +207,8 @@
// drive clk and rst_n from clk_if
clk_rst_if.set_active();
uvm_config_db#(virtual clk_rst_if)::set(null, "*.env", "clk_rst_vif", clk_rst_if);
+ uvm_config_db#(virtual rst_shadowed_if)::set(null, "*.env", "rst_shadowed_vif",
+ rst_shadowed_if);
uvm_config_db#(intr_vif)::set(null, "*.env", "intr_vif", intr_if);
uvm_config_db#(devmode_vif)::set(null, "*.env", "devmode_vif", devmode_if);
uvm_config_db#(virtual tl_if)::set(null, "*.env.m_tl_agent_flash_ctrl_core_reg_block*", "vif",
