feat(chip): Scaffolds SV test env for sleep_pin_retention
Signed-off-by: Eli Kim <eli@opentitan.org>
diff --git a/hw/top_earlgrey/dv/chip_sim_cfg.hjson b/hw/top_earlgrey/dv/chip_sim_cfg.hjson
index 6c4f397..9fac6f4 100644
--- a/hw/top_earlgrey/dv/chip_sim_cfg.hjson
+++ b/hw/top_earlgrey/dv/chip_sim_cfg.hjson
@@ -344,6 +344,12 @@
en_run_modes: ["sw_test_mode_test_rom"]
}
{
+ name: chip_sw_sleep_pin_retention
+ uvm_test_seq: chip_sw_sleep_pin_retention_vseq
+ sw_images: ["//sw/device/tests/sim_dv:sleep_pin_retention_test:1"]
+ en_run_modes: ["sw_test_mode_test_rom"]
+ }
+ {
name: chip_sw_sleep_pwm_pulses
uvm_test_seq: chip_sw_pwm_pulses_vseq
sw_images: ["//sw/device/tests:sleep_pwm_pulses_test:1"]
diff --git a/hw/top_earlgrey/dv/env/chip_env.core b/hw/top_earlgrey/dv/env/chip_env.core
index df879af..9fc3b5d 100644
--- a/hw/top_earlgrey/dv/env/chip_env.core
+++ b/hw/top_earlgrey/dv/env/chip_env.core
@@ -63,6 +63,7 @@
- seq_lib/chip_sw_deep_sleep_all_reset_vseq.sv: {is_include_file: true}
- seq_lib/chip_sw_sleep_pin_mio_dio_val_vseq.sv: {is_include_file: true}
- seq_lib/chip_sw_sleep_pin_wake_vseq.sv: {is_include_file: true}
+ - seq_lib/chip_sw_sleep_pin_retention_vseq.sv: {is_include_file: true}
- seq_lib/chip_sw_pwm_pulses_vseq.sv: {is_include_file: true}
- seq_lib/chip_sw_uart_tx_rx_vseq.sv: {is_include_file: true}
- seq_lib/chip_sw_uart_rand_baudrate_vseq.sv: {is_include_file: true}
diff --git a/hw/top_earlgrey/dv/env/seq_lib/chip_sw_sleep_pin_retention_vseq.sv b/hw/top_earlgrey/dv/env/seq_lib/chip_sw_sleep_pin_retention_vseq.sv
new file mode 100644
index 0000000..2a6e7be
--- /dev/null
+++ b/hw/top_earlgrey/dv/env/seq_lib/chip_sw_sleep_pin_retention_vseq.sv
@@ -0,0 +1,45 @@
+// Copyright lowRISC contributors.
+// Licensed under the Apache License, Version 2.0, see LICENSE for details.
+// SPDX-License-Identifier: Apache-2.0
+
+class chip_sw_sleep_pin_retention_vseq extends chip_sw_base_vseq;
+ `uvm_object_utils(chip_sw_sleep_pin_retention_vseq)
+
+ `uvm_object_new
+
+ import chip_common_pkg::*;
+
+ rand bit [7:0] rounds;
+
+ constraint rounds_c { rounds inside {[8'h 1 : 8'h 7]}; }
+
+ virtual task cpu_init();
+ bit [7:0] byte_arr [];
+ byte_arr = '{rounds};
+
+ super.cpu_init();
+
+ sw_symbol_backdoor_overwrite("kRounds", byte_arr);
+
+ endtask : cpu_init
+
+ virtual task body();
+ super.body();
+
+ `DV_WAIT(cfg.sw_test_status_vif.sw_test_status == SwTestStatusInTest)
+
+ for (int unsigned round = 0 ; round < rounds ; round++) begin
+ // TODO: Receive values from SW via sw_logger_vif
+
+ // TODO: Check PIN
+
+ // TODO: Wait sleep (normal vs deep)
+
+ // TODO: Check PIN value
+
+ // TODO: Wake up DUT
+ end
+
+ endtask : body
+
+endclass : chip_sw_sleep_pin_retention_vseq
diff --git a/hw/top_earlgrey/dv/env/seq_lib/chip_vseq_list.sv b/hw/top_earlgrey/dv/env/seq_lib/chip_vseq_list.sv
index 6efc6dc..c6f1a24 100644
--- a/hw/top_earlgrey/dv/env/seq_lib/chip_vseq_list.sv
+++ b/hw/top_earlgrey/dv/env/seq_lib/chip_vseq_list.sv
@@ -43,6 +43,7 @@
`include "chip_sw_sram_ctrl_scrambled_access_vseq.sv"
`include "chip_sw_sleep_pin_mio_dio_val_vseq.sv"
`include "chip_sw_sleep_pin_wake_vseq.sv"
+`include "chip_sw_sleep_pin_retention_vseq.sv"
`include "chip_sw_pwm_pulses_vseq.sv"
`include "chip_sw_keymgr_key_derivation_vseq.sv"
`include "chip_sw_ast_clk_outputs_vseq.sv"
