[lint/top] Various lint fixes in order to get the top level lint clean
diff --git a/hw/ip/flash_ctrl/rtl/flash_ctrl.sv b/hw/ip/flash_ctrl/rtl/flash_ctrl.sv
index a55eaaf..a9e6929 100644
--- a/hw/ip/flash_ctrl/rtl/flash_ctrl.sv
+++ b/hw/ip/flash_ctrl/rtl/flash_ctrl.sv
@@ -152,7 +152,8 @@
.Depth(FifoDepth)
) u_prog_fifo (
.clk_i,
- .rst_ni (rst_ni & ~reg2hw.control.fifo_rst.q),
+ .rst_ni (rst_ni),
+ .clr_i (reg2hw.control.fifo_rst.q),
.wvalid (prog_fifo_req & prog_fifo_wen),
.wready (prog_fifo_wready),
.wdata (prog_fifo_wdata),
@@ -227,7 +228,8 @@
.Depth(FifoDepth)
) u_rd_fifo (
.clk_i,
- .rst_ni (rst_ni & ~reg2hw.control.fifo_rst.q),
+ .rst_ni (rst_ni),
+ .clr_i (reg2hw.control.fifo_rst.q),
.wvalid (rd_fifo_wen),
.wready (rd_fifo_wready),
.wdata (rd_fifo_wdata),
diff --git a/hw/ip/flash_ctrl/rtl/flash_phy.sv b/hw/ip/flash_ctrl/rtl/flash_phy.sv
index ecea0f9..59179a4 100644
--- a/hw/ip/flash_ctrl/rtl/flash_phy.sv
+++ b/hw/ip/flash_ctrl/rtl/flash_phy.sv
@@ -97,6 +97,7 @@
) bank_sequence_fifo (
.clk_i,
.rst_ni,
+ .clr_i (1'b0),
.wvalid (host_req_i & host_req_rdy_o),
.wready (seq_fifo_rdy),
.wdata (host_bank_sel),
@@ -118,6 +119,7 @@
) host_rsp_fifo (
.clk_i,
.rst_ni,
+ .clr_i (1'b0),
.wvalid (host_req_done[bank]),
.wready (host_rsp_avail[bank]),
.wdata (rd_data[bank]),
diff --git a/hw/ip/prim/rtl/prim_fifo_sync.sv b/hw/ip/prim/rtl/prim_fifo_sync.sv
index d066eda..310b222 100644
--- a/hw/ip/prim/rtl/prim_fifo_sync.sv
+++ b/hw/ip/prim/rtl/prim_fifo_sync.sv
@@ -40,6 +40,10 @@
// host facing
assign wready = rready;
+ // this avoids lint warnings
+ logic unused_clr;
+ assign unused_clr = clr_i;
+
// Normal FIFO construction
end else begin : gen_normal_fifo
`ASSERT_INIT(paramCheckDepthW, DepthW == $clog2(Depth+1))
diff --git a/hw/ip/prim/rtl/prim_packer.sv b/hw/ip/prim/rtl/prim_packer.sv
index 97ef15e..e9b47ca 100644
--- a/hw/ip/prim/rtl/prim_packer.sv
+++ b/hw/ip/prim/rtl/prim_packer.sv
@@ -51,7 +51,7 @@
end
end
- assign pos_next = (valid_i) ? pos + inmask_ones : pos; // pos always stays (% OutW)
+ assign pos_next = (valid_i) ? pos + PtrW'(inmask_ones) : pos; // pos always stays (% OutW)
always_ff @(posedge clk_i or negedge rst_ni) begin
if (!rst_ni) begin
diff --git a/hw/ip/rv_plic/rtl/rv_plic_target.sv b/hw/ip/rv_plic/rtl/rv_plic_target.sv
index 17f19a5..648137f 100644
--- a/hw/ip/rv_plic/rtl/rv_plic_target.sv
+++ b/hw/ip/rv_plic/rtl/rv_plic_target.sv
@@ -48,12 +48,12 @@
max_prio = 1'b0;
irq_id_next = '0; // default: No Interrupt
for (int i = N_SOURCE-1 ; i >= 0 ; i--) begin
- if ((ip[i] & ie[i]) == 1'b1 && prio[i] >= max_prio) begin
+ if ((ip[i] & ie[i]) == 1'b1 && MAX_PRIOW'(prio[i]) >= max_prio) begin
max_prio = MAX_PRIOW'(prio[i]);
irq_id_next = SRCW'(i+1);
end
end // for i
- irq_next = (max_prio > threshold) ? 1'b1 : 1'b0;
+ irq_next = (max_prio > MAX_PRIOW'(threshold)) ? 1'b1 : 1'b0;
end
always_ff @(posedge clk_i or negedge rst_ni) begin
diff --git a/hw/ip/tlul/rtl/tlul_socket_m1.sv b/hw/ip/tlul/rtl/tlul_socket_m1.sv
index 6b68ea0..62e527d 100644
--- a/hw/ip/tlul/rtl/tlul_socket_m1.sv
+++ b/hw/ip/tlul/rtl/tlul_socket_m1.sv
@@ -211,8 +211,11 @@
drsp_fifo_o.d_source[IDW-1:STIDW]
};
for (genvar i = 0 ; i < M ; i++) begin : gen_idrouting
- assign hfifo_rspvalid[i] = drsp_fifo_o.d_valid & (drsp_fifo_o.d_source[0+:STIDW] == i);
- assign dfifo_rspready[i] = hreq_fifo_o[i].d_ready & (drsp_fifo_o.d_source[0+:STIDW] == i) & drsp_fifo_o.d_valid;
+ assign hfifo_rspvalid[i] = drsp_fifo_o.d_valid &
+ (drsp_fifo_o.d_source[0+:STIDW] == i);
+ assign dfifo_rspready[i] = hreq_fifo_o[i].d_ready &
+ (drsp_fifo_o.d_source[0+:STIDW] == i) &
+ drsp_fifo_o.d_valid;
assign hrsp_fifo_i[i] = '{
d_valid: hfifo_rspvalid[i],
diff --git a/hw/top_earlgrey/doc/top_earlgrey.sv.tpl b/hw/top_earlgrey/doc/top_earlgrey.sv.tpl
index dce7bd1..bc19c90 100644
--- a/hw/top_earlgrey/doc/top_earlgrey.sv.tpl
+++ b/hw/top_earlgrey/doc/top_earlgrey.sv.tpl
@@ -154,11 +154,14 @@
% endfor
% endfor
-
- logic [0:0] irq_plic;
+ <% add_spaces = " " * len(str((interrupt_num).bit_length()-1)) %>
+ logic [0:0]${add_spaces}irq_plic;
+ logic [0:0]${add_spaces}msip;
logic [${(interrupt_num).bit_length()-1}:0] irq_id[1];
- logic [0:0] msip;
+ logic [${(interrupt_num).bit_length()-1}:0] unused_irq_id[1];
+ // this avoids lint errors
+ assign unused_irq_id = irq_id;
// clock assignments
% for clock in top['clocks']:
diff --git a/hw/top_earlgrey/ip/xbar/rtl/autogen/xbar_main.sv b/hw/top_earlgrey/ip/xbar/rtl/autogen/xbar_main.sv
index b866e6c..80c5a72 100644
--- a/hw/top_earlgrey/ip/xbar/rtl/autogen/xbar_main.sv
+++ b/hw/top_earlgrey/ip/xbar/rtl/autogen/xbar_main.sv
@@ -117,6 +117,11 @@
import tlul_pkg::*;
import tl_main_pkg::*;
+ // scanmode_i is currently not used, but provisioned for future use
+ // this assignment prevents lint warnings
+ logic unused_scanmode;
+ assign unused_scanmode = scanmode_i;
+
tl_h2d_t tl_s1n_16_us_h2d ;
tl_d2h_t tl_s1n_16_us_d2h ;
diff --git a/hw/top_earlgrey/rtl/autogen/top_earlgrey.sv b/hw/top_earlgrey/rtl/autogen/top_earlgrey.sv
index 345bd6e..70c228c 100644
--- a/hw/top_earlgrey/rtl/autogen/top_earlgrey.sv
+++ b/hw/top_earlgrey/rtl/autogen/top_earlgrey.sv
@@ -151,11 +151,14 @@
logic intr_hmac_fifo_full;
logic intr_hmac_hmac_err;
-
- logic [0:0] irq_plic;
+
+ logic [0:0] irq_plic;
+ logic [0:0] msip;
logic [5:0] irq_id[1];
- logic [0:0] msip;
+ logic [5:0] unused_irq_id[1];
+ // this avoids lint errors
+ assign unused_irq_id = irq_id;
// clock assignments
assign main_clk = clk_i;
diff --git a/util/tlgen/xbar.rtl.sv.tpl b/util/tlgen/xbar.rtl.sv.tpl
index 90685b6..4d0f176 100644
--- a/util/tlgen/xbar.rtl.sv.tpl
+++ b/util/tlgen/xbar.rtl.sv.tpl
@@ -34,6 +34,11 @@
import tlul_pkg::*;
import tl_${xbar.name}_pkg::*;
+ // scanmode_i is currently not used, but provisioned for future use
+ // this assignment prevents lint warnings
+ logic unused_scanmode;
+ assign unused_scanmode = scanmode_i;
+
% for block in xbar.nodes:
## Create enum type for Upstream and Downstream ports connection
% if block.node_type.name == "ASYNC_FIFO":
