[dif/rv_timer] Integrate autogen'd DIF artifacts into src tree.
This commit partially addresses #8142. Specifically it:
1. deprecates existing (manually implemented) **RV Timer**
specific DIF return codes, toggle types, and params,
2. integrates the auto-generated **RV Timer** DIFs into meson build
targets,
3. refactors all existing source code to make use of the new shared DIF
types and error codes, and
Signed-off-by: Timothy Trippel <ttrippel@google.com>
diff --git a/hw/top_englishbreakfast/util/sw_sources.patch b/hw/top_englishbreakfast/util/sw_sources.patch
index 6a43b38..0ce987b 100644
--- a/hw/top_englishbreakfast/util/sw_sources.patch
+++ b/hw/top_englishbreakfast/util/sw_sources.patch
@@ -75,7 +75,7 @@
simple_serial_process_packet();
}
diff --git a/sw/device/sca/lib/sca.c b/sw/device/sca/lib/sca.c
-index 592e09547..37a172411 100644
+index 770b830eb..ec3e3be22 100644
--- a/sw/device/sca/lib/sca.c
+++ b/sw/device/sca/lib/sca.c
@@ -56,7 +56,6 @@ enum {
@@ -102,7 +102,7 @@
}
/**
-@@ -148,25 +143,6 @@ void handler_irq_timer(void) {
+@@ -147,25 +142,6 @@ void handler_irq_timer(void) {
* @param disable Set of peripherals to disable.
*/
void sca_disable_peripherals(sca_peripherals_t disable) {
@@ -128,7 +128,7 @@
// Disable HMAC, KMAC, OTBN and USB clocks through CLKMGR DIF.
dif_clkmgr_t clkmgr;
IGNORE_RESULT(dif_clkmgr_init(
-@@ -180,17 +156,6 @@ void sca_disable_peripherals(sca_peripherals_t disable) {
+@@ -179,17 +155,6 @@ void sca_disable_peripherals(sca_peripherals_t disable) {
IGNORE_RESULT(dif_clkmgr_hintable_clock_set_hint(
&clkmgr, CLKMGR_CLK_HINTS_CLK_MAIN_HMAC_HINT_BIT, kDifToggleDisabled));
}
@@ -169,10 +169,10 @@
CHECK_DIF_OK(
dif_aes_init(mmio_region_from_addr(TOP_EARLGREY_AES_BASE_ADDR), &aes));
diff --git a/sw/device/tests/meson.build b/sw/device/tests/meson.build
-index 230bbb613..5e5676718 100644
+index 770328dd9..8aaa642db 100644
--- a/sw/device/tests/meson.build
+++ b/sw/device/tests/meson.build
-@@ -207,7 +207,6 @@ aes_smoketest_lib = declare_dependency(
+@@ -224,7 +224,6 @@ aes_smoketest_lib = declare_dependency(
sw_lib_dif_aes,
sw_lib_mmio,
sw_lib_runtime_log,
diff --git a/sw/device/lib/dif/autogen/meson.build b/sw/device/lib/dif/autogen/meson.build
index bc6544c..0766c9f 100644
--- a/sw/device/lib/dif/autogen/meson.build
+++ b/sw/device/lib/dif/autogen/meson.build
@@ -268,6 +268,20 @@
)
)
+# Autogen RV Timer DIF library
+sw_lib_dif_autogen_rv_timer = declare_dependency(
+ link_with: static_library(
+ 'sw_lib_dif_autogen_rv_timer',
+ sources: [
+ hw_ip_rv_timer_reg_h,
+ 'dif_rv_timer_autogen.c',
+ ],
+ dependencies: [
+ sw_lib_mmio,
+ ],
+ )
+)
+
# Autogen SPI Device DIF library
sw_lib_dif_autogen_spi_device = declare_dependency(
link_with: static_library(
diff --git a/sw/device/lib/dif/dif_rv_timer.c b/sw/device/lib/dif/dif_rv_timer.c
index 2b6051e..a11315f 100644
--- a/sw/device/lib/dif/dif_rv_timer.c
+++ b/sw/device/lib/dif/dif_rv_timer.c
@@ -4,12 +4,18 @@
#include "sw/device/lib/dif/dif_rv_timer.h"
+#include <assert.h>
#include <stddef.h>
#include "sw/device/lib/base/bitfield.h"
#include "rv_timer_regs.h" // Generated.
+static_assert(RV_TIMER_PARAM_N_HARTS > 0,
+ "RV Timer must support at least one hart.");
+static_assert(RV_TIMER_PARAM_N_TIMERS > 0,
+ "RV Timer must support at least one timer per hart.");
+
/**
* The factor to multiply by to find the registers for the Nth hart.
*
@@ -30,16 +36,13 @@
return kHartRegisterSpacing * hart + reg_offset;
}
-dif_rv_timer_result_t dif_rv_timer_init(mmio_region_t base_addr,
- dif_rv_timer_config_t config,
- dif_rv_timer_t *timer_out) {
- if (timer_out == NULL || config.hart_count < 1 ||
- config.comparator_count < 1) {
- return kDifRvTimerBadArg;
+dif_result_t dif_rv_timer_init(mmio_region_t base_addr,
+ dif_rv_timer_t *timer_out) {
+ if (timer_out == NULL) {
+ return kDifBadArg;
}
timer_out->base_addr = base_addr;
- timer_out->config = config;
return dif_rv_timer_reset(timer_out);
}
@@ -59,11 +62,11 @@
return a;
}
-dif_rv_timer_approximate_tick_params_result_t
-dif_rv_timer_approximate_tick_params(uint64_t clock_freq, uint64_t counter_freq,
- dif_rv_timer_tick_params_t *out) {
+dif_result_t dif_rv_timer_approximate_tick_params(
+ uint64_t clock_freq, uint64_t counter_freq,
+ dif_rv_timer_tick_params_t *out) {
if (out == NULL) {
- return kDifRvTimerApproximateTickParamsBadArg;
+ return kDifBadArg;
}
// We have the following relation:
@@ -78,20 +81,20 @@
if (prescale > RV_TIMER_CFG0_PRESCALE_MASK ||
step > RV_TIMER_CFG0_STEP_MASK) {
- return kDifRvTimerApproximateTickParamsUnrepresentable;
+ return kDifBadArg;
}
out->prescale = (uint16_t)prescale;
out->tick_step = (uint8_t)step;
- return kDifRvTimerApproximateTickParamsOk;
+ return kDifOk;
}
-dif_rv_timer_result_t dif_rv_timer_set_tick_params(
- const dif_rv_timer_t *timer, uint32_t hart_id,
- dif_rv_timer_tick_params_t params) {
- if (timer == NULL || hart_id >= timer->config.hart_count) {
- return kDifRvTimerBadArg;
+dif_result_t dif_rv_timer_set_tick_params(const dif_rv_timer_t *timer,
+ uint32_t hart_id,
+ dif_rv_timer_tick_params_t params) {
+ if (timer == NULL || hart_id >= RV_TIMER_PARAM_N_HARTS) {
+ return kDifBadArg;
}
uint32_t config_value = 0;
@@ -103,37 +106,36 @@
reg_for_hart(hart_id, RV_TIMER_CFG0_REG_OFFSET),
config_value);
- return kDifRvTimerOk;
+ return kDifOk;
}
-dif_rv_timer_result_t dif_rv_timer_counter_set_enabled(
- const dif_rv_timer_t *timer, uint32_t hart_id,
- dif_rv_timer_enabled_t state) {
- if (timer == NULL || hart_id >= timer->config.hart_count) {
- return kDifRvTimerBadArg;
+dif_result_t dif_rv_timer_counter_set_enabled(const dif_rv_timer_t *timer,
+ uint32_t hart_id,
+ dif_toggle_t state) {
+ if (timer == NULL || hart_id >= RV_TIMER_PARAM_N_HARTS) {
+ return kDifBadArg;
}
switch (state) {
- case kDifRvTimerEnabled:
+ case kDifToggleEnabled:
mmio_region_nonatomic_set_bit32(timer->base_addr,
RV_TIMER_CTRL_REG_OFFSET, hart_id);
break;
- case kDifRvTimerDisabled:
+ case kDifToggleDisabled:
mmio_region_nonatomic_clear_bit32(timer->base_addr,
RV_TIMER_CTRL_REG_OFFSET, hart_id);
break;
default:
- return kDifRvTimerBadArg;
+ return kDifBadArg;
}
- return kDifRvTimerOk;
+ return kDifOk;
}
-dif_rv_timer_result_t dif_rv_timer_counter_read(const dif_rv_timer_t *timer,
- uint32_t hart_id,
- uint64_t *out) {
- if (timer == NULL || out == NULL || hart_id >= timer->config.hart_count) {
- return kDifRvTimerBadArg;
+dif_result_t dif_rv_timer_counter_read(const dif_rv_timer_t *timer,
+ uint32_t hart_id, uint64_t *out) {
+ if (timer == NULL || out == NULL || hart_id >= RV_TIMER_PARAM_N_HARTS) {
+ return kDifBadArg;
}
// We need to read a monotonically increasing, volatile uint64. To do so,
@@ -154,16 +156,15 @@
if (upper == overflow_check) {
*out = (((uint64_t)upper) << 32) | lower;
- return kDifRvTimerOk;
+ return kDifOk;
}
}
}
-dif_rv_timer_result_t dif_rv_timer_counter_write(const dif_rv_timer_t *timer,
- uint32_t hart_id,
- uint64_t count) {
- if (timer == NULL || hart_id >= timer->config.hart_count) {
- return kDifRvTimerBadArg;
+dif_result_t dif_rv_timer_counter_write(const dif_rv_timer_t *timer,
+ uint32_t hart_id, uint64_t count) {
+ if (timer == NULL || hart_id >= RV_TIMER_PARAM_N_HARTS) {
+ return kDifBadArg;
}
// Disable the counter.
@@ -186,15 +187,14 @@
// Re-enable the counter (if it was previously enabled).
mmio_region_write32(timer->base_addr, RV_TIMER_CTRL_REG_OFFSET, ctrl_reg);
- return kDifRvTimerOk;
+ return kDifOk;
}
-dif_rv_timer_result_t dif_rv_timer_arm(const dif_rv_timer_t *timer,
- uint32_t hart_id, uint32_t comp_id,
- uint64_t threshold) {
- if (timer == NULL || hart_id >= timer->config.hart_count ||
- comp_id >= timer->config.comparator_count) {
- return kDifRvTimerBadArg;
+dif_result_t dif_rv_timer_arm(const dif_rv_timer_t *timer, uint32_t hart_id,
+ uint32_t comp_id, uint64_t threshold) {
+ if (timer == NULL || hart_id >= RV_TIMER_PARAM_N_HARTS ||
+ comp_id >= RV_TIMER_PARAM_N_TIMERS) {
+ return kDifBadArg;
}
uint32_t lower = threshold;
@@ -217,7 +217,7 @@
// Finish writing the new value; this may set off an alarm immediately.
mmio_region_write32(timer->base_addr, upper_reg, upper);
- return kDifRvTimerOk;
+ return kDifOk;
}
/**
@@ -252,140 +252,28 @@
return reg_for_hart(hart_id, reg_offset) + extra_comparator_offset;
}
-dif_rv_timer_result_t dif_rv_timer_irq_enable(const dif_rv_timer_t *timer,
- uint32_t hart_id,
- uint32_t comp_id,
- dif_rv_timer_enabled_t state) {
- if (timer == NULL || hart_id >= timer->config.hart_count ||
- comp_id >= timer->config.comparator_count) {
- return kDifRvTimerBadArg;
- }
-
- ptrdiff_t reg = irq_reg_for_hart(hart_id, timer->config.comparator_count,
- RV_TIMER_INTR_ENABLE0_REG_OFFSET);
-
- switch (state) {
- case kDifRvTimerEnabled:
- mmio_region_nonatomic_set_bit32(timer->base_addr, reg, comp_id);
- break;
- case kDifRvTimerDisabled:
- mmio_region_nonatomic_clear_bit32(timer->base_addr, reg, comp_id);
- break;
- default:
- return kDifRvTimerBadArg;
- }
-
- return kDifRvTimerOk;
-}
-
-dif_rv_timer_result_t dif_rv_timer_irq_get(const dif_rv_timer_t *timer,
- uint32_t hart_id, uint32_t comp_id,
- bool *flag_out) {
- if (timer == NULL || flag_out == NULL ||
- hart_id >= timer->config.hart_count ||
- comp_id >= timer->config.comparator_count) {
- return kDifRvTimerBadArg;
- }
-
- ptrdiff_t reg = irq_reg_for_hart(hart_id, timer->config.comparator_count,
- RV_TIMER_INTR_STATE0_REG_OFFSET);
-
- *flag_out = mmio_region_get_bit32(timer->base_addr, reg, comp_id);
-
- return kDifRvTimerOk;
-}
-
-dif_rv_timer_result_t dif_rv_timer_irq_clear(const dif_rv_timer_t *timer,
- uint32_t hart_id,
- uint32_t comp_id) {
- if (timer == NULL || hart_id >= timer->config.hart_count ||
- comp_id >= timer->config.comparator_count) {
- return kDifRvTimerBadArg;
- }
-
- ptrdiff_t reg = irq_reg_for_hart(hart_id, timer->config.comparator_count,
- RV_TIMER_INTR_STATE0_REG_OFFSET);
-
- mmio_region_write32(timer->base_addr, reg, 1 << comp_id);
-
- return kDifRvTimerOk;
-}
-
-dif_rv_timer_result_t dif_rv_timer_irq_disable(const dif_rv_timer_t *timer,
- uint32_t hart_id,
- uint32_t *state) {
- if (timer == NULL || hart_id >= timer->config.hart_count) {
- return kDifRvTimerBadArg;
- }
-
- ptrdiff_t reg = irq_reg_for_hart(hart_id, timer->config.comparator_count,
- RV_TIMER_INTR_ENABLE0_REG_OFFSET);
-
- if (state != NULL) {
- *state = mmio_region_read32(timer->base_addr, reg);
- }
-
- mmio_region_write32(timer->base_addr, reg, 0);
-
- return kDifRvTimerOk;
-}
-
-dif_rv_timer_result_t dif_rv_timer_irq_restore(const dif_rv_timer_t *timer,
- uint32_t hart_id,
- uint32_t state) {
- if (timer == NULL || hart_id >= timer->config.hart_count) {
- return kDifRvTimerBadArg;
- }
-
- ptrdiff_t reg = irq_reg_for_hart(hart_id, timer->config.comparator_count,
- RV_TIMER_INTR_ENABLE0_REG_OFFSET);
-
- mmio_region_write32(timer->base_addr, reg, state);
-
- return kDifRvTimerOk;
-}
-
-dif_rv_timer_result_t dif_rv_timer_irq_force(const dif_rv_timer_t *timer,
- uint32_t hart_id,
- uint32_t comp_id) {
- if (timer == NULL || hart_id >= timer->config.hart_count ||
- comp_id >= timer->config.comparator_count) {
- return kDifRvTimerBadArg;
- }
-
- ptrdiff_t reg = irq_reg_for_hart(hart_id, timer->config.comparator_count,
- RV_TIMER_INTR_TEST0_REG_OFFSET);
-
- mmio_region_write32(timer->base_addr, reg, 1 << comp_id);
-
- return kDifRvTimerOk;
-}
-
-dif_rv_timer_result_t dif_rv_timer_reset(const dif_rv_timer_t *timer) {
+dif_result_t dif_rv_timer_reset(const dif_rv_timer_t *timer) {
if (timer == NULL) {
- return kDifRvTimerBadArg;
+ return kDifBadArg;
}
// Disable all counters.
mmio_region_write32(timer->base_addr, RV_TIMER_CTRL_REG_OFFSET, 0x0);
- for (uint32_t hart_id = 0; hart_id < timer->config.hart_count; ++hart_id) {
+ for (uint32_t hart_id = 0; hart_id < RV_TIMER_PARAM_N_HARTS; ++hart_id) {
// Clear and disable all interrupts.
- ptrdiff_t irq_status =
- irq_reg_for_hart(hart_id, timer->config.comparator_count,
- RV_TIMER_INTR_STATE0_REG_OFFSET);
- ptrdiff_t irq_enable =
- irq_reg_for_hart(hart_id, timer->config.comparator_count,
- RV_TIMER_INTR_ENABLE0_REG_OFFSET);
+ ptrdiff_t irq_status = irq_reg_for_hart(hart_id, RV_TIMER_PARAM_N_TIMERS,
+ RV_TIMER_INTR_STATE0_REG_OFFSET);
+ ptrdiff_t irq_enable = irq_reg_for_hart(hart_id, RV_TIMER_PARAM_N_TIMERS,
+ RV_TIMER_INTR_ENABLE0_REG_OFFSET);
mmio_region_write32(timer->base_addr, irq_enable, 0x0);
mmio_region_write32(timer->base_addr, irq_status, UINT32_MAX);
// Reset all comparators to their default all-ones state.
- for (uint32_t comp_id = 0; comp_id < timer->config.comparator_count;
- ++comp_id) {
- dif_rv_timer_result_t error =
+ for (uint32_t comp_id = 0; comp_id < RV_TIMER_PARAM_N_TIMERS; ++comp_id) {
+ dif_result_t error =
dif_rv_timer_arm(timer, hart_id, comp_id, UINT64_MAX);
- if (error != kDifRvTimerOk) {
+ if (error != kDifOk) {
return error;
}
}
@@ -399,5 +287,5 @@
reg_for_hart(hart_id, RV_TIMER_TIMER_V_UPPER0_REG_OFFSET), 0x0);
}
- return kDifRvTimerOk;
+ return kDifOk;
}
diff --git a/sw/device/lib/dif/dif_rv_timer.h b/sw/device/lib/dif/dif_rv_timer.h
index f73b5a9..0b2d3c1 100644
--- a/sw/device/lib/dif/dif_rv_timer.h
+++ b/sw/device/lib/dif/dif_rv_timer.h
@@ -13,20 +13,15 @@
#include <stdint.h>
#include "sw/device/lib/base/mmio.h"
+#include "sw/device/lib/dif/dif_base.h"
+
+#include "sw/device/lib/dif/autogen/dif_rv_timer_autogen.h"
#ifdef __cplusplus
extern "C" {
#endif // __cplusplus
/**
- * Represents an "enabled" state for a timer.
- */
-typedef enum dif_rv_timer_enabled {
- kDifRvTimerDisabled = 0,
- kDifRvTimerEnabled,
-} dif_rv_timer_enabled_t;
-
-/**
* Represents timekeeping parameters for a particular timer.
*/
typedef struct dif_rv_timer_tick_params {
@@ -63,29 +58,6 @@
} dif_rv_timer_tick_params_t;
/**
- * Represents the result of an RV timer operation..
- */
-typedef enum dif_rv_timer_result {
- kDifRvTimerOk = 0,
- kDifRvTimerBadArg = 1,
- kDifRvTimerError = 2,
-} dif_rv_timer_result_t;
-
-/**
- * Errors returned by `dif_rv_timer_approximate_tick_params()`.
- */
-typedef enum dif_rv_timer_approximate_tick_params_result {
- kDifRvTimerApproximateTickParamsOk = kDifRvTimerOk,
- kDifRvTimerApproximateTickParamsBadArg = kDifRvTimerBadArg,
- kDifRvTimerApproximateTickParamsError = kDifRvTimerError,
- /**
- * Indicates that the requested counter frequency cannot be represented
- * without loss in precission.
- */
- kDifRvTimerApproximateTickParamsUnrepresentable,
-} dif_rv_timer_approximate_tick_params_result_t;
-
-/**
* Generates an aproximate `dif_rv_timer_tick_params_t` given the device
* clock frequency and desired counter frequency (both given in Hertz).
*
@@ -108,40 +80,9 @@
* counter frequency.
* @return The result of the operation.
*/
-dif_rv_timer_approximate_tick_params_result_t
-dif_rv_timer_approximate_tick_params(uint64_t clock_freq, uint64_t counter_freq,
- dif_rv_timer_tick_params_t *out);
-/**
- * Configuration for initializing the RISC-V timer device.
- */
-typedef struct dif_rv_timer_config {
- /**
- * The number of harts that this device supports time counters for.
- * Must be at least one.
- *
- * This value is determined entirely by the hardware configuration.
- */
- uint32_t hart_count;
-
- /**
- * The number of comparators (i.e, timers that can be set) associated
- * with each hart. Must be at least one.
- *
- * This value is determined entirely by the hardware configuration.
- */
- uint32_t comparator_count;
-} dif_rv_timer_config_t;
-
-/**
- * State for a RISC-V timer, associated with a particular hardware thread.
- *
- * Its member variables should be considered private, and are only provided so
- * that callers can allocate it.
- */
-typedef struct dif_rv_timer {
- mmio_region_t base_addr;
- dif_rv_timer_config_t config;
-} dif_rv_timer_t;
+dif_result_t dif_rv_timer_approximate_tick_params(
+ uint64_t clock_freq, uint64_t counter_freq,
+ dif_rv_timer_tick_params_t *out);
/**
* Initialize a RISC-V timer device with the given configuration.
@@ -150,13 +91,11 @@
* each be configured and turned on manually after this function returns.
*
* @param base_addr MMIO region for the device hardware registers.
- * @param config Configuration for initializing a particular timer.
* @param[out] timer_out The timer device.
* @return The result of the operation.
*/
-dif_rv_timer_result_t dif_rv_timer_init(mmio_region_t base_addr,
- dif_rv_timer_config_t config,
- dif_rv_timer_t *timer_out);
+dif_result_t dif_rv_timer_init(mmio_region_t base_addr,
+ dif_rv_timer_t *timer_out);
/**
* Completely resets a timer device, disabling all IRQs, counters, and
@@ -165,7 +104,7 @@
* @param timer A timer device.
* @return The result of the operation.
*/
-dif_rv_timer_result_t dif_rv_timer_reset(const dif_rv_timer_t *timer);
+dif_result_t dif_rv_timer_reset(const dif_rv_timer_t *timer);
/**
* Configures the tick params for a particular hart's counter.
@@ -180,9 +119,9 @@
* @param params The timing parameters.
* @return The result of the operation.
*/
-dif_rv_timer_result_t dif_rv_timer_set_tick_params(
- const dif_rv_timer_t *timer, uint32_t hart_id,
- dif_rv_timer_tick_params_t params);
+dif_result_t dif_rv_timer_set_tick_params(const dif_rv_timer_t *timer,
+ uint32_t hart_id,
+ dif_rv_timer_tick_params_t params);
/**
* Starts or stops a particular hart's counter.
@@ -195,9 +134,9 @@
* @param state The new enablement state.
* @return The result of the operation.
*/
-dif_rv_timer_result_t dif_rv_timer_counter_set_enabled(
- const dif_rv_timer_t *timer, uint32_t hart_id,
- dif_rv_timer_enabled_t state);
+dif_result_t dif_rv_timer_counter_set_enabled(const dif_rv_timer_t *timer,
+ uint32_t hart_id,
+ dif_toggle_t state);
/**
* Reads the current value on a particular hart's timer.
@@ -207,9 +146,8 @@
* @param[out] out The counter value.
* @return The result of the operation.
*/
-dif_rv_timer_result_t dif_rv_timer_counter_read(const dif_rv_timer_t *timer,
- uint32_t hart_id,
- uint64_t *out);
+dif_result_t dif_rv_timer_counter_read(const dif_rv_timer_t *timer,
+ uint32_t hart_id, uint64_t *out);
/**
* Writes the given value to a particular hart's timer.
@@ -219,9 +157,8 @@
* @param count The counter value to write.
* @return The result of the operation.
*/
-dif_rv_timer_result_t dif_rv_timer_counter_write(const dif_rv_timer_t *timer,
- uint32_t hart_id,
- uint64_t count);
+dif_result_t dif_rv_timer_counter_write(const dif_rv_timer_t *timer,
+ uint32_t hart_id, uint64_t count);
/**
* Arms the timer to go off once the counter value is greater than
@@ -251,88 +188,8 @@
* @param threshold The value to go off at.
* @return The result of the operation.
*/
-dif_rv_timer_result_t dif_rv_timer_arm(const dif_rv_timer_t *timer,
- uint32_t hart_id, uint32_t comp_id,
- uint64_t threshold);
-
-/**
- * Enables or disables a particular timer's IRQ. That is, this function controls
- * whether or not an IRQ is fired when the timer reaches its configured
- * threshold.
- *
- * @param timer A timer device.
- * @param hart_id The hart counter associated with the timer.
- * @param comp_id The comparator associated with the timer.
- * @param state The desired status.
- * @return the result of the operation.
- */
-dif_rv_timer_result_t dif_rv_timer_irq_enable(const dif_rv_timer_t *timer,
- uint32_t hart_id,
- uint32_t comp_id,
- dif_rv_timer_enabled_t state);
-
-/**
- * Returns whether the IRQ for a particular timer is currently being serviced.
- *
- * @param timer A timer device.
- * @param hart_id The hart counter associated with the timer.
- * @param comp_id The comparator associated with the timer.
- * @param[out] flag_out The interrupt status.
- * @return the result of the operation.
- */
-dif_rv_timer_result_t dif_rv_timer_irq_get(const dif_rv_timer_t *timer,
- uint32_t hart_id, uint32_t comp_id,
- bool *flag_out);
-
-/**
- * Clears the IRQ for a particular timer.
- *
- * @param timer A timer device.
- * @param hart_id The hart counter associated with the timer.
- * @param comp_id The comparator associated with the timer.
- * @return the result of the operation.
- */
-dif_rv_timer_result_t dif_rv_timer_irq_clear(const dif_rv_timer_t *timer,
- uint32_t hart_id,
- uint32_t comp_id);
-
-/**
- * Forces the IRQ for a particular timer to fire.
- *
- * @param timer A timer device.
- * @param hart_id The hart counter associated with the timer.
- * @param comp_id The comparator associated with the timer.
- * @return the result of the operation.
- */
-dif_rv_timer_result_t dif_rv_timer_irq_force(const dif_rv_timer_t *timer,
- uint32_t hart_id,
- uint32_t comp_id);
-
-/**
- * Disables all IRQs for a particular hart.
- *
- * Optionally returns a `state` value containing the previous itnerrupt state.
- * `state` may be NULL. See `dif_rv_timer_irq_restore()`.
- *
- * @param timer a timer device.
- * @param[out] state IRQ state information for use with
- * `dif_rv_timer_irq_restore`.
- * @return the result of the operation.
- */
-dif_rv_timer_result_t dif_rv_timer_irq_disable(const dif_rv_timer_t *timer,
- uint32_t hart_id,
- uint32_t *state);
-
-/**
- * Restores IRQ state for a particular hart.
- *
- * @param timer a timer device.
- * @param state IRQ state information to restore.
- * @return the result of the operation.
- */
-dif_rv_timer_result_t dif_rv_timer_irq_restore(const dif_rv_timer_t *timer,
- uint32_t hart_id,
- uint32_t state);
+dif_result_t dif_rv_timer_arm(const dif_rv_timer_t *timer, uint32_t hart_id,
+ uint32_t comp_id, uint64_t threshold);
#ifdef __cplusplus
} // extern "C"
diff --git a/sw/device/lib/dif/dif_rv_timer_unittest.cc b/sw/device/lib/dif/dif_rv_timer_unittest.cc
index 6b81809..5c71591 100644
--- a/sw/device/lib/dif/dif_rv_timer_unittest.cc
+++ b/sw/device/lib/dif/dif_rv_timer_unittest.cc
@@ -43,7 +43,7 @@
constexpr uint32_t kFastTimer = 120'000'000; // 120 MHz
constexpr uint32_t kSluggishTimer = 3; // 3 Hz
-TEST(ApproximateParamsTest, Baseline) {
+TEST(ApproximateParamsTest, Success) {
// The timer frequency devices the clock speed, so their quotient minus 1 is
// the prescale.
dif_rv_timer_tick_params_t params, expected = {
@@ -52,7 +52,7 @@
};
EXPECT_EQ(
dif_rv_timer_approximate_tick_params(kClockSpeed, kSlowTimer, ¶ms),
- kDifRvTimerOk);
+ kDifOk);
EXPECT_EQ(params, expected);
}
@@ -64,7 +64,7 @@
};
EXPECT_EQ(
dif_rv_timer_approximate_tick_params(kClockSpeed, kFastTimer, ¶ms),
- kDifRvTimerOk);
+ kDifOk);
EXPECT_EQ(params, expected);
}
@@ -75,7 +75,7 @@
dif_rv_timer_tick_params_t params;
EXPECT_EQ(dif_rv_timer_approximate_tick_params(kFastClockSpeed,
kSluggishTimer, ¶ms),
- kDifRvTimerApproximateTickParamsUnrepresentable);
+ kDifBadArg);
}
TEST(ApproximateParamsTest, UnrepresenableTooFast) {
@@ -84,23 +84,18 @@
dif_rv_timer_tick_params_t params;
EXPECT_EQ(dif_rv_timer_approximate_tick_params(kSlowClockSpeed, kFastTimer,
¶ms),
- kDifRvTimerApproximateTickParamsUnrepresentable);
+ kDifBadArg);
}
TEST(ApproximateParamsTest, NullArgs) {
EXPECT_EQ(dif_rv_timer_approximate_tick_params(kSlowClockSpeed, kFastTimer,
nullptr),
- kDifRvTimerBadArg);
+ kDifBadArg);
}
class TimerTest : public testing::Test, public MmioTest {
protected:
- dif_rv_timer_t MakeTimer(dif_rv_timer_config_t config) {
- return {
- .base_addr = dev().region(),
- .config = config,
- };
- }
+ dif_rv_timer_t rv_timer_ = {.base_addr = dev().region()};
};
// Copy of `reg_for_hart()` in the C translation unit under test.
@@ -120,7 +115,7 @@
class InitTest : public TimerTest {};
-TEST_F(InitTest, OneEach) {
+TEST_F(InitTest, Success) {
EXPECT_WRITE32(RV_TIMER_CTRL_REG_OFFSET, 0x0);
EXPECT_WRITE32(IrqRegForHart(0, 1, RV_TIMER_INTR_ENABLE0_REG_OFFSET), 0x0);
@@ -134,292 +129,128 @@
EXPECT_WRITE32(RegForHart(0, RV_TIMER_TIMER_V_LOWER0_REG_OFFSET), 0x0);
EXPECT_WRITE32(RegForHart(0, RV_TIMER_TIMER_V_UPPER0_REG_OFFSET), 0x0);
- dif_rv_timer timer;
- EXPECT_EQ(dif_rv_timer_init(dev().region(),
- {
- .hart_count = 1,
- .comparator_count = 1,
- },
- &timer),
- kDifRvTimerOk);
-}
-
-TEST_F(InitTest, FourCmps) {
- EXPECT_WRITE32(RV_TIMER_CTRL_REG_OFFSET, 0x0);
-
- EXPECT_WRITE32(IrqRegForHart(0, 4, RV_TIMER_INTR_ENABLE0_REG_OFFSET), 0x0);
- EXPECT_WRITE32(IrqRegForHart(0, 4, RV_TIMER_INTR_STATE0_REG_OFFSET),
- kAllOnes);
-
- for (ptrdiff_t cmp_offset = 0; cmp_offset < 32; cmp_offset += 8) {
- EXPECT_WRITE32(
- RegForHart(0, RV_TIMER_COMPARE_UPPER0_0_REG_OFFSET) + cmp_offset,
- kAllOnes);
- EXPECT_WRITE32(
- RegForHart(0, RV_TIMER_COMPARE_LOWER0_0_REG_OFFSET) + cmp_offset,
- kAllOnes);
- EXPECT_WRITE32(
- RegForHart(0, RV_TIMER_COMPARE_UPPER0_0_REG_OFFSET) + cmp_offset,
- kAllOnes);
- }
-
- EXPECT_WRITE32(RegForHart(0, RV_TIMER_TIMER_V_LOWER0_REG_OFFSET), 0x0);
- EXPECT_WRITE32(RegForHart(0, RV_TIMER_TIMER_V_UPPER0_REG_OFFSET), 0x0);
-
- dif_rv_timer timer;
- EXPECT_EQ(dif_rv_timer_init(dev().region(),
- {
- .hart_count = 1,
- .comparator_count = 4,
- },
- &timer),
- kDifRvTimerOk);
-}
-
-TEST_F(InitTest, FourEach) {
- EXPECT_WRITE32(RV_TIMER_CTRL_REG_OFFSET, 0x0);
-
- for (uint32_t hart = 0; hart < 4; ++hart) {
- EXPECT_WRITE32(IrqRegForHart(hart, 4, RV_TIMER_INTR_ENABLE0_REG_OFFSET),
- 0x0);
- EXPECT_WRITE32(IrqRegForHart(hart, 4, RV_TIMER_INTR_STATE0_REG_OFFSET),
- kAllOnes);
-
- for (ptrdiff_t cmp_offset = 0; cmp_offset < 32; cmp_offset += 8) {
- EXPECT_WRITE32(
- RegForHart(hart, RV_TIMER_COMPARE_UPPER0_0_REG_OFFSET) + cmp_offset,
- kAllOnes);
- EXPECT_WRITE32(
- RegForHart(hart, RV_TIMER_COMPARE_LOWER0_0_REG_OFFSET) + cmp_offset,
- kAllOnes);
- EXPECT_WRITE32(
- RegForHart(hart, RV_TIMER_COMPARE_UPPER0_0_REG_OFFSET) + cmp_offset,
- kAllOnes);
- }
-
- EXPECT_WRITE32(RegForHart(hart, RV_TIMER_TIMER_V_LOWER0_REG_OFFSET), 0x0);
- EXPECT_WRITE32(RegForHart(hart, RV_TIMER_TIMER_V_UPPER0_REG_OFFSET), 0x0);
- }
-
- dif_rv_timer timer;
- EXPECT_EQ(dif_rv_timer_init(dev().region(),
- {
- .hart_count = 4,
- .comparator_count = 4,
- },
- &timer),
- kDifRvTimerOk);
+ EXPECT_EQ(dif_rv_timer_init(dev().region(), &rv_timer_), kDifOk);
}
TEST_F(InitTest, NullArgs) {
- EXPECT_EQ(dif_rv_timer_init(dev().region(),
- {
- .hart_count = 1,
- .comparator_count = 1,
- },
- nullptr),
- kDifRvTimerBadArg);
-}
-
-TEST_F(InitTest, NoHartNoTimers) {
- dif_rv_timer_t timer;
- EXPECT_EQ(dif_rv_timer_init(dev().region(),
- {
- .hart_count = 0,
- .comparator_count = 1,
- },
- &timer),
- kDifRvTimerBadArg);
- EXPECT_EQ(dif_rv_timer_init(dev().region(),
- {
- .hart_count = 1,
- .comparator_count = 0,
- },
- &timer),
- kDifRvTimerBadArg);
+ EXPECT_EQ(dif_rv_timer_init(dev().region(), nullptr), kDifBadArg);
}
class ResetTest : public TimerTest {};
-TEST_F(ResetTest, OneEach) {
+TEST_F(ResetTest, Success) {
EXPECT_WRITE32(RV_TIMER_CTRL_REG_OFFSET, 0x0);
- EXPECT_WRITE32(IrqRegForHart(0, 1, RV_TIMER_INTR_ENABLE0_REG_OFFSET), 0x0);
- EXPECT_WRITE32(IrqRegForHart(0, 1, RV_TIMER_INTR_STATE0_REG_OFFSET),
- kAllOnes);
-
- EXPECT_WRITE32(RegForHart(0, RV_TIMER_COMPARE_UPPER0_0_REG_OFFSET), kAllOnes);
- EXPECT_WRITE32(RegForHart(0, RV_TIMER_COMPARE_LOWER0_0_REG_OFFSET), kAllOnes);
- EXPECT_WRITE32(RegForHart(0, RV_TIMER_COMPARE_UPPER0_0_REG_OFFSET), kAllOnes);
-
- EXPECT_WRITE32(RegForHart(0, RV_TIMER_TIMER_V_LOWER0_REG_OFFSET), 0x0);
- EXPECT_WRITE32(RegForHart(0, RV_TIMER_TIMER_V_UPPER0_REG_OFFSET), 0x0);
-
- auto timer = MakeTimer({1, 1});
- EXPECT_EQ(dif_rv_timer_reset(&timer), kDifRvTimerOk);
-}
-
-TEST_F(ResetTest, FourCmps) {
- EXPECT_WRITE32(RV_TIMER_CTRL_REG_OFFSET, 0x0);
-
- EXPECT_WRITE32(IrqRegForHart(0, 4, RV_TIMER_INTR_ENABLE0_REG_OFFSET), 0x0);
- EXPECT_WRITE32(IrqRegForHart(0, 4, RV_TIMER_INTR_STATE0_REG_OFFSET),
- kAllOnes);
-
- for (ptrdiff_t cmp_offset = 0; cmp_offset < 32; cmp_offset += 8) {
- EXPECT_WRITE32(
- RegForHart(0, RV_TIMER_COMPARE_UPPER0_0_REG_OFFSET) + cmp_offset,
- kAllOnes);
- EXPECT_WRITE32(
- RegForHart(0, RV_TIMER_COMPARE_LOWER0_0_REG_OFFSET) + cmp_offset,
- kAllOnes);
- EXPECT_WRITE32(
- RegForHart(0, RV_TIMER_COMPARE_UPPER0_0_REG_OFFSET) + cmp_offset,
- kAllOnes);
- }
-
- EXPECT_WRITE32(RegForHart(0, RV_TIMER_TIMER_V_LOWER0_REG_OFFSET), 0x0);
- EXPECT_WRITE32(RegForHart(0, RV_TIMER_TIMER_V_UPPER0_REG_OFFSET), 0x0);
-
- auto timer = MakeTimer({1, 4});
- EXPECT_EQ(dif_rv_timer_reset(&timer), kDifRvTimerOk);
-}
-
-TEST_F(ResetTest, FourSix) {
- EXPECT_WRITE32(RV_TIMER_CTRL_REG_OFFSET, 0x0);
-
- for (uint32_t hart = 0; hart < 4; ++hart) {
- EXPECT_WRITE32(IrqRegForHart(hart, 6, RV_TIMER_INTR_ENABLE0_REG_OFFSET),
- 0x0);
- EXPECT_WRITE32(IrqRegForHart(hart, 6, RV_TIMER_INTR_STATE0_REG_OFFSET),
+ for (uint32_t hart_id = 0; hart_id < RV_TIMER_PARAM_N_HARTS; ++hart_id) {
+ EXPECT_WRITE32(IrqRegForHart(0, 1, RV_TIMER_INTR_ENABLE0_REG_OFFSET), 0x0);
+ EXPECT_WRITE32(IrqRegForHart(0, 1, RV_TIMER_INTR_STATE0_REG_OFFSET),
kAllOnes);
- for (ptrdiff_t cmp_offset = 0; cmp_offset < 48; cmp_offset += 8) {
- EXPECT_WRITE32(
- RegForHart(hart, RV_TIMER_COMPARE_UPPER0_0_REG_OFFSET) + cmp_offset,
- kAllOnes);
- EXPECT_WRITE32(
- RegForHart(hart, RV_TIMER_COMPARE_LOWER0_0_REG_OFFSET) + cmp_offset,
- kAllOnes);
- EXPECT_WRITE32(
- RegForHart(hart, RV_TIMER_COMPARE_UPPER0_0_REG_OFFSET) + cmp_offset,
- kAllOnes);
+ for (uint32_t comp_id = 0; comp_id < RV_TIMER_PARAM_N_TIMERS; ++comp_id) {
+ EXPECT_WRITE32(RegForHart(0, RV_TIMER_COMPARE_UPPER0_0_REG_OFFSET),
+ kAllOnes);
+ EXPECT_WRITE32(RegForHart(0, RV_TIMER_COMPARE_LOWER0_0_REG_OFFSET),
+ kAllOnes);
+ EXPECT_WRITE32(RegForHart(0, RV_TIMER_COMPARE_UPPER0_0_REG_OFFSET),
+ kAllOnes);
}
-
- EXPECT_WRITE32(RegForHart(hart, RV_TIMER_TIMER_V_LOWER0_REG_OFFSET), 0x0);
- EXPECT_WRITE32(RegForHart(hart, RV_TIMER_TIMER_V_UPPER0_REG_OFFSET), 0x0);
}
+ EXPECT_WRITE32(RegForHart(0, RV_TIMER_TIMER_V_LOWER0_REG_OFFSET), 0x0);
+ EXPECT_WRITE32(RegForHart(0, RV_TIMER_TIMER_V_UPPER0_REG_OFFSET), 0x0);
- auto timer = MakeTimer({4, 6});
- EXPECT_EQ(dif_rv_timer_reset(&timer), kDifRvTimerOk);
+ EXPECT_EQ(dif_rv_timer_reset(&rv_timer_), kDifOk);
}
TEST_F(ResetTest, NullArgs) {
- EXPECT_EQ(dif_rv_timer_reset(nullptr), kDifRvTimerBadArg);
+ EXPECT_EQ(dif_rv_timer_reset(nullptr), kDifBadArg);
}
-class SetParamsTest : public TimerTest {};
+class SetTickParamsTest : public TimerTest {};
-TEST_F(SetParamsTest, Baseline) {
+TEST_F(SetTickParamsTest, Success) {
EXPECT_WRITE32(
- RegForHart(2, RV_TIMER_CFG0_REG_OFFSET),
+ RegForHart(0, RV_TIMER_CFG0_REG_OFFSET),
{{RV_TIMER_CFG0_PRESCALE_OFFSET, 400}, {RV_TIMER_CFG0_STEP_OFFSET, 25}});
- auto timer = MakeTimer({4, 6});
- EXPECT_EQ(dif_rv_timer_set_tick_params(&timer, 2,
+ EXPECT_EQ(dif_rv_timer_set_tick_params(&rv_timer_, 0,
{.prescale = 400, .tick_step = 25}),
- kDifRvTimerOk);
+ kDifOk);
}
-TEST_F(SetParamsTest, NullArgs) {
- EXPECT_EQ(dif_rv_timer_set_tick_params(nullptr, 2,
+TEST_F(SetTickParamsTest, NullArgs) {
+ EXPECT_EQ(dif_rv_timer_set_tick_params(nullptr, 0,
{.prescale = 400, .tick_step = 25}),
- kDifRvTimerBadArg);
+ kDifBadArg);
}
-TEST_F(SetParamsTest, BadHart) {
- auto timer = MakeTimer({4, 6});
- EXPECT_EQ(dif_rv_timer_set_tick_params(&timer, 4,
+TEST_F(SetTickParamsTest, BadHartId) {
+ EXPECT_EQ(dif_rv_timer_set_tick_params(&rv_timer_, RV_TIMER_PARAM_N_HARTS,
{.prescale = 400, .tick_step = 25}),
- kDifRvTimerBadArg);
- EXPECT_EQ(dif_rv_timer_set_tick_params(&timer, 500,
- {.prescale = 400, .tick_step = 25}),
- kDifRvTimerBadArg);
+ kDifBadArg);
}
-class TimerEnableTest : public TimerTest {};
+class CounterSetEnabledTest : public TimerTest {};
-TEST_F(TimerEnableTest, Baseline) {
+TEST_F(CounterSetEnabledTest, Success) {
EXPECT_MASK32(RV_TIMER_CTRL_REG_OFFSET,
- {{/*offset=*/1, /*mask=*/1, /*value=*/1}});
- EXPECT_MASK32(RV_TIMER_CTRL_REG_OFFSET,
- {{/*offset=*/3, /*mask=*/1, /*value=*/0}});
-
- auto timer = MakeTimer({4, 6});
- EXPECT_EQ(dif_rv_timer_counter_set_enabled(&timer, 1, kDifRvTimerEnabled),
- kDifRvTimerOk);
- EXPECT_EQ(dif_rv_timer_counter_set_enabled(&timer, 3, kDifRvTimerDisabled),
- kDifRvTimerOk);
+ {{/*offset=*/0, /*mask=*/1, /*value=*/1}});
+ EXPECT_EQ(dif_rv_timer_counter_set_enabled(&rv_timer_, 0, kDifToggleEnabled),
+ kDifOk);
}
-TEST_F(TimerEnableTest, NullArgs) {
- EXPECT_EQ(dif_rv_timer_counter_set_enabled(nullptr, 1, kDifRvTimerEnabled),
- kDifRvTimerBadArg);
+TEST_F(CounterSetEnabledTest, NullArgs) {
+ EXPECT_EQ(dif_rv_timer_counter_set_enabled(nullptr, 0, kDifToggleEnabled),
+ kDifBadArg);
}
-TEST_F(TimerEnableTest, BadHart) {
- auto timer = MakeTimer({4, 6});
- EXPECT_EQ(dif_rv_timer_counter_set_enabled(&timer, 4, kDifRvTimerEnabled),
- kDifRvTimerBadArg);
- EXPECT_EQ(dif_rv_timer_counter_set_enabled(&timer, 5, kDifRvTimerDisabled),
- kDifRvTimerBadArg);
+TEST_F(CounterSetEnabledTest, BadHartId) {
+ EXPECT_EQ(dif_rv_timer_counter_set_enabled(&rv_timer_, RV_TIMER_PARAM_N_HARTS,
+ kDifToggleEnabled),
+ kDifBadArg);
}
class CounterReadTest : public TimerTest {};
-TEST_F(CounterReadTest, Baseline) {
+TEST_F(CounterReadTest, Success) {
EXPECT_READ32(RegForHart(0, RV_TIMER_TIMER_V_UPPER0_REG_OFFSET), 0x0222'0222);
EXPECT_READ32(RegForHart(0, RV_TIMER_TIMER_V_LOWER0_REG_OFFSET), 0x0333'0333);
EXPECT_READ32(RegForHart(0, RV_TIMER_TIMER_V_UPPER0_REG_OFFSET), 0x0222'0222);
- auto timer = MakeTimer({4, 6});
uint64_t value;
- EXPECT_EQ(dif_rv_timer_counter_read(&timer, 0, &value), kDifRvTimerOk);
+ EXPECT_EQ(dif_rv_timer_counter_read(&rv_timer_, 0, &value), kDifOk);
EXPECT_EQ(value, 0x0222'0222'0333'0333);
}
TEST_F(CounterReadTest, Overflow) {
- EXPECT_READ32(RegForHart(1, RV_TIMER_TIMER_V_UPPER0_REG_OFFSET), 0x0222'0222);
- EXPECT_READ32(RegForHart(1, RV_TIMER_TIMER_V_LOWER0_REG_OFFSET), 0x0333'0333);
- EXPECT_READ32(RegForHart(1, RV_TIMER_TIMER_V_UPPER0_REG_OFFSET), 0x0222'0223);
+ EXPECT_READ32(RegForHart(0, RV_TIMER_TIMER_V_UPPER0_REG_OFFSET), 0x0222'0222);
+ EXPECT_READ32(RegForHart(0, RV_TIMER_TIMER_V_LOWER0_REG_OFFSET), 0x0333'0333);
+ EXPECT_READ32(RegForHart(0, RV_TIMER_TIMER_V_UPPER0_REG_OFFSET), 0x0222'0223);
- EXPECT_READ32(RegForHart(1, RV_TIMER_TIMER_V_UPPER0_REG_OFFSET), 0x0222'0223);
- EXPECT_READ32(RegForHart(1, RV_TIMER_TIMER_V_LOWER0_REG_OFFSET), 0x0333'0444);
- EXPECT_READ32(RegForHart(1, RV_TIMER_TIMER_V_UPPER0_REG_OFFSET), 0x0222'0223);
+ EXPECT_READ32(RegForHart(0, RV_TIMER_TIMER_V_UPPER0_REG_OFFSET), 0x0222'0223);
+ EXPECT_READ32(RegForHart(0, RV_TIMER_TIMER_V_LOWER0_REG_OFFSET), 0x0333'0444);
+ EXPECT_READ32(RegForHart(0, RV_TIMER_TIMER_V_UPPER0_REG_OFFSET), 0x0222'0223);
- auto timer = MakeTimer({4, 6});
uint64_t value;
- EXPECT_EQ(dif_rv_timer_counter_read(&timer, 1, &value), kDifRvTimerOk);
+ EXPECT_EQ(dif_rv_timer_counter_read(&rv_timer_, 0, &value), kDifOk);
EXPECT_EQ(value, 0x0222'0223'0333'0444);
}
TEST_F(CounterReadTest, NullArgs) {
- auto timer = MakeTimer({4, 6});
uint64_t value;
- EXPECT_EQ(dif_rv_timer_counter_read(nullptr, 2, &value), kDifRvTimerBadArg);
- EXPECT_EQ(dif_rv_timer_counter_read(&timer, 2, nullptr), kDifRvTimerBadArg);
+ EXPECT_EQ(dif_rv_timer_counter_read(nullptr, 0, &value), kDifBadArg);
+ EXPECT_EQ(dif_rv_timer_counter_read(&rv_timer_, 0, nullptr), kDifBadArg);
}
-TEST_F(CounterReadTest, BadHart) {
- auto timer = MakeTimer({4, 6});
+TEST_F(CounterReadTest, BadHartId) {
uint64_t value;
- EXPECT_EQ(dif_rv_timer_counter_read(&timer, 4, &value), kDifRvTimerBadArg);
- EXPECT_EQ(dif_rv_timer_counter_read(&timer, 5, &value), kDifRvTimerBadArg);
+ EXPECT_EQ(
+ dif_rv_timer_counter_read(&rv_timer_, RV_TIMER_PARAM_N_HARTS, &value),
+ kDifBadArg);
}
class CounterWriteTest : public TimerTest {};
-TEST_F(CounterWriteTest, Baseline) {
+TEST_F(CounterWriteTest, Success) {
EXPECT_READ32(RV_TIMER_CTRL_REG_OFFSET, 0x0000'0001);
EXPECT_WRITE32(RV_TIMER_CTRL_REG_OFFSET, 0x0000'0000);
EXPECT_WRITE32(RegForHart(0, RV_TIMER_TIMER_V_LOWER0_REG_OFFSET),
@@ -428,236 +259,50 @@
0xCAFE'FEED);
EXPECT_WRITE32(RV_TIMER_CTRL_REG_OFFSET, 0x0000'0001);
- auto timer = MakeTimer({1, 1});
uint64_t count = 0xCAFE'FEED'DEAD'BEEF;
- EXPECT_EQ(dif_rv_timer_counter_write(&timer, 0, count), kDifRvTimerOk);
+ EXPECT_EQ(dif_rv_timer_counter_write(&rv_timer_, 0, count), kDifOk);
}
TEST_F(CounterWriteTest, NullArgs) {
uint64_t count = 0xCAFE'FEED'DEAD'BEEF;
- EXPECT_EQ(dif_rv_timer_counter_write(nullptr, 0, count), kDifRvTimerBadArg);
+ EXPECT_EQ(dif_rv_timer_counter_write(nullptr, 0, count), kDifBadArg);
}
-TEST_F(CounterWriteTest, BadHart) {
- auto timer = MakeTimer({1, 1});
+TEST_F(CounterWriteTest, BadHartId) {
uint64_t count = 0xCAFE'FEED'DEAD'BEEF;
- EXPECT_EQ(dif_rv_timer_counter_write(&timer, 1, count), kDifRvTimerBadArg);
- EXPECT_EQ(dif_rv_timer_counter_write(&timer, 2, count), kDifRvTimerBadArg);
+ EXPECT_EQ(
+ dif_rv_timer_counter_write(&rv_timer_, RV_TIMER_PARAM_N_HARTS, count),
+ kDifBadArg);
}
class ArmTest : public TimerTest {};
-TEST_F(ArmTest, Baseline) {
- // Note: 16 = 2 * sizeof(uint64_t), since these need to be the registers
- // for the third (index 2) comparator.
- auto lower_reg = RegForHart(1, RV_TIMER_COMPARE_LOWER0_0_REG_OFFSET) + 16;
- auto upper_reg = RegForHart(1, RV_TIMER_COMPARE_UPPER0_0_REG_OFFSET) + 16;
+TEST_F(ArmTest, Success) {
+ auto lower_reg = RegForHart(0, RV_TIMER_COMPARE_LOWER0_0_REG_OFFSET);
+ auto upper_reg = RegForHart(0, RV_TIMER_COMPARE_UPPER0_0_REG_OFFSET);
EXPECT_WRITE32(upper_reg, kAllOnes);
EXPECT_WRITE32(lower_reg, 0x0444'0555);
EXPECT_WRITE32(upper_reg, 0x0222'0333);
- auto timer = MakeTimer({4, 6});
- EXPECT_EQ(dif_rv_timer_arm(&timer, 1, 2, 0x0222'0333'0444'0555),
- kDifRvTimerOk);
+ EXPECT_EQ(dif_rv_timer_arm(&rv_timer_, 0, 0, 0x0222'0333'0444'0555), kDifOk);
}
TEST_F(ArmTest, NullArgs) {
- EXPECT_EQ(dif_rv_timer_arm(nullptr, 1, 2, 0x0222'0333'0444'0555),
- kDifRvTimerBadArg);
+ EXPECT_EQ(dif_rv_timer_arm(nullptr, 0, 0, 0x0222'0333'0444'0555), kDifBadArg);
}
-TEST_F(ArmTest, BadHartBadComp) {
- auto timer = MakeTimer({4, 6});
- EXPECT_EQ(dif_rv_timer_arm(&timer, 4, 2, 0x0222'0333'0444'0555),
- kDifRvTimerBadArg);
- EXPECT_EQ(dif_rv_timer_arm(&timer, 5, 2, 0x0222'0333'0444'0555),
- kDifRvTimerBadArg);
- EXPECT_EQ(dif_rv_timer_arm(&timer, 1, 6, 0x0222'0333'0444'0555),
- kDifRvTimerBadArg);
- EXPECT_EQ(dif_rv_timer_arm(&timer, 1, 7, 0x0222'0333'0444'0555),
- kDifRvTimerBadArg);
+TEST_F(ArmTest, BadHartIdBadCompId) {
+ EXPECT_EQ(dif_rv_timer_arm(&rv_timer_, RV_TIMER_PARAM_N_HARTS, 0,
+ 0x0222'0333'0444'0555),
+ kDifBadArg);
+ EXPECT_EQ(dif_rv_timer_arm(&rv_timer_, 0, RV_TIMER_PARAM_N_TIMERS,
+ 0x0222'0333'0444'0555),
+ kDifBadArg);
+ EXPECT_EQ(dif_rv_timer_arm(&rv_timer_, RV_TIMER_PARAM_N_HARTS,
+ RV_TIMER_PARAM_N_TIMERS, 0x0222'0333'0444'0555),
+ kDifBadArg);
}
-class IrqEnableTest : public TimerTest {};
-
-TEST_F(IrqEnableTest, Baseline) {
- EXPECT_MASK32(IrqRegForHart(1, 6, RV_TIMER_INTR_ENABLE0_REG_OFFSET),
- {{/*offset=*/2, /*mask=*/1, /*value=*/1}});
- EXPECT_MASK32(IrqRegForHart(3, 6, RV_TIMER_INTR_ENABLE0_REG_OFFSET),
- {{/*offset=*/4, /*mask=*/1, /*value=*/0}});
-
- auto timer = MakeTimer({4, 6});
- EXPECT_EQ(dif_rv_timer_irq_enable(&timer, 1, 2, kDifRvTimerEnabled),
- kDifRvTimerOk);
- EXPECT_EQ(dif_rv_timer_irq_enable(&timer, 3, 4, kDifRvTimerDisabled),
- kDifRvTimerOk);
-}
-
-TEST_F(IrqEnableTest, NullArgs) {
- EXPECT_EQ(dif_rv_timer_irq_enable(nullptr, 1, 2, kDifRvTimerEnabled),
- kDifRvTimerBadArg);
-}
-
-TEST_F(IrqEnableTest, BadHartBadComp) {
- auto timer = MakeTimer({4, 6});
- EXPECT_EQ(dif_rv_timer_irq_enable(&timer, 4, 2, kDifRvTimerEnabled),
- kDifRvTimerBadArg);
- EXPECT_EQ(dif_rv_timer_irq_enable(&timer, 5, 4, kDifRvTimerDisabled),
- kDifRvTimerBadArg);
- EXPECT_EQ(dif_rv_timer_irq_enable(&timer, 1, 6, kDifRvTimerEnabled),
- kDifRvTimerBadArg);
- EXPECT_EQ(dif_rv_timer_irq_enable(&timer, 3, 7, kDifRvTimerDisabled),
- kDifRvTimerBadArg);
-}
-
-class IrqGetTest : public TimerTest {};
-
-TEST_F(IrqGetTest, Baseline) {
- EXPECT_READ32(IrqRegForHart(1, 6, RV_TIMER_INTR_STATE0_REG_OFFSET),
- {
- {/*offset=*/0, /*value=*/1},
- {/*offset=*/2, /*value=*/1},
- {/*offset=*/5, /*value=*/1},
- });
- EXPECT_READ32(IrqRegForHart(3, 6, RV_TIMER_INTR_STATE0_REG_OFFSET),
- {
- {/*offset=*/0, /*value=*/1},
- {/*offset=*/2, /*value=*/1},
- {/*offset=*/5, /*value=*/1},
- });
-
- auto timer = MakeTimer({4, 6});
- bool flag;
- EXPECT_EQ(dif_rv_timer_irq_get(&timer, 1, 2, &flag), kDifRvTimerOk);
- EXPECT_TRUE(flag);
- EXPECT_EQ(dif_rv_timer_irq_get(&timer, 3, 4, &flag), kDifRvTimerOk);
- EXPECT_FALSE(flag);
-}
-
-TEST_F(IrqGetTest, NullArgs) {
- auto timer = MakeTimer({4, 6});
- bool flag;
- EXPECT_EQ(dif_rv_timer_irq_get(nullptr, 1, 2, &flag), kDifRvTimerBadArg);
- EXPECT_EQ(dif_rv_timer_irq_get(&timer, 3, 4, nullptr), kDifRvTimerBadArg);
-}
-
-TEST_F(IrqGetTest, BadHartBadComp) {
- auto timer = MakeTimer({4, 6});
- bool flag;
- EXPECT_EQ(dif_rv_timer_irq_get(&timer, 4, 2, &flag), kDifRvTimerBadArg);
- EXPECT_EQ(dif_rv_timer_irq_get(&timer, 5, 4, &flag), kDifRvTimerBadArg);
- EXPECT_EQ(dif_rv_timer_irq_get(&timer, 1, 6, &flag), kDifRvTimerBadArg);
- EXPECT_EQ(dif_rv_timer_irq_get(&timer, 3, 7, &flag), kDifRvTimerBadArg);
-}
-
-class IrqClearTest : public TimerTest {};
-
-TEST_F(IrqClearTest, Baseline) {
- EXPECT_WRITE32(IrqRegForHart(1, 6, RV_TIMER_INTR_STATE0_REG_OFFSET),
- {
- {/*offset=*/2, /*value=*/1},
- });
- EXPECT_WRITE32(IrqRegForHart(3, 6, RV_TIMER_INTR_STATE0_REG_OFFSET),
- {
- {/*offset=*/4, /*value=*/1},
- });
-
- auto timer = MakeTimer({4, 6});
- EXPECT_EQ(dif_rv_timer_irq_clear(&timer, 1, 2), kDifRvTimerOk);
- EXPECT_EQ(dif_rv_timer_irq_clear(&timer, 3, 4), kDifRvTimerOk);
-}
-
-TEST_F(IrqClearTest, NullArgs) {
- EXPECT_EQ(dif_rv_timer_irq_clear(nullptr, 1, 2), kDifRvTimerBadArg);
-}
-
-TEST_F(IrqClearTest, BadHartBadComp) {
- auto timer = MakeTimer({4, 6});
- EXPECT_EQ(dif_rv_timer_irq_clear(&timer, 4, 2), kDifRvTimerBadArg);
- EXPECT_EQ(dif_rv_timer_irq_clear(&timer, 5, 4), kDifRvTimerBadArg);
- EXPECT_EQ(dif_rv_timer_irq_clear(&timer, 1, 6), kDifRvTimerBadArg);
- EXPECT_EQ(dif_rv_timer_irq_clear(&timer, 3, 7), kDifRvTimerBadArg);
-}
-
-class IrqDisableTest : public TimerTest {};
-
-TEST_F(IrqDisableTest, Baseline) {
- EXPECT_READ32(IrqRegForHart(1, 6, RV_TIMER_INTR_ENABLE0_REG_OFFSET),
- 0b101010);
- EXPECT_WRITE32(IrqRegForHart(1, 6, RV_TIMER_INTR_ENABLE0_REG_OFFSET), 0);
-
- EXPECT_WRITE32(IrqRegForHart(3, 6, RV_TIMER_INTR_ENABLE0_REG_OFFSET), 0);
-
- auto timer = MakeTimer({4, 6});
- uint32_t state;
- EXPECT_EQ(dif_rv_timer_irq_disable(&timer, 1, &state), kDifRvTimerOk);
- EXPECT_EQ(state, 0b101010);
- EXPECT_EQ(dif_rv_timer_irq_disable(&timer, 3, nullptr), kDifRvTimerOk);
-}
-
-TEST_F(IrqDisableTest, NullArgs) {
- uint32_t state;
- EXPECT_EQ(dif_rv_timer_irq_disable(nullptr, 1, &state), kDifRvTimerBadArg);
-}
-
-TEST_F(IrqDisableTest, BadHart) {
- auto timer = MakeTimer({4, 6});
- uint32_t state;
- EXPECT_EQ(dif_rv_timer_irq_disable(&timer, 4, &state), kDifRvTimerBadArg);
- EXPECT_EQ(dif_rv_timer_irq_disable(&timer, 5, &state), kDifRvTimerBadArg);
-}
-
-class IrqRestoreTest : public TimerTest {};
-
-TEST_F(IrqRestoreTest, Baseline) {
- EXPECT_WRITE32(IrqRegForHart(1, 6, RV_TIMER_INTR_ENABLE0_REG_OFFSET),
- 0b101010);
- EXPECT_WRITE32(IrqRegForHart(3, 6, RV_TIMER_INTR_ENABLE0_REG_OFFSET),
- 0b011011);
-
- auto timer = MakeTimer({4, 6});
- EXPECT_EQ(dif_rv_timer_irq_restore(&timer, 1, 0b101010), kDifRvTimerOk);
- EXPECT_EQ(dif_rv_timer_irq_restore(&timer, 3, 0b011011), kDifRvTimerOk);
-}
-
-TEST_F(IrqRestoreTest, NullArgs) {
- EXPECT_EQ(dif_rv_timer_irq_restore(nullptr, 1, 0), kDifRvTimerBadArg);
-}
-
-TEST_F(IrqRestoreTest, BadHart) {
- auto timer = MakeTimer({4, 6});
- EXPECT_EQ(dif_rv_timer_irq_restore(&timer, 4, 0), kDifRvTimerBadArg);
- EXPECT_EQ(dif_rv_timer_irq_restore(&timer, 5, 0), kDifRvTimerBadArg);
-}
-
-class IrqForceTest : public TimerTest {};
-
-TEST_F(IrqForceTest, Baseline) {
- EXPECT_WRITE32(IrqRegForHart(1, 6, RV_TIMER_INTR_TEST0_REG_OFFSET),
- {
- {/*offset=*/2, /*value=*/1},
- });
- EXPECT_WRITE32(IrqRegForHart(3, 6, RV_TIMER_INTR_TEST0_REG_OFFSET),
- {
- {/*offset=*/4, /*value=*/1},
- });
-
- auto timer = MakeTimer({4, 6});
- EXPECT_EQ(dif_rv_timer_irq_force(&timer, 1, 2), kDifRvTimerOk);
- EXPECT_EQ(dif_rv_timer_irq_force(&timer, 3, 4), kDifRvTimerOk);
-}
-
-TEST_F(IrqForceTest, NullArgs) {
- EXPECT_EQ(dif_rv_timer_irq_force(nullptr, 1, 2), kDifRvTimerBadArg);
-}
-
-TEST_F(IrqForceTest, BadHartBadComp) {
- auto timer = MakeTimer({4, 6});
- EXPECT_EQ(dif_rv_timer_irq_force(&timer, 4, 2), kDifRvTimerBadArg);
- EXPECT_EQ(dif_rv_timer_irq_force(&timer, 5, 4), kDifRvTimerBadArg);
- EXPECT_EQ(dif_rv_timer_irq_force(&timer, 1, 6), kDifRvTimerBadArg);
- EXPECT_EQ(dif_rv_timer_irq_force(&timer, 3, 7), kDifRvTimerBadArg);
-}
} // namespace
} // namespace dif_rv_timer_unittest
diff --git a/sw/device/lib/dif/meson.build b/sw/device/lib/dif/meson.build
index 610bc57..0f87c07 100644
--- a/sw/device/lib/dif/meson.build
+++ b/sw/device/lib/dif/meson.build
@@ -257,7 +257,8 @@
'dif_rv_timer.c',
],
dependencies: [
- sw_lib_mmio
+ sw_lib_mmio,
+ sw_lib_dif_autogen_rv_timer,
],
)
)
@@ -265,9 +266,11 @@
test('dif_rv_timer_unittest', executable(
'dif_rv_timer_unittest',
sources: [
- hw_ip_rv_timer_reg_h,
- meson.source_root() / 'sw/device/lib/dif/dif_rv_timer.c',
'dif_rv_timer_unittest.cc',
+ 'autogen/dif_rv_timer_autogen_unittest.cc',
+ meson.source_root() / 'sw/device/lib/dif/dif_rv_timer.c',
+ meson.source_root() / 'sw/device/lib/dif/autogen/dif_rv_timer_autogen.c',
+ hw_ip_rv_timer_reg_h,
],
dependencies: [
sw_vendor_gtest,
diff --git a/sw/device/lib/testing/test_framework/example_earlgrey_test.c b/sw/device/lib/testing/test_framework/example_earlgrey_test.c
index ff9d978..4328aa5 100644
--- a/sw/device/lib/testing/test_framework/example_earlgrey_test.c
+++ b/sw/device/lib/testing/test_framework/example_earlgrey_test.c
@@ -17,22 +17,19 @@
.test_name = "ExampleTest",
};
+static dif_rv_timer_t timer;
+
// This example test just queries the RV Timer count and logs it over UART.
// Currently, this test runs forever, but once test teardown logic has been
// implemented this example will be updated.
void test_main(void *result) {
- mmio_region_t timer_reg =
- mmio_region_from_addr(TOP_EARLGREY_RV_TIMER_BASE_ADDR);
- dif_rv_timer_t timer = {
- .base_addr = timer_reg,
- {.hart_count = 1, .comparator_count = 1},
- };
+ CHECK_DIF_OK(dif_rv_timer_init(
+ mmio_region_from_addr(TOP_EARLGREY_RV_TIMER_BASE_ADDR), &timer));
uint64_t current_time;
const uint32_t kHart = (uint32_t)kTopEarlgreyPlicTargetIbex0;
while (true) {
- CHECK(dif_rv_timer_counter_read(&timer, kHart, ¤t_time) ==
- kDifRvTimerOk);
+ CHECK_DIF_OK(dif_rv_timer_counter_read(&timer, kHart, ¤t_time));
LOG_INFO("(FreeRTOS Task) Current Time: %u", (uint32_t)current_time);
}
diff --git a/sw/device/lib/testing/test_framework/freertos_port.c b/sw/device/lib/testing/test_framework/freertos_port.c
index c30d346..e6270be 100644
--- a/sw/device/lib/testing/test_framework/freertos_port.c
+++ b/sw/device/lib/testing/test_framework/freertos_port.c
@@ -33,13 +33,15 @@
// Override the timer ISR to support preemptive context switching.
void ottf_timer_isr(void) {
LOG_INFO("Handling timer IQR ...");
- CHECK(dif_rv_timer_irq_disable(&timer, kTimerHartId, NULL) == kDifRvTimerOk);
- CHECK(dif_rv_timer_counter_write(&timer, kTimerHartId, 0) == kDifRvTimerOk);
- CHECK(dif_rv_timer_irq_clear(&timer, kTimerHartId, kTimerComparatorId) ==
- kDifRvTimerOk);
+ dif_rv_timer_irq_enable_snapshot_t irq_enable_snapshot;
+ CHECK_DIF_OK(
+ dif_rv_timer_irq_disable_all(&timer, kTimerHartId, &irq_enable_snapshot));
+ CHECK_DIF_OK(dif_rv_timer_counter_write(&timer, kTimerHartId, 0));
+ CHECK_DIF_OK(dif_rv_timer_irq_acknowledge(
+ &timer, kDifRvTimerIrqTimerExpiredHart0Timer0));
// TODO: increment scheduler tick and switch context if necessary
- CHECK(dif_rv_timer_irq_enable(&timer, kTimerHartId, kTimerComparatorId,
- kDifRvTimerEnabled) == kDifRvTimerOk);
+ CHECK_DIF_OK(
+ dif_rv_timer_irq_restore_all(&timer, kTimerHartId, &irq_enable_snapshot));
LOG_INFO("Done.");
}
@@ -47,32 +49,27 @@
LOG_INFO("Configuring timer interrupt ...");
// Initialize and reset the timer.
- mmio_region_t timer_reg =
- mmio_region_from_addr(TOP_EARLGREY_RV_TIMER_BASE_ADDR);
- CHECK(dif_rv_timer_init(
- timer_reg,
- (dif_rv_timer_config_t){.hart_count = 1, .comparator_count = 1},
- &timer) == kDifRvTimerOk);
+ CHECK_DIF_OK(dif_rv_timer_init(
+ mmio_region_from_addr(TOP_EARLGREY_RV_TIMER_BASE_ADDR), &timer));
// Compute and set tick parameters (i.e., step, prescale, etc.).
dif_rv_timer_tick_params_t tick_params;
- CHECK(dif_rv_timer_approximate_tick_params(
- kClockFreqPeripheralHz, configTICK_RATE_HZ * kTimerDeadline,
- &tick_params) == kDifRvTimerApproximateTickParamsOk);
+ CHECK_DIF_OK(dif_rv_timer_approximate_tick_params(
+ kClockFreqPeripheralHz, configTICK_RATE_HZ * kTimerDeadline,
+ &tick_params));
LOG_INFO("Tick Freq. (Hz): %u, Prescale: %u; Tick Step: %u",
(uint32_t)kClockFreqPeripheralHz, (uint32_t)tick_params.prescale,
(uint32_t)tick_params.tick_step);
- CHECK(dif_rv_timer_set_tick_params(&timer, kTimerHartId, tick_params) ==
- kDifRvTimerOk);
+ CHECK_DIF_OK(dif_rv_timer_set_tick_params(&timer, kTimerHartId, tick_params));
// Enable RV Timer interrupts and arm/enable the timer.
- CHECK(dif_rv_timer_irq_enable(&timer, kTimerHartId, kTimerComparatorId,
- kDifRvTimerEnabled) == kDifRvTimerOk);
- CHECK(dif_rv_timer_arm(&timer, kTimerHartId, kTimerComparatorId,
- kTimerDeadline) == kDifRvTimerOk);
+ CHECK_DIF_OK(dif_rv_timer_irq_set_enabled(
+ &timer, kDifRvTimerIrqTimerExpiredHart0Timer0, kDifToggleEnabled));
+ CHECK_DIF_OK(dif_rv_timer_arm(&timer, kTimerHartId, kTimerComparatorId,
+ kTimerDeadline));
- CHECK(dif_rv_timer_counter_set_enabled(&timer, kTimerHartId,
- kDifRvTimerEnabled) == kDifRvTimerOk);
+ CHECK_DIF_OK(dif_rv_timer_counter_set_enabled(&timer, kTimerHartId,
+ kDifToggleEnabled));
}
#endif // configUSE_PREEMPTION
diff --git a/sw/device/sca/lib/sca.c b/sw/device/sca/lib/sca.c
index 592e095..770b830 100644
--- a/sw/device/sca/lib/sca.c
+++ b/sw/device/sca/lib/sca.c
@@ -109,15 +109,14 @@
*/
static void sca_init_timer(void) {
IGNORE_RESULT(dif_rv_timer_init(
- mmio_region_from_addr(TOP_EARLGREY_RV_TIMER_BASE_ADDR),
- (dif_rv_timer_config_t){.hart_count = 1, .comparator_count = 1}, &timer));
+ mmio_region_from_addr(TOP_EARLGREY_RV_TIMER_BASE_ADDR), &timer));
dif_rv_timer_tick_params_t tick_params;
IGNORE_RESULT(dif_rv_timer_approximate_tick_params(
kClockFreqPeripheralHz, kClockFreqCpuHz, &tick_params));
IGNORE_RESULT(
dif_rv_timer_set_tick_params(&timer, kRvTimerHart, tick_params));
- IGNORE_RESULT(dif_rv_timer_irq_enable(
- &timer, kRvTimerHart, kRvTimerComparator, kDifRvTimerEnabled));
+ IGNORE_RESULT(dif_rv_timer_irq_set_enabled(
+ &timer, kDifRvTimerIrqTimerExpiredHart0Timer0, kDifToggleEnabled));
irq_timer_ctrl(true);
irq_global_ctrl(true);
}
@@ -131,9 +130,9 @@
// Return values of below functions are ignored to improve capture
// performance.
IGNORE_RESULT(dif_rv_timer_counter_set_enabled(&timer, kRvTimerHart,
- kDifRvTimerDisabled));
- IGNORE_RESULT(
- dif_rv_timer_irq_clear(&timer, kRvTimerHart, kRvTimerComparator));
+ kDifToggleDisabled));
+ IGNORE_RESULT(dif_rv_timer_irq_acknowledge(
+ &timer, kDifRvTimerIrqTimerExpiredHart0Timer0));
}
/**
@@ -224,7 +223,7 @@
IGNORE_RESULT(dif_rv_timer_arm(&timer, kRvTimerHart, kRvTimerComparator,
current_time + sleep_cycles));
IGNORE_RESULT(dif_rv_timer_counter_set_enabled(&timer, kRvTimerHart,
- kDifRvTimerEnabled));
+ kDifToggleEnabled));
callee();
diff --git a/sw/device/tests/rv_timer_smoketest.c b/sw/device/tests/rv_timer_smoketest.c
index b79fe34..9957004 100644
--- a/sw/device/tests/rv_timer_smoketest.c
+++ b/sw/device/tests/rv_timer_smoketest.c
@@ -33,13 +33,14 @@
CHECK(!irq_fired, "Entered IRQ handler, but `irq_fired` was not false!");
bool irq_flag;
- CHECK(dif_rv_timer_irq_get(&timer, kHart, kComparator, &irq_flag) ==
- kDifRvTimerOk);
+ CHECK_DIF_OK(dif_rv_timer_irq_is_pending(
+ &timer, kDifRvTimerIrqTimerExpiredHart0Timer0, &irq_flag));
CHECK(irq_flag, "Entered IRQ handler but the expected IRQ flag wasn't set!");
- CHECK(dif_rv_timer_counter_set_enabled(&timer, kHart, kDifRvTimerDisabled) ==
- kDifRvTimerOk);
- CHECK(dif_rv_timer_irq_clear(&timer, kHart, kComparator) == kDifRvTimerOk);
+ CHECK_DIF_OK(
+ dif_rv_timer_counter_set_enabled(&timer, kHart, kDifToggleDisabled));
+ CHECK_DIF_OK(dif_rv_timer_irq_acknowledge(
+ &timer, kDifRvTimerIrqTimerExpiredHart0Timer0));
irq_fired = true;
}
@@ -57,21 +58,15 @@
irq_global_ctrl(true);
irq_timer_ctrl(true);
- mmio_region_t timer_reg =
- mmio_region_from_addr(TOP_EARLGREY_RV_TIMER_BASE_ADDR);
- CHECK(dif_rv_timer_init(
- timer_reg,
- (dif_rv_timer_config_t){.hart_count = 1, .comparator_count = 1},
- &timer) == kDifRvTimerOk);
+ CHECK_DIF_OK(dif_rv_timer_init(
+ mmio_region_from_addr(TOP_EARLGREY_RV_TIMER_BASE_ADDR), &timer));
dif_rv_timer_tick_params_t tick_params;
- CHECK(dif_rv_timer_approximate_tick_params(kClockFreqPeripheralHz,
- kTickFreqHz, &tick_params) ==
- kDifRvTimerApproximateTickParamsOk);
- CHECK(dif_rv_timer_set_tick_params(&timer, kHart, tick_params) ==
- kDifRvTimerOk);
- CHECK(dif_rv_timer_irq_enable(&timer, kHart, kComparator,
- kDifRvTimerEnabled) == kDifRvTimerOk);
+ CHECK_DIF_OK(dif_rv_timer_approximate_tick_params(kClockFreqPeripheralHz,
+ kTickFreqHz, &tick_params));
+ CHECK_DIF_OK(dif_rv_timer_set_tick_params(&timer, kHart, tick_params));
+ CHECK_DIF_OK(dif_rv_timer_irq_set_enabled(
+ &timer, kDifRvTimerIrqTimerExpiredHart0Timer0, kDifToggleEnabled));
uint64_t current_time;
// Logs over UART incur a large runtime overhead. To accommodate that, the
@@ -80,16 +75,15 @@
// deadline (30 ms vs 100 us).
uint64_t kDeadline =
(kDeviceType == kDeviceSimDV) ? 100 /* 100 us */ : 30000 /* 30 ms */;
- CHECK(dif_rv_timer_counter_read(&timer, kHart, ¤t_time) ==
- kDifRvTimerOk);
+ CHECK_DIF_OK(dif_rv_timer_counter_read(&timer, kHart, ¤t_time));
LOG_INFO("Current time: %d; timer theshold: %d", (uint32_t)current_time,
(uint32_t)(current_time + kDeadline));
- CHECK(dif_rv_timer_arm(&timer, kHart, kComparator,
- current_time + kDeadline) == kDifRvTimerOk);
+ CHECK_DIF_OK(
+ dif_rv_timer_arm(&timer, kHart, kComparator, current_time + kDeadline));
irq_fired = false;
- CHECK(dif_rv_timer_counter_set_enabled(&timer, kHart, kDifRvTimerEnabled) ==
- kDifRvTimerOk);
+ CHECK_DIF_OK(
+ dif_rv_timer_counter_set_enabled(&timer, kHart, kDifToggleEnabled));
LOG_INFO("Waiting...");
while (!irq_fired) {
