commit 1b4293480568f9bb6ac97836fff952f1e6c63fba
author Cindy Chen <chencindy@opentitan.org> Wed Jun 01 13:44:54 2022 -0700
committer weicaiyang <49293026+weicaiyang@users.noreply.github.com> Wed Jun 01 17:23:07 2022 -0700
tree 0980f18e97bd251b0ef83ea8f6c8897ca22b50e8
parent 6c32a3aa08440e994de820681cfc1e2ca6f0fbb0

[dv/pattgen] Remove memory testplan entry

This PR removes testplan entries regarding memory. Pattgen does not
contain any memory so this test is not needed.

Signed-off-by: Cindy Chen <chencindy@opentitan.org>

hw/ip/pattgen/dv/pattgen_sim_cfg.hjson

diff --git a/hw/ip/pattgen/dv/pattgen_sim_cfg.hjson b/hw/ip/pattgen/dv/pattgen_sim_cfg.hjson
index 0ccdc9e..d62cb99 100644
--- a/hw/ip/pattgen/dv/pattgen_sim_cfg.hjson
+++ b/hw/ip/pattgen/dv/pattgen_sim_cfg.hjson
@@ -29,7 +29,6 @@
                 "{proj_root}/hw/dv/tools/dvsim/common_sim_cfg.hjson",
                 // Common CIP test lists
                 "{proj_root}/hw/dv/tools/dvsim/tests/csr_tests.hjson",
-                "{proj_root}/hw/dv/tools/dvsim/tests/mem_tests.hjson",
                 "{proj_root}/hw/dv/tools/dvsim/tests/alert_test.hjson",
                 "{proj_root}/hw/dv/tools/dvsim/tests/intr_test.hjson",
                 "{proj_root}/hw/dv/tools/dvsim/tests/stress_tests.hjson",