[top_earlgrey] BRAM implementation FPGA check for ROM memory
modified: hw/top_earlgrey/top_earlgrey_nexysvideo.core
modified: hw/top_earlgrey/util/vivado_setup_hooks.tcl
modified: hw/top_earlgrey/data/placement.xdc
new file: hw/top_earlgrey/util/vivado_hook_opt_design_post.tcl
diff --git a/hw/top_earlgrey/data/placement.xdc b/hw/top_earlgrey/data/placement.xdc
index ca97e59..8df2ed5 100644
--- a/hw/top_earlgrey/data/placement.xdc
+++ b/hw/top_earlgrey/data/placement.xdc
@@ -1,2 +1,5 @@
+# Any change in ROM instances path should be updated in following two files
+# 1. hw/top_earlgrey/data/placement.xdc and
+# 2. hw/top_earlgrey/util/vivado_hook_opt_design_post.tcl
set_property LOC RAMB36_X4Y18 [get_cells -hierarchical -filter { NAME =~ "*rom_rom*dout_o_reg_0" && PRIMITIVE_TYPE =~ BMEM.*.* }]
set_property LOC RAMB36_X4Y19 [get_cells -hierarchical -filter { NAME =~ "*rom_rom*dout_o_reg_1" && PRIMITIVE_TYPE =~ BMEM.*.* }]
diff --git a/hw/top_earlgrey/top_earlgrey_nexysvideo.core b/hw/top_earlgrey/top_earlgrey_nexysvideo.core
index 2c6eb6c..370d067 100644
--- a/hw/top_earlgrey/top_earlgrey_nexysvideo.core
+++ b/hw/top_earlgrey/top_earlgrey_nexysvideo.core
@@ -25,6 +25,7 @@
# File copied by fusesoc into the workroot (the file containing the
# .eda.yml file), and referenced from vivado_setup_hooks.tcl
- util/vivado_hook_write_bitstream_pre.tcl: { file_type: data, copyto: vivado_hook_write_bitstream_pre.tcl }
+ - util/vivado_hook_opt_design_post.tcl: { file_type: data, copyto: vivado_hook_opt_design_post.tcl }
parameters:
# XXX: This parameter needs to be absolute, or relative to the *.runs/synth_1
diff --git a/hw/top_earlgrey/util/vivado_hook_opt_design_post.tcl b/hw/top_earlgrey/util/vivado_hook_opt_design_post.tcl
new file mode 100644
index 0000000..22312a8
--- /dev/null
+++ b/hw/top_earlgrey/util/vivado_hook_opt_design_post.tcl
@@ -0,0 +1,16 @@
+# Copyright lowRISC contributors.
+# Licensed under the Apache License, Version 2.0, see LICENSE for details.
+# SPDX-License-Identifier: Apache-2.0
+
+# Any change in ROM instances path should be updated in following two files
+# 1. hw/top_earlgrey/data/placement.xdc and
+# 2. hw/top_earlgrey/util/vivado_hook_opt_design_post.tcl
+
+send_msg "Designcheck 1-1" INFO "Checking if ROM memory is mapped to BRAM memory."
+
+if {[catch [get_cells -hierarchical -filter { NAME =~ "*rom_rom*dout_o_reg_0" && PRIMITIVE_TYPE =~ BMEM.*.* }]]\
+ && [catch [get_cells -hierarchical -filter { NAME =~ "*rom_rom*dout_o_reg_1" && PRIMITIVE_TYPE =~ BMEM.*.* }]] } {
+ send_msg "Designcheck 1-3" INFO "BRAM implementation found for ROM memory."
+} else {
+ send_msg "Designcheck 1-2" ERROR "BRAM implementation not found for ROM memory."
+}
diff --git a/hw/top_earlgrey/util/vivado_setup_hooks.tcl b/hw/top_earlgrey/util/vivado_setup_hooks.tcl
index 15de18d..9ef9e5f 100644
--- a/hw/top_earlgrey/util/vivado_setup_hooks.tcl
+++ b/hw/top_earlgrey/util/vivado_setup_hooks.tcl
@@ -8,6 +8,9 @@
# fusesoc-generated workroot containing the Vivado project file
set workroot [pwd]
+# Hook to check BRAM implementation for ROM memory
+set_property STEPS.OPT_DESIGN.TCL.POST "${workroot}/vivado_hook_opt_design_post.tcl" [get_runs impl_1]
+
# TODO: This hook is not getting called by Vivado when running through our
# fusesoc flow (it gets called when writing a bitstream through the GUI).
# Requires an update to edalize, see https://github.com/olofk/edalize/pull/60.
