[xbar/dv] Update chip-level xbar to drive from each IP ports
1. detail discussion at #2464
2. re-enable chip xbar tests (tmp disabled at #3040)
3. exceptionis (non-comportable instance/port name) are handled in
termodule.py:find_otherside_module
1. all mem IPs (rom, ram_main, eflash, ram_ret), which can be removed
when we make memory as comportable IP
2. corei, cored, debug_mem, dm_sba: need more discussion
Signed-off-by: Weicai Yang <weicai@google.com>
diff --git a/util/topgen/intermodule.py b/util/topgen/intermodule.py
index 1a7cb4f..cb4116f 100644
--- a/util/topgen/intermodule.py
+++ b/util/topgen/intermodule.py
@@ -6,7 +6,7 @@
import re
from collections import OrderedDict
from enum import Enum
-from typing import Dict, Tuple, List
+from typing import Dict, List, Tuple
from reggen.validate import check_int
from topgen import lib
@@ -525,6 +525,22 @@
s) -> List[Tuple[str, str, str]]:
"""Find far-end port based on given module and signal name
"""
+ # TODO: handle special cases
+ special_inst_names = {
+ ('main', 'tl_rom'): ('tl_adapter_rom', 'tl'),
+ ('main', 'tl_ram_main'): ('tl_adapter_ram_main', 'tl'),
+ ('main', 'tl_eflash'): ('tl_adapter_eflash', 'tl'),
+ ('peri', 'tl_ram_ret'): ('tl_adapter_ram_ret', 'tl'),
+ ('main', 'tl_corei'): ('rv_core_ibex', 'tl_i'),
+ ('main', 'tl_cored'): ('rv_core_ibex', 'tl_d'),
+ ('main', 'tl_dm_sba'): ('dm_top', 'tl_h'),
+ ('main', 'tl_debug_mem'): ('dm_top', 'tl_d')
+ }
+ for pair in special_inst_names:
+ if pair == (m, s):
+ result = special_inst_names.get(pair)
+ return [('top', result[0], result[1])]
+
signame = "{}.{}".format(m, s)
for req, rsps in topcfg["inter_module"]["connect"].items():
if req.startswith(signame):
@@ -540,24 +556,6 @@
req_m, req_s, req_i = filter_index(req)
return [('connect', req_m, req_s)]
- # If reaches here, no matching results in 'connect'
- # so search 'top' or 'external'
-
- # todo: something here
- # check special cases
- pairs = {
- ('main', 'tl_corei'): ('rv_core_ibex', 'tl_i'),
- ('main', 'tl_cored'): ('rv_core_ibex', 'tl_d'),
- ('main', 'tl_dm_sba'): ('dm_top', 'tl_h'),
- ('main', 'tl_debug_mem'): ('dm_top', 'tl_d')
- }
- for sig in topcfg["inter_signal"]["signals"]:
- pairs[(sig['inst_name'], sig['name'])] = ('', sig['top_signame'])
-
- pair = pairs.get((m, s))
- if pair is not None:
- return [('top', pair[0], pair[1])]
-
# if reaches here, it means either the format is wrong, or floating port.
log.error("`find_otherside_modules()`: "
"No such signal {}.{} exists.".format(m, s))
diff --git a/util/topgen/lib.py b/util/topgen/lib.py
index ea3fdf5..c887595 100644
--- a/util/topgen/lib.py
+++ b/util/topgen/lib.py
@@ -3,16 +3,18 @@
# SPDX-License-Identifier: Apache-2.0
import logging as log
+import re
+import sys
+from collections import OrderedDict
from copy import deepcopy
from pathlib import Path
-from collections import OrderedDict
-import hjson
-import sys
-import re
+import hjson
# Ignore flake8 warning as the function is used in the template
-from .intermodule import im_defname, im_netname, im_portname # noqa : F401
+# disable isort formating, as conflicting with flake8
+from .intermodule import find_otherside_modules # noqa : F401 # isort:skip
+from .intermodule import im_portname, im_defname, im_netname # noqa : F401 # isort:skip
def is_ipcfg(ip: Path) -> bool: # return bool
