[tlul] Add instruction type to tlul

Signed-off-by: Timothy Chen <timothytim@google.com>

[all] Minor updates to extra tlul_sram_adapter port

Signed-off-by: Timothy Chen <timothytim@google.com>
diff --git a/hw/ip/flash_ctrl/data/flash_ctrl.sv.tpl b/hw/ip/flash_ctrl/data/flash_ctrl.sv.tpl
index fdf48de..27d4f21 100644
--- a/hw/ip/flash_ctrl/data/flash_ctrl.sv.tpl
+++ b/hw/ip/flash_ctrl/data/flash_ctrl.sv.tpl
@@ -429,17 +429,18 @@
   ) u_to_prog_fifo (
     .clk_i,
     .rst_ni,
-    .tl_i       (tl_win_h2d[0]),
-    .tl_o       (tl_win_d2h[0]),
-    .req_o      (sw_wvalid),
-    .gnt_i      (sw_wready),
-    .we_o       (sw_wen),
-    .addr_o     (),
-    .wmask_o    (),
-    .wdata_o    (sw_wdata),
-    .rdata_i    (BusWidth'(0)),
-    .rvalid_i   (1'b0),
-    .rerror_i   (2'b0)
+    .tl_i        (tl_win_h2d[0]),
+    .tl_o        (tl_win_d2h[0]),
+    .en_ifetch_i (tlul_pkg::InstrDis),
+    .req_o       (sw_wvalid),
+    .gnt_i       (sw_wready),
+    .we_o        (sw_wen),
+    .addr_o      (),
+    .wmask_o     (),
+    .wdata_o     (sw_wdata),
+    .rdata_i     (BusWidth'(0)),
+    .rvalid_i    (1'b0),
+    .rerror_i    (2'b0)
   );
 
   prim_fifo_sync #(
@@ -511,17 +512,18 @@
   ) u_to_rd_fifo (
     .clk_i,
     .rst_ni,
-    .tl_i       (tl_win_h2d[1]),
-    .tl_o       (tl_win_d2h[1]),
-    .req_o      (rd_fifo_ren),
-    .gnt_i      (rd_fifo_rvalid),
-    .we_o       (),
-    .addr_o     (),
-    .wmask_o    (),
-    .wdata_o    (),
-    .rdata_i    (rd_fifo_rdata),
-    .rvalid_i   (adapter_rvalid),
-    .rerror_i   (2'b0)
+    .tl_i        (tl_win_h2d[1]),
+    .tl_o        (tl_win_d2h[1]),
+    .en_ifetch_i (tlul_pkg::InstrDis),
+    .req_o       (rd_fifo_ren),
+    .gnt_i       (rd_fifo_rvalid),
+    .we_o        (),
+    .addr_o      (),
+    .wmask_o     (),
+    .wdata_o     (),
+    .rdata_i     (rd_fifo_rdata),
+    .rvalid_i    (adapter_rvalid),
+    .rerror_i    (2'b0)
   );
 
   prim_fifo_sync #(
diff --git a/hw/ip/hmac/rtl/hmac.sv b/hw/ip/hmac/rtl/hmac.sv
index d943d8b..bb62790 100644
--- a/hw/ip/hmac/rtl/hmac.sv
+++ b/hw/ip/hmac/rtl/hmac.sv
@@ -291,18 +291,18 @@
   ) u_tlul_adapter (
     .clk_i,
     .rst_ni,
-    .tl_i   (tl_win_h2d[0]),
-    .tl_o   (tl_win_d2h[0]),
-
-    .req_o    (msg_fifo_req   ),
-    .gnt_i    (msg_fifo_gnt   ),
-    .we_o     (msg_fifo_we    ),
-    .addr_o   (msg_fifo_addr  ), // Doesn't care the address other than sub-word
-    .wdata_o  (msg_fifo_wdata ),
-    .wmask_o  (msg_fifo_wmask ),
-    .rdata_i  (msg_fifo_rdata ),
-    .rvalid_i (msg_fifo_rvalid),
-    .rerror_i (msg_fifo_rerror)
+    .tl_i        (tl_win_h2d[0]),
+    .tl_o        (tl_win_d2h[0]),
+    .en_ifetch_i (tlul_pkg::InstrDis),
+    .req_o       (msg_fifo_req   ),
+    .gnt_i       (msg_fifo_gnt   ),
+    .we_o        (msg_fifo_we    ),
+    .addr_o      (msg_fifo_addr  ), // Doesn't care the address other than sub-word
+    .wdata_o     (msg_fifo_wdata ),
+    .wmask_o     (msg_fifo_wmask ),
+    .rdata_i     (msg_fifo_rdata ),
+    .rvalid_i    (msg_fifo_rvalid),
+    .rerror_i    (msg_fifo_rerror)
   );
 
   // TL-UL to MSG_FIFO byte write handling
diff --git a/hw/ip/kmac/rtl/kmac.sv b/hw/ip/kmac/rtl/kmac.sv
index 8e5fdc2..823f3fb 100644
--- a/hw/ip/kmac/rtl/kmac.sv
+++ b/hw/ip/kmac/rtl/kmac.sv
@@ -639,19 +639,19 @@
   ) u_tlul_adapter_msgfifo (
     .clk_i,
     .rst_ni,
+    .en_ifetch_i (tlul_pkg::InstrDis),
+    .tl_i        (tl_win_h2d[WinMsgFifo]),
+    .tl_o        (tl_win_d2h[WinMsgFifo]),
 
-    .tl_i (tl_win_h2d[WinMsgFifo]),
-    .tl_o (tl_win_d2h[WinMsgFifo]),
-
-    .req_o    (tlram_req),
-    .gnt_i    (tlram_gnt),
-    .we_o     (tlram_we ),
-    .addr_o   (tlram_addr),
-    .wdata_o  (tlram_wdata),
-    .wmask_o  (tlram_wmask),
-    .rdata_i  (tlram_rdata),
-    .rvalid_i (tlram_rvalid),
-    .rerror_i (tlram_rerror)
+    .req_o       (tlram_req),
+    .gnt_i       (tlram_gnt),
+    .we_o        (tlram_we ),
+    .addr_o      (tlram_addr),
+    .wdata_o     (tlram_wdata),
+    .wmask_o     (tlram_wmask),
+    .rdata_i     (tlram_rdata),
+    .rvalid_i    (tlram_rvalid),
+    .rerror_i    (tlram_rerror)
   );
 
   assign sw_msg_valid = tlram_req & tlram_we ;
@@ -886,4 +886,3 @@
   // Command input should be onehot0
   `ASSUME(CmdOneHot0_M, reg2hw.cmd.qe |-> $onehot0(reg2hw.cmd.q))
 endmodule
-
diff --git a/hw/ip/kmac/rtl/kmac_staterd.sv b/hw/ip/kmac/rtl/kmac_staterd.sv
index 4cb11d6..a31ae99 100644
--- a/hw/ip/kmac/rtl/kmac_staterd.sv
+++ b/hw/ip/kmac/rtl/kmac_staterd.sv
@@ -64,16 +64,16 @@
 
     .tl_i,
     .tl_o,
-
-    .req_o    (tlram_req),
-    .gnt_i    (tlram_gnt),
-    .we_o     (tlram_we ),
-    .addr_o   (tlram_addr),
-    .wdata_o  (unused_tlram_wdata),
-    .wmask_o  (unused_tlram_wmask),
-    .rdata_i  (tlram_rdata),
-    .rvalid_i (tlram_rvalid),
-    .rerror_i (tlram_rerror)
+    .en_ifetch_i (tlul_pkg::InstrDis),
+    .req_o       (tlram_req),
+    .gnt_i       (tlram_gnt),
+    .we_o        (tlram_we ),
+    .addr_o      (tlram_addr),
+    .wdata_o     (unused_tlram_wdata),
+    .wmask_o     (unused_tlram_wmask),
+    .rdata_i     (tlram_rdata),
+    .rvalid_i    (tlram_rvalid),
+    .rerror_i    (tlram_rerror)
   );
 
   always_ff @(posedge clk_i or negedge rst_ni) begin
@@ -123,4 +123,3 @@
   end
 
 endmodule
-
diff --git a/hw/ip/otbn/rtl/otbn.sv b/hw/ip/otbn/rtl/otbn.sv
index bd79f4c..7d85645 100644
--- a/hw/ip/otbn/rtl/otbn.sv
+++ b/hw/ip/otbn/rtl/otbn.sv
@@ -171,18 +171,18 @@
   ) u_tlul_adapter_sram_imem (
     .clk_i,
     .rst_ni,
-    .tl_i   (tl_win_h2d[TlWinImem]),
-    .tl_o   (tl_win_d2h[TlWinImem]),
-
-    .req_o    (imem_req_bus   ),
-    .gnt_i    (imem_gnt_bus   ),
-    .we_o     (imem_write_bus ),
-    .addr_o   (imem_index_bus ),
-    .wdata_o  (imem_wdata_bus ),
-    .wmask_o  (imem_wmask_bus ),
-    .rdata_i  (imem_rdata_bus ),
-    .rvalid_i (imem_rvalid_bus),
-    .rerror_i (imem_rerror_bus)
+    .tl_i        (tl_win_h2d[TlWinImem]),
+    .tl_o        (tl_win_d2h[TlWinImem]),
+    .en_ifetch_i (tlul_pkg::InstrDis),
+    .req_o       (imem_req_bus   ),
+    .gnt_i       (imem_gnt_bus   ),
+    .we_o        (imem_write_bus ),
+    .addr_o      (imem_index_bus ),
+    .wdata_o     (imem_wdata_bus ),
+    .wmask_o     (imem_wmask_bus ),
+    .rdata_i     (imem_rdata_bus ),
+    .rvalid_i    (imem_rvalid_bus),
+    .rerror_i    (imem_rerror_bus)
   );
 
   // Mux core and bus access into IMEM
@@ -305,18 +305,18 @@
     .clk_i,
     .rst_ni,
 
-    .tl_i     (tl_win_h2d[TlWinDmem]),
-    .tl_o     (tl_win_d2h[TlWinDmem]),
-
-    .req_o    (dmem_req_bus   ),
-    .gnt_i    (dmem_gnt_bus   ),
-    .we_o     (dmem_write_bus ),
-    .addr_o   (dmem_index_bus ),
-    .wdata_o  (dmem_wdata_bus ),
-    .wmask_o  (dmem_wmask_bus ),
-    .rdata_i  (dmem_rdata_bus ),
-    .rvalid_i (dmem_rvalid_bus),
-    .rerror_i (dmem_rerror_bus)
+    .tl_i        (tl_win_h2d[TlWinDmem]),
+    .tl_o        (tl_win_d2h[TlWinDmem]),
+    .en_ifetch_i (tlul_pkg::InstrDis),
+    .req_o       (dmem_req_bus   ),
+    .gnt_i       (dmem_gnt_bus   ),
+    .we_o        (dmem_write_bus ),
+    .addr_o      (dmem_index_bus ),
+    .wdata_o     (dmem_wdata_bus ),
+    .wmask_o     (dmem_wmask_bus ),
+    .rdata_i     (dmem_rdata_bus ),
+    .rvalid_i    (dmem_rvalid_bus),
+    .rerror_i    (dmem_rerror_bus)
   );
 
   // Mux core and bus access into dmem
diff --git a/hw/ip/otp_ctrl/rtl/otp_ctrl.sv b/hw/ip/otp_ctrl/rtl/otp_ctrl.sv
index 2940401..d5695e4 100644
--- a/hw/ip/otp_ctrl/rtl/otp_ctrl.sv
+++ b/hw/ip/otp_ctrl/rtl/otp_ctrl.sv
@@ -184,17 +184,18 @@
   ) u_tlul_adapter_sram (
     .clk_i,
     .rst_ni,
-    .tl_i     ( tl_win_h2d[0] ),
-    .tl_o     ( tl_win_d2h[0] ),
-    .req_o    (  tlul_req     ),
-    .gnt_i    (  tlul_gnt     ),
-    .we_o     (               ), // unused
-    .addr_o   (  tlul_addr    ),
-    .wdata_o  (               ), // unused
-    .wmask_o  (               ), // unused
-    .rdata_i  (  tlul_rdata   ),
-    .rvalid_i (  tlul_rvalid  ),
-    .rerror_i (  tlul_rerror  )
+    .en_ifetch_i ( 1'b0          ),
+    .tl_i        ( tl_win_h2d[0] ),
+    .tl_o        ( tl_win_d2h[0] ),
+    .req_o       (  tlul_req     ),
+    .gnt_i       (  tlul_gnt     ),
+    .we_o        (               ), // unused
+    .addr_o      (  tlul_addr    ),
+    .wdata_o     (               ), // unused
+    .wmask_o     (               ), // unused
+    .rdata_i     (  tlul_rdata   ),
+    .rvalid_i    (  tlul_rvalid  ),
+    .rerror_i    (  tlul_rerror  )
   );
 
   logic [NumPart-1:0] tlul_part_sel_oh;
diff --git a/hw/ip/prim_generic/rtl/prim_generic_flash.sv b/hw/ip/prim_generic/rtl/prim_generic_flash.sv
index 2a744ec..8483fbd 100644
--- a/hw/ip/prim_generic/rtl/prim_generic_flash.sv
+++ b/hw/ip/prim_generic/rtl/prim_generic_flash.sv
@@ -144,6 +144,7 @@
     .rst_ni,
     .tl_i,
     .tl_o,
+    .en_ifetch_i(tlul_pkg::InstrDis),
     .req_o(cfg_req),
     .gnt_i(1'b1),
     .we_o(cfg_we),
diff --git a/hw/ip/prim_generic/rtl/prim_generic_otp.sv b/hw/ip/prim_generic/rtl/prim_generic_otp.sv
index 42dc2d7..149d6e7 100644
--- a/hw/ip/prim_generic/rtl/prim_generic_otp.sv
+++ b/hw/ip/prim_generic/rtl/prim_generic_otp.sv
@@ -69,17 +69,18 @@
   ) u_tlul_adapter_sram (
     .clk_i,
     .rst_ni,
-    .tl_i     ( test_tl_i         ),
-    .tl_o     ( test_tl_o         ),
-    .req_o    ( tlul_req          ),
-    .gnt_i    ( tlul_req          ),
-    .we_o     ( tlul_wren         ),
-    .addr_o   ( tlul_addr         ),
-    .wdata_o  ( tlul_wdata        ),
-    .wmask_o  (                   ),
-    .rdata_i  ( tlul_rdata_q      ),
-    .rvalid_i ( tlul_rvalid_q     ),
-    .rerror_i ( '0                )
+    .tl_i        ( test_tl_i          ),
+    .tl_o        ( test_tl_o          ),
+    .en_ifetch_i ( tlul_pkg::InstrDis ),
+    .req_o       ( tlul_req           ),
+    .gnt_i       ( tlul_req           ),
+    .we_o        ( tlul_wren          ),
+    .addr_o      ( tlul_addr          ),
+    .wdata_o     ( tlul_wdata         ),
+    .wmask_o     (                    ),
+    .rdata_i     ( tlul_rdata_q       ),
+    .rvalid_i    ( tlul_rvalid_q      ),
+    .rerror_i    ( '0                 )
   );
 
   always_ff @(posedge clk_i or negedge rst_ni) begin : p_tlul_testreg
diff --git a/hw/ip/rv_dm/rtl/rv_dm.sv b/hw/ip/rv_dm/rtl/rv_dm.sv
index 3caeff4..f014679 100644
--- a/hw/ip/rv_dm/rtl/rv_dm.sv
+++ b/hw/ip/rv_dm/rtl/rv_dm.sv
@@ -19,6 +19,7 @@
   input  logic               clk_i,       // clock
   input  logic               rst_ni,      // asynchronous reset active low, connect PoR
                                           // here, not the system reset
+  input  lc_ctrl_pkg::lc_tx_t hw_debug_en,
   input  logic               testmode_i,
   output logic               ndmreset_o,  // non-debug module reset
   output logic               dmactive_o,  // debug module is active
@@ -198,6 +199,7 @@
     .clk_i,
     .rst_ni,
     .req_i        (host_req),
+    .type_i       (tlul_pkg::DataType),
     .gnt_o        (host_gnt),
     .addr_i       (host_add),
     .we_i         (host_we),
@@ -298,6 +300,9 @@
   );
 `endif
 
+
+  tlul_pkg::tl_instr_en_e en_ifetch;
+  assign en_ifetch = hw_debug_en == lc_ctrl_pkg::On ? tlul_pkg::InstrEn : tlul_pkg::InstrDis;
   tlul_adapter_sram #(
     .SramAw(AddressWidthWords),
     .SramDw(BusWidth),
@@ -306,19 +311,19 @@
   ) tl_adapter_device_mem (
     .clk_i,
     .rst_ni,
+    .en_ifetch_i (en_ifetch),
+    .req_o       (req),
+    .gnt_i       (1'b1),
+    .we_o        (we),
+    .addr_o      (addr_w),
+    .wdata_o     (wdata),
+    .wmask_o     (),
+    .rdata_i     (rdata),
+    .rvalid_i    (rvalid),
+    .rerror_i    (2'b00),
 
-    .req_o    (req),
-    .gnt_i    (1'b1),
-    .we_o     (we),
-    .addr_o   (addr_w),
-    .wdata_o  (wdata),
-    .wmask_o  (),
-    .rdata_i  (rdata),
-    .rvalid_i (rvalid),
-    .rerror_i (2'b00),
-
-    .tl_o     (tl_d_o),
-    .tl_i     (tl_d_i)
+    .tl_o        (tl_d_o),
+    .tl_i        (tl_d_i)
   );
 
   always_ff @(posedge clk_i or negedge rst_ni) begin
diff --git a/hw/ip/spi_device/rtl/spi_device.sv b/hw/ip/spi_device/rtl/spi_device.sv
index b4fcb4a..bec6e68 100644
--- a/hw/ip/spi_device/rtl/spi_device.sv
+++ b/hw/ip/spi_device/rtl/spi_device.sv
@@ -638,18 +638,18 @@
     .clk_i,
     .rst_ni,
 
-    .tl_i (tl_sram_h2d [0]),
-    .tl_o (tl_sram_d2h [0]),
-
-    .req_o    (mem_a_req),
-    .gnt_i    (mem_a_req),  //Always grant when request
-    .we_o     (mem_a_write),
-    .addr_o   (mem_a_addr),
-    .wdata_o  (mem_a_wdata),
-    .wmask_o  (),           // Not used
-    .rdata_i  (mem_a_rdata),
-    .rvalid_i (mem_a_rvalid),
-    .rerror_i (mem_a_rerror)
+    .tl_i        (tl_sram_h2d [0]),
+    .tl_o        (tl_sram_d2h [0]),
+    .en_ifetch_i (tlul_pkg::InstrDis),
+    .req_o       (mem_a_req),
+    .gnt_i       (mem_a_req),  //Always grant when request
+    .we_o        (mem_a_write),
+    .addr_o      (mem_a_addr),
+    .wdata_o     (mem_a_wdata),
+    .wmask_o     (),           // Not used
+    .rdata_i     (mem_a_rdata),
+    .rvalid_i    (mem_a_rvalid),
+    .rerror_i    (mem_a_rerror)
   );
 
   // SRAM Wrapper
diff --git a/hw/ip/tlul/rtl/tlul_adapter_host.sv b/hw/ip/tlul/rtl/tlul_adapter_host.sv
index 199a992..9248a09 100644
--- a/hw/ip/tlul/rtl/tlul_adapter_host.sv
+++ b/hw/ip/tlul/rtl/tlul_adapter_host.sv
@@ -21,7 +21,7 @@
 
 `include "prim_assert.sv"
 
-module tlul_adapter_host #(
+module tlul_adapter_host import tlul_pkg::*; #(
   parameter int unsigned MAX_REQS = 2
 ) (
   input clk_i,
@@ -33,13 +33,14 @@
   input  logic                       we_i,
   input  logic [top_pkg::TL_DW-1:0]  wdata_i,
   input  logic [top_pkg::TL_DBW-1:0] be_i,
+  input  tl_type_e                   type_i,
 
   output logic                       valid_o,
   output logic [top_pkg::TL_DW-1:0]  rdata_o,
   output logic                       err_o,
 
-  output tlul_pkg::tl_h2d_t          tl_o,
-  input  tlul_pkg::tl_d2h_t          tl_i
+  output tl_h2d_t                    tl_o,
+  input  tl_d2h_t                    tl_i
 );
   localparam int WordSize = $clog2(top_pkg::TL_DBW);
 
@@ -84,16 +85,16 @@
 
   assign tl_o = '{
     a_valid:   req_i,
-    a_opcode:  (~we_i) ? tlul_pkg::Get           :
-               (&be_i) ? tlul_pkg::PutFullData   :
-                         tlul_pkg::PutPartialData,
+    a_opcode:  (~we_i) ? Get           :
+               (&be_i) ? PutFullData   :
+                         PutPartialData,
     a_param:   3'h0,
     a_size:    top_pkg::TL_SZW'(WordSize),
     a_mask:    tl_be,
     a_source:  tl_source,
     a_address: {addr_i[31:WordSize], {WordSize{1'b0}}},
     a_data:    wdata_i,
-    a_user:    '{default:'0},
+    a_user:    '{parity_en: '0, parity: '0, tl_type: type_i},
 
     d_ready:   1'b1
   };
diff --git a/hw/ip/tlul/rtl/tlul_adapter_sram.sv b/hw/ip/tlul/rtl/tlul_adapter_sram.sv
index 5403b5f..89baa19 100644
--- a/hw/ip/tlul/rtl/tlul_adapter_sram.sv
+++ b/hw/ip/tlul/rtl/tlul_adapter_sram.sv
@@ -11,7 +11,7 @@
  *   it means that aliasing can happen if target device size in TL-UL crossbar is bigger
  *   than SRAM size
  */
-module tlul_adapter_sram #(
+module tlul_adapter_sram import tlul_pkg::*; #(
   parameter int SramAw      = 12,
   parameter int SramDw      = 32, // Must be multiple of the TL width
   parameter int Outstanding = 1,  // Only one request is accepted
@@ -23,8 +23,11 @@
   input   rst_ni,
 
   // TL-UL interface
-  input   tlul_pkg::tl_h2d_t  tl_i,
-  output  tlul_pkg::tl_d2h_t  tl_o,
+  input   tl_h2d_t          tl_i,
+  output  tl_d2h_t          tl_o,
+
+  // control interface
+  input   tl_instr_en_e     en_ifetch_i,
 
   // SRAM interface
   output logic              req_o,
@@ -38,8 +41,6 @@
   input        [1:0]        rerror_i // 2 bit error [1]: Uncorrectable, [0]: Correctable
 );
 
-  import tlul_pkg::*;
-
   localparam int SramByte = SramDw/8;
   localparam int DataBitWidth = prim_util_pkg::vbits(SramByte);
   localparam int WidthMult = SramDw / top_pkg::TL_DW;
@@ -91,6 +92,7 @@
 
   logic error_internal; // Internal protocol error checker
   logic wr_attr_error;
+  logic instr_error;
   logic wr_vld_error;
   logic rd_vld_error;
   logic tlul_error;     // Error from `tlul_err` module
@@ -198,6 +200,10 @@
                          (ByteAccess == 0) ? (tl_i.a_mask != '1 || tl_i.a_size != 2'h2) : 1'b0 :
                          1'b0;
 
+  // An instruction type transaction is only valid if en_ifetch is enabled
+  assign instr_error = tl_i.a_user.tl_type == InstrType &
+                       en_ifetch_i == InstrDis;
+
   if (ErrOnWrite == 1) begin : gen_no_writes
     assign wr_vld_error = tl_i.a_opcode != Get;
   end else begin : gen_writes_allowed
@@ -217,7 +223,7 @@
     .err_o (tlul_error)
   );
 
-  assign error_internal = wr_attr_error | wr_vld_error | rd_vld_error | tlul_error;
+  assign error_internal = wr_attr_error | wr_vld_error | rd_vld_error | instr_error | tlul_error;
   // End: Request Error Detection
 
   assign reqfifo_wvalid = a_ack ; // Push to FIFO only when granted
diff --git a/hw/ip/tlul/rtl/tlul_err.sv b/hw/ip/tlul/rtl/tlul_err.sv
index add8477..8a9afbe 100644
--- a/hw/ip/tlul/rtl/tlul_err.sv
+++ b/hw/ip/tlul/rtl/tlul_err.sv
@@ -27,8 +27,13 @@
   assign op_partial = (tl_i.a_opcode == PutPartialData);
   assign op_get     = (tl_i.a_opcode == Get);
 
+  // An instruction type transaction cannot be write
+  logic instr_wr_err;
+  assign instr_wr_err = (tl_i.a_user.tl_type == InstrType) &
+                        (op_full | op_partial);
+
   // Anything that doesn't fall into the permitted category, it raises an error
-  assign err_o = ~(opcode_allowed & a_config_allowed);
+  assign err_o = ~(opcode_allowed & a_config_allowed) | instr_wr_err;
 
   // opcode check
   assign opcode_allowed = (tl_i.a_opcode == PutFullData)
@@ -92,4 +97,3 @@
   `ASSERT_INIT(dataWidthOnly32_A, DW == 32)
 
 endmodule
-
diff --git a/hw/ip/tlul/rtl/tlul_pkg.sv b/hw/ip/tlul/rtl/tlul_pkg.sv
index 7fc4668..46c66ba 100644
--- a/hw/ip/tlul/rtl/tlul_pkg.sv
+++ b/hw/ip/tlul/rtl/tlul_pkg.sv
@@ -18,13 +18,27 @@
     PutPartialData = 3'h 1,
     Get            = 3'h 4
   } tl_a_op_e;
+
   typedef enum logic [2:0] {
     AccessAck     = 3'h 0,
     AccessAckData = 3'h 1
   } tl_d_op_e;
 
+  typedef enum logic [2:0] {
+    InstrEn       = 3'b101,
+    InstrDis      = 3'b010
+  } tl_instr_en_e;
+
+  // used for intermodule connections
+  typedef tl_instr_en_e tl_instr_en_t;
+
+  typedef enum logic [1:0] {
+    InstrType     = 2'b01,
+    DataType      = 2'b10
+  } tl_type_e;
+
   typedef struct packed {
-    logic [6:0] rsvd1; // Reserved for future use
+    tl_type_e   tl_type;
     logic       parity_en;
     logic [7:0] parity; // Use only lower TL_DBW bit
   } tl_a_user_t;
diff --git a/hw/ip/usbdev/rtl/usbdev.sv b/hw/ip/usbdev/rtl/usbdev.sv
index 3d19f58..ca14c5f 100644
--- a/hw/ip/usbdev/rtl/usbdev.sv
+++ b/hw/ip/usbdev/rtl/usbdev.sv
@@ -665,21 +665,21 @@
     .SramAw(SramAw),
     .ByteAccess(0)
   ) u_tlul2sram (
-    .clk_i    (clk_i),
-    .rst_ni   (rst_ni),
+    .clk_i       (clk_i),
+    .rst_ni      (rst_ni),
 
-    .tl_i     (tl_sram_h2d [0]),
-    .tl_o     (tl_sram_d2h [0]),
-
-    .req_o    (mem_a_req),
-    .gnt_i    (mem_a_req),  //Always grant when request
-    .we_o     (mem_a_write),
-    .addr_o   (mem_a_addr),
-    .wdata_o  (mem_a_wdata),
-    .wmask_o  (),           // Not used
-    .rdata_i  (mem_a_rdata),
-    .rvalid_i (mem_a_rvalid),
-    .rerror_i (mem_a_rerror)
+    .tl_i        (tl_sram_h2d [0]),
+    .tl_o        (tl_sram_d2h [0]),
+    .en_ifetch_i (tlul_pkg::InstrDis),
+    .req_o       (mem_a_req),
+    .gnt_i       (mem_a_req),  //Always grant when request
+    .we_o        (mem_a_write),
+    .addr_o      (mem_a_addr),
+    .wdata_o     (mem_a_wdata),
+    .wmask_o     (),           // Not used
+    .rdata_i     (mem_a_rdata),
+    .rvalid_i    (mem_a_rvalid),
+    .rerror_i    (mem_a_rerror)
   );
 
   // SRAM Wrapper
diff --git a/hw/top_earlgrey/data/top_earlgrey.sv.tpl b/hw/top_earlgrey/data/top_earlgrey.sv.tpl
index ec494a0..0580174 100644
--- a/hw/top_earlgrey/data/top_earlgrey.sv.tpl
+++ b/hw/top_earlgrey/data/top_earlgrey.sv.tpl
@@ -369,18 +369,18 @@
     % for key, value in resets.items():
     .${key}   (${value}),
     % endfor
-    .tl_i     (${m["name"]}_tl_req),
-    .tl_o     (${m["name"]}_tl_rsp),
-
-    .req_o    (${m["name"]}_req),
-    .gnt_i    (${m["name"]}_gnt),
-    .we_o     (${m["name"]}_we),
-    .addr_o   (${m["name"]}_addr),
-    .wdata_o  (${m["name"]}_wdata),
-    .wmask_o  (${m["name"]}_wmask),
-    .rdata_i  (${m["name"]}_rdata),
-    .rvalid_i (${m["name"]}_rvalid),
-    .rerror_i (${m["name"]}_rerror)
+    .tl_i        (${m["name"]}_tl_req),
+    .tl_o        (${m["name"]}_tl_rsp),
+    .en_ifetch_i (1'b1),
+    .req_o       (${m["name"]}_req),
+    .gnt_i       (${m["name"]}_gnt),
+    .we_o        (${m["name"]}_we),
+    .addr_o      (${m["name"]}_addr),
+    .wdata_o     (${m["name"]}_wdata),
+    .wmask_o     (${m["name"]}_wmask),
+    .rdata_i     (${m["name"]}_rdata),
+    .rvalid_i    (${m["name"]}_rvalid),
+    .rerror_i    (${m["name"]}_rerror)
   );
 
   prim_ram_1p_scr #(
@@ -442,18 +442,18 @@
     .${key}   (${value}),
     % endfor
 
-    .tl_i     (${m["name"]}_tl_req),
-    .tl_o     (${m["name"]}_tl_rsp),
-
-    .req_o    (${m["name"]}_req),
-    .gnt_i    (1'b1), // Always grant as only one requester exists
-    .we_o     (),
-    .addr_o   (${m["name"]}_addr),
-    .wdata_o  (),
-    .wmask_o  (),
-    .rdata_i  (${m["name"]}_rdata),
-    .rvalid_i (${m["name"]}_rvalid),
-    .rerror_i (2'b00)
+    .tl_i        (${m["name"]}_tl_req),
+    .tl_o        (${m["name"]}_tl_rsp),
+    .en_ifetch_i (1'b1),
+    .req_o       (${m["name"]}_req),
+    .gnt_i       (1'b1), // Always grant as only one requester exists
+    .we_o        (),
+    .addr_o      (${m["name"]}_addr),
+    .wdata_o     (),
+    .wmask_o     (),
+    .rdata_i     (${m["name"]}_rdata),
+    .rvalid_i    (${m["name"]}_rvalid),
+    .rerror_i    (2'b00)
   );
 
   prim_rom_adv #(
@@ -498,18 +498,18 @@
     .${key}   (${value}),
     % endfor
 
-    .tl_i     (${m["name"]}_tl_req),
-    .tl_o     (${m["name"]}_tl_rsp),
-
-    .req_o    (flash_host_req),
-    .gnt_i    (flash_host_req_rdy),
-    .we_o     (),
-    .addr_o   (flash_host_addr),
-    .wdata_o  (),
-    .wmask_o  (),
-    .rdata_i  (flash_host_rdata),
-    .rvalid_i (flash_host_req_done),
-    .rerror_i ({flash_host_rderr,1'b0})
+    .tl_i        (${m["name"]}_tl_req),
+    .tl_o        (${m["name"]}_tl_rsp),
+    .en_ifetch_i (1'b1), // tie this to secure boot somehow
+    .req_o       (flash_host_req),
+    .gnt_i       (flash_host_req_rdy),
+    .we_o        (),
+    .addr_o      (flash_host_addr),
+    .wdata_o     (),
+    .wmask_o     (),
+    .rdata_i     (flash_host_rdata),
+    .rvalid_i    (flash_host_req_done),
+    .rerror_i    ({flash_host_rderr,1'b0})
   );
 
   flash_phy u_flash_${m["name"]} (