[otbn] Avoid "sanity" terminology in UVM code
Signed-off-by: Rupert Swarbrick <rswarbrick@lowrisc.org>
diff --git a/hw/ip/otbn/doc/checklist.md b/hw/ip/otbn/doc/checklist.md
index b02cba5..771fff0 100644
--- a/hw/ip/otbn/doc/checklist.md
+++ b/hw/ip/otbn/doc/checklist.md
@@ -41,7 +41,7 @@
Documentation | [MISSING_FUNC][] | Not Started |
Documentation | [FEATURE_FROZEN][] | Not Started |
RTL | [FEATURE_COMPLETE][] | Not Started |
-RTL | [AREA_SANITY_CHECK][] | Not Started |
+RTL | [AREA_CROSS_CHECK][] | Not Started |
RTL | [PORT_FROZEN][] | Not Started |
RTL | [ARCHITECTURE_FROZEN][] | Not Started |
RTL | [REVIEW_TODO][] | Not Started |
@@ -61,7 +61,7 @@
[MISSING_FUNC]: {{<relref "/doc/project/checklist.md#missing_func" >}}
[FEATURE_FROZEN]: {{<relref "/doc/project/checklist.md#feature_frozen" >}}
[FEATURE_COMPLETE]: {{<relref "/doc/project/checklist.md#feature_complete" >}}
-[AREA_SANITY_CHECK]: {{<relref "/doc/project/checklist.md#area_sanity_check" >}}
+[AREA_CROSS_CHECK]: {{<relref "/doc/project/checklist.md#area_cross_check" >}}
[PORT_FROZEN]: {{<relref "/doc/project/checklist.md#port_frozen" >}}
[ARCHITECTURE_FROZEN]: {{<relref "/doc/project/checklist.md#architecture_frozen" >}}
[REVIEW_TODO]: {{<relref "/doc/project/checklist.md#review_todo" >}}
@@ -118,11 +118,11 @@
Testbench | [SIM_RAL_MODEL_GEN_AUTOMATED][] | Not Started |
Testbench | [CSR_CHECK_GEN_AUTOMATED][] | Not Started |
Testbench | [TB_GEN_AUTOMATED][] | Not Started |
-Tests | [SIM_SANITY_TEST_PASSING][] | Not Started |
+Tests | [SIM_SMOKE_TEST_PASSING][] | Not Started |
Tests | [SIM_CSR_MEM_TEST_SUITE_PASSING][] | Not Started |
Tests | [FPV_MAIN_ASSERTIONS_PROVEN][] | Not Started |
Tool Setup | [SIM_ALT_TOOL_SETUP][] | Not Started |
-Regression | [SIM_SANITY_REGRESSION_SETUP][] | Not Started |
+Regression | [SIM_SMOKE_REGRESSION_SETUP][] | Not Started |
Regression | [SIM_NIGHTLY_REGRESSION_SETUP][] | Not Started |
Regression | [FPV_REGRESSION_SETUP][] | Not Started |
Coverage | [SIM_COVERAGE_MODEL_ADDED][] | Not Started |
@@ -140,11 +140,11 @@
[SIM_RAL_MODEL_GEN_AUTOMATED]: {{<relref "/doc/project/checklist.md#sim_ral_model_gen_automated" >}}
[CSR_CHECK_GEN_AUTOMATED]: {{<relref "/doc/project/checklist.md#csr_check_gen_automated" >}}
[TB_GEN_AUTOMATED]: {{<relref "/doc/project/checklist.md#tb_gen_automated" >}}
-[SIM_SANITY_TEST_PASSING]: {{<relref "/doc/project/checklist.md#sim_sanity_test_passing" >}}
+[SIM_SMOKE_TEST_PASSING]: {{<relref "/doc/project/checklist.md#sim_smoke_test_passing" >}}
[SIM_CSR_MEM_TEST_SUITE_PASSING]: {{<relref "/doc/project/checklist.md#sim_csr_mem_test_suite_passing" >}}
[FPV_MAIN_ASSERTIONS_PROVEN]: {{<relref "/doc/project/checklist.md#fpv_main_assertions_proven" >}}
[SIM_ALT_TOOL_SETUP]: {{<relref "/doc/project/checklist.md#sim_alt_tool_setup" >}}
-[SIM_SANITY_REGRESSION_SETUP]: {{<relref "/doc/project/checklist.md#sim_sanity_regression_setup" >}}
+[SIM_SMOKE_REGRESSION_SETUP]: {{<relref "/doc/project/checklist.md#sim_smoke_regression_setup" >}}
[SIM_NIGHTLY_REGRESSION_SETUP]: {{<relref "/doc/project/checklist.md#sim_nightly_regression_setup" >}}
[FPV_REGRESSION_SETUP]: {{<relref "/doc/project/checklist.md#fpv_regression_setup" >}}
[SIM_COVERAGE_MODEL_ADDED]: {{<relref "/doc/project/checklist.md#sim_coverage_model_added" >}}
diff --git a/hw/ip/otbn/doc/dv_plan/index.md b/hw/ip/otbn/doc/dv_plan/index.md
index 541e81d..b02cd4d 100644
--- a/hw/ip/otbn/doc/dv_plan/index.md
+++ b/hw/ip/otbn/doc/dv_plan/index.md
@@ -76,7 +76,7 @@
- behaviour that is triggered by particular external stimuli (register writes; surprise resets etc.)
Testing lots of different instruction streams doesn't really use the UVM machinery, so we have a "pre-DV" phase of testing that generates constrained-random instruction streams (as ELF binaries) and runs a simple block-level simulation on each to check that the RTL matches the model.
-The idea is that this is much quicker for designers to use to sanity-test proposed changes, and can be run with Verilator, so it doesn't require an EDA tool licence.
+The idea is that this is much quicker for designers to use to smoke-test proposed changes, and can be run with Verilator, so it doesn't require an EDA tool licence.
This pre-DV phase cannot drive sign-off, but it does use much of the same tooling.
Once we are running full DV tests, we re-use this work, by using the same collection of randomised instruction streams and randomly picking from them for most of the sequences.
@@ -132,7 +132,7 @@
Tests can be run with [`dvsim.py`]({{< relref "hw/dv/tools/README.md" >}}).
The link gives details of the tool's features and command line arguments.
-To run a basic sanity test, go to the top of the repository and run:
+To run a basic smoke test, go to the top of the repository and run:
```console
$ util/dvsim/dvsim.py hw/ip/otbn/dv/uvm/otbn_sim_cfg.hjson -i otbn_single
```
diff --git a/hw/ip/otbn/dv/uvm/env/seq_lib/otbn_base_vseq.sv b/hw/ip/otbn/dv/uvm/env/seq_lib/otbn_base_vseq.sv
index 6f12e0a..4e58d78 100644
--- a/hw/ip/otbn/dv/uvm/env/seq_lib/otbn_base_vseq.sv
+++ b/hw/ip/otbn/dv/uvm/env/seq_lib/otbn_base_vseq.sv
@@ -59,7 +59,7 @@
protected function automatic void
get_queue_entries(bit for_imem, ref otbn_loaded_word entries[$]);
- // Get the size of this memory (for a sanity check on the loaded words)
+ // Get the size of this memory (to make sure the number of loaded words makes sense)
logic [21:0] mem_size = for_imem ? OTBN_IMEM_SIZE : OTBN_DMEM_SIZE;
// Iterate over the segments for this memory
