[alert_handler] Make critical alert handler CSRs shadowed regs
This also aligns the DV environment, the DIF and ROM drivers.
Signed-off-by: Michael Schaffner <msf@opentitan.org>
diff --git a/sw/device/lib/dif/dif_alert_handler.c b/sw/device/lib/dif/dif_alert_handler.c
index 94ec214..840e5d4 100644
--- a/sw/device/lib/dif/dif_alert_handler.c
+++ b/sw/device/lib/dif/dif_alert_handler.c
@@ -50,10 +50,11 @@
return false;
}
- uint32_t enable_reg = mmio_region_read32(handler->params.base_addr,
- ALERT_HANDLER_ALERT_EN_0_REG_OFFSET);
- uint32_t alerts_reg = mmio_region_read32(
- handler->params.base_addr, ALERT_HANDLER_ALERT_CLASS_0_REG_OFFSET);
+ uint32_t enable_reg = mmio_region_read32(
+ handler->params.base_addr, ALERT_HANDLER_ALERT_EN_SHADOWED_0_REG_OFFSET);
+ uint32_t alerts_reg =
+ mmio_region_read32(handler->params.base_addr,
+ ALERT_HANDLER_ALERT_CLASS_SHADOWED_0_REG_OFFSET);
for (int i = 0; i < class->alerts_len; ++i) {
if (class->alerts[i] >= handler->params.alert_count) {
@@ -67,16 +68,20 @@
uint32_t classification;
switch (class->alert_class) {
case kDifAlertHandlerClassA:
- classification = ALERT_HANDLER_ALERT_CLASS_0_CLASS_A_0_VALUE_CLASSA;
+ classification =
+ ALERT_HANDLER_ALERT_CLASS_SHADOWED_0_CLASS_A_0_VALUE_CLASSA;
break;
case kDifAlertHandlerClassB:
- classification = ALERT_HANDLER_ALERT_CLASS_0_CLASS_A_0_VALUE_CLASSB;
+ classification =
+ ALERT_HANDLER_ALERT_CLASS_SHADOWED_0_CLASS_A_0_VALUE_CLASSB;
break;
case kDifAlertHandlerClassC:
- classification = ALERT_HANDLER_ALERT_CLASS_0_CLASS_A_0_VALUE_CLASSC;
+ classification =
+ ALERT_HANDLER_ALERT_CLASS_SHADOWED_0_CLASS_A_0_VALUE_CLASSC;
break;
case kDifAlertHandlerClassD:
- classification = ALERT_HANDLER_ALERT_CLASS_0_CLASS_A_0_VALUE_CLASSD;
+ classification =
+ ALERT_HANDLER_ALERT_CLASS_SHADOWED_0_CLASS_A_0_VALUE_CLASSD;
break;
default:
return false;
@@ -84,23 +89,25 @@
// TODO: Currently, we assume all fields are of equal width.
// See: #3826
- uint32_t field_width =
- bitfield_popcount32(ALERT_HANDLER_ALERT_CLASS_0_CLASS_A_0_MASK);
+ uint32_t field_width = bitfield_popcount32(
+ ALERT_HANDLER_ALERT_CLASS_SHADOWED_0_CLASS_A_0_MASK);
uint32_t field_offset = field_width * class->alerts[i];
alerts_reg = bitfield_field32_write(
alerts_reg,
(bitfield_field32_t){
- .mask = ALERT_HANDLER_ALERT_CLASS_0_CLASS_A_0_MASK,
+ .mask = ALERT_HANDLER_ALERT_CLASS_SHADOWED_0_CLASS_A_0_MASK,
.index = field_offset,
},
classification);
}
- mmio_region_write32(handler->params.base_addr,
- ALERT_HANDLER_ALERT_EN_0_REG_OFFSET, enable_reg);
- mmio_region_write32(handler->params.base_addr,
- ALERT_HANDLER_ALERT_CLASS_0_REG_OFFSET, alerts_reg);
+ mmio_region_write32_shadowed(handler->params.base_addr,
+ ALERT_HANDLER_ALERT_EN_SHADOWED_0_REG_OFFSET,
+ enable_reg);
+ mmio_region_write32_shadowed(handler->params.base_addr,
+ ALERT_HANDLER_ALERT_CLASS_SHADOWED_0_REG_OFFSET,
+ alerts_reg);
return true;
}
@@ -116,29 +123,31 @@
return false;
}
- uint32_t enable_reg = mmio_region_read32(
- handler->params.base_addr, ALERT_HANDLER_LOC_ALERT_EN_0_REG_OFFSET);
- uint32_t alerts_reg = mmio_region_read32(
- handler->params.base_addr, ALERT_HANDLER_LOC_ALERT_CLASS_0_REG_OFFSET);
+ uint32_t enable_reg =
+ mmio_region_read32(handler->params.base_addr,
+ ALERT_HANDLER_LOC_ALERT_EN_SHADOWED_0_REG_OFFSET);
+ uint32_t alerts_reg =
+ mmio_region_read32(handler->params.base_addr,
+ ALERT_HANDLER_LOC_ALERT_CLASS_SHADOWED_0_REG_OFFSET);
for (int i = 0; i < class->local_alerts_len; ++i) {
uint32_t classification;
switch (class->alert_class) {
case kDifAlertHandlerClassA:
classification =
- ALERT_HANDLER_LOC_ALERT_CLASS_0_CLASS_LA_0_VALUE_CLASSA;
+ ALERT_HANDLER_LOC_ALERT_CLASS_SHADOWED_0_CLASS_LA_0_VALUE_CLASSA;
break;
case kDifAlertHandlerClassB:
classification =
- ALERT_HANDLER_LOC_ALERT_CLASS_0_CLASS_LA_0_VALUE_CLASSB;
+ ALERT_HANDLER_LOC_ALERT_CLASS_SHADOWED_0_CLASS_LA_0_VALUE_CLASSB;
break;
case kDifAlertHandlerClassC:
classification =
- ALERT_HANDLER_LOC_ALERT_CLASS_0_CLASS_LA_0_VALUE_CLASSC;
+ ALERT_HANDLER_LOC_ALERT_CLASS_SHADOWED_0_CLASS_LA_0_VALUE_CLASSC;
break;
case kDifAlertHandlerClassD:
classification =
- ALERT_HANDLER_LOC_ALERT_CLASS_0_CLASS_LA_0_VALUE_CLASSD;
+ ALERT_HANDLER_LOC_ALERT_CLASS_SHADOWED_0_CLASS_LA_0_VALUE_CLASSD;
break;
default:
return false;
@@ -148,20 +157,28 @@
bitfield_field32_t field;
switch (class->local_alerts[i]) {
case kDifAlertHandlerLocalAlertAlertPingFail:
- enable_bit = ALERT_HANDLER_LOC_ALERT_EN_0_EN_LA_0_BIT;
- field = ALERT_HANDLER_LOC_ALERT_CLASS_0_CLASS_LA_0_FIELD;
+ enable_bit = ALERT_HANDLER_LOC_ALERT_EN_SHADOWED_0_EN_LA_0_BIT;
+ field = ALERT_HANDLER_LOC_ALERT_CLASS_SHADOWED_0_CLASS_LA_0_FIELD;
break;
case kDifAlertHandlerLocalAlertEscalationPingFail:
- enable_bit = ALERT_HANDLER_LOC_ALERT_EN_1_EN_LA_1_BIT;
- field = ALERT_HANDLER_LOC_ALERT_CLASS_1_CLASS_LA_1_FIELD;
+ enable_bit = ALERT_HANDLER_LOC_ALERT_EN_SHADOWED_1_EN_LA_1_BIT;
+ field = ALERT_HANDLER_LOC_ALERT_CLASS_SHADOWED_1_CLASS_LA_1_FIELD;
break;
case kDifAlertHandlerLocalAlertAlertIntegrityFail:
- enable_bit = ALERT_HANDLER_LOC_ALERT_EN_2_EN_LA_2_BIT;
- field = ALERT_HANDLER_LOC_ALERT_CLASS_2_CLASS_LA_2_FIELD;
+ enable_bit = ALERT_HANDLER_LOC_ALERT_EN_SHADOWED_2_EN_LA_2_BIT;
+ field = ALERT_HANDLER_LOC_ALERT_CLASS_SHADOWED_2_CLASS_LA_2_FIELD;
break;
case kDifAlertHandlerLocalAlertEscalationIntegrityFail:
- enable_bit = ALERT_HANDLER_LOC_ALERT_EN_3_EN_LA_3_BIT;
- field = ALERT_HANDLER_LOC_ALERT_CLASS_3_CLASS_LA_3_FIELD;
+ enable_bit = ALERT_HANDLER_LOC_ALERT_EN_SHADOWED_3_EN_LA_3_BIT;
+ field = ALERT_HANDLER_LOC_ALERT_CLASS_SHADOWED_3_CLASS_LA_3_FIELD;
+ break;
+ case kDifAlertHandlerLocalAlertShadowedUpdateError:
+ enable_bit = ALERT_HANDLER_LOC_ALERT_EN_SHADOWED_4_EN_LA_4_BIT;
+ field = ALERT_HANDLER_LOC_ALERT_CLASS_SHADOWED_4_CLASS_LA_4_FIELD;
+ break;
+ case kDifAlertHandlerLocalAlertShadowedStorageError:
+ enable_bit = ALERT_HANDLER_LOC_ALERT_EN_SHADOWED_4_EN_LA_4_BIT;
+ field = ALERT_HANDLER_LOC_ALERT_CLASS_SHADOWED_4_CLASS_LA_4_FIELD;
break;
default:
return false;
@@ -171,10 +188,12 @@
alerts_reg = bitfield_field32_write(alerts_reg, field, classification);
}
- mmio_region_write32(handler->params.base_addr,
- ALERT_HANDLER_LOC_ALERT_EN_0_REG_OFFSET, enable_reg);
- mmio_region_write32(handler->params.base_addr,
- ALERT_HANDLER_LOC_ALERT_CLASS_0_REG_OFFSET, alerts_reg);
+ mmio_region_write32_shadowed(handler->params.base_addr,
+ ALERT_HANDLER_LOC_ALERT_EN_SHADOWED_0_REG_OFFSET,
+ enable_reg);
+ mmio_region_write32_shadowed(
+ handler->params.base_addr,
+ ALERT_HANDLER_LOC_ALERT_CLASS_SHADOWED_0_REG_OFFSET, alerts_reg);
return true;
}
@@ -207,16 +226,16 @@
ptrdiff_t reg_offset;
switch (class->alert_class) {
case kDifAlertHandlerClassA:
- reg_offset = ALERT_HANDLER_CLASSA_CTRL_REG_OFFSET;
+ reg_offset = ALERT_HANDLER_CLASSA_CTRL_SHADOWED_REG_OFFSET;
break;
case kDifAlertHandlerClassB:
- reg_offset = ALERT_HANDLER_CLASSB_CTRL_REG_OFFSET;
+ reg_offset = ALERT_HANDLER_CLASSB_CTRL_SHADOWED_REG_OFFSET;
break;
case kDifAlertHandlerClassC:
- reg_offset = ALERT_HANDLER_CLASSC_CTRL_REG_OFFSET;
+ reg_offset = ALERT_HANDLER_CLASSC_CTRL_SHADOWED_REG_OFFSET;
break;
case kDifAlertHandlerClassD:
- reg_offset = ALERT_HANDLER_CLASSD_CTRL_REG_OFFSET;
+ reg_offset = ALERT_HANDLER_CLASSD_CTRL_SHADOWED_REG_OFFSET;
break;
default:
return false;
@@ -236,16 +255,17 @@
&use_escalation_protocol)) {
return false;
}
- ctrl_reg = bitfield_bit32_write(ctrl_reg, ALERT_HANDLER_CLASSA_CTRL_EN_BIT,
- use_escalation_protocol);
+ ctrl_reg =
+ bitfield_bit32_write(ctrl_reg, ALERT_HANDLER_CLASSA_CTRL_SHADOWED_EN_BIT,
+ use_escalation_protocol);
// Configure the escalation protocol auto-lock flag.
bool automatic_locking;
if (!toggle_to_bool(class->automatic_locking, &automatic_locking)) {
return false;
}
- ctrl_reg = bitfield_bit32_write(ctrl_reg, ALERT_HANDLER_CLASSA_CTRL_LOCK_BIT,
- automatic_locking);
+ ctrl_reg = bitfield_bit32_write(
+ ctrl_reg, ALERT_HANDLER_CLASSA_CTRL_SHADOWED_LOCK_BIT, automatic_locking);
if (class->phase_signals == NULL && class->phase_signals_len != 0) {
return false;
@@ -262,20 +282,20 @@
bitfield_field32_t map_field;
switch (class->phase_signals[i].phase) {
case kDifAlertHandlerClassStatePhase0:
- enable_bit = ALERT_HANDLER_CLASSA_CTRL_EN_E0_BIT;
- map_field = ALERT_HANDLER_CLASSA_CTRL_MAP_E0_FIELD;
+ enable_bit = ALERT_HANDLER_CLASSA_CTRL_SHADOWED_EN_E0_BIT;
+ map_field = ALERT_HANDLER_CLASSA_CTRL_SHADOWED_MAP_E0_FIELD;
break;
case kDifAlertHandlerClassStatePhase1:
- enable_bit = ALERT_HANDLER_CLASSA_CTRL_EN_E1_BIT;
- map_field = ALERT_HANDLER_CLASSA_CTRL_MAP_E1_FIELD;
+ enable_bit = ALERT_HANDLER_CLASSA_CTRL_SHADOWED_EN_E1_BIT;
+ map_field = ALERT_HANDLER_CLASSA_CTRL_SHADOWED_MAP_E1_FIELD;
break;
case kDifAlertHandlerClassStatePhase2:
- enable_bit = ALERT_HANDLER_CLASSA_CTRL_EN_E2_BIT;
- map_field = ALERT_HANDLER_CLASSA_CTRL_MAP_E2_FIELD;
+ enable_bit = ALERT_HANDLER_CLASSA_CTRL_SHADOWED_EN_E2_BIT;
+ map_field = ALERT_HANDLER_CLASSA_CTRL_SHADOWED_MAP_E2_FIELD;
break;
case kDifAlertHandlerClassStatePhase3:
- enable_bit = ALERT_HANDLER_CLASSA_CTRL_EN_E3_BIT;
- map_field = ALERT_HANDLER_CLASSA_CTRL_MAP_E3_FIELD;
+ enable_bit = ALERT_HANDLER_CLASSA_CTRL_SHADOWED_EN_E3_BIT;
+ map_field = ALERT_HANDLER_CLASSA_CTRL_SHADOWED_MAP_E3_FIELD;
break;
default:
return false;
@@ -286,49 +306,49 @@
class->phase_signals[i].signal);
}
- mmio_region_write32(handler->params.base_addr, reg_offset, ctrl_reg);
+ mmio_region_write32_shadowed(handler->params.base_addr, reg_offset, ctrl_reg);
// Configure the class accumulator threshold.
ptrdiff_t acc_offset;
switch (class->alert_class) {
case kDifAlertHandlerClassA:
- acc_offset = ALERT_HANDLER_CLASSA_ACCUM_THRESH_REG_OFFSET;
+ acc_offset = ALERT_HANDLER_CLASSA_ACCUM_THRESH_SHADOWED_REG_OFFSET;
break;
case kDifAlertHandlerClassB:
- acc_offset = ALERT_HANDLER_CLASSB_ACCUM_THRESH_REG_OFFSET;
+ acc_offset = ALERT_HANDLER_CLASSB_ACCUM_THRESH_SHADOWED_REG_OFFSET;
break;
case kDifAlertHandlerClassC:
- acc_offset = ALERT_HANDLER_CLASSC_ACCUM_THRESH_REG_OFFSET;
+ acc_offset = ALERT_HANDLER_CLASSC_ACCUM_THRESH_SHADOWED_REG_OFFSET;
break;
case kDifAlertHandlerClassD:
- acc_offset = ALERT_HANDLER_CLASSD_ACCUM_THRESH_REG_OFFSET;
+ acc_offset = ALERT_HANDLER_CLASSD_ACCUM_THRESH_SHADOWED_REG_OFFSET;
break;
default:
return false;
}
- mmio_region_write32(handler->params.base_addr, acc_offset,
- class->accumulator_threshold);
+ mmio_region_write32_shadowed(handler->params.base_addr, acc_offset,
+ class->accumulator_threshold);
// Configure the class IRQ deadline.
ptrdiff_t deadline_offset;
switch (class->alert_class) {
case kDifAlertHandlerClassA:
- deadline_offset = ALERT_HANDLER_CLASSA_TIMEOUT_CYC_REG_OFFSET;
+ deadline_offset = ALERT_HANDLER_CLASSA_TIMEOUT_CYC_SHADOWED_REG_OFFSET;
break;
case kDifAlertHandlerClassB:
- deadline_offset = ALERT_HANDLER_CLASSB_TIMEOUT_CYC_REG_OFFSET;
+ deadline_offset = ALERT_HANDLER_CLASSB_TIMEOUT_CYC_SHADOWED_REG_OFFSET;
break;
case kDifAlertHandlerClassC:
- deadline_offset = ALERT_HANDLER_CLASSC_TIMEOUT_CYC_REG_OFFSET;
+ deadline_offset = ALERT_HANDLER_CLASSC_TIMEOUT_CYC_SHADOWED_REG_OFFSET;
break;
case kDifAlertHandlerClassD:
- deadline_offset = ALERT_HANDLER_CLASSD_TIMEOUT_CYC_REG_OFFSET;
+ deadline_offset = ALERT_HANDLER_CLASSD_TIMEOUT_CYC_SHADOWED_REG_OFFSET;
break;
default:
return false;
}
- mmio_region_write32(handler->params.base_addr, deadline_offset,
- class->irq_deadline_cycles);
+ mmio_region_write32_shadowed(handler->params.base_addr, deadline_offset,
+ class->irq_deadline_cycles);
return true;
}
@@ -347,38 +367,37 @@
for (int i = 0; i < class->phase_durations_len; ++i) {
// To save on writing a fairly ridiculous `if` chain, we use a lookup table
// that leverages the numeric values of enum constants.
- static const ptrdiff_t
- kRegOffsets[ALERT_HANDLER_PARAM_N_CLASSES]
- [ALERT_HANDLER_PARAM_N_PHASES] = {
- [kDifAlertHandlerClassA] =
- {
- ALERT_HANDLER_CLASSA_PHASE0_CYC_REG_OFFSET,
- ALERT_HANDLER_CLASSA_PHASE1_CYC_REG_OFFSET,
- ALERT_HANDLER_CLASSA_PHASE2_CYC_REG_OFFSET,
- ALERT_HANDLER_CLASSA_PHASE3_CYC_REG_OFFSET,
- },
- [kDifAlertHandlerClassB] =
- {
- ALERT_HANDLER_CLASSB_PHASE0_CYC_REG_OFFSET,
- ALERT_HANDLER_CLASSB_PHASE1_CYC_REG_OFFSET,
- ALERT_HANDLER_CLASSB_PHASE2_CYC_REG_OFFSET,
- ALERT_HANDLER_CLASSB_PHASE3_CYC_REG_OFFSET,
- },
- [kDifAlertHandlerClassC] =
- {
- ALERT_HANDLER_CLASSC_PHASE0_CYC_REG_OFFSET,
- ALERT_HANDLER_CLASSC_PHASE1_CYC_REG_OFFSET,
- ALERT_HANDLER_CLASSC_PHASE2_CYC_REG_OFFSET,
- ALERT_HANDLER_CLASSC_PHASE3_CYC_REG_OFFSET,
- },
- [kDifAlertHandlerClassD] =
- {
- ALERT_HANDLER_CLASSD_PHASE0_CYC_REG_OFFSET,
- ALERT_HANDLER_CLASSD_PHASE1_CYC_REG_OFFSET,
- ALERT_HANDLER_CLASSD_PHASE2_CYC_REG_OFFSET,
- ALERT_HANDLER_CLASSD_PHASE3_CYC_REG_OFFSET,
- },
- };
+ static const ptrdiff_t kRegOffsets
+ [ALERT_HANDLER_PARAM_N_CLASSES][ALERT_HANDLER_PARAM_N_PHASES] = {
+ [kDifAlertHandlerClassA] =
+ {
+ ALERT_HANDLER_CLASSA_PHASE0_CYC_SHADOWED_REG_OFFSET,
+ ALERT_HANDLER_CLASSA_PHASE1_CYC_SHADOWED_REG_OFFSET,
+ ALERT_HANDLER_CLASSA_PHASE2_CYC_SHADOWED_REG_OFFSET,
+ ALERT_HANDLER_CLASSA_PHASE3_CYC_SHADOWED_REG_OFFSET,
+ },
+ [kDifAlertHandlerClassB] =
+ {
+ ALERT_HANDLER_CLASSB_PHASE0_CYC_SHADOWED_REG_OFFSET,
+ ALERT_HANDLER_CLASSB_PHASE1_CYC_SHADOWED_REG_OFFSET,
+ ALERT_HANDLER_CLASSB_PHASE2_CYC_SHADOWED_REG_OFFSET,
+ ALERT_HANDLER_CLASSB_PHASE3_CYC_SHADOWED_REG_OFFSET,
+ },
+ [kDifAlertHandlerClassC] =
+ {
+ ALERT_HANDLER_CLASSC_PHASE0_CYC_SHADOWED_REG_OFFSET,
+ ALERT_HANDLER_CLASSC_PHASE1_CYC_SHADOWED_REG_OFFSET,
+ ALERT_HANDLER_CLASSC_PHASE2_CYC_SHADOWED_REG_OFFSET,
+ ALERT_HANDLER_CLASSC_PHASE3_CYC_SHADOWED_REG_OFFSET,
+ },
+ [kDifAlertHandlerClassD] =
+ {
+ ALERT_HANDLER_CLASSD_PHASE0_CYC_SHADOWED_REG_OFFSET,
+ ALERT_HANDLER_CLASSD_PHASE1_CYC_SHADOWED_REG_OFFSET,
+ ALERT_HANDLER_CLASSD_PHASE2_CYC_SHADOWED_REG_OFFSET,
+ ALERT_HANDLER_CLASSD_PHASE3_CYC_SHADOWED_REG_OFFSET,
+ },
+ };
if (class->alert_class >= ALERT_HANDLER_PARAM_N_CLASSES) {
return false;
@@ -394,8 +413,8 @@
kRegOffsets[class->alert_class]
[phase - kDifAlertHandlerClassStatePhase0];
- mmio_region_write32(handler->params.base_addr, reg_offset,
- class->phase_durations[i].cycles);
+ mmio_region_write32_shadowed(handler->params.base_addr, reg_offset,
+ class->phase_durations[i].cycles);
}
return true;
@@ -409,7 +428,7 @@
// Check that the provided ping timeout actually fits in the timeout register,
// which is smaller than a native word length.
if (config.ping_timeout >
- ALERT_HANDLER_PING_TIMEOUT_CYC_PING_TIMEOUT_CYC_MASK) {
+ ALERT_HANDLER_PING_TIMEOUT_CYC_SHADOWED_PING_TIMEOUT_CYC_SHADOWED_MASK) {
return kDifAlertHandlerConfigBadArg;
}
if (config.classes == NULL && config.classes_len != 0) {
@@ -442,11 +461,12 @@
}
uint32_t ping_timeout_reg = bitfield_field32_write(
- 0, ALERT_HANDLER_PING_TIMEOUT_CYC_PING_TIMEOUT_CYC_FIELD,
+ 0,
+ ALERT_HANDLER_PING_TIMEOUT_CYC_SHADOWED_PING_TIMEOUT_CYC_SHADOWED_FIELD,
config.ping_timeout);
- mmio_region_write32(handler->params.base_addr,
- ALERT_HANDLER_PING_TIMEOUT_CYC_REG_OFFSET,
- ping_timeout_reg);
+ mmio_region_write32_shadowed(
+ handler->params.base_addr,
+ ALERT_HANDLER_PING_TIMEOUT_CYC_SHADOWED_REG_OFFSET, ping_timeout_reg);
return kDifAlertHandlerConfigOk;
}
@@ -458,9 +478,10 @@
}
uint32_t reg = bitfield_bit32_write(
- 1, ALERT_HANDLER_PING_TIMER_EN_PING_TIMER_EN_BIT, true);
- mmio_region_write32(handler->params.base_addr,
- ALERT_HANDLER_PING_TIMER_EN_REG_OFFSET, reg);
+ 1, ALERT_HANDLER_PING_TIMER_EN_SHADOWED_PING_TIMER_EN_SHADOWED_BIT, true);
+ mmio_region_write32_shadowed(handler->params.base_addr,
+ ALERT_HANDLER_PING_TIMER_EN_SHADOWED_REG_OFFSET,
+ reg);
return kDifAlertHandlerOk;
}
@@ -471,10 +492,11 @@
return kDifAlertHandlerBadArg;
}
- uint32_t reg = mmio_region_read32(handler->params.base_addr,
- ALERT_HANDLER_PING_TIMER_EN_REG_OFFSET);
- *is_locked =
- bitfield_bit32_read(reg, ALERT_HANDLER_PING_TIMER_EN_PING_TIMER_EN_BIT);
+ uint32_t reg =
+ mmio_region_read32(handler->params.base_addr,
+ ALERT_HANDLER_PING_TIMER_EN_SHADOWED_REG_OFFSET);
+ *is_locked = bitfield_bit32_read(
+ reg, ALERT_HANDLER_PING_TIMER_EN_SHADOWED_PING_TIMER_EN_SHADOWED_BIT);
return kDifAlertHandlerOk;
}
@@ -679,6 +701,12 @@
case kDifAlertHandlerLocalAlertEscalationIntegrityFail:
*index = ALERT_HANDLER_LOC_ALERT_CAUSE_3_LA_3_BIT;
break;
+ case kDifAlertHandlerLocalAlertShadowedUpdateError:
+ *index = ALERT_HANDLER_LOC_ALERT_CAUSE_4_LA_4_BIT;
+ break;
+ case kDifAlertHandlerLocalAlertShadowedStorageError:
+ *index = ALERT_HANDLER_LOC_ALERT_CAUSE_5_LA_5_BIT;
+ break;
default:
return false;
}
diff --git a/sw/device/lib/dif/dif_alert_handler.h b/sw/device/lib/dif/dif_alert_handler.h
index 3cec0a9..8079a0b 100644
--- a/sw/device/lib/dif/dif_alert_handler.h
+++ b/sw/device/lib/dif/dif_alert_handler.h
@@ -186,6 +186,8 @@
kDifAlertHandlerLocalAlertEscalationPingFail,
kDifAlertHandlerLocalAlertAlertIntegrityFail,
kDifAlertHandlerLocalAlertEscalationIntegrityFail,
+ kDifAlertHandlerLocalAlertShadowedUpdateError,
+ kDifAlertHandlerLocalAlertShadowedStorageError,
} dif_alert_handler_local_alert_t;
/**
diff --git a/sw/device/lib/dif/dif_alert_handler_unittest.cc b/sw/device/lib/dif/dif_alert_handler_unittest.cc
index e342389..a352dd6 100644
--- a/sw/device/lib/dif/dif_alert_handler_unittest.cc
+++ b/sw/device/lib/dif/dif_alert_handler_unittest.cc
@@ -98,7 +98,7 @@
.ping_timeout = 0,
};
- EXPECT_READ32(ALERT_HANDLER_PING_TIMER_EN_REG_OFFSET, 1);
+ EXPECT_READ32(ALERT_HANDLER_PING_TIMER_EN_SHADOWED_REG_OFFSET, 1);
EXPECT_EQ(dif_alert_handler_configure(&handler_, config),
kDifAlertHandlerConfigLocked);
@@ -109,12 +109,15 @@
.ping_timeout = 50,
};
- EXPECT_READ32(ALERT_HANDLER_PING_TIMER_EN_REG_OFFSET,
- {{ALERT_HANDLER_PING_TIMER_EN_PING_TIMER_EN_BIT, false}});
+ EXPECT_READ32(
+ ALERT_HANDLER_PING_TIMER_EN_SHADOWED_REG_OFFSET,
+ {{ALERT_HANDLER_PING_TIMER_EN_SHADOWED_PING_TIMER_EN_SHADOWED_BIT,
+ false}});
- EXPECT_WRITE32(
- ALERT_HANDLER_PING_TIMEOUT_CYC_REG_OFFSET,
- {{ALERT_HANDLER_PING_TIMEOUT_CYC_PING_TIMEOUT_CYC_OFFSET, 50}});
+ EXPECT_WRITE32_SHADOWED(
+ ALERT_HANDLER_PING_TIMEOUT_CYC_SHADOWED_REG_OFFSET,
+ {{ALERT_HANDLER_PING_TIMEOUT_CYC_SHADOWED_PING_TIMEOUT_CYC_SHADOWED_OFFSET,
+ 50}});
EXPECT_EQ(dif_alert_handler_configure(&handler_, config),
kDifAlertHandlerConfigOk);
@@ -122,7 +125,9 @@
TEST_F(ConfigTest, TimeoutTooBig) {
dif_alert_handler_config_t config = {
- .ping_timeout = ALERT_HANDLER_PING_TIMEOUT_CYC_PING_TIMEOUT_CYC_MASK + 1,
+ .ping_timeout =
+ ALERT_HANDLER_PING_TIMEOUT_CYC_SHADOWED_PING_TIMEOUT_CYC_SHADOWED_MASK +
+ 1,
};
EXPECT_EQ(dif_alert_handler_configure(&handler_, config),
@@ -207,8 +212,9 @@
// .classes_len = classes.size(),
// };
-// EXPECT_READ32(ALERT_HANDLER_PING_TIMER_EN_REG_OFFSET,
-// {{ALERT_HANDLER_PING_TIMER_EN_PING_TIMER_EN_BIT, true}});
+// EXPECT_READ32(ALERT_HANDLER_PING_TIMER_EN_SHADOWED_REG_OFFSET,
+// {{ALERT_HANDLER_PING_TIMER_EN_SHADOWED_PING_TIMER_EN_SHADOWED_BIT,
+// true}});
// // Unfortunately, we can't use EXPECT_MASK for these reads and writes,
// // since there are not sequenced exactly.
@@ -318,8 +324,9 @@
// EXPECT_WRITE32(ALERT_HANDLER_CLASSB_PHASE3_CYC_REG_OFFSET, 150000);
// EXPECT_WRITE32(
-// ALERT_HANDLER_PING_TIMEOUT_CYC_REG_OFFSET,
-// {{ALERT_HANDLER_PING_TIMEOUT_CYC_PING_TIMEOUT_CYC_OFFSET, 50}});
+// ALERT_HANDLER_PING_TIMEOUT_CYC_SHADOWED_REG_OFFSET,
+// {{ALERT_HANDLER_PING_TIMEOUT_CYC_SHADOWED_PING_TIMEOUT_CYC_SHADOWED_OFFSET,
+// 50}});
// EXPECT_EQ(dif_alert_handler_configure(&handler_, config),
// kDifAlertHandlerConfigOk);
@@ -571,20 +578,26 @@
TEST_F(LockTest, IsLocked) {
bool flag;
- EXPECT_READ32(ALERT_HANDLER_PING_TIMER_EN_REG_OFFSET,
- {{ALERT_HANDLER_PING_TIMER_EN_PING_TIMER_EN_BIT, false}});
+ EXPECT_READ32(
+ ALERT_HANDLER_PING_TIMER_EN_SHADOWED_REG_OFFSET,
+ {{ALERT_HANDLER_PING_TIMER_EN_SHADOWED_PING_TIMER_EN_SHADOWED_BIT,
+ false}});
EXPECT_EQ(dif_alert_handler_is_locked(&handler_, &flag), kDifAlertHandlerOk);
EXPECT_FALSE(flag);
- EXPECT_READ32(ALERT_HANDLER_PING_TIMER_EN_REG_OFFSET,
- {{ALERT_HANDLER_PING_TIMER_EN_PING_TIMER_EN_BIT, true}});
+ EXPECT_READ32(
+ ALERT_HANDLER_PING_TIMER_EN_SHADOWED_REG_OFFSET,
+ {{ALERT_HANDLER_PING_TIMER_EN_SHADOWED_PING_TIMER_EN_SHADOWED_BIT,
+ true}});
EXPECT_EQ(dif_alert_handler_is_locked(&handler_, &flag), kDifAlertHandlerOk);
EXPECT_TRUE(flag);
}
TEST_F(LockTest, Lock) {
- EXPECT_WRITE32(ALERT_HANDLER_PING_TIMER_EN_REG_OFFSET,
- {{ALERT_HANDLER_PING_TIMER_EN_PING_TIMER_EN_BIT, true}});
+ EXPECT_WRITE32_SHADOWED(
+ ALERT_HANDLER_PING_TIMER_EN_SHADOWED_REG_OFFSET,
+ {{ALERT_HANDLER_PING_TIMER_EN_SHADOWED_PING_TIMER_EN_SHADOWED_BIT,
+ true}});
EXPECT_EQ(dif_alert_handler_lock(&handler_), kDifAlertHandlerOk);
}
diff --git a/sw/device/silicon_creator/lib/drivers/alert.c b/sw/device/silicon_creator/lib/drivers/alert.c
index 0ff4881..63aa050 100644
--- a/sw/device/silicon_creator/lib/drivers/alert.c
+++ b/sw/device/silicon_creator/lib/drivers/alert.c
@@ -17,27 +17,31 @@
rom_error_t alert_configure(size_t index, alert_class_t cls,
alert_enable_t enabled) {
- if (index >= ALERT_HANDLER_ALERT_CLASS_MULTIREG_COUNT) {
+ if (index >= ALERT_HANDLER_ALERT_CLASS_SHADOWED_MULTIREG_COUNT) {
return kErrorAlertBadIndex;
}
index *= 4;
switch (cls) {
case kAlertClassA:
- abs_mmio_write32(kBase + ALERT_HANDLER_ALERT_CLASS_0_REG_OFFSET + index,
- ALERT_HANDLER_ALERT_CLASS_0_CLASS_A_0_VALUE_CLASSA);
+ abs_mmio_write32_shadowed(
+ kBase + ALERT_HANDLER_ALERT_CLASS_SHADOWED_0_REG_OFFSET + index,
+ ALERT_HANDLER_ALERT_CLASS_SHADOWED_0_CLASS_A_0_VALUE_CLASSA);
break;
case kAlertClassB:
- abs_mmio_write32(kBase + ALERT_HANDLER_ALERT_CLASS_0_REG_OFFSET + index,
- ALERT_HANDLER_ALERT_CLASS_0_CLASS_A_0_VALUE_CLASSB);
+ abs_mmio_write32_shadowed(
+ kBase + ALERT_HANDLER_ALERT_CLASS_SHADOWED_0_REG_OFFSET + index,
+ ALERT_HANDLER_ALERT_CLASS_SHADOWED_0_CLASS_A_0_VALUE_CLASSB);
break;
case kAlertClassC:
- abs_mmio_write32(kBase + ALERT_HANDLER_ALERT_CLASS_0_REG_OFFSET + index,
- ALERT_HANDLER_ALERT_CLASS_0_CLASS_A_0_VALUE_CLASSC);
+ abs_mmio_write32_shadowed(
+ kBase + ALERT_HANDLER_ALERT_CLASS_SHADOWED_0_REG_OFFSET + index,
+ ALERT_HANDLER_ALERT_CLASS_SHADOWED_0_CLASS_A_0_VALUE_CLASSC);
break;
case kAlertClassD:
- abs_mmio_write32(kBase + ALERT_HANDLER_ALERT_CLASS_0_REG_OFFSET + index,
- ALERT_HANDLER_ALERT_CLASS_0_CLASS_A_0_VALUE_CLASSD);
+ abs_mmio_write32_shadowed(
+ kBase + ALERT_HANDLER_ALERT_CLASS_SHADOWED_0_REG_OFFSET + index,
+ ALERT_HANDLER_ALERT_CLASS_SHADOWED_0_CLASS_A_0_VALUE_CLASSD);
break;
case kAlertClassX:
return kErrorOk;
@@ -50,12 +54,14 @@
break;
case kAlertEnableLocked:
// Enable, then lock.
- abs_mmio_write32(kBase + ALERT_HANDLER_ALERT_EN_0_REG_OFFSET + index, 1);
+ abs_mmio_write32_shadowed(
+ kBase + ALERT_HANDLER_ALERT_EN_SHADOWED_0_REG_OFFSET + index, 1);
abs_mmio_write32(kBase + ALERT_HANDLER_ALERT_REGWEN_0_REG_OFFSET + index,
0);
break;
case kAlertEnableEnabled:
- abs_mmio_write32(kBase + ALERT_HANDLER_ALERT_EN_0_REG_OFFSET + index, 1);
+ abs_mmio_write32_shadowed(
+ kBase + ALERT_HANDLER_ALERT_EN_SHADOWED_0_REG_OFFSET + index, 1);
break;
default:
return kErrorAlertBadEnable;
@@ -66,31 +72,31 @@
rom_error_t alert_local_configure(size_t index, alert_class_t cls,
alert_enable_t enabled) {
- if (index >= ALERT_HANDLER_LOC_ALERT_CLASS_MULTIREG_COUNT) {
+ if (index >= ALERT_HANDLER_LOC_ALERT_CLASS_SHADOWED_MULTIREG_COUNT) {
return kErrorAlertBadIndex;
}
index *= 4;
switch (cls) {
case kAlertClassA:
- abs_mmio_write32(
- kBase + ALERT_HANDLER_LOC_ALERT_CLASS_0_REG_OFFSET + index,
- ALERT_HANDLER_LOC_ALERT_CLASS_0_CLASS_LA_0_VALUE_CLASSA);
+ abs_mmio_write32_shadowed(
+ kBase + ALERT_HANDLER_LOC_ALERT_CLASS_SHADOWED_0_REG_OFFSET + index,
+ ALERT_HANDLER_LOC_ALERT_CLASS_SHADOWED_0_CLASS_LA_0_VALUE_CLASSA);
break;
case kAlertClassB:
- abs_mmio_write32(
- kBase + ALERT_HANDLER_LOC_ALERT_CLASS_0_REG_OFFSET + index,
- ALERT_HANDLER_LOC_ALERT_CLASS_0_CLASS_LA_0_VALUE_CLASSB);
+ abs_mmio_write32_shadowed(
+ kBase + ALERT_HANDLER_LOC_ALERT_CLASS_SHADOWED_0_REG_OFFSET + index,
+ ALERT_HANDLER_LOC_ALERT_CLASS_SHADOWED_0_CLASS_LA_0_VALUE_CLASSB);
break;
case kAlertClassC:
- abs_mmio_write32(
- kBase + ALERT_HANDLER_LOC_ALERT_CLASS_0_REG_OFFSET + index,
- ALERT_HANDLER_LOC_ALERT_CLASS_0_CLASS_LA_0_VALUE_CLASSC);
+ abs_mmio_write32_shadowed(
+ kBase + ALERT_HANDLER_LOC_ALERT_CLASS_SHADOWED_0_REG_OFFSET + index,
+ ALERT_HANDLER_LOC_ALERT_CLASS_SHADOWED_0_CLASS_LA_0_VALUE_CLASSC);
break;
case kAlertClassD:
- abs_mmio_write32(
- kBase + ALERT_HANDLER_LOC_ALERT_CLASS_0_REG_OFFSET + index,
- ALERT_HANDLER_LOC_ALERT_CLASS_0_CLASS_LA_0_VALUE_CLASSD);
+ abs_mmio_write32_shadowed(
+ kBase + ALERT_HANDLER_LOC_ALERT_CLASS_SHADOWED_0_REG_OFFSET + index,
+ ALERT_HANDLER_LOC_ALERT_CLASS_SHADOWED_0_CLASS_LA_0_VALUE_CLASSD);
break;
case kAlertClassX:
return kErrorOk;
@@ -103,14 +109,14 @@
break;
case kAlertEnableLocked:
// Enable, then lock.
- abs_mmio_write32(kBase + ALERT_HANDLER_LOC_ALERT_EN_0_REG_OFFSET + index,
- 1);
+ abs_mmio_write32_shadowed(
+ kBase + ALERT_HANDLER_LOC_ALERT_EN_SHADOWED_0_REG_OFFSET + index, 1);
abs_mmio_write32(
kBase + ALERT_HANDLER_LOC_ALERT_REGWEN_0_REG_OFFSET + index, 0);
break;
case kAlertEnableEnabled:
- abs_mmio_write32(kBase + ALERT_HANDLER_LOC_ALERT_EN_0_REG_OFFSET + index,
- 1);
+ abs_mmio_write32_shadowed(
+ kBase + ALERT_HANDLER_LOC_ALERT_EN_SHADOWED_0_REG_OFFSET + index, 1);
break;
default:
return kErrorAlertBadEnable;
@@ -125,30 +131,34 @@
uint32_t reg = 0;
// Each escalation signal should be asserted in its corresponding phase.
- reg = bitfield_field32_write(reg, ALERT_HANDLER_CLASSA_CTRL_MAP_E0_FIELD, 0);
- reg = bitfield_field32_write(reg, ALERT_HANDLER_CLASSA_CTRL_MAP_E1_FIELD, 1);
- reg = bitfield_field32_write(reg, ALERT_HANDLER_CLASSA_CTRL_MAP_E2_FIELD, 2);
- reg = bitfield_field32_write(reg, ALERT_HANDLER_CLASSA_CTRL_MAP_E3_FIELD, 3);
+ reg = bitfield_field32_write(
+ reg, ALERT_HANDLER_CLASSA_CTRL_SHADOWED_MAP_E0_FIELD, 0);
+ reg = bitfield_field32_write(
+ reg, ALERT_HANDLER_CLASSA_CTRL_SHADOWED_MAP_E1_FIELD, 1);
+ reg = bitfield_field32_write(
+ reg, ALERT_HANDLER_CLASSA_CTRL_SHADOWED_MAP_E2_FIELD, 2);
+ reg = bitfield_field32_write(
+ reg, ALERT_HANDLER_CLASSA_CTRL_SHADOWED_MAP_E3_FIELD, 3);
// All of the alert class register blocks are identical but at different
// offsets. We'll treat everything like Class A, but add in the offset
// to the other classes.
switch (cls) {
case kAlertClassA:
- offset = ALERT_HANDLER_CLASSA_CTRL_REG_OFFSET -
- ALERT_HANDLER_CLASSA_CTRL_REG_OFFSET;
+ offset = ALERT_HANDLER_CLASSA_CTRL_SHADOWED_REG_OFFSET -
+ ALERT_HANDLER_CLASSA_CTRL_SHADOWED_REG_OFFSET;
break;
case kAlertClassB:
- offset = ALERT_HANDLER_CLASSB_CTRL_REG_OFFSET -
- ALERT_HANDLER_CLASSA_CTRL_REG_OFFSET;
+ offset = ALERT_HANDLER_CLASSB_CTRL_SHADOWED_REG_OFFSET -
+ ALERT_HANDLER_CLASSA_CTRL_SHADOWED_REG_OFFSET;
break;
case kAlertClassC:
- offset = ALERT_HANDLER_CLASSC_CTRL_REG_OFFSET -
- ALERT_HANDLER_CLASSA_CTRL_REG_OFFSET;
+ offset = ALERT_HANDLER_CLASSC_CTRL_SHADOWED_REG_OFFSET -
+ ALERT_HANDLER_CLASSA_CTRL_SHADOWED_REG_OFFSET;
break;
case kAlertClassD:
- offset = ALERT_HANDLER_CLASSD_CTRL_REG_OFFSET -
- ALERT_HANDLER_CLASSA_CTRL_REG_OFFSET;
+ offset = ALERT_HANDLER_CLASSD_CTRL_SHADOWED_REG_OFFSET -
+ ALERT_HANDLER_CLASSA_CTRL_SHADOWED_REG_OFFSET;
break;
case kAlertClassX:
default:
@@ -156,10 +166,12 @@
}
switch (config->enabled) {
case kAlertEnableLocked:
- reg = bitfield_bit32_write(reg, ALERT_HANDLER_CLASSA_CTRL_LOCK_BIT, true);
+ reg = bitfield_bit32_write(
+ reg, ALERT_HANDLER_CLASSA_CTRL_SHADOWED_LOCK_BIT, true);
FALLTHROUGH_INTENDED;
case kAlertEnableEnabled:
- reg = bitfield_bit32_write(reg, ALERT_HANDLER_CLASSA_CTRL_EN_BIT, true);
+ reg = bitfield_bit32_write(reg, ALERT_HANDLER_CLASSA_CTRL_SHADOWED_EN_BIT,
+ true);
FALLTHROUGH_INTENDED;
case kAlertEnableNone:
break;
@@ -168,20 +180,20 @@
}
switch (config->escalation) {
case kAlertEscalatePhase3:
- reg =
- bitfield_bit32_write(reg, ALERT_HANDLER_CLASSA_CTRL_EN_E3_BIT, true);
+ reg = bitfield_bit32_write(
+ reg, ALERT_HANDLER_CLASSA_CTRL_SHADOWED_EN_E3_BIT, true);
FALLTHROUGH_INTENDED;
case kAlertEscalatePhase2:
- reg =
- bitfield_bit32_write(reg, ALERT_HANDLER_CLASSA_CTRL_EN_E2_BIT, true);
+ reg = bitfield_bit32_write(
+ reg, ALERT_HANDLER_CLASSA_CTRL_SHADOWED_EN_E2_BIT, true);
FALLTHROUGH_INTENDED;
case kAlertEscalatePhase1:
- reg =
- bitfield_bit32_write(reg, ALERT_HANDLER_CLASSA_CTRL_EN_E1_BIT, true);
+ reg = bitfield_bit32_write(
+ reg, ALERT_HANDLER_CLASSA_CTRL_SHADOWED_EN_E1_BIT, true);
FALLTHROUGH_INTENDED;
case kAlertEscalatePhase0:
- reg =
- bitfield_bit32_write(reg, ALERT_HANDLER_CLASSA_CTRL_EN_E0_BIT, true);
+ reg = bitfield_bit32_write(
+ reg, ALERT_HANDLER_CLASSA_CTRL_SHADOWED_EN_E0_BIT, true);
FALLTHROUGH_INTENDED;
case kAlertEscalateNone:
break;
@@ -189,15 +201,18 @@
return kErrorAlertBadEscalation;
}
- abs_mmio_write32(kBase + ALERT_HANDLER_CLASSA_CTRL_REG_OFFSET + offset, reg);
- abs_mmio_write32(
- kBase + ALERT_HANDLER_CLASSA_ACCUM_THRESH_REG_OFFSET + offset,
+ abs_mmio_write32_shadowed(
+ kBase + ALERT_HANDLER_CLASSA_CTRL_SHADOWED_REG_OFFSET + offset, reg);
+ abs_mmio_write32_shadowed(
+ kBase + ALERT_HANDLER_CLASSA_ACCUM_THRESH_SHADOWED_REG_OFFSET + offset,
config->accum_threshold);
- abs_mmio_write32(kBase + ALERT_HANDLER_CLASSA_TIMEOUT_CYC_REG_OFFSET + offset,
- config->timeout_cycles);
+ abs_mmio_write32_shadowed(
+ kBase + ALERT_HANDLER_CLASSA_TIMEOUT_CYC_SHADOWED_REG_OFFSET + offset,
+ config->timeout_cycles);
for (size_t i = 0; i < 4; ++i) {
- abs_mmio_write32(
- kBase + ALERT_HANDLER_CLASSA_PHASE0_CYC_REG_OFFSET + offset + i * 4,
+ abs_mmio_write32_shadowed(
+ kBase + ALERT_HANDLER_CLASSA_PHASE0_CYC_SHADOWED_REG_OFFSET + offset +
+ i * 4,
config->phase_cycles[i]);
}
if (config->enabled == kAlertEnableLocked) {
@@ -210,7 +225,8 @@
rom_error_t alert_ping_enable(void) {
// Enable the ping timer, then lock it.
- abs_mmio_write32(kBase + ALERT_HANDLER_PING_TIMER_EN_REG_OFFSET, 1);
+ abs_mmio_write32_shadowed(
+ kBase + ALERT_HANDLER_PING_TIMER_EN_SHADOWED_REG_OFFSET, 1);
abs_mmio_write32(kBase + ALERT_HANDLER_PING_TIMER_REGWEN_REG_OFFSET, 0);
return kErrorOk;
}
diff --git a/sw/device/silicon_creator/lib/drivers/alert_unittest.cc b/sw/device/silicon_creator/lib/drivers/alert_unittest.cc
index 0f37e9c..64607cb 100644
--- a/sw/device/silicon_creator/lib/drivers/alert_unittest.cc
+++ b/sw/device/silicon_creator/lib/drivers/alert_unittest.cc
@@ -23,7 +23,7 @@
class InitTest : public AlertTest {};
TEST_F(InitTest, AlertConfigureAlertBadIndex) {
- EXPECT_EQ(alert_configure(ALERT_HANDLER_ALERT_CLASS_MULTIREG_COUNT,
+ EXPECT_EQ(alert_configure(ALERT_HANDLER_ALERT_CLASS_SHADOWED_MULTIREG_COUNT,
kAlertClassA, kAlertEnableNone),
kErrorAlertBadIndex);
}
@@ -36,7 +36,8 @@
TEST_F(InitTest, AlertConfigureAlertBadEnable) {
// We expect the alert to get configured as class A, but then to
// experience an error when evaluating the enable parameter.
- EXPECT_ABS_WRITE32(mmio_, base_ + ALERT_HANDLER_ALERT_CLASS_0_REG_OFFSET, 0);
+ EXPECT_ABS_WRITE32_SHADOWED(
+ mmio_, base_ + ALERT_HANDLER_ALERT_CLASS_SHADOWED_0_REG_OFFSET, 0);
EXPECT_EQ(alert_configure(0, kAlertClassA, (alert_enable_t)-1),
kErrorAlertBadEnable);
}
@@ -50,58 +51,70 @@
}
TEST_F(InitTest, AlertConfigure0AsClassA) {
- EXPECT_ABS_WRITE32(mmio_, base_ + ALERT_HANDLER_ALERT_CLASS_0_REG_OFFSET, 0);
- EXPECT_ABS_WRITE32(mmio_, base_ + ALERT_HANDLER_ALERT_EN_0_REG_OFFSET, 1);
+ EXPECT_ABS_WRITE32_SHADOWED(
+ mmio_, base_ + ALERT_HANDLER_ALERT_CLASS_SHADOWED_0_REG_OFFSET, 0);
+ EXPECT_ABS_WRITE32_SHADOWED(
+ mmio_, base_ + ALERT_HANDLER_ALERT_EN_SHADOWED_0_REG_OFFSET, 1);
EXPECT_EQ(alert_configure(0, kAlertClassA, kAlertEnableEnabled), kErrorOk);
}
TEST_F(InitTest, LocalAlertConfigure0AsClassA) {
- EXPECT_ABS_WRITE32(mmio_, base_ + ALERT_HANDLER_LOC_ALERT_CLASS_0_REG_OFFSET,
- 0);
- EXPECT_ABS_WRITE32(mmio_, base_ + ALERT_HANDLER_LOC_ALERT_EN_0_REG_OFFSET, 1);
+ EXPECT_ABS_WRITE32_SHADOWED(
+ mmio_, base_ + ALERT_HANDLER_LOC_ALERT_CLASS_SHADOWED_0_REG_OFFSET, 0);
+ EXPECT_ABS_WRITE32_SHADOWED(
+ mmio_, base_ + ALERT_HANDLER_LOC_ALERT_EN_SHADOWED_0_REG_OFFSET, 1);
EXPECT_EQ(alert_local_configure(0, kAlertClassA, kAlertEnableEnabled),
kErrorOk);
}
TEST_F(InitTest, AlertConfigure1AsClassB) {
- EXPECT_ABS_WRITE32(mmio_, base_ + ALERT_HANDLER_ALERT_CLASS_1_REG_OFFSET, 1);
- EXPECT_ABS_WRITE32(mmio_, base_ + ALERT_HANDLER_ALERT_EN_1_REG_OFFSET, 1);
+ EXPECT_ABS_WRITE32_SHADOWED(
+ mmio_, base_ + ALERT_HANDLER_ALERT_CLASS_SHADOWED_1_REG_OFFSET, 1);
+ EXPECT_ABS_WRITE32_SHADOWED(
+ mmio_, base_ + ALERT_HANDLER_ALERT_EN_SHADOWED_1_REG_OFFSET, 1);
EXPECT_EQ(alert_configure(1, kAlertClassB, kAlertEnableEnabled), kErrorOk);
}
TEST_F(InitTest, LocalAlertConfigure1AsClassB) {
- EXPECT_ABS_WRITE32(mmio_, base_ + ALERT_HANDLER_LOC_ALERT_CLASS_1_REG_OFFSET,
- 1);
- EXPECT_ABS_WRITE32(mmio_, base_ + ALERT_HANDLER_LOC_ALERT_EN_1_REG_OFFSET, 1);
+ EXPECT_ABS_WRITE32_SHADOWED(
+ mmio_, base_ + ALERT_HANDLER_LOC_ALERT_CLASS_SHADOWED_1_REG_OFFSET, 1);
+ EXPECT_ABS_WRITE32_SHADOWED(
+ mmio_, base_ + ALERT_HANDLER_LOC_ALERT_EN_SHADOWED_1_REG_OFFSET, 1);
EXPECT_EQ(alert_local_configure(1, kAlertClassB, kAlertEnableEnabled),
kErrorOk);
}
TEST_F(InitTest, AlertConfigure2AsClassC) {
- EXPECT_ABS_WRITE32(mmio_, base_ + ALERT_HANDLER_ALERT_CLASS_2_REG_OFFSET, 2);
- EXPECT_ABS_WRITE32(mmio_, base_ + ALERT_HANDLER_ALERT_EN_2_REG_OFFSET, 1);
+ EXPECT_ABS_WRITE32_SHADOWED(
+ mmio_, base_ + ALERT_HANDLER_ALERT_CLASS_SHADOWED_2_REG_OFFSET, 2);
+ EXPECT_ABS_WRITE32_SHADOWED(
+ mmio_, base_ + ALERT_HANDLER_ALERT_EN_SHADOWED_2_REG_OFFSET, 1);
EXPECT_EQ(alert_configure(2, kAlertClassC, kAlertEnableEnabled), kErrorOk);
}
TEST_F(InitTest, LocalAlertConfigure2AsClassC) {
- EXPECT_ABS_WRITE32(mmio_, base_ + ALERT_HANDLER_LOC_ALERT_CLASS_2_REG_OFFSET,
- 2);
- EXPECT_ABS_WRITE32(mmio_, base_ + ALERT_HANDLER_LOC_ALERT_EN_2_REG_OFFSET, 1);
+ EXPECT_ABS_WRITE32_SHADOWED(
+ mmio_, base_ + ALERT_HANDLER_LOC_ALERT_CLASS_SHADOWED_2_REG_OFFSET, 2);
+ EXPECT_ABS_WRITE32_SHADOWED(
+ mmio_, base_ + ALERT_HANDLER_LOC_ALERT_EN_SHADOWED_2_REG_OFFSET, 1);
EXPECT_EQ(alert_local_configure(2, kAlertClassC, kAlertEnableEnabled),
kErrorOk);
}
TEST_F(InitTest, AlertConfigure3AsClassDLocked) {
- EXPECT_ABS_WRITE32(mmio_, base_ + ALERT_HANDLER_ALERT_CLASS_3_REG_OFFSET, 3);
- EXPECT_ABS_WRITE32(mmio_, base_ + ALERT_HANDLER_ALERT_EN_3_REG_OFFSET, 1);
+ EXPECT_ABS_WRITE32_SHADOWED(
+ mmio_, base_ + ALERT_HANDLER_ALERT_CLASS_SHADOWED_3_REG_OFFSET, 3);
+ EXPECT_ABS_WRITE32_SHADOWED(
+ mmio_, base_ + ALERT_HANDLER_ALERT_EN_SHADOWED_3_REG_OFFSET, 1);
EXPECT_ABS_WRITE32(mmio_, base_ + ALERT_HANDLER_ALERT_REGWEN_3_REG_OFFSET, 0);
EXPECT_EQ(alert_configure(3, kAlertClassD, kAlertEnableLocked), kErrorOk);
}
TEST_F(InitTest, LocalAlertConfigure3AsClassDLocked) {
- EXPECT_ABS_WRITE32(mmio_, base_ + ALERT_HANDLER_LOC_ALERT_CLASS_3_REG_OFFSET,
- 3);
- EXPECT_ABS_WRITE32(mmio_, base_ + ALERT_HANDLER_LOC_ALERT_EN_3_REG_OFFSET, 1);
+ EXPECT_ABS_WRITE32_SHADOWED(
+ mmio_, base_ + ALERT_HANDLER_LOC_ALERT_CLASS_SHADOWED_3_REG_OFFSET, 3);
+ EXPECT_ABS_WRITE32_SHADOWED(
+ mmio_, base_ + ALERT_HANDLER_LOC_ALERT_EN_SHADOWED_3_REG_OFFSET, 1);
EXPECT_ABS_WRITE32(mmio_, base_ + ALERT_HANDLER_LOC_ALERT_REGWEN_3_REG_OFFSET,
0);
EXPECT_EQ(alert_local_configure(3, kAlertClassD, kAlertEnableLocked),
@@ -121,31 +134,32 @@
.timeout_cycles = 2,
.phase_cycles = {1, 10, 100, 1000},
};
- EXPECT_ABS_WRITE32(mmio_, base_ + ALERT_HANDLER_CLASSA_CTRL_REG_OFFSET,
- {
- {ALERT_HANDLER_CLASSA_CTRL_EN_BIT, true},
- {ALERT_HANDLER_CLASSA_CTRL_LOCK_BIT, true},
- {ALERT_HANDLER_CLASSA_CTRL_EN_E3_BIT, true},
- {ALERT_HANDLER_CLASSA_CTRL_EN_E2_BIT, true},
- {ALERT_HANDLER_CLASSA_CTRL_EN_E1_BIT, true},
- {ALERT_HANDLER_CLASSA_CTRL_EN_E0_BIT, true},
- {ALERT_HANDLER_CLASSA_CTRL_MAP_E0_OFFSET, 0},
- {ALERT_HANDLER_CLASSA_CTRL_MAP_E1_OFFSET, 1},
- {ALERT_HANDLER_CLASSA_CTRL_MAP_E2_OFFSET, 2},
- {ALERT_HANDLER_CLASSA_CTRL_MAP_E3_OFFSET, 3},
- });
- EXPECT_ABS_WRITE32(mmio_,
- base_ + ALERT_HANDLER_CLASSA_ACCUM_THRESH_REG_OFFSET, 1);
- EXPECT_ABS_WRITE32(mmio_, base_ + ALERT_HANDLER_CLASSA_TIMEOUT_CYC_REG_OFFSET,
- 2);
- EXPECT_ABS_WRITE32(mmio_, base_ + ALERT_HANDLER_CLASSA_PHASE0_CYC_REG_OFFSET,
- 1);
- EXPECT_ABS_WRITE32(mmio_, base_ + ALERT_HANDLER_CLASSA_PHASE1_CYC_REG_OFFSET,
- 10);
- EXPECT_ABS_WRITE32(mmio_, base_ + ALERT_HANDLER_CLASSA_PHASE2_CYC_REG_OFFSET,
- 100);
- EXPECT_ABS_WRITE32(mmio_, base_ + ALERT_HANDLER_CLASSA_PHASE3_CYC_REG_OFFSET,
- 1000);
+ EXPECT_ABS_WRITE32_SHADOWED(
+ mmio_, base_ + ALERT_HANDLER_CLASSA_CTRL_SHADOWED_REG_OFFSET,
+ {
+ {ALERT_HANDLER_CLASSA_CTRL_SHADOWED_EN_BIT, true},
+ {ALERT_HANDLER_CLASSA_CTRL_SHADOWED_LOCK_BIT, true},
+ {ALERT_HANDLER_CLASSA_CTRL_SHADOWED_EN_E3_BIT, true},
+ {ALERT_HANDLER_CLASSA_CTRL_SHADOWED_EN_E2_BIT, true},
+ {ALERT_HANDLER_CLASSA_CTRL_SHADOWED_EN_E1_BIT, true},
+ {ALERT_HANDLER_CLASSA_CTRL_SHADOWED_EN_E0_BIT, true},
+ {ALERT_HANDLER_CLASSA_CTRL_SHADOWED_MAP_E0_OFFSET, 0},
+ {ALERT_HANDLER_CLASSA_CTRL_SHADOWED_MAP_E1_OFFSET, 1},
+ {ALERT_HANDLER_CLASSA_CTRL_SHADOWED_MAP_E2_OFFSET, 2},
+ {ALERT_HANDLER_CLASSA_CTRL_SHADOWED_MAP_E3_OFFSET, 3},
+ });
+ EXPECT_ABS_WRITE32_SHADOWED(
+ mmio_, base_ + ALERT_HANDLER_CLASSA_ACCUM_THRESH_SHADOWED_REG_OFFSET, 1);
+ EXPECT_ABS_WRITE32_SHADOWED(
+ mmio_, base_ + ALERT_HANDLER_CLASSA_TIMEOUT_CYC_SHADOWED_REG_OFFSET, 2);
+ EXPECT_ABS_WRITE32_SHADOWED(
+ mmio_, base_ + ALERT_HANDLER_CLASSA_PHASE0_CYC_SHADOWED_REG_OFFSET, 1);
+ EXPECT_ABS_WRITE32_SHADOWED(
+ mmio_, base_ + ALERT_HANDLER_CLASSA_PHASE1_CYC_SHADOWED_REG_OFFSET, 10);
+ EXPECT_ABS_WRITE32_SHADOWED(
+ mmio_, base_ + ALERT_HANDLER_CLASSA_PHASE2_CYC_SHADOWED_REG_OFFSET, 100);
+ EXPECT_ABS_WRITE32_SHADOWED(
+ mmio_, base_ + ALERT_HANDLER_CLASSA_PHASE3_CYC_SHADOWED_REG_OFFSET, 1000);
EXPECT_ABS_WRITE32(mmio_, base_ + ALERT_HANDLER_CLASSA_REGWEN_REG_OFFSET, 0);
EXPECT_EQ(alert_class_configure(kAlertClassA, &config), kErrorOk);
}
@@ -158,31 +172,32 @@
.timeout_cycles = 2,
.phase_cycles = {1, 10, 100, 1000},
};
- EXPECT_ABS_WRITE32(mmio_, base_ + ALERT_HANDLER_CLASSB_CTRL_REG_OFFSET,
- {
- {ALERT_HANDLER_CLASSA_CTRL_EN_BIT, true},
- {ALERT_HANDLER_CLASSA_CTRL_LOCK_BIT, false},
- {ALERT_HANDLER_CLASSA_CTRL_EN_E3_BIT, false},
- {ALERT_HANDLER_CLASSA_CTRL_EN_E2_BIT, true},
- {ALERT_HANDLER_CLASSA_CTRL_EN_E1_BIT, true},
- {ALERT_HANDLER_CLASSA_CTRL_EN_E0_BIT, true},
- {ALERT_HANDLER_CLASSA_CTRL_MAP_E0_OFFSET, 0},
- {ALERT_HANDLER_CLASSA_CTRL_MAP_E1_OFFSET, 1},
- {ALERT_HANDLER_CLASSA_CTRL_MAP_E2_OFFSET, 2},
- {ALERT_HANDLER_CLASSA_CTRL_MAP_E3_OFFSET, 3},
- });
- EXPECT_ABS_WRITE32(mmio_,
- base_ + ALERT_HANDLER_CLASSB_ACCUM_THRESH_REG_OFFSET, 1);
- EXPECT_ABS_WRITE32(mmio_, base_ + ALERT_HANDLER_CLASSB_TIMEOUT_CYC_REG_OFFSET,
- 2);
- EXPECT_ABS_WRITE32(mmio_, base_ + ALERT_HANDLER_CLASSB_PHASE0_CYC_REG_OFFSET,
- 1);
- EXPECT_ABS_WRITE32(mmio_, base_ + ALERT_HANDLER_CLASSB_PHASE1_CYC_REG_OFFSET,
- 10);
- EXPECT_ABS_WRITE32(mmio_, base_ + ALERT_HANDLER_CLASSB_PHASE2_CYC_REG_OFFSET,
- 100);
- EXPECT_ABS_WRITE32(mmio_, base_ + ALERT_HANDLER_CLASSB_PHASE3_CYC_REG_OFFSET,
- 1000);
+ EXPECT_ABS_WRITE32_SHADOWED(
+ mmio_, base_ + ALERT_HANDLER_CLASSB_CTRL_SHADOWED_REG_OFFSET,
+ {
+ {ALERT_HANDLER_CLASSA_CTRL_SHADOWED_EN_BIT, true},
+ {ALERT_HANDLER_CLASSA_CTRL_SHADOWED_LOCK_BIT, false},
+ {ALERT_HANDLER_CLASSA_CTRL_SHADOWED_EN_E3_BIT, false},
+ {ALERT_HANDLER_CLASSA_CTRL_SHADOWED_EN_E2_BIT, true},
+ {ALERT_HANDLER_CLASSA_CTRL_SHADOWED_EN_E1_BIT, true},
+ {ALERT_HANDLER_CLASSA_CTRL_SHADOWED_EN_E0_BIT, true},
+ {ALERT_HANDLER_CLASSA_CTRL_SHADOWED_MAP_E0_OFFSET, 0},
+ {ALERT_HANDLER_CLASSA_CTRL_SHADOWED_MAP_E1_OFFSET, 1},
+ {ALERT_HANDLER_CLASSA_CTRL_SHADOWED_MAP_E2_OFFSET, 2},
+ {ALERT_HANDLER_CLASSA_CTRL_SHADOWED_MAP_E3_OFFSET, 3},
+ });
+ EXPECT_ABS_WRITE32_SHADOWED(
+ mmio_, base_ + ALERT_HANDLER_CLASSB_ACCUM_THRESH_SHADOWED_REG_OFFSET, 1);
+ EXPECT_ABS_WRITE32_SHADOWED(
+ mmio_, base_ + ALERT_HANDLER_CLASSB_TIMEOUT_CYC_SHADOWED_REG_OFFSET, 2);
+ EXPECT_ABS_WRITE32_SHADOWED(
+ mmio_, base_ + ALERT_HANDLER_CLASSB_PHASE0_CYC_SHADOWED_REG_OFFSET, 1);
+ EXPECT_ABS_WRITE32_SHADOWED(
+ mmio_, base_ + ALERT_HANDLER_CLASSB_PHASE1_CYC_SHADOWED_REG_OFFSET, 10);
+ EXPECT_ABS_WRITE32_SHADOWED(
+ mmio_, base_ + ALERT_HANDLER_CLASSB_PHASE2_CYC_SHADOWED_REG_OFFSET, 100);
+ EXPECT_ABS_WRITE32_SHADOWED(
+ mmio_, base_ + ALERT_HANDLER_CLASSB_PHASE3_CYC_SHADOWED_REG_OFFSET, 1000);
EXPECT_EQ(alert_class_configure(kAlertClassB, &config), kErrorOk);
}
@@ -194,31 +209,32 @@
.timeout_cycles = 2,
.phase_cycles = {1, 10, 100, 1000},
};
- EXPECT_ABS_WRITE32(mmio_, base_ + ALERT_HANDLER_CLASSC_CTRL_REG_OFFSET,
- {
- {ALERT_HANDLER_CLASSA_CTRL_EN_BIT, true},
- {ALERT_HANDLER_CLASSA_CTRL_LOCK_BIT, false},
- {ALERT_HANDLER_CLASSA_CTRL_EN_E3_BIT, false},
- {ALERT_HANDLER_CLASSA_CTRL_EN_E2_BIT, false},
- {ALERT_HANDLER_CLASSA_CTRL_EN_E1_BIT, true},
- {ALERT_HANDLER_CLASSA_CTRL_EN_E0_BIT, true},
- {ALERT_HANDLER_CLASSA_CTRL_MAP_E0_OFFSET, 0},
- {ALERT_HANDLER_CLASSA_CTRL_MAP_E1_OFFSET, 1},
- {ALERT_HANDLER_CLASSA_CTRL_MAP_E2_OFFSET, 2},
- {ALERT_HANDLER_CLASSA_CTRL_MAP_E3_OFFSET, 3},
- });
- EXPECT_ABS_WRITE32(mmio_,
- base_ + ALERT_HANDLER_CLASSC_ACCUM_THRESH_REG_OFFSET, 1);
- EXPECT_ABS_WRITE32(mmio_, base_ + ALERT_HANDLER_CLASSC_TIMEOUT_CYC_REG_OFFSET,
- 2);
- EXPECT_ABS_WRITE32(mmio_, base_ + ALERT_HANDLER_CLASSC_PHASE0_CYC_REG_OFFSET,
- 1);
- EXPECT_ABS_WRITE32(mmio_, base_ + ALERT_HANDLER_CLASSC_PHASE1_CYC_REG_OFFSET,
- 10);
- EXPECT_ABS_WRITE32(mmio_, base_ + ALERT_HANDLER_CLASSC_PHASE2_CYC_REG_OFFSET,
- 100);
- EXPECT_ABS_WRITE32(mmio_, base_ + ALERT_HANDLER_CLASSC_PHASE3_CYC_REG_OFFSET,
- 1000);
+ EXPECT_ABS_WRITE32_SHADOWED(
+ mmio_, base_ + ALERT_HANDLER_CLASSC_CTRL_SHADOWED_REG_OFFSET,
+ {
+ {ALERT_HANDLER_CLASSA_CTRL_SHADOWED_EN_BIT, true},
+ {ALERT_HANDLER_CLASSA_CTRL_SHADOWED_LOCK_BIT, false},
+ {ALERT_HANDLER_CLASSA_CTRL_SHADOWED_EN_E3_BIT, false},
+ {ALERT_HANDLER_CLASSA_CTRL_SHADOWED_EN_E2_BIT, false},
+ {ALERT_HANDLER_CLASSA_CTRL_SHADOWED_EN_E1_BIT, true},
+ {ALERT_HANDLER_CLASSA_CTRL_SHADOWED_EN_E0_BIT, true},
+ {ALERT_HANDLER_CLASSA_CTRL_SHADOWED_MAP_E0_OFFSET, 0},
+ {ALERT_HANDLER_CLASSA_CTRL_SHADOWED_MAP_E1_OFFSET, 1},
+ {ALERT_HANDLER_CLASSA_CTRL_SHADOWED_MAP_E2_OFFSET, 2},
+ {ALERT_HANDLER_CLASSA_CTRL_SHADOWED_MAP_E3_OFFSET, 3},
+ });
+ EXPECT_ABS_WRITE32_SHADOWED(
+ mmio_, base_ + ALERT_HANDLER_CLASSC_ACCUM_THRESH_SHADOWED_REG_OFFSET, 1);
+ EXPECT_ABS_WRITE32_SHADOWED(
+ mmio_, base_ + ALERT_HANDLER_CLASSC_TIMEOUT_CYC_SHADOWED_REG_OFFSET, 2);
+ EXPECT_ABS_WRITE32_SHADOWED(
+ mmio_, base_ + ALERT_HANDLER_CLASSC_PHASE0_CYC_SHADOWED_REG_OFFSET, 1);
+ EXPECT_ABS_WRITE32_SHADOWED(
+ mmio_, base_ + ALERT_HANDLER_CLASSC_PHASE1_CYC_SHADOWED_REG_OFFSET, 10);
+ EXPECT_ABS_WRITE32_SHADOWED(
+ mmio_, base_ + ALERT_HANDLER_CLASSC_PHASE2_CYC_SHADOWED_REG_OFFSET, 100);
+ EXPECT_ABS_WRITE32_SHADOWED(
+ mmio_, base_ + ALERT_HANDLER_CLASSC_PHASE3_CYC_SHADOWED_REG_OFFSET, 1000);
EXPECT_EQ(alert_class_configure(kAlertClassC, &config), kErrorOk);
}
@@ -230,31 +246,32 @@
.timeout_cycles = 2,
.phase_cycles = {1, 10, 100, 1000},
};
- EXPECT_ABS_WRITE32(mmio_, base_ + ALERT_HANDLER_CLASSD_CTRL_REG_OFFSET,
- {
- {ALERT_HANDLER_CLASSA_CTRL_EN_BIT, true},
- {ALERT_HANDLER_CLASSA_CTRL_LOCK_BIT, false},
- {ALERT_HANDLER_CLASSA_CTRL_EN_E3_BIT, false},
- {ALERT_HANDLER_CLASSA_CTRL_EN_E2_BIT, false},
- {ALERT_HANDLER_CLASSA_CTRL_EN_E1_BIT, false},
- {ALERT_HANDLER_CLASSA_CTRL_EN_E0_BIT, false},
- {ALERT_HANDLER_CLASSA_CTRL_MAP_E0_OFFSET, 0},
- {ALERT_HANDLER_CLASSA_CTRL_MAP_E1_OFFSET, 1},
- {ALERT_HANDLER_CLASSA_CTRL_MAP_E2_OFFSET, 2},
- {ALERT_HANDLER_CLASSA_CTRL_MAP_E3_OFFSET, 3},
- });
- EXPECT_ABS_WRITE32(mmio_,
- base_ + ALERT_HANDLER_CLASSD_ACCUM_THRESH_REG_OFFSET, 1);
- EXPECT_ABS_WRITE32(mmio_, base_ + ALERT_HANDLER_CLASSD_TIMEOUT_CYC_REG_OFFSET,
- 2);
- EXPECT_ABS_WRITE32(mmio_, base_ + ALERT_HANDLER_CLASSD_PHASE0_CYC_REG_OFFSET,
- 1);
- EXPECT_ABS_WRITE32(mmio_, base_ + ALERT_HANDLER_CLASSD_PHASE1_CYC_REG_OFFSET,
- 10);
- EXPECT_ABS_WRITE32(mmio_, base_ + ALERT_HANDLER_CLASSD_PHASE2_CYC_REG_OFFSET,
- 100);
- EXPECT_ABS_WRITE32(mmio_, base_ + ALERT_HANDLER_CLASSD_PHASE3_CYC_REG_OFFSET,
- 1000);
+ EXPECT_ABS_WRITE32_SHADOWED(
+ mmio_, base_ + ALERT_HANDLER_CLASSD_CTRL_SHADOWED_REG_OFFSET,
+ {
+ {ALERT_HANDLER_CLASSA_CTRL_SHADOWED_EN_BIT, true},
+ {ALERT_HANDLER_CLASSA_CTRL_SHADOWED_LOCK_BIT, false},
+ {ALERT_HANDLER_CLASSA_CTRL_SHADOWED_EN_E3_BIT, false},
+ {ALERT_HANDLER_CLASSA_CTRL_SHADOWED_EN_E2_BIT, false},
+ {ALERT_HANDLER_CLASSA_CTRL_SHADOWED_EN_E1_BIT, false},
+ {ALERT_HANDLER_CLASSA_CTRL_SHADOWED_EN_E0_BIT, false},
+ {ALERT_HANDLER_CLASSA_CTRL_SHADOWED_MAP_E0_OFFSET, 0},
+ {ALERT_HANDLER_CLASSA_CTRL_SHADOWED_MAP_E1_OFFSET, 1},
+ {ALERT_HANDLER_CLASSA_CTRL_SHADOWED_MAP_E2_OFFSET, 2},
+ {ALERT_HANDLER_CLASSA_CTRL_SHADOWED_MAP_E3_OFFSET, 3},
+ });
+ EXPECT_ABS_WRITE32_SHADOWED(
+ mmio_, base_ + ALERT_HANDLER_CLASSD_ACCUM_THRESH_SHADOWED_REG_OFFSET, 1);
+ EXPECT_ABS_WRITE32_SHADOWED(
+ mmio_, base_ + ALERT_HANDLER_CLASSD_TIMEOUT_CYC_SHADOWED_REG_OFFSET, 2);
+ EXPECT_ABS_WRITE32_SHADOWED(
+ mmio_, base_ + ALERT_HANDLER_CLASSD_PHASE0_CYC_SHADOWED_REG_OFFSET, 1);
+ EXPECT_ABS_WRITE32_SHADOWED(
+ mmio_, base_ + ALERT_HANDLER_CLASSD_PHASE1_CYC_SHADOWED_REG_OFFSET, 10);
+ EXPECT_ABS_WRITE32_SHADOWED(
+ mmio_, base_ + ALERT_HANDLER_CLASSD_PHASE2_CYC_SHADOWED_REG_OFFSET, 100);
+ EXPECT_ABS_WRITE32_SHADOWED(
+ mmio_, base_ + ALERT_HANDLER_CLASSD_PHASE3_CYC_SHADOWED_REG_OFFSET, 1000);
EXPECT_EQ(alert_class_configure(kAlertClassD, &config), kErrorOk);
}
diff --git a/sw/device/silicon_creator/lib/shutdown.c b/sw/device/silicon_creator/lib/shutdown.c
index c27df60..afe77a2 100644
--- a/sw/device/silicon_creator/lib/shutdown.c
+++ b/sw/device/silicon_creator/lib/shutdown.c
@@ -22,7 +22,7 @@
#include "otp_ctrl_regs.h"
#include "sram_ctrl_regs.h"
-static_assert(ALERT_HANDLER_ALERT_CLASS_MULTIREG_COUNT <=
+static_assert(ALERT_HANDLER_ALERT_CLASS_SHADOWED_MULTIREG_COUNT <=
OTP_CTRL_PARAM_ROM_ALERT_CLASSIFICATION_SIZE / 4,
"More alerts than alert classification OTP words!");
@@ -110,7 +110,8 @@
// For each alert, read its corresponding OTP word and extract the class
// configuration for the current lifecycle state.
rom_error_t error = kErrorOk;
- for (size_t i = 0; i < ALERT_HANDLER_ALERT_CLASS_MULTIREG_COUNT; ++i) {
+ for (size_t i = 0; i < ALERT_HANDLER_ALERT_CLASS_SHADOWED_MULTIREG_COUNT;
+ ++i) {
uint32_t value = otp_read32(OTP_CTRL_PARAM_ROM_ALERT_CLASSIFICATION_OFFSET +
i * sizeof(uint32_t));
alert_class_t cls = (alert_class_t)bitfield_field32_read(
diff --git a/sw/device/silicon_creator/lib/shutdown_unittest.cc b/sw/device/silicon_creator/lib/shutdown_unittest.cc
index 73fae00..7a0c96c 100644
--- a/sw/device/silicon_creator/lib/shutdown_unittest.cc
+++ b/sw/device/silicon_creator/lib/shutdown_unittest.cc
@@ -339,7 +339,7 @@
TEST_F(ShutdownTest, InitializeProd) {
SetupOtpReads();
- for(size_t i = 0; i < ALERT_HANDLER_ALERT_CLASS_MULTIREG_COUNT; ++i) {
+ for(size_t i = 0; i < ALERT_HANDLER_ALERT_CLASS_SHADOWED_MULTIREG_COUNT; ++i) {
const auto &c = kDefaultAlertClassification[i];
alert_class_t cls = c.prod;
alert_enable_t en = RomAlertClassEnable(cls);
@@ -352,7 +352,7 @@
TEST_F(ShutdownTest, InitializeProdWithError) {
SetupOtpReads();
- for(size_t i = 0; i < ALERT_HANDLER_ALERT_CLASS_MULTIREG_COUNT; ++i) {
+ for(size_t i = 0; i < ALERT_HANDLER_ALERT_CLASS_SHADOWED_MULTIREG_COUNT; ++i) {
const auto &c = kDefaultAlertClassification[i];
alert_class_t cls = c.prod;
alert_enable_t en = RomAlertClassEnable(cls);
@@ -369,7 +369,7 @@
TEST_F(ShutdownTest, InitializeProdEnd) {
SetupOtpReads();
- for(size_t i = 0; i < ALERT_HANDLER_ALERT_CLASS_MULTIREG_COUNT; ++i) {
+ for(size_t i = 0; i < ALERT_HANDLER_ALERT_CLASS_SHADOWED_MULTIREG_COUNT; ++i) {
const auto &c = kDefaultAlertClassification[i];
alert_class_t cls = c.prodend;
alert_enable_t en = RomAlertClassEnable(cls);
@@ -382,7 +382,7 @@
TEST_F(ShutdownTest, InitializeDev) {
SetupOtpReads();
- for(size_t i = 0; i < ALERT_HANDLER_ALERT_CLASS_MULTIREG_COUNT; ++i) {
+ for(size_t i = 0; i < ALERT_HANDLER_ALERT_CLASS_SHADOWED_MULTIREG_COUNT; ++i) {
const auto &c = kDefaultAlertClassification[i];
alert_class_t cls = c.dev;
alert_enable_t en = RomAlertClassEnable(cls);
@@ -395,7 +395,7 @@
TEST_F(ShutdownTest, InitializeRma) {
SetupOtpReads();
- for(size_t i = 0; i < ALERT_HANDLER_ALERT_CLASS_MULTIREG_COUNT; ++i) {
+ for(size_t i = 0; i < ALERT_HANDLER_ALERT_CLASS_SHADOWED_MULTIREG_COUNT; ++i) {
const auto &c = kDefaultAlertClassification[i];
alert_class_t cls = c.rma;
alert_enable_t en = RomAlertClassEnable(cls);
