commit 19a07f8d8987b9b9e8afe9d167e6024fbd5bf880
author Timothy Chen <timothytim@google.com> Fri Aug 19 12:51:24 2022 -0700
committer tjaychen <timothytim@google.com> Fri Aug 19 18:43:25 2022 -0700
tree 96ffb8f8f58c58f13b8001de2deb1be611dd59b8
parent c8bac79b2d78b62799caa41f74ba4335116b3aed

[prim] Add () to s_eventually

Signed-off-by: Timothy Chen <timothytim@google.com>

hw/ip/prim/rtl/prim_reg_cdc_arb.sv

diff --git a/hw/ip/prim/rtl/prim_reg_cdc_arb.sv b/hw/ip/prim/rtl/prim_reg_cdc_arb.sv
index d804df8..0194de2 100644
--- a/hw/ip/prim/rtl/prim_reg_cdc_arb.sv
+++ b/hw/ip/prim/rtl/prim_reg_cdc_arb.sv
@@ -236,7 +236,7 @@
     assign src_update_o = src_req & (id_q == SelHwReq);
 
     // once hardware makes an update request, we must eventually see an update pulse
-    `ASSERT(ReqTimeout_A, $rose(id_q == SelHwReq) |-> s_eventually src_update_o,
+    `ASSERT(ReqTimeout_A, $rose(id_q == SelHwReq) |-> s_eventually(src_update_o),
       clk_src_i, !rst_src_ni)
 
     `ifdef INC_ASSERT
@@ -252,7 +252,7 @@
       end
 
      // once hardware makes an update request, we must eventually see an update pulse
-     `ASSERT(UpdateTimeout_A, $rose(async_flag) |-> s_eventually src_update_o,
+     `ASSERT(UpdateTimeout_A, $rose(async_flag) |-> s_eventually(src_update_o),
        clk_src_i, !rst_src_ni)
     `endif