[dv] Update CIP lib to use bus_params_pkg
Replaces parameters from top_pkg with parameters from bus_params_pkg.
Signed-off-by: Srikrishna Iyer <sriyer@google.com>
diff --git a/hw/dv/sv/cip_lib/cip_base_env_cfg.sv b/hw/dv/sv/cip_lib/cip_base_env_cfg.sv
index 08c27fc..a419580 100644
--- a/hw/dv/sv/cip_lib/cip_base_env_cfg.sv
+++ b/hw/dv/sv/cip_lib/cip_base_env_cfg.sv
@@ -26,7 +26,7 @@
`uvm_object_new
- virtual function void initialize(bit [TL_AW-1:0] csr_base_addr = '1);
+ virtual function void initialize(bit [BUS_AW-1:0] csr_base_addr = '1);
super.initialize(csr_base_addr);
// create tl agent config obj
m_tl_agent_cfg = tl_agent_cfg::type_id::create("m_tl_agent_cfg");
diff --git a/hw/dv/sv/cip_lib/cip_base_pkg.sv b/hw/dv/sv/cip_lib/cip_base_pkg.sv
index ccbff1f..161b2ea 100644
--- a/hw/dv/sv/cip_lib/cip_base_pkg.sv
+++ b/hw/dv/sv/cip_lib/cip_base_pkg.sv
@@ -5,7 +5,7 @@
package cip_base_pkg;
// dep packages
import uvm_pkg::*;
- import top_pkg::*;
+ import bus_params_pkg::*;
import dv_utils_pkg::*;
import csr_utils_pkg::*;
import dv_lib_pkg::*;
diff --git a/hw/dv/sv/cip_lib/cip_base_scoreboard.sv b/hw/dv/sv/cip_lib/cip_base_scoreboard.sv
index 21f0b77..3658c1f 100644
--- a/hw/dv/sv/cip_lib/cip_base_scoreboard.sv
+++ b/hw/dv/sv/cip_lib/cip_base_scoreboard.sv
@@ -121,7 +121,7 @@
// only lsb addr is used, the other can be ignored, use this function to normalize the addr to
// the format that RAL uses
virtual function uvm_reg_addr_t get_normalized_addr(uvm_reg_addr_t addr);
- return ({addr[TL_AW-1:2], 2'b00} & (cfg.csr_addr_map_size - 1)) + cfg.csr_base_addr;
+ return ({addr[BUS_AW-1:2], 2'b00} & (cfg.csr_addr_map_size - 1)) + cfg.csr_base_addr;
endfunction
// check if it's mem addr
diff --git a/hw/dv/sv/cip_lib/cip_base_vseq.sv b/hw/dv/sv/cip_lib/cip_base_vseq.sv
index 2435164..8dd7362 100644
--- a/hw/dv/sv/cip_lib/cip_base_vseq.sv
+++ b/hw/dv/sv/cip_lib/cip_base_vseq.sv
@@ -24,8 +24,8 @@
// address mask struct
typedef struct packed {
- bit [TL_AW-1:0] addr;
- bit [TL_DBW-1:0] mask;
+ bit [BUS_AW-1:0] addr;
+ bit [BUS_DBW-1:0] mask;
} addr_mask_t;
addr_mask_t mem_exist_addr_q[$];
@@ -33,7 +33,7 @@
// mem_ranges without base address
addr_range_t updated_mem_ranges[$];
// mask out bits out of the csr/mem range and LSB 2 bits
- bit [TL_AW-1:0] csr_addr_mask;
+ bit [BUS_AW-1:0] csr_addr_mask;
rand uint delay_to_reset;
constraint delay_to_reset_c {
@@ -57,7 +57,7 @@
endtask
task pre_start();
- csr_utils_pkg::max_outstanding_accesses = 1 << TL_AIW;
+ csr_utils_pkg::max_outstanding_accesses = 1 << BUS_AIW;
super.pre_start();
extract_common_csrs();
endtask
@@ -72,21 +72,21 @@
if (do_clear_all_interrupts) clear_all_interrupts();
endtask
- // tl_access task: does a single TL_W-bit write or read transaction to the specified address
+ // tl_access task: does a single BUS_DW-bit write or read transaction to the specified address
// note that this task does not update ral model; optionally also checks for error response
// TODO: randomize size, addr here based on given addr range, data, and mask, eventually can be
// reused for mem_read, partial read, and hmac msg fifo write
- virtual task tl_access(input bit [TL_AW-1:0] addr,
- input bit write,
- inout bit [TL_DW-1:0] data,
- input bit [TL_DBW-1:0] mask = '1,
- input bit check_rsp = 1'b1,
- input bit exp_err_rsp = 1'b0,
- input bit [TL_DW-1:0] exp_data = 0,
- input bit check_exp_data = 1'b0,
- input bit [TL_DW-1:0] compare_mask = '1,
- input bit blocking = csr_utils_pkg::default_csr_blocking,
- tl_sequencer tl_sequencer_h = p_sequencer.tl_sequencer_h);
+ virtual task tl_access(input bit [BUS_AW-1:0] addr,
+ input bit write,
+ inout bit [BUS_DW-1:0] data,
+ input bit [BUS_DBW-1:0] mask = '1,
+ input bit check_rsp = 1'b1,
+ input bit exp_err_rsp = 1'b0,
+ input bit [BUS_DW-1:0] exp_data = 0,
+ input bit check_exp_data = 1'b0,
+ input bit [BUS_DW-1:0] compare_mask = '1,
+ input bit blocking = csr_utils_pkg::default_csr_blocking,
+ tl_sequencer tl_sequencer_h = p_sequencer.tl_sequencer_h);
if (blocking) begin
tl_access_sub(addr, write, data, mask, check_rsp, exp_err_rsp, exp_data,
compare_mask, check_exp_data, tl_sequencer_h);
@@ -100,16 +100,16 @@
end
endtask
- virtual task tl_access_sub(input bit [TL_AW-1:0] addr,
- input bit write,
- inout bit [TL_DW-1:0] data,
- input bit [TL_DBW-1:0] mask = '1,
- input bit check_rsp = 1'b1,
- input bit exp_err_rsp = 1'b0,
- input bit [TL_DW-1:0] exp_data = 0,
- input bit [TL_DW-1:0] compare_mask = '1,
- input bit check_exp_data = 1'b0,
- tl_sequencer tl_sequencer_h = p_sequencer.tl_sequencer_h);
+ virtual task tl_access_sub(input bit [BUS_AW-1:0] addr,
+ input bit write,
+ inout bit [BUS_DW-1:0] data,
+ input bit [BUS_DBW-1:0] mask = '1,
+ input bit check_rsp = 1'b1,
+ input bit exp_err_rsp = 1'b0,
+ input bit [BUS_DW-1:0] exp_data = 0,
+ input bit [BUS_DW-1:0] compare_mask = '1,
+ input bit check_exp_data = 1'b0,
+ tl_sequencer tl_sequencer_h = p_sequencer.tl_sequencer_h);
`DV_SPINWAIT(
// thread to read/write tlul
tl_host_single_seq tl_seq;
@@ -128,7 +128,7 @@
if (!write) begin
data = tl_seq.rsp.d_data;
if (check_exp_data && !cfg.under_reset) begin
- bit [TL_DW-1:0] masked_data = data & compare_mask;
+ bit [BUS_DW-1:0] masked_data = data & compare_mask;
exp_data &= compare_mask;
`DV_CHECK_EQ(masked_data, exp_data, $sformatf("addr 0x%0h read out mismatch", addr))
end
@@ -146,7 +146,7 @@
// are descriptions of some of the args:
// interrupts: bit vector indicating which interrupts to process
- // suffix: if there are more than TL_DW interrupts, then add suffix 'hi' or 'lo' to the interrupt
+ // suffix: if there are more than BUS_DW interrupts, then add suffix 'hi' or 'lo' to the interrupt
// TODO add support for suffix
// csr to configure the right one (ex: intr_enable_hi, intr_enable_lo, etc)
// indices[$]: registers could be indexed (example, rv_timer) in which case, push as many desired
@@ -205,14 +205,14 @@
// task to enable multiple interrupts
// enable: if set, then selected interrupts are enabled, else disabled
// see description above for other args
- virtual task cfg_interrupts(bit [TL_DW-1:0] interrupts,
+ virtual task cfg_interrupts(bit [BUS_DW-1:0] interrupts,
bit enable = 1'b1,
string suffix = "",
int indices[$] = {},
uvm_reg_block scope = null);
- uvm_reg csr;
- bit [TL_DW-1:0] data;
+ uvm_reg csr;
+ bit [BUS_DW-1:0] data;
csr = get_interrupt_csr("intr_enable", "", indices, scope);
data = csr.get_mirrored_value();
@@ -226,16 +226,16 @@
// check_set: check if interrupts are set (1) or unset (0)
// clear: bit vector indicating which interrupt bit to clear
// see description above for other args
- virtual task check_interrupts(bit [TL_DW-1:0] interrupts,
+ virtual task check_interrupts(bit [BUS_DW-1:0] interrupts,
bit check_set,
string suffix = "",
int indices[$] = {},
uvm_reg_block scope = null,
- bit [TL_DW-1:0] clear = '1);
- uvm_reg csr_intr_state, csr_intr_enable;
- bit [TL_DW-1:0] act_pins;
- bit [TL_DW-1:0] exp_pins;
- bit [TL_DW-1:0] exp_intr_state;
+ bit [BUS_DW-1:0] clear = '1);
+ uvm_reg csr_intr_state, csr_intr_enable;
+ bit [BUS_DW-1:0] act_pins;
+ bit [BUS_DW-1:0] exp_pins;
+ bit [BUS_DW-1:0] exp_intr_state;
if (cfg.under_reset) return;
@@ -275,7 +275,7 @@
// generic task to check interrupt test reg functionality
virtual task run_intr_test_vseq(int num_times = 1);
- bit [TL_DW-1:0] exp_intr_state[$];
+ bit [BUS_DW-1:0] exp_intr_state[$];
int test_index[$];
foreach (intr_test_csrs[i]) begin
@@ -285,13 +285,13 @@
end
for (int trans = 1; trans <= num_times; trans++) begin
- bit [TL_DW-1:0] num_used_bits;
- bit [TL_DW-1:0] intr_enable_val[$];
+ bit [BUS_DW-1:0] num_used_bits;
+ bit [BUS_DW-1:0] intr_enable_val[$];
`uvm_info(`gfn, $sformatf("Running intr test iteration %0d/%0d", trans, num_times), UVM_LOW)
// Random Write to all intr enable registers
test_index.shuffle();
foreach (test_index[i]) begin
- bit [TL_DW-1:0] wr_data;
+ bit [BUS_DW-1:0] wr_data;
wr_data = $urandom_range(0, ((1 << intr_enable_csrs[test_index[i]].get_n_used_bits()) - 1));
intr_enable_val.insert(test_index[i], wr_data);
csr_wr(.csr(intr_enable_csrs[test_index[i]]), .value(wr_data));
@@ -300,7 +300,7 @@
// Random write to all interrupt test reg
test_index.shuffle();
foreach (test_index[i]) begin
- bit [TL_DW-1:0] wr_data;
+ bit [BUS_DW-1:0] wr_data;
wr_data = $urandom_range(0, ((1 << intr_test_csrs[test_index[i]].get_n_used_bits()) - 1));
// Add wr_data to expected state queue
exp_intr_state[test_index[i]] |= wr_data;
@@ -310,7 +310,7 @@
// Read all intr state
test_index.shuffle();
foreach (test_index[i]) begin
- bit [TL_DW-1:0] dut_intr_state;
+ bit [BUS_DW-1:0] dut_intr_state;
`uvm_info(`gtn, $sformatf("Verifying %0s", intr_test_csrs[test_index[i]].get_full_name()),
UVM_LOW)
csr_rd(.ptr(intr_state_csrs[test_index[i]]), .value(dut_intr_state));
@@ -320,7 +320,7 @@
// check interrupt pins
if (!cfg.under_reset) begin
foreach (intr_test_csrs[i]) begin
- bit [TL_DW-1:0] exp_intr_pin;
+ bit [BUS_DW-1:0] exp_intr_pin;
exp_intr_pin = exp_intr_state[i] & intr_enable_val[i];
for (int j = 0; j < intr_test_csrs[i].get_n_used_bits(); j++) begin
bit act_intr_pin_val = cfg.intr_vif.sample_pin(j + num_used_bits);
@@ -335,7 +335,7 @@
test_index.shuffle();
foreach (test_index[i]) begin
if ($urandom_range(0, 1)) begin
- bit [TL_DW-1:0] wr_data;
+ bit [BUS_DW-1:0] wr_data;
wr_data = $urandom_range((1 << intr_state_csrs[test_index[i]].get_n_used_bits()) - 1);
exp_intr_state[test_index[i]] &= (~wr_data);
csr_wr(.csr(intr_state_csrs[test_index[i]]), .value(wr_data));
@@ -346,7 +346,7 @@
// Task to clear register intr status bits
virtual task clear_all_interrupts();
- bit [TL_DW-1:0] data;
+ bit [BUS_DW-1:0] data;
foreach (intr_state_csrs[i]) begin
csr_rd(.ptr(intr_state_csrs[i]), .value(data));
if (data != 0) begin
@@ -497,9 +497,9 @@
repeat (num_accesses * num_times) begin
fork
begin
- bit [TL_AW-1:0] addr;
- bit [TL_DW-1:0] data;
- bit [TL_DBW-1:0] mask;
+ bit [BUS_AW-1:0] addr;
+ bit [BUS_DW-1:0] data;
+ bit [BUS_DBW-1:0] mask;
randcase
1: begin // write
dv_base_mem mem;
@@ -587,10 +587,10 @@
endtask
// TLUL mask must be contiguous, e.g. 'b1001, 'b1010 aren't allowed
- virtual function bit[TL_DBW-1:0] get_rand_contiguous_mask(bit [TL_DBW-1:0] valid_mask = '1);
- bit [TL_DBW-1:0] mask;
+ virtual function bit[BUS_DBW-1:0] get_rand_contiguous_mask(bit [BUS_DBW-1:0] valid_mask = '1);
+ bit [BUS_DBW-1:0] mask;
`DV_CHECK_STD_RANDOMIZE_WITH_FATAL(mask,
- $countones(mask ^ {mask[TL_DBW-2:0], 1'b0}) <= 2;
+ $countones(mask ^ {mask[BUS_DBW-2:0], 1'b0}) <= 2;
// for data bits aren't valid (unknown), mask bit should be 0
foreach (valid_mask[i]) {
!valid_mask[i] -> !mask[i];
diff --git a/hw/dv/sv/cip_lib/cip_base_vseq__tl_errors.svh b/hw/dv/sv/cip_lib/cip_base_vseq__tl_errors.svh
index 2fe2aad..b395524 100644
--- a/hw/dv/sv/cip_lib/cip_base_vseq__tl_errors.svh
+++ b/hw/dv/sv/cip_lib/cip_base_vseq__tl_errors.svh
@@ -21,12 +21,12 @@
end
virtual task tl_access_unmapped_addr();
- bit [TL_AW-1:0] normalized_csr_addrs[] = new[cfg.csr_addrs.size()];
+ bit [BUS_AW-1:0] normalized_csr_addrs[] = new[cfg.csr_addrs.size()];
// calculate normalized address outside the loop to improve perf
foreach (cfg.csr_addrs[i]) normalized_csr_addrs[i] = cfg.csr_addrs[i] - cfg.csr_base_addr;
// randomize unmapped_addr first to improve perf
repeat ($urandom_range(10, 100)) begin
- bit [TL_AW-1:0] unmapped_addr;
+ bit [BUS_AW-1:0] unmapped_addr;
`DV_CHECK_STD_RANDOMIZE_WITH_FATAL(unmapped_addr,
!((unmapped_addr & csr_addr_mask) inside {normalized_csr_addrs});
foreach (updated_mem_ranges[i]) {
@@ -56,9 +56,9 @@
uvm_reg all_csrs[$];
ral.get_registers(all_csrs);
foreach (all_csrs[i]) begin
- dv_base_reg csr;
- uint msb_pos;
- bit [TL_AW-1:0] addr;
+ dv_base_reg csr;
+ uint msb_pos;
+ bit [BUS_AW-1:0] addr;
`DV_CHECK_FATAL($cast(csr, all_csrs[i]))
msb_pos = csr.get_msb_pos();
addr = csr.get_address();
diff --git a/hw/dv/sv/cip_lib/cip_lib.core b/hw/dv/sv/cip_lib/cip_lib.core
index 74d3dbd..4156ca3 100644
--- a/hw/dv/sv/cip_lib/cip_lib.core
+++ b/hw/dv/sv/cip_lib/cip_lib.core
@@ -13,6 +13,7 @@
- lowrisc:dv:alert_esc_agent
- lowrisc:dv:dv_base_reg
- lowrisc:dv:mem_model
+ - lowrisc:opentitan:bus_params_pkg
files:
- cip_base_pkg.sv
- cip_base_env_cfg.sv: {is_include_file: true}
