| commit | 18a09cbe4652e5ab62730576a8fec73ff27edb71 | [log] [tgz] |
|---|---|---|
| author | Greg Chadwick <gac@lowrisc.org> | Fri Nov 06 18:15:18 2020 +0000 |
| committer | Greg Chadwick <gac@lowrisc.org> | Thu Nov 19 13:38:16 2020 +0000 |
| tree | dcc9cf4be00ac2bf228210e6e7b681bbc5e585bd | |
| parent | e8ade050acea4e4de9027461f490df51a7a2c484 [diff] |
[otbn] Introduce tracer for RTL This adds a tracer module and interface. Both the module and interface should be bound into a top-level instantiation of otbn_core with the interface instance passed to the module. The tracer collects records using the trace interface to gather relevant information and passes it to the simulation via a DPI call. The new tracer setup is added to the OTBN standalone verilator simulation. An optional log file (via --trace-log-file) can be specified which causes the trace to be output there. Fixes #2624 Signed-off-by: Greg Chadwick <gac@lowrisc.org>
OpenTitan is an open source silicon Root of Trust (RoT) project. OpenTitan will make the silicon RoT design and implementation more transparent, trustworthy, and secure for enterprises, platform providers, and chip manufacturers. OpenTitan is administered by lowRISC CIC as a collaborative project to produce high quality, open IP for instantiation as a full-featured product. See the OpenTitan site and OpenTitan docs for more information about the project.
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