[rv_core_ibex] Adjust number and width of performance counters

A while ago, two new performance counters were added upstream to measure
the number of stall cycles due to mul/div instructions. Reducing the
width of the optional counters from 40 to 32 bits allows to save around
400 FFs on Xilinx FPGAs as in this case the output regsiter of the DSP
slices can be used. The two mandatory counters mcycle(h) and minstret(h)
remain 64 bits wide.

Signed-off-by: Pirmin Vogel <vogelpi@lowrisc.org>

hw/top_earlgrey/data/top_earlgrey.sv.tpl

diff --git a/hw/top_earlgrey/data/top_earlgrey.sv.tpl b/hw/top_earlgrey/data/top_earlgrey.sv.tpl
index 2fff9f4..37c6612 100644
--- a/hw/top_earlgrey/data/top_earlgrey.sv.tpl
+++ b/hw/top_earlgrey/data/top_earlgrey.sv.tpl
@@ -189,8 +189,8 @@
     .PMPEnable                (1),
     .PMPGranularity           (0), // 2^(PMPGranularity+2) == 4 byte granularity
     .PMPNumRegions            (16),
-    .MHPMCounterNum           (8),
-    .MHPMCounterWidth         (40),
+    .MHPMCounterNum           (10),
+    .MHPMCounterWidth         (32),
     .RV32E                    (0),
     .RV32M                    (ibex_pkg::RV32MSingleCycle),
     .RV32B                    (ibex_pkg::RV32BNone),