Update lowrisc_ibex to lowRISC/ibex@ee1098f
Update code from upstream repository
https://github.com/lowRISC/ibex.git to revision
ee1098f9afb1a63a34d613a8949c00e5b0c75b47
* Tracer: Reference Verilator bug for miscompilation (Philipp Wagner)
* Include rs1 and rd in trace of c.addi16sp (Philipp Wagner)
* [DV] Top level toggle coverage (lowRISC/ibex#371) (udinator)
* [Doc] Add more pipeline details (Greg Chadwick)
* [Doc] Fix for table wrapping in RTD theme (Greg Chadwick)
* Add missing enum cast (Philipp Wagner)
* [Doc] Fix some rendering issues in cs_registers (Tom Roberts)
* [RTL PMP] Fix address matching bugs (Tom Roberts)
* [Priv modes] Add support for U-Mode (Tom Roberts)
* RISC-V Compliance test: Enable tracing (Philipp Wagner)
* [DV] Update ibex log regex (lowRISC/ibex#366) (udinator)
* Tracer: Fix default file name (Philipp Wagner)
* CI: Also check tracer in lint (Philipp Wagner)
* Lint: Enable lint for ibex_core_tracing (Philipp Wagner)
* Update gitignore to include trace log file (Philipp Wagner)
* Document new tracer implementation (Philipp Wagner)
* Implement Verilator-compatible tracer, and use it (Philipp Wagner)
* Remove tracer testbench (Philipp Wagner)
* [RTL] Fix timing path around exceptions and pc_set (Greg Chadwick)
* [RTL] Keep instr in ID valid for FLUSH state (Greg Chadwick)
* Pull `csr_we_int` around case in CSR (Marek PikuĊa)
* CI: Unbreak build after simplesat breakage (Philipp Wagner)
* Docs: Fix Sphinx warnings and errors (Philipp Wagner)
* [DV] Debug single step test (lowRISC/ibex#362) (udinator)
* Add more parameters to core file (Philipp Wagner)
* ibex_core_tracing: Pass through all parameters (Philipp Wagner)
* ibex_core: Use correct width for param assignments (Philipp Wagner)
* Tracer: Update copyright notice to match other files (Philipp
Wagner)
* [Prefetch buffer] - various bug fixes (Tom Roberts)
* [DV]Add Makefile target for functional coverage (lowRISC/ibex#358)
(taoliug)
* [rtl/ibex_core] Added missing parameter assignment
(lowRISC/ibex#356) (NilsGraf)
* [DV] Fix ovpsim compare issue (lowRISC/ibex#355) (udinator)
* [DV] Refactor debug stress stimulus to avoid race conditions
(lowRISC/ibex#354) (udinator)
* Update google_riscv-dv to google/riscv-dv@d341944 (lowRISC/ibex#353)
(udinator)
* [DV] Basic performance test (lowRISC/ibex#352) (udinator)
* Tighten debug stimulus assertion (lowRISC/ibex#351) (udinator)
* Update google_riscv-dv to google/riscv-dv@e3e1e30 (lowRISC/ibex#349)
(udinator)
* Update google_riscv-dv to google/riscv-dv@4450592 (lowRISC/ibex#347)
(udinator)
* [DV] Fix implemented_csr[] compile issue (lowRISC/ibex#346)
(udinator)
* [DV] Update implemented CSRs (lowRISC/ibex#345) (udinator)
* Fix memory error test logic (lowRISC/ibex#344) (udinator)
* Tracing: Wrap fatal error message with `$fatal()` (Pirmin Vogel)
* [DV] Illegal instruction monitoring (lowRISC/ibex#338) (udinator)
* [DV] Shorten length of interrupt tests to prevent timeouts
(lowRISC/ibex#337) (udinator)
* [DV] Drive external stimulus to 0 after reset (lowRISC/ibex#334)
(udinator)
* Update google_riscv-dv to google/riscv-dv@80d4294 (lowRISC/ibex#333)
(udinator)
* Add memory error testing (lowRISC/ibex#330) (udinator)
* Compliance test suite: Prefer D over I accesses (Philipp Wagner)
* Consolidate the script logging (lowRISC/ibex#329) (taoliug)
* Add dsim support (lowRISC/ibex#328) (taoliug)
* Lint: Enable RVFI when doing lint checks (Philipp Wagner)
* Lint: Fix signal width in tracer (Philipp Wagner)
* Ignore common editor files in Git (Philipp Wagner)
* Add interrupt testing, and update some debug test checks
(lowRISC/ibex#324) (udinator)
* Integrate with the new riscv-dv user extension flow
(lowRISC/ibex#323) (taoliug)
* Update google_riscv-dv to google/riscv-dv@0d2b5b7 (lowRISC/ibex#321)
(udinator)
* ibex_riscv_compliance: Adjust to simutil_verilator (Philipp Wagner)
* simutil_verilator: Always produce toplevel class (Philipp Wagner)
* [DV] Fix latch in simple bus (Greg Chadwick)
* [DV] Standardize logging, allow parallel simulation
(lowRISC/ibex#315) (taoliug)
* Fix ELF section name (lowRISC/ibex#314) (taoliug)
* Fix regression failure (lowRISC/ibex#313) (taoliug)
* Update google_riscv-dv to google/riscv-dv@c98d89c (lowRISC/ibex#312)
(udinator)
diff --git a/hw/vendor/lowrisc_ibex.lock.hjson b/hw/vendor/lowrisc_ibex.lock.hjson
index acd95e5..9dc6ae6 100644
--- a/hw/vendor/lowrisc_ibex.lock.hjson
+++ b/hw/vendor/lowrisc_ibex.lock.hjson
@@ -9,6 +9,6 @@
upstream:
{
url: https://github.com/lowRISC/ibex.git
- rev: f025236a22e4d2290acf856de60449f24d79bc6f
+ rev: ee1098f9afb1a63a34d613a8949c00e5b0c75b47
}
}
diff --git a/hw/vendor/lowrisc_ibex/.gitignore b/hw/vendor/lowrisc_ibex/.gitignore
index 8b9e9c8..fd37ef5 100644
--- a/hw/vendor/lowrisc_ibex/.gitignore
+++ b/hw/vendor/lowrisc_ibex/.gitignore
@@ -1,3 +1,10 @@
-*.swp
-include/riscv_config.sv.bak
+# Build output
build
+
+# Common editor/IDE config and temporary files
+.project
+.vscode/
+.sw[a-p]
+
+# ibex_tracer log file
+trace_core_*.log
diff --git a/hw/vendor/lowrisc_ibex/azure-pipelines.yml b/hw/vendor/lowrisc_ibex/azure-pipelines.yml
index e95f9f1..d559403 100644
--- a/hw/vendor/lowrisc_ibex/azure-pipelines.yml
+++ b/hw/vendor/lowrisc_ibex/azure-pipelines.yml
@@ -31,6 +31,9 @@
# Installing six is a workaround for pip dependency resolution: six is already
# installed as system package with a version below the required one.
# Explicitly installing six through pip gets us a supported version.
+ #
+ # attrs is correctly declared as dependency, but currently broken.
+ # Tracked in https://github.com/enthought/sat-solver/issues/270
- bash: |
sudo apt-get install -y \
python3 \
@@ -45,7 +48,7 @@
flex \
bison \
curl \
- && sudo pip3 install -U six fusesoc
+ && sudo pip3 install -U six attrs==19.1.0 fusesoc
displayName: Install dependencies
- bash: |
@@ -86,10 +89,10 @@
displayName: Display environment
- bash: |
- fusesoc --cores-root . run --target=lint lowrisc:ibex:ibex_core
+ fusesoc --cores-root . run --target=lint lowrisc:ibex:ibex_core_tracing
if [ $? != 0 ]; then
echo -n "##vso[task.logissue type=error]"
- echo "Verilog lint failed. Run 'fusesoc --cores-root . run --target=lint lowrisc:ibex:ibex_core' to check and fix all errors."
+ echo "Verilog lint failed. Run 'fusesoc --cores-root . run --target=lint lowrisc:ibex:ibex_core_tracing' to check and fix all errors."
exit 1
fi
displayName: Lint Verilog source files with Verilator
@@ -115,7 +118,7 @@
export RISCV_DEVICE=rv32imc
fail=0
for isa in rv32i rv32im rv32imc; do
- make -C build/riscv-compliance RISCV_ISA=$isa 2>&1 | tee run.log
+ make -C build/riscv-compliance RISCV_ISA=$isa 2>&1 | tee run.log
if [ ${PIPESTATUS[0]} != 0 ]; then
echo -n "##vso[task.logissue type=error]"
echo "The RISC-V compliance test suite failed for $isa"
diff --git a/hw/vendor/lowrisc_ibex/doc/_static/theme_overrides.css b/hw/vendor/lowrisc_ibex/doc/_static/theme_overrides.css
new file mode 100644
index 0000000..63ee6cc
--- /dev/null
+++ b/hw/vendor/lowrisc_ibex/doc/_static/theme_overrides.css
@@ -0,0 +1,13 @@
+/* override table width restrictions */
+@media screen and (min-width: 767px) {
+
+ .wy-table-responsive table td {
+ /* !important prevents the common CSS stylesheets from overriding
+ this as on RTD they are loaded after this stylesheet */
+ white-space: normal !important;
+ }
+
+ .wy-table-responsive {
+ overflow: visible !important;
+ }
+}
diff --git a/hw/vendor/lowrisc_ibex/doc/conf.py b/hw/vendor/lowrisc_ibex/doc/conf.py
index 47ab96a..de2a370 100644
--- a/hw/vendor/lowrisc_ibex/doc/conf.py
+++ b/hw/vendor/lowrisc_ibex/doc/conf.py
@@ -103,7 +103,13 @@
# Add any paths that contain custom static files (such as style sheets) here,
# relative to this directory. They are copied after the builtin static files,
# so a file named "default.css" will overwrite the builtin "default.css".
-#html_static_path = ['_static']
+html_static_path = ['_static']
+
+html_context = {
+ 'css_files' : [
+ '_static/theme_overrides.css', # Fix wide tables in RTD theme
+ ],
+ }
# -- Options for HTMLHelp output ------------------------------------------
diff --git a/hw/vendor/lowrisc_ibex/doc/cs_registers.rst b/hw/vendor/lowrisc_ibex/doc/cs_registers.rst
index 9f29a7c..978aca7 100644
--- a/hw/vendor/lowrisc_ibex/doc/cs_registers.rst
+++ b/hw/vendor/lowrisc_ibex/doc/cs_registers.rst
@@ -90,18 +90,24 @@
+-------+-----+---------------------------------------------------------------------------------+
| Bit# | R/W | Description |
+-------+-----+---------------------------------------------------------------------------------+
-| 12:11 | R | **MPP:** Statically 2'b11 and cannot be altered (read-only). |
+| 21 | RW | **TW:** Timeout Wait (WFI executed in User Mode will trap to Machine Mode). |
++-------+-----+---------------------------------------------------------------------------------+
+| 17 | RW | **MPRV:** Modify Privilege (Loads and stores use MPP for privilege checking). |
++-------+-----+---------------------------------------------------------------------------------+
+| 12:11 | RW | **MPP:** Machine Previous Privilege mode. |
+-------+-----+---------------------------------------------------------------------------------+
| 7 | RW | **Previous Interrupt Enable (MPIE)**, i.e., before entering exception handling. |
+-------+-----+---------------------------------------------------------------------------------+
| 3 | RW | **Interrupt Enable (MIE):** If set to 1'b1, interrupts are globally enabled. |
+-------+-----+---------------------------------------------------------------------------------+
-When an exception is encountered, ``mstatus``.MPIE will be set to ``mstatus``.MIE.
-When the MRET instruction is executed, the value of MPIE will be stored back to ``mstatus``.MIE.
+When an exception is encountered, ``mstatus``.MPIE will be set to ``mstatus``.MIE, and ``mstatus``.MPP will be set to the current privilege mode.
+When the MRET instruction is executed, the value of MPIE will be stored back to ``mstatus``.MIE, and the privilege mode will be restored from ``mstatus``.MPP.
If you want to enable interrupt handling in your exception handler, set ``mstatus``.MIE to 1'b1 inside your handler code.
+Only Machine Mode and User Mode are supported.
+Any write to ``mstatus``.MPP of an unsupported value will be interpreted as Machine Mode.
Machine ISA Register (misa)
---------------------------
@@ -225,7 +231,7 @@
+-------+---------------------------------------------------------------------------------------+
PMP Configuration Register (pmpcfgx)
-----------------------------------------
+------------------------------------
CSR Address: ``0x3A0 - 0x3A3``
@@ -233,11 +239,11 @@
``pmpcfgx`` are registers to configure PMP regions. Each register configures 4 PMP regions.
-+---------------------------------------+
++---------+---------+---------+---------+
| 31:24 | 23:16 | 15:8 | 7:0 |
-+---------------------------------------+
++---------+---------+---------+---------+
| pmp3cfg | pmp2cfg | pmp1cfg | pmp0cfg |
-+---------------------------------------+
++---------+---------+---------+---------+
The configuration fields for each region are as follows:
@@ -262,7 +268,7 @@
Note that the combination of Write permission = 1, Read permission = 0 is reserved, and will be treated by the core as Read/Write permission = 0.
PMP Address Register (pmpaddrx)
-----------------------------------------
+-------------------------------
CSR Address: ``0x3B0 - 0x3BF``
@@ -276,6 +282,15 @@
| address[33:2] |
+----------------+
+Time Registers (time(h))
+------------------------
+
+CSR Address: ``0xC01 / 0xC81``
+
+The User Mode ``time(h)`` registers are not implemented in Ibex.
+Any access to these registers will trap.
+It is recommended that trap handler software provides a means of accessing platform-defined ``mtime(h)`` timers where available.
+
.. _csr-mhartid:
Hardware Thread ID (mhartid)
diff --git a/hw/vendor/lowrisc_ibex/doc/exception_interrupts.rst b/hw/vendor/lowrisc_ibex/doc/exception_interrupts.rst
index 99be67e..3f9a0fb 100644
--- a/hw/vendor/lowrisc_ibex/doc/exception_interrupts.rst
+++ b/hw/vendor/lowrisc_ibex/doc/exception_interrupts.rst
@@ -15,6 +15,12 @@
The core starts fetching at the address made by concatenating the most significant 3 bytes of the boot address and the reset value (0x80) as the least significant byte.
It is assumed that the boot address is supplied via a register to avoid long paths to the instruction fetch unit.
+Privilege Modes
+---------------
+
+Ibex supports operation in Machine Mode (M-Mode) and User Mode (U-Mode).
+The core resets into M-Mode and will jump to M-Mode on any interrupt or exception.
+On execution of an MRET instruction, the core will return to the Privilege Mode stored in ``mstatus``.MPP.
Interrupts
----------
@@ -80,7 +86,9 @@
+----------------+---------------------------------------------------------------+
| 7 | Store access fault |
+----------------+---------------------------------------------------------------+
-| 11 | Environment call from M-mode (ECALL) |
+| 8 | Environment call from U-Mode (ECALL) |
++----------------+---------------------------------------------------------------+
+| 11 | Environment call from M-Mode (ECALL) |
+----------------+---------------------------------------------------------------+
The illegal instruction exception, instruction access fault, LSU error exceptions and ECALL instruction exceptions cannot be disabled and are always active.
diff --git a/hw/vendor/lowrisc_ibex/doc/images/blockdiagram.svg b/hw/vendor/lowrisc_ibex/doc/images/blockdiagram.svg
index b8421a3..60ef641 100644
--- a/hw/vendor/lowrisc_ibex/doc/images/blockdiagram.svg
+++ b/hw/vendor/lowrisc_ibex/doc/images/blockdiagram.svg
@@ -183,19 +183,19 @@
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+ id="tspan1260">EX</tspan></text>
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new file mode 100644
index 0000000..5b0d1eb
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+++ b/hw/vendor/lowrisc_ibex/doc/images/de_ex_stage.svg
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diff --git a/hw/vendor/lowrisc_ibex/doc/index.rst b/hw/vendor/lowrisc_ibex/doc/index.rst
index 7b241fd..331c2e4 100644
--- a/hw/vendor/lowrisc_ibex/doc/index.rst
+++ b/hw/vendor/lowrisc_ibex/doc/index.rst
@@ -8,7 +8,9 @@
introduction
getting_started
integration
+ pipeline_details
instruction_fetch
+ instruction_decode_execute
load_store_unit
register_file
cs_registers
diff --git a/hw/vendor/lowrisc_ibex/doc/instruction_decode_execute.rst b/hw/vendor/lowrisc_ibex/doc/instruction_decode_execute.rst
new file mode 100644
index 0000000..af1cbef
--- /dev/null
+++ b/hw/vendor/lowrisc_ibex/doc/instruction_decode_execute.rst
@@ -0,0 +1,111 @@
+.. _instruction-decode-execute:
+
+Instruction Decode and Execute
+==============================
+
+.. figure:: images/de_ex_stage.svg
+ :name: de_ex_stage
+ :align: center
+
+ Instruction Decode and Execute
+
+The Instruction Decode and Execute stage takes instruction data from the instruction fetch stage (which has been converted to the uncompressed representation in the compressed instruction case).
+The instructions are decoded and executed all within one cycle including the register read and write.
+The stage is made up of multiple sub-blocks which are described below.
+
+Instruction Decode Block (ID)
+-----------------------------
+Source File: :file:`rtl/ibex_id_stage.sv`
+
+The Instruction Decode (ID) controls the overall decode/execution process.
+It contains the muxes to choose what is sent to the ALU inputs and where the write data for the register file comes from.
+A small state machine is used to control multi-cycle instructions (see :ref:`pipeline-details` for more details), which stalls the whole stage whilst a multi-cycle instruction is executing.
+
+Controller
+----------
+Source File: :file:`rtl/ibex_controller.sv`
+
+The Controller contains the state machine that controls the overall execution of the processor.
+It is responsible for:
+
+* Handling core startup from reset
+* Setting the PC for the IF stage on jump/branch
+* Dealing with exceptions/interrupts (jump to appropriate PC, set relevant CSR values)
+* Controlling sleep/wakeup on WFI
+* Debugging control
+
+Decoder
+-------
+Source File: :file:`rtl/ibex_decoder.sv`
+
+The decoder takes uncompressed instruction data and issues appropriate control signals to the other blocks to execute the instruction.
+
+Register File
+-------------
+Source Files: :file:`rtl/ibex_register_file_ff.sv` :file:`rtl/ibex_register_file_latch.sv`
+
+See :ref:`register-file` for more details.
+
+Execute Block
+-------------
+Source File: :file:`rtl/ibex_ex_block.sv`
+
+The execute block contains the ALU and the multiplier/divider blocks, it does little beyond wiring and instantiating these blocks.
+
+Arithmetic Logic Unit (ALU)
+---------------------------
+Source File: :file:`rtl/ibex_alu.sv`
+
+The Arithmetic Logic Logic (ALU) is a purely combinational block that implements operations required for the Integer Computational Instructions and the comparison operations required for the Control Transfer Instructions in the RV32I RISC-V Specification.
+Other blocks use the ALU for the following tasks:
+
+* Mult/Div uses it to perform addition as part of the multiplication and division algorithms
+* It computes branch targets with a PC + Imm calculation
+* It computes memory addresses for loads and stores with a Reg + Imm calculation
+* The LSU uses it to increment addresses when performing two accesses to handle an unaligned access
+
+.. _mult-div:
+
+Multiplier/Divider Block (MULT/DIV)
+-----------------------------------
+Source Files: :file:`rtl/ibex_multdiv_slow.sv` :file:`rtl/ibex_multdiv_fast.sv`
+
+The Multiplier/Divider (MULT/DIV) is a state machine driven block to perform multiplication and division.
+The fast and slow versions differ in multiplier only, both implement the same form of long division algorithm.
+The ALU block is used by the long division algorithm in both the fast and slow blocks.
+
+Fast Multiplier
+ - Completes multiply in 3-4 cycles using a MAC (multiply accumulate) which is capable of a 17-bit x 17-bit multiplication with a 34-bit accumulator.
+ - A MUL instruction takes 3 cycles, MULH takes 4.
+ - This MAC is internal to the mult/div block (no external ALU use).
+ - Beware it is simply implemented with the ``*`` and ``+`` operators so results heavily depend upon the synthesis tool used.
+ - In some cases it may be desirable to replace this with a specific implementation (such as a hard macro in an FPGA or an explicit gate level implementation).
+
+Slow Multiplier
+ - Completes multiply in 33 cycles using a Baugh-Wooley multiplier (for both MUL and MULH).
+ - The ALU block is used to compute additions.
+
+Divider
+ Both the fast and slow blocks use the same long division algorithm, it takes 37 cycles to compute (though only requires 2 cycles when there is a divide by 0) and proceeds as follows:
+
+ - Cycle 0: Check for divide by 0
+ - Cycle 1: Compute absolute value of operand A (or return result on divide by 0)
+ - Cycle 2: Compute absolute value of operand B
+ - Cycles 4 - 36: Perform long division as described here: https://en.wikipedia.org/wiki/Division_algorithm#Integer_division_(unsigned)_with_remainder.
+
+Control and Status Register Block (CSR)
+---------------------------------------
+Source File: :file:`rtl/ibex_cs_registers.sv`
+
+The CSR contains all of the CSRs (control/status registers).
+Any CSR read/write is handled through this block.
+Performance counters are held in this block and incremented when appropriate (this includes ``mcycle`` and ``minstret``).
+Read data from a CSR is available the same cycle it is requested.
+Further detail on the implemented CSRs can be found in :ref:`cs-registers`
+
+Load-Store Unit (LSU)
+---------------------
+Source File: :file:`rtl/ibex_load_store_unit.sv`
+
+The Load-Store Unit (LSU) interfaces with main memory to perform load and store operations.
+See :ref:`load-store-unit` for more details.
diff --git a/hw/vendor/lowrisc_ibex/doc/instruction_fetch.rst b/hw/vendor/lowrisc_ibex/doc/instruction_fetch.rst
index 3c62b85..82f0e62 100644
--- a/hw/vendor/lowrisc_ibex/doc/instruction_fetch.rst
+++ b/hw/vendor/lowrisc_ibex/doc/instruction_fetch.rst
@@ -2,9 +2,27 @@
Instruction Fetch
=================
+:file:`rtl/ibex_if_stage.sv.`
-The Instruction-Fetch (IF) stage of the core is able to supply one instruction to the Instruction-Decode (ID) stage per cycle if the instruction cache or the instruction memory is able to serve one instruction per cycle.
-For optimal performance and timing closure reasons, a prefetcher is used which fetches instructions from the instruction memory, or instruction cache.
+.. figure:: images/if_stage.svg
+ :name: if_stage
+ :align: center
+
+ Instruction Fetch (IF) stage
+
+The Instruction Fetch (IF) stage of the core is able to supply one instruction to the Instruction-Decode (ID) stage per cycle if the instruction cache or the instruction memory is able to serve one instruction per cycle.
+
+Instructions are fetched into a prefetch buffer (:file:`rtl/ibex_prefetch_buffer.sv`) for optimal performance and timing closure reasons.
+This buffer simply fetches instructions linearly until it is full.
+The instructions themselves are stored along with the Program Counter (PC) they came from in the fetch FIFO (:file:`rtl/ibex_fetch_fifo.sv`).
+The fetch FIFO has a feedthrough path so when empty a new instruction entering the FIFO is immediately made available on the FIFO output.
+A localparam ``DEPTH`` gives a configurable depth which is set to 3 by default.
+
+The top-level of the instruction fetch controls the prefetch buffer (in particular flushing it on branches/jumps/exception and beginning prefetching from the appropriate new PC) and supplies new instructions to the ID/EX stage along with their PC.
+Compressed instructions are expanded by the IF stage so the decoder can always deal with uncompressed instructions (the ID stage still receives the compressed instruction for placing into ``mtval`` on an illegal instruction exception).
+
+Instruction-Side Memory Interface
+---------------------------------
The following table describes the signals that are used to fetch instructions.
This interface is a simplified version of the interface used on the data interface as described in :ref:`load-store-unit`.
@@ -49,25 +67,3 @@
The protocol used to communicate with the instruction cache or the instruction memory is very similar to the protocol used by the LSU on the data interface of Ibex.
See the description of the LSU in :ref:`LSU Protocol<lsu-protocol>` for details about this protocol.
-.. caution::
-
- The IF protocol differs from the LSU protocol in that the address can change while the request is valid (``instr_req_o`` is high).
- This allows the core to immediately update the instruction fetch address when a branch occurs.
- As depicted in :numref:`if_timing_difference`, care has to be taken when working with the address.
- The data returned must match the address during the grant cycle.
-
- .. wavedrom::
- :name: if_timing_difference
- :caption: Memory transaction with wait states
-
- {"signal":
- [
- {"name": "clk", "wave": "p......"},
- {"name": "instr_req_o", "wave": "01..0.."},
- {"name": "instr_addr_o", "wave": "x=.=xxx", "data": ["Addr1", "Addr2"]},
- {"name": "instr_gnt_i", "wave": "0..10.."},
- {"name": "instr_rvalid_i", "wave": "0....10"},
- {"name": "instr_rdata_i", "wave": "xxxxx=x", "data": ["RData2"]}
- ],
- "config": { "hscale": 2 }
- }
diff --git a/hw/vendor/lowrisc_ibex/doc/integration.rst b/hw/vendor/lowrisc_ibex/doc/integration.rst
index 309083b..122cd9f 100644
--- a/hw/vendor/lowrisc_ibex/doc/integration.rst
+++ b/hw/vendor/lowrisc_ibex/doc/integration.rst
@@ -120,7 +120,7 @@
| ``fetch_enable_i`` | 1 | in | Enable the core, won't fetch when 0 |
+-------------------------+-------------------------+-----+----------------------------------------+
| ``core_sleep_o`` | 1 | out | Core in WFI with no outstanding data |
-| | | | or instruction accesses. Deasserts |
+| | | | or instruction accesses. Deasserts |
| | | | if an external event (interrupt or |
| | | | debug req) wakes the core up |
+-------------------------+-------------------------+-----+----------------------------------------+
diff --git a/hw/vendor/lowrisc_ibex/doc/introduction.rst b/hw/vendor/lowrisc_ibex/doc/introduction.rst
index b21235d..fcd9410 100644
--- a/hw/vendor/lowrisc_ibex/doc/introduction.rst
+++ b/hw/vendor/lowrisc_ibex/doc/introduction.rst
@@ -53,7 +53,7 @@
Most content of the RISC-V privileged specification is optional.
Ibex currently supports the following features according to the RISC-V Privileged Specification, version 1.11.
-* M mode
+* M-Mode and U-Mode
* All CSRs listed in :ref:`cs-registers`
* Performance counters as described in :ref:`performance-counters`
* Vectorized trap handling as described at :ref:`exceptions-interrupts`
@@ -75,18 +75,20 @@
Contents
--------
-:ref:`getting-started` discusses the requirements and initial steps to start using Ibex.
-:ref:`core-integration` provides the instantiation template and gives descriptions of the design parameters as well as the input and output ports.
-The instruction and data interfaces of Ibex are explained in :ref:`instruction-fetch` and :ref:`load-store-unit`, respectively.
-The two register-file flavors are described in :ref:`register-file`.
-The control and status registers are explained in :ref:`cs-registers`.
-:ref:`performance-counters` gives an overview of the performance monitors and event counters available in Ibex.
-:ref:`exceptions-interrupts` deals with the infrastructure for handling exceptions and interrupts,
-:ref:`pmp` gives a brief overview of PMP support.
-:ref:`debug-support` gives a brief overview on the debug infrastructure.
-:ref:`tracer` gives a brief overview of the tracer module.
-For information regarding formal verification support, check out :ref:`rvfi`.
-:ref:`examples` gives an overview of how Ibex can be used.
+ * :ref:`getting-started` discusses the requirements and initial steps to start using Ibex.
+ * :ref:`core-integration` provides the instantiation template and gives descriptions of the design parameters as well as the input and output ports.
+ * :ref:`pipeline-details` described the overal pipeline structure.
+ * :ref:`instruction-decode-execute` describes how the Instruction Decode and Execute stage works.
+ * The instruction and data interfaces of Ibex are explained in :ref:`instruction-fetch` and :ref:`load-store-unit`, respectively.
+ * The two register-file flavors are described in :ref:`register-file`.
+ * The control and status registers are explained in :ref:`cs-registers`.
+ * :ref:`performance-counters` gives an overview of the performance monitors and event counters available in Ibex.
+ * :ref:`exceptions-interrupts` deals with the infrastructure for handling exceptions and interrupts,
+ * :ref:`pmp` gives a brief overview of PMP support.
+ * :ref:`debug-support` gives a brief overview on the debug infrastructure.
+ * :ref:`tracer` gives a brief overview of the tracer module.
+ * For information regarding formal verification support, check out :ref:`rvfi`.
+ * :ref:`examples` gives an overview of how Ibex can be used.
History
diff --git a/hw/vendor/lowrisc_ibex/doc/load_store_unit.rst b/hw/vendor/lowrisc_ibex/doc/load_store_unit.rst
index cedfe61..55b7737 100644
--- a/hw/vendor/lowrisc_ibex/doc/load_store_unit.rst
+++ b/hw/vendor/lowrisc_ibex/doc/load_store_unit.rst
@@ -2,10 +2,16 @@
Load-Store Unit
===============
+:file:`rtl/ibex_load_store_unit.sv`
The Load-Store Unit (LSU) of the core takes care of accessing the data memory.
Loads and stores of words (32 bit), half words (16 bit) and bytes (8 bit) are supported.
+Any load or store will stall the ID/EX stage for at least a cycle to await the response (whether that is awaiting load data or a response indicating whether an error has been seen for a store).
+
+Data-Side Memory Interface
+--------------------------
+
Signals that are used by the LSU:
+-------------------------+-----------+-----------------------------------------------+
@@ -81,7 +87,7 @@
{"name": "data_we_o", "wave": "x=.xxxx", "data": ["WE"]},
{"name": "data_be_o", "wave": "x=.xxxx", "data": ["BE"]},
{"name": "data_wdata_o", "wave": "x=.xxxx", "data": ["WData"]},
- {"name": "data_gnt_i", "wave": "0.10..."},
+ {"name": "data_gnt_i", "wave": "0.10..."},
{"name": "data_rvalid_i", "wave": "0..10.."},
{"name": "data_err_i", "wave": "xxx=xxx", "data": ["Err"]},
{"name": "data_rdata_i", "wave": "xxx=xxx", "data": ["RData"]}
@@ -109,7 +115,7 @@
],
"config": { "hscale": 2 }
}
-
+
.. wavedrom::
:name: timing3
:caption: Slow Response Memory Transaction
@@ -122,7 +128,7 @@
{"name": "data_we_o", "wave": "x=..xxx", "data": ["WE"]},
{"name": "data_be_o", "wave": "x=..xxx", "data": ["BE"]},
{"name": "data_wdata_o", "wave": "x=..xxx", "data": ["WData"]},
- {"name": "data_gnt_i", "wave": "0..10.."},
+ {"name": "data_gnt_i", "wave": "0..10.."},
{"name": "data_rvalid_i", "wave": "0....10"},
{"name": "data_err_i", "wave": "xxxxx=x", "data": ["Err"]},
{"name": "data_rdata_i", "wave": "xxxxx=x", "data": ["RData"]}
diff --git a/hw/vendor/lowrisc_ibex/doc/performance_counters.rst b/hw/vendor/lowrisc_ibex/doc/performance_counters.rst
index 5c17148..e42b32b 100644
--- a/hw/vendor/lowrisc_ibex/doc/performance_counters.rst
+++ b/hw/vendor/lowrisc_ibex/doc/performance_counters.rst
@@ -71,7 +71,7 @@
Unavailable counters always read 0.
-The association of events with the ``mphmcounter``s is hardwired as listed in the following table.
+The association of events with the ``mphmcounter`` registers is hardwired as listed in the following table.
+----------------------+----------------+--------------+------------------+
| Event Counter | CSR Address | Event ID/Bit | Event Name |
diff --git a/hw/vendor/lowrisc_ibex/doc/pipeline_details.rst b/hw/vendor/lowrisc_ibex/doc/pipeline_details.rst
new file mode 100644
index 0000000..eb13dd6
--- /dev/null
+++ b/hw/vendor/lowrisc_ibex/doc/pipeline_details.rst
@@ -0,0 +1,77 @@
+.. _pipeline-details:
+
+.. figure:: images/blockdiagram.svg
+ :name: ibex-pipeline
+ :align: center
+
+ Ibex Pipeline
+
+Pipeline Details
+================
+Ibex has a 2-stage pipeline, the 2 stages are:
+
+Instruction Fetch (IF)
+ Fetches instructions from memory via a prefetch buffer, capable of fetching 1 instruction per cycle if the instruction side memory system allows. See :ref:`instruction-fetch` for details.
+
+Instruction Decode and Execute (ID/EX)
+ Decodes fetched instruction and immediately executes it, register read and write all occurs in this stage.
+ Multi-cycle instructions will stall this stage until they are complete See :ref:`instruction-decode-execute` for details.
+
+All instructions require two cycles minimum to pass down the pipeline.
+One cycle in the IF stage and one in the ID/EX stage.
+Not all instructions can complete in the ID/EX stage in one cycle so will stall there until they complete.
+This means the maximum IPC (Instructions per Cycle) Ibex can achieve is 1 when multi-cycle instructions aren't used.
+See Multi- and Single-Cycle Instructions below for the details.
+
+Multi- and Single-Cycle Instructions
+------------------------------------
+
+In the table below when an instruction stalls for X cycles X + 1 cycles pass before a new instruction enters the ID/EX stage.
+Some instructions stall for a variable time, this is indicated as a range e.g. 1 - N means the instruction stalls a minimum of 1 cycle with an indeterminate maximum cycles.
+Read the description for more information.
+
++-----------------------+-----------------------+-------------------------------------------------------------+
+| Instruction Type | Stall Cycles | Description |
++=======================+=======================+=============================================================+
+| Integer Computational | 0 | Integer Computational Instructions are defined in the |
+| | | RISCV-V RV32I Base Integer Instruction Set. |
++-----------------------+-----------------------+-------------------------------------------------------------+
+| CSR Access | 0 | CSR Access Instruction are defined in 'Zicsr' of the |
+| | | RISC-V specification. |
++-----------------------+-----------------------+-------------------------------------------------------------+
+| Load/Store | 1 - N | Both loads and stores stall for at least one cycle to await |
+| | | a response. For loads this response is the load data |
+| | | (which is written directly to the register file the same |
+| | | cycle it is received). For stores this is whether an error |
+| | | was seen or not. The longer the data side memory interface |
+| | | takes to receive a response the longer loads and stores |
+| | | will stall. |
++-----------------------+-----------------------+-------------------------------------------------------------+
+| Multiplication | 2/3 (Fast Multiplier) | 2 for MUL, 3 for MULH. |
+| | | See details in :ref:`mult-div` |
+| | 32 (Slow Multiplier) | |
++-----------------------+-----------------------+-------------------------------------------------------------+
+| Division | 1 or 37 | 1 stall cycle if divide by 0, otherwise full long division. |
+| | | See details in :ref:`mult-div` |
+| Remainder | | |
++-----------------------+-----------------------+-------------------------------------------------------------+
+| Jump | 1 - N | Minimum one cycle stall to flush the prefetch counter and |
+| | | begin fetching from the new Program Counter (PC). The new |
+| | | PC request will appear on the instruction-side memory |
+| | | interface the same cycle the jump instruction enters ID/EX. |
+| | | The longer the instruction-side memory interface takes to |
+| | | receive data the longer the jump will stall. |
++-----------------------+-----------------------+-------------------------------------------------------------+
+| Branch (Not-Taken) | 0 | Any branch where the condition is not met will |
+| | | not stall. |
++-----------------------+-----------------------+-------------------------------------------------------------+
+| Branch (Taken) | 2 - N | Any branch where the condition is met will stall for 2 |
+| | | cycles as in the first cycle the branch is in ID/EX the ALU |
+| | | is used to calculate the branch condition. The following |
+| | | cycle the ALU is used again to calculate the branch target |
+| | | where it proceeds as Jump does above (Flush IF stage and |
+| | | prefetch buffer, new PC on instruction-side memory |
+| | | interface the same cycle it is calculated). The longer the |
+| | | instruction-side memory interface takes to receive data the |
+| | | longer the branch will stall. |
++-----------------------+-----------------------+-------------------------------------------------------------+
diff --git a/hw/vendor/lowrisc_ibex/doc/register_file.rst b/hw/vendor/lowrisc_ibex/doc/register_file.rst
index 60b1684..8c98879 100644
--- a/hw/vendor/lowrisc_ibex/doc/register_file.rst
+++ b/hw/vendor/lowrisc_ibex/doc/register_file.rst
@@ -2,10 +2,14 @@
Register File
=============
+Source FIles: :file:`rtl/ibex_register_file_ff.sv` :file:`rtl/ibex_register_file_latch.sv`
Ibex has either 31 or 15 32-bit registers if the RV32E extension is disabled or enabled, respectively.
Register ``x0`` is statically bound to 0 and can only be read, it does not contain any sequential logic.
+The register file has two read ports and one write port, register file data is available the same cycle a read is requested.
+There is no write to read forwarding path so if one register is being both read and written the read will return the current value rather than the value being written.
+
There are two flavors of register file available, both having their own benefits and trade-offs.
Flip-Flop-Based Register File
diff --git a/hw/vendor/lowrisc_ibex/doc/tracer.rst b/hw/vendor/lowrisc_ibex/doc/tracer.rst
index 7b67845..9e87950 100644
--- a/hw/vendor/lowrisc_ibex/doc/tracer.rst
+++ b/hw/vendor/lowrisc_ibex/doc/tracer.rst
@@ -4,8 +4,40 @@
======
The module ``ibex_tracer`` can be used to create a log of the executed instructions.
-It is used by ``ibex_core_tracing`` which forwards the signals added by :ref:`rvfi` as an input for the tracer.
+It is used by ``ibex_core_tracing`` which forwards the `RVFI signals <https://github.com/SymbioticEDA/riscv-formal/blob/master/docs/rvfi.md>`_ to the tracer (see also :ref:`rvfi`).
-.. note::
+Output file
+-----------
- ``ibex_tracer`` is not compatible with Verilator.
+All traced instructions are written to a log file.
+By default, the log file is named ``trace_core_<HARTID>.log``, with ``<HARTID>`` being the 8 digit hart ID of the core being traced.
+
+The file name base, defaulting to ``trace_core`` can be set using the ``ibex_tracer_file_base`` plusarg passed to the simulation.
+For example, ``+ibex_tracer_file_base=ibex_my_trace`` will produce log files named ``ibex_my_trace_<HARTID>.log``.
+The exact syntax of passing plusargs to a simulation depends on the simulator.
+
+Trace output format
+-------------------
+
+The trace output is in tab-separated columns.
+
+1. **Time**: The current simulation time.
+2. **Cycle**: The number of cycles since the last reset.
+3. **PC**: The program counter
+4. **Instr**: The executed instruction (base 16).
+ 32 bit wide instructions (8 hex digits) are uncompressed instructions, 16 bit wide instructions (4 hex digits) are compressed instructions.
+5. **Decoded instruction**: The decoded (disassembled) instruction in a format equal to what objdump produces when calling it like ``objdump -Mnumeric -Mno-aliases -D``.
+ - Unsigned numbers are given in hex (prefixed with ``0x``), signed numbers are given as decimal numbers.
+ - Numeric register names are used (e.g. ``x1``).
+ - Symbolic CSR names are used.
+ - Jump/branch targets are given as absolute address if possible (PC + immediate).
+6. **Register and memory contents**: For all accessed registers, the value before and after the instruction execution is given. Writes to registers are indicated as ``registername=value``, reads as ``registername:value``. For memory accesses, the address and the loaded and stored data are given.
+
+.. code-block:: text
+
+ Time Cycle PC Instr Decoded instruction Register and memory contents
+ 130 61 00000150 4481 c.li x9,0 x9=0x00000000
+ 132 62 00000152 00008437 lui x8,0x8 x8=0x00008000
+ 134 63 00000156 fff40413 addi x8,x8,-1 x8:0x00008000 x8=0x00007fff
+ 136 64 0000015a 8c65 c.and x8,x9 x8:0x00007fff x9:0x00000000 x8=0x00000000
+ 142 67 0000015c c622 c.swsp x8,12(x2) x2:0x00002000 x8:0x00000000 PA:0x0000200c store:0x00000000 load:0xffffffff
diff --git a/hw/vendor/lowrisc_ibex/doc/verification.rst b/hw/vendor/lowrisc_ibex/doc/verification.rst
index 66cd79b..c011d51 100644
--- a/hw/vendor/lowrisc_ibex/doc/verification.rst
+++ b/hw/vendor/lowrisc_ibex/doc/verification.rst
@@ -47,7 +47,7 @@
The flow is controlled by a `Makefile <https://github.com/lowRISC/ibex/blob/master/dv/uvm/Makefile>`_, here’s the list of frequently
used commands:
-.. codeblock:: bash
+.. code-block:: bash
# Run a full regression
make
@@ -90,7 +90,7 @@
You can add the compile/simulation options in `simulator.yaml <https://github.com/lowRISC/ibex/blob/master/dv/uvm/yaml/rtl_simulation.yaml>`_.
-.. codeblock:: bash
+.. code-block:: bash
# Use the new RTL simulator to run
make ... SIMULATOR=xxx
diff --git a/hw/vendor/lowrisc_ibex/dv/riscv_compliance/ibex_riscv_compliance.cc b/hw/vendor/lowrisc_ibex/dv/riscv_compliance/ibex_riscv_compliance.cc
index 7a02524..e5f02ee 100644
--- a/hw/vendor/lowrisc_ibex/dv/riscv_compliance/ibex_riscv_compliance.cc
+++ b/hw/vendor/lowrisc_ibex/dv/riscv_compliance/ibex_riscv_compliance.cc
@@ -6,12 +6,9 @@
#include <iostream>
-#include "Vibex_riscv_compliance.h"
#include "verilated_toplevel.h"
#include "verilator_sim_ctrl.h"
-VERILATED_TOPLEVEL(ibex_riscv_compliance)
-
ibex_riscv_compliance *top;
VerilatorSimCtrl *simctrl;
diff --git a/hw/vendor/lowrisc_ibex/dv/riscv_compliance/ibex_riscv_compliance.core b/hw/vendor/lowrisc_ibex/dv/riscv_compliance/ibex_riscv_compliance.core
index 5f7a316..6139e9b 100644
--- a/hw/vendor/lowrisc_ibex/dv/riscv_compliance/ibex_riscv_compliance.core
+++ b/hw/vendor/lowrisc_ibex/dv/riscv_compliance/ibex_riscv_compliance.core
@@ -8,7 +8,7 @@
files_sim_verilator:
depend:
- lowrisc:dv_verilator:simutil_verilator
- - lowrisc:ibex:ibex_core
+ - lowrisc:ibex:ibex_core_tracing
files:
- rtl/ibex_riscv_compliance.sv
@@ -56,7 +56,7 @@
# -O
# Optimization levels have a large impact on the runtime performance of the
# simulation model. -O2 and -O3 are pretty similar, -Os is slower than -O2/-O3
- - '-CFLAGS "-std=c++11 -Wall -DVM_TRACE_FMT_FST -g -O0"'
+ - '-CFLAGS "-std=c++11 -Wall -DVM_TRACE_FMT_FST -DTOPLEVEL_NAME=ibex_riscv_compliance -g -O0"'
- '-LDFLAGS "-pthread -lutil"'
- "-Wall"
- "-Wno-PINCONNECTEMPTY"
diff --git a/hw/vendor/lowrisc_ibex/dv/riscv_compliance/rtl/bus.sv b/hw/vendor/lowrisc_ibex/dv/riscv_compliance/rtl/bus.sv
index 4491e9e..188a2b8 100644
--- a/hw/vendor/lowrisc_ibex/dv/riscv_compliance/rtl/bus.sv
+++ b/hw/vendor/lowrisc_ibex/dv/riscv_compliance/rtl/bus.sv
@@ -104,12 +104,13 @@
always_comb begin
for (integer host = 0; host < NrHosts; host = host + 1) begin
+ host_gnt_o[host] = 1'b0;
+
if ($clog2(NrHosts)'(host) == host_sel_resp) begin
host_rvalid_o[host] = device_rvalid_i[device_sel_resp];
host_err_o[host] = device_err_i[device_sel_resp];
host_rdata_o[host] = device_rdata_i[device_sel_resp];
end else begin
- host_gnt_o[host] = 1'b0;
host_rvalid_o[host] = 1'b0;
host_err_o[host] = 1'b0;
host_rdata_o[host] = 'b0;
diff --git a/hw/vendor/lowrisc_ibex/dv/riscv_compliance/rtl/ibex_riscv_compliance.sv b/hw/vendor/lowrisc_ibex/dv/riscv_compliance/rtl/ibex_riscv_compliance.sv
index c55ec67..fc3facf 100644
--- a/hw/vendor/lowrisc_ibex/dv/riscv_compliance/rtl/ibex_riscv_compliance.sv
+++ b/hw/vendor/lowrisc_ibex/dv/riscv_compliance/rtl/ibex_riscv_compliance.sv
@@ -23,10 +23,11 @@
assign clk_sys = IO_CLK;
assign rst_sys_n = IO_RST_N;
+ // Bus hosts, ordered in decreasing priority
typedef enum {
TestUtilHost,
- CoreI,
- CoreD
+ CoreD,
+ CoreI
} bus_host_e;
typedef enum {
@@ -99,7 +100,7 @@
.cfg_device_addr_mask
);
- ibex_core #(
+ ibex_core_tracing #(
.DmHaltAddr(32'h00000000),
.DmExceptionAddr(32'h00000000),
.RV32E(RV32E),
diff --git a/hw/vendor/lowrisc_ibex/dv/uvm/Makefile b/hw/vendor/lowrisc_ibex/dv/uvm/Makefile
index b113a3c..d1e9534 100644
--- a/hw/vendor/lowrisc_ibex/dv/uvm/Makefile
+++ b/hw/vendor/lowrisc_ibex/dv/uvm/Makefile
@@ -73,11 +73,11 @@
--steps=gen \
--gen_timeout=${TIMEOUT} \
--lsf_cmd="${LSF_CMD}" \
+ --core_setting_dir=${DV_DIR}/riscv_dv_extension \
+ --user_extension_dir=${DV_DIR}/riscv_dv_extension \
+ --simulator=${SIMULATOR} \
${COMMON_OPTS} \
${CSR_OPTS} \
- --cmp_opts="+define+RISCV_CORE_SETTING=${DV_DIR}/riscv_dv_extension/ibex_core_setting.sv \
- +define+RISCV_DV_EXT_FILE_LIST=${DV_DIR}/riscv_dv_extension/flist \
- +incdir+${DV_DIR}/riscv_dv_extension/ " \
--sim_opts="+uvm_set_type_override=riscv_asm_program_gen,ibex_asm_program_gen \
+signature_addr=${SIGNATURE_ADDR}";
@@ -123,6 +123,7 @@
--simulator=${SIMULATOR} \
--en_cov ${COV} \
--en_wave ${WAVES} \
+ --lsf_cmd="${LSF_CMD}" \
--sim_opts="+signature_addr=0x${SIGNATURE_ADDR}" \
${SIM_OPTS}
@@ -136,6 +137,12 @@
--simulator=${SIMULATOR} \
--iss=${ISS}
+
+# Generate functional coverage
+fcov:
+ cd ${GEN_DIR}; \
+ python3 ./cov.py --dir ${OUT}/instr_gen/spike_sim -o ${OUT}/fcov
+
# Load verdi to review coverage
cov:
cd ${OUT}/rtl_sim; verdi -cov -covdir test.vdb &
diff --git a/hw/vendor/lowrisc_ibex/dv/uvm/common/ibex_mem_intf_agent/ibex_mem_intf.sv b/hw/vendor/lowrisc_ibex/dv/uvm/common/ibex_mem_intf_agent/ibex_mem_intf.sv
index 8285e56..6d0cf08 100644
--- a/hw/vendor/lowrisc_ibex/dv/uvm/common/ibex_mem_intf_agent/ibex_mem_intf.sv
+++ b/hw/vendor/lowrisc_ibex/dv/uvm/common/ibex_mem_intf_agent/ibex_mem_intf.sv
@@ -14,5 +14,6 @@
logic rvalid;
logic [DATA_WIDTH-1:0] wdata;
logic [DATA_WIDTH-1:0] rdata;
+ logic error;
endinterface : ibex_mem_intf
diff --git a/hw/vendor/lowrisc_ibex/dv/uvm/common/ibex_mem_intf_agent/ibex_mem_intf_seq_item.sv b/hw/vendor/lowrisc_ibex/dv/uvm/common/ibex_mem_intf_agent/ibex_mem_intf_seq_item.sv
index ae1ff19..fc218c0 100644
--- a/hw/vendor/lowrisc_ibex/dv/uvm/common/ibex_mem_intf_agent/ibex_mem_intf_seq_item.sv
+++ b/hw/vendor/lowrisc_ibex/dv/uvm/common/ibex_mem_intf_agent/ibex_mem_intf_seq_item.sv
@@ -15,6 +15,7 @@
rand bit [3:0] gnt_delay;
rand bit [3:0] req_delay;
rand bit [5:0] rvalid_delay;
+ rand bit error;
`uvm_object_utils_begin(ibex_mem_intf_seq_item)
`uvm_field_int (addr, UVM_DEFAULT)
@@ -23,6 +24,7 @@
`uvm_field_int (data, UVM_DEFAULT)
`uvm_field_int (gnt_delay, UVM_DEFAULT)
`uvm_field_int (rvalid_delay, UVM_DEFAULT)
+ `uvm_field_int (error, UVM_DEFAULT)
`uvm_object_utils_end
`uvm_object_new
diff --git a/hw/vendor/lowrisc_ibex/dv/uvm/common/ibex_mem_intf_agent/ibex_mem_intf_slave_driver.sv b/hw/vendor/lowrisc_ibex/dv/uvm/common/ibex_mem_intf_agent/ibex_mem_intf_slave_driver.sv
index 2a48b9d..49c76e0 100644
--- a/hw/vendor/lowrisc_ibex/dv/uvm/common/ibex_mem_intf_agent/ibex_mem_intf_slave_driver.sv
+++ b/hw/vendor/lowrisc_ibex/dv/uvm/common/ibex_mem_intf_agent/ibex_mem_intf_slave_driver.sv
@@ -10,15 +10,16 @@
protected virtual ibex_mem_intf vif;
+ int unsigned min_grant_delay = 0;
+ int unsigned max_grant_delay = 10;
+
`uvm_component_utils(ibex_mem_intf_slave_driver)
`uvm_component_new
- mailbox #(ibex_mem_intf_seq_item) grant_queue;
mailbox #(ibex_mem_intf_seq_item) rdata_queue;
function void build_phase(uvm_phase phase);
super.build_phase(phase);
- grant_queue = new();
rdata_queue = new();
if(!uvm_config_db#(virtual ibex_mem_intf)::get(this, "", "vif", vif))
`uvm_fatal("NOVIF",{"virtual interface must be set for: ",get_full_name(),".vif"});
@@ -36,6 +37,7 @@
vif.rvalid <= 1'b0;
vif.grant <= 1'b0;
vif.rdata <= 'b0;
+ vif.error <= 1'b0;
endtask : reset_signals
virtual protected task get_and_drive();
@@ -55,15 +57,22 @@
join_none
endtask : get_and_drive
- // TODO(udinator) - this direct send_grant logic is temporary until instruction fetch protocol
- // issue is clarified (https://github.com/lowRISC/ibex/pull/293). After resolution, will re-add
- // random delays insertion before driving grant to the ibex core.
virtual protected task send_grant();
int gnt_delay;
forever begin
while(vif.request !== 1'b1) begin
@(negedge vif.clock);
end
+ if (!std::randomize(gnt_delay) with {
+ gnt_delay dist {
+ min_grant_delay :/ 1,
+ [min_grant_delay+1 : max_grant_delay-1] :/ 1,
+ max_grant_delay :/ 1
+ };
+ }) begin
+ `uvm_fatal(`gfn, $sformatf("Cannot randomize grant"))
+ end
+ repeat(gnt_delay) @(negedge vif.clock);
if(~vif.reset) begin
vif.grant = 1'b1;
@(negedge vif.clock);
@@ -78,11 +87,13 @@
@(posedge vif.clock);
vif.rvalid <= 1'b0;
vif.rdata <= 'x;
+ vif.error <= 1'b0;
rdata_queue.get(tr);
if(vif.reset) continue;
repeat(tr.rvalid_delay) @(posedge vif.clock);
if(~vif.reset) begin
vif.rvalid <= 1'b1;
+ vif.error <= tr.error;
vif.rdata <= tr.data;
end
end
diff --git a/hw/vendor/lowrisc_ibex/dv/uvm/common/ibex_mem_intf_agent/ibex_mem_intf_slave_seq_lib.sv b/hw/vendor/lowrisc_ibex/dv/uvm/common/ibex_mem_intf_agent/ibex_mem_intf_slave_seq_lib.sv
index 9ece388..1dc80ef 100644
--- a/hw/vendor/lowrisc_ibex/dv/uvm/common/ibex_mem_intf_agent/ibex_mem_intf_slave_seq_lib.sv
+++ b/hw/vendor/lowrisc_ibex/dv/uvm/common/ibex_mem_intf_agent/ibex_mem_intf_slave_seq_lib.sv
@@ -12,6 +12,10 @@
int min_rvalid_delay = 0;
ibex_mem_intf_seq_item item;
mem_model m_mem;
+ bit enable_error = 1'b0;
+ // Used to ensure that whenever inject_error() is called, the very next transaction will inject an
+ // error, and that enable_error will not be flipped back to 0 immediately
+ bit error_synch = 1'b1;
`uvm_object_utils(ibex_mem_intf_slave_seq)
`uvm_declare_p_sequencer(ibex_mem_intf_slave_sequencer)
@@ -23,9 +27,11 @@
forever
begin
bit [ADDR_WIDTH-1:0] aligned_addr;
+ bit [DATA_WIDTH-1:0] rand_data;
p_sequencer.addr_ph_port.get(item);
req = ibex_mem_intf_seq_item::type_id::create("req");
- req.randomize() with {
+ error_synch = 1'b0;
+ if (!req.randomize() with {
addr == item.addr;
read_write == item.read_write;
data == item.data;
@@ -36,10 +42,20 @@
[max_rvalid_delay/2 : max_rvalid_delay-1] :/ 1,
max_rvalid_delay :/ 1
};
- };
+ error == enable_error;
+ }) begin
+ `uvm_fatal(`gfn, "Cannot randomize slave request")
+ end
+ enable_error = 1'b0;
+ error_synch = 1'b1;
aligned_addr = {req.addr[DATA_WIDTH-1:2], 2'b0};
- if(req.read_write == READ) begin : READ_block
- req.data = m_mem.read(aligned_addr);
+ if (req.error) begin
+ `DV_CHECK_STD_RANDOMIZE_FATAL(rand_data)
+ req.data = rand_data;
+ end else begin
+ if(req.read_write == READ) begin : READ_block
+ req.data = m_mem.read(aligned_addr);
+ end
end
`uvm_info(get_full_name(), $sformatf("Response transfer:\n%0s", req.sprint()), UVM_HIGH)
start_item(req);
@@ -56,4 +72,12 @@
end
endtask : body
+ virtual function inject_error();
+ this.enable_error = 1'b1;
+ endfunction
+
+ virtual function bit get_error_synch();
+ return this.error_synch;
+ endfunction
+
endclass : ibex_mem_intf_slave_seq
diff --git a/hw/vendor/lowrisc_ibex/dv/uvm/common/irq_agent/irq_master_driver.sv b/hw/vendor/lowrisc_ibex/dv/uvm/common/irq_agent/irq_master_driver.sv
index 23ad25a..89709c6 100644
--- a/hw/vendor/lowrisc_ibex/dv/uvm/common/irq_agent/irq_master_driver.sv
+++ b/hw/vendor/lowrisc_ibex/dv/uvm/common/irq_agent/irq_master_driver.sv
@@ -40,10 +40,8 @@
endtask : get_and_drive
virtual protected task reset_signals();
- forever begin
- @(posedge vif.reset);
- drive_reset_value();
- end
+ @(negedge vif.reset);
+ drive_reset_value();
endtask : reset_signals
virtual protected task drive_seq_item (irq_seq_item trans);
@@ -52,11 +50,6 @@
vif.irq_external <= trans.irq_external;
vif.irq_fast <= trans.irq_fast;
vif.irq_nm <= trans.irq_nm;
- // We hold the interrupt high for two cycles as Ibex is level sensitive,
- // so this guarantees that Ibex will respond appropriately to the
- // interrupt
- repeat (2) @(posedge vif.clock);
- drive_reset_value();
endtask : drive_seq_item
task drive_reset_value();
diff --git a/hw/vendor/lowrisc_ibex/dv/uvm/common/irq_agent/irq_monitor.sv b/hw/vendor/lowrisc_ibex/dv/uvm/common/irq_agent/irq_monitor.sv
index f3332f3..d4c5362 100644
--- a/hw/vendor/lowrisc_ibex/dv/uvm/common/irq_agent/irq_monitor.sv
+++ b/hw/vendor/lowrisc_ibex/dv/uvm/common/irq_agent/irq_monitor.sv
@@ -25,11 +25,23 @@
collect_irq();
endtask : run_phase
+ // We know that for Ibex, any given interrupt stimulus will be asserted until the core signals the
+ // testbench that it has finished handling, and this stimulus will not change until the testbench
+ // receives the signal, at which point it will drop.
+ // Given this, as well as how the interrupt handshakes are designed, sending an irq_seq_item every
+ // cycle is not useful at all.
+ // In order to not send unnecessary sequence items, but to also send enough information that the
+ // testbench can handle nested interrupt scenarios, the monitor will send out a sequence
+ // item every time the interrupt lines change.
virtual protected task collect_irq();
irq_seq_item irq;
+ bit[DATA_WIDTH-1:0] stored_irq_val = '0;
+ bit[DATA_WIDTH-1:0] current_irq = '0;
forever begin
- if (|{vif.irq_software, vif.irq_timer, vif.irq_external,
- vif.irq_fast, vif.irq_nm}) begin
+ current_irq = {vif.irq_nm, vif.irq_fast, 4'b0, vif.irq_external, 3'b0,
+ vif.irq_timer, 3'b0, vif.irq_software, 3'b0};
+ if (current_irq !== stored_irq_val) begin
+ stored_irq_val = current_irq;
irq = irq_seq_item::type_id::create("irq");
irq.irq_software = vif.irq_software;
irq.irq_timer = vif.irq_timer;
diff --git a/hw/vendor/lowrisc_ibex/dv/uvm/common/irq_agent/irq_seq_item.sv b/hw/vendor/lowrisc_ibex/dv/uvm/common/irq_agent/irq_seq_item.sv
index 771fa03..ccc99bc 100644
--- a/hw/vendor/lowrisc_ibex/dv/uvm/common/irq_agent/irq_seq_item.sv
+++ b/hw/vendor/lowrisc_ibex/dv/uvm/common/irq_agent/irq_seq_item.sv
@@ -12,7 +12,7 @@
rand int num_of_interrupt;
constraint num_of_interrupt_c {
- num_of_interrupt inside {[1:19]};
+ num_of_interrupt inside {[0:DATA_WIDTH-1]};
$countones({irq_software, irq_timer, irq_external, irq_fast, irq_nm}) == num_of_interrupt;
}
diff --git a/hw/vendor/lowrisc_ibex/dv/uvm/common/mem_model/mem_model.sv b/hw/vendor/lowrisc_ibex/dv/uvm/common/mem_model/mem_model.sv
index 4609a7f..a31529d 100644
--- a/hw/vendor/lowrisc_ibex/dv/uvm/common/mem_model/mem_model.sv
+++ b/hw/vendor/lowrisc_ibex/dv/uvm/common/mem_model/mem_model.sv
@@ -23,7 +23,7 @@
$sformatf("Read Mem : Addr[0x%0h], Data[0x%0h]", addr, data), UVM_HIGH)
end
else begin
- std::randomize(data);
+ void'(std::randomize(data));
`uvm_error(get_full_name(), $sformatf("read to uninitialzed addr 0x%0h", addr))
end
return data;
diff --git a/hw/vendor/lowrisc_ibex/dv/uvm/cover.cfg b/hw/vendor/lowrisc_ibex/dv/uvm/cover.cfg
index e3a4a0d..452ce7f 100644
--- a/hw/vendor/lowrisc_ibex/dv/uvm/cover.cfg
+++ b/hw/vendor/lowrisc_ibex/dv/uvm/cover.cfg
@@ -1 +1,4 @@
+tree core_ibex_tb_top.dut
+begin tgl
+ -tree core_ibex_tb_top.dut.*
+end
diff --git a/hw/vendor/lowrisc_ibex/dv/uvm/env/core_ibex_dut_probe_if.sv b/hw/vendor/lowrisc_ibex/dv/uvm/env/core_ibex_dut_probe_if.sv
index 48fa34c..efa9ff3 100644
--- a/hw/vendor/lowrisc_ibex/dv/uvm/env/core_ibex_dut_probe_if.sv
+++ b/hw/vendor/lowrisc_ibex/dv/uvm/env/core_ibex_dut_probe_if.sv
@@ -11,5 +11,6 @@
logic dret;
logic mret;
logic fetch_enable;
+ logic core_sleep;
logic debug_req;
endinterface
diff --git a/hw/vendor/lowrisc_ibex/dv/uvm/env/core_ibex_env.sv b/hw/vendor/lowrisc_ibex/dv/uvm/env/core_ibex_env.sv
index 58af297..3e20b3d 100644
--- a/hw/vendor/lowrisc_ibex/dv/uvm/env/core_ibex_env.sv
+++ b/hw/vendor/lowrisc_ibex/dv/uvm/env/core_ibex_env.sv
@@ -25,9 +25,7 @@
create("data_if_slave_agent", this);
instr_if_slave_agent = ibex_mem_intf_slave_agent::type_id::
create("instr_if_slave_agent", this);
- if (cfg.enable_irq_stress_seq || cfg.enable_irq_single_seq) begin
- irq_agent = irq_master_agent::type_id::create("irq_agent", this);
- end
+ irq_agent = irq_master_agent::type_id::create("irq_agent", this);
// Create virtual sequencer
vseqr = core_ibex_vseqr::type_id::create("vseqr", this);
endfunction : build_phase
@@ -36,9 +34,7 @@
super.connect_phase(phase);
vseqr.data_if_seqr = data_if_slave_agent.sequencer;
vseqr.instr_if_seqr = instr_if_slave_agent.sequencer;
- if (cfg.enable_irq_stress_seq || cfg.enable_irq_single_seq) begin
- vseqr.irq_seqr = irq_agent.sequencer;
- end
+ vseqr.irq_seqr = irq_agent.sequencer;
endfunction : connect_phase
endclass
diff --git a/hw/vendor/lowrisc_ibex/dv/uvm/env/core_ibex_env_cfg.sv b/hw/vendor/lowrisc_ibex/dv/uvm/env/core_ibex_env_cfg.sv
index 388bc24..988de60 100644
--- a/hw/vendor/lowrisc_ibex/dv/uvm/env/core_ibex_env_cfg.sv
+++ b/hw/vendor/lowrisc_ibex/dv/uvm/env/core_ibex_env_cfg.sv
@@ -4,8 +4,7 @@
class core_ibex_env_cfg extends uvm_object;
- bit enable_irq_stress_seq;
- bit enable_irq_single_seq;
+ bit enable_irq_seq;
bit enable_debug_stress_seq;
bit enable_debug_single_seq;
bit[31:0] max_interval;
@@ -13,8 +12,7 @@
bit[31:0] signature_addr;
`uvm_object_utils_begin(core_ibex_env_cfg)
- `uvm_field_int(enable_irq_stress_seq, UVM_DEFAULT)
- `uvm_field_int(enable_irq_single_seq, UVM_DEFAULT)
+ `uvm_field_int(enable_irq_seq, UVM_DEFAULT)
`uvm_field_int(enable_debug_single_seq, UVM_DEFAULT)
`uvm_field_int(enable_debug_stress_seq, UVM_DEFAULT)
`uvm_field_int(max_interval, UVM_DEFAULT)
@@ -24,8 +22,7 @@
function new(string name = "");
super.new(name);
- void'($value$plusargs("enable_irq_stress_seq=%0d", enable_irq_stress_seq));
- void'($value$plusargs("enable_irq_single_seq=%0d", enable_irq_single_seq));
+ void'($value$plusargs("enable_irq_seq=%0d", enable_irq_seq));
void'($value$plusargs("enable_debug_stress_seq=%0d", enable_debug_stress_seq));
void'($value$plusargs("enable_debug_single_seq=%0d", enable_debug_single_seq));
void'($value$plusargs("max_interval=%0d", max_interval));
diff --git a/hw/vendor/lowrisc_ibex/dv/uvm/env/core_ibex_env_pkg.sv b/hw/vendor/lowrisc_ibex/dv/uvm/env/core_ibex_env_pkg.sv
index c8b69db..63ee631 100644
--- a/hw/vendor/lowrisc_ibex/dv/uvm/env/core_ibex_env_pkg.sv
+++ b/hw/vendor/lowrisc_ibex/dv/uvm/env/core_ibex_env_pkg.sv
@@ -7,6 +7,7 @@
// ---------------------------------------------
`include "core_ibex_dut_probe_if.sv"
+`include "core_ibex_rvfi_if.sv"
package core_ibex_env_pkg;
diff --git a/hw/vendor/lowrisc_ibex/dv/uvm/env/core_ibex_rvfi_if.sv b/hw/vendor/lowrisc_ibex/dv/uvm/env/core_ibex_rvfi_if.sv
new file mode 100644
index 0000000..1515adf
--- /dev/null
+++ b/hw/vendor/lowrisc_ibex/dv/uvm/env/core_ibex_rvfi_if.sv
@@ -0,0 +1,27 @@
+// Copyright lowRISC contributors.
+// Licensed under the Apache License, Version 2.0, see LICENSE for details.
+// SPDX-License-Identifier: Apache-2.0
+
+// Interface to probe Ibex RVFI interface
+interface core_ibex_rvfi_if(input logic clk);
+ logic valid;
+ logic [63:0] order;
+ logic [31:0] insn;
+ logic trap;
+ logic halt;
+ logic intr;
+ logic [1:0] mode;
+ logic [4:0] rs1_addr;
+ logic [4:0] rs2_addr;
+ logic [31:0] rs1_rdata;
+ logic [31:0] rs2_rdata;
+ logic [4:0] rd_addr;
+ logic [31:0] rd_wdata;
+ logic [31:0] pc_rdata;
+ logic [31:0] pc_wdata;
+ logic [31:0] mem_addr;
+ logic [3:0] mem_rmask;
+ logic [3:0] mem_wmask;
+ logic [31:0] mem_rdata;
+ logic [31:0] mem_wdata;
+endinterface
diff --git a/hw/vendor/lowrisc_ibex/dv/uvm/riscv_dv_extension/ibex_asm_program_gen.sv b/hw/vendor/lowrisc_ibex/dv/uvm/riscv_dv_extension/ibex_asm_program_gen.sv
index 1abe405..e81d962 100644
--- a/hw/vendor/lowrisc_ibex/dv/uvm/riscv_dv_extension/ibex_asm_program_gen.sv
+++ b/hw/vendor/lowrisc_ibex/dv/uvm/riscv_dv_extension/ibex_asm_program_gen.sv
@@ -21,9 +21,7 @@
// with ibex.
cfg.check_misa_init_val = 1'b0;
cfg.check_xstatus = 1'b0;
- instr_stream.push_back(".macro init");
- instr_stream.push_back(".endm");
- instr_stream.push_back(".section .text.init");
+ instr_stream.push_back(".section .text");
instr_stream.push_back(".globl _start");
instr_stream.push_back(".option norvc");
// 0x0 debug mode entry
diff --git a/hw/vendor/lowrisc_ibex/dv/uvm/riscv_dv_extension/ibex_core_setting.sv b/hw/vendor/lowrisc_ibex/dv/uvm/riscv_dv_extension/ibex_core_setting.sv
deleted file mode 100644
index 4f4c598..0000000
--- a/hw/vendor/lowrisc_ibex/dv/uvm/riscv_dv_extension/ibex_core_setting.sv
+++ /dev/null
@@ -1,103 +0,0 @@
-/*
- * Copyright 2019 Google LLC
- *
- * Licensed under the Apache License, Version 2.0 (the "License");
- * you may not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- * http://www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS,
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- */
-
-//-----------------------------------------------------------------------------
-// Processor feature configuration
-//-----------------------------------------------------------------------------
-// XLEN
-parameter int XLEN = 32;
-
-// Parameter for SATP mode, set to BARE if address translation is not supported
-parameter satp_mode_t SATP_MODE = BARE;
-
-// Supported Privileged mode
-privileged_mode_t supported_privileged_mode[] = {MACHINE_MODE};
-
-// Unsupported instructions
-// Avoid generating these instructions in regular regression
-// FENCE.I is intentionally treated as illegal instruction by ibex core
-riscv_instr_name_t unsupported_instr[] = {FENCEI};
-
-// ISA supported by the processor
-riscv_instr_group_t supported_isa[$] = {RV32I, RV32M, RV32C};
-
-// Interrupt mode support
-mtvec_mode_t supported_interrupt_mode[$] = {VECTORED};
-
-// Debug mode support
-bit support_debug_mode = 1;
-
-// Support delegate trap to user mode
-bit support_umode_trap = 0;
-
-// Support sfence.vma instruction
-bit support_sfence = 0;
-
-// Cache line size (in bytes)
-// If processor does not support caches, set to XLEN/8
-int dcache_line_size_in_bytes = 128;
-
-// Number of data section
-// For processor that doesn't have data TLB, this can be set to 1
-// For processor that supports data TLB, this should be set to be larger than the number
-// of entries of dTLB to cover dTLB hit/miss scenario
-int num_of_data_pages = 4;
-
-// Data section byte size
-// For processor with no dTLB and data cache, keep the value below 10K
-// For processor with dTLB support, set it to the physical memory size that covers one entry
-// of the dTLB
-int data_page_size = 4096;
-int data_page_alignment = $clog2(data_page_size);
-
-// Stack section word length
-int stack_len = 5000;
-
-//-----------------------------------------------------------------------------
-// Kernel section setting, used by supervisor mode programs
-//-----------------------------------------------------------------------------
-
-// Number of kernel data pages
-int num_of_kernel_data_pages = 2;
-
-// Byte size of kernel data pages
-int kernel_data_page_size = 4096;
-
-// Kernel Stack section word length
-int kernel_stack_len = 5000;
-
-// Number of instructions for each kernel program
-int kernel_program_instr_cnt = 400;
-
-// ----------------------------------------------------------------------------
-// Previleged CSR implementation
-// ----------------------------------------------------------------------------
-
-// Implemented previlieged CSR list
-privileged_reg_t implemented_csr[$] = {
- // Machine mode mode CSR
- MVENDORID, // Vendor ID
- MARCHID, // Architecture ID
- MHARTID, // Hardware thread ID
- MSTATUS, // Machine status
- MISA, // ISA and extensions
- MTVEC, // Machine trap-handler base address
- MEPC, // Machine exception program counter
- MCAUSE, // Machine trap cause
- MTVAL, // Machine bad address or instruction
- MIE // Machine interrupt enable
- // TODO: Add performance CSRs and debug mode CSR
-};
diff --git a/hw/vendor/lowrisc_ibex/dv/uvm/riscv_dv_extension/ibex_log_to_trace_csv.py b/hw/vendor/lowrisc_ibex/dv/uvm/riscv_dv_extension/ibex_log_to_trace_csv.py
index d6c7fac..03d508c 100644
--- a/hw/vendor/lowrisc_ibex/dv/uvm/riscv_dv_extension/ibex_log_to_trace_csv.py
+++ b/hw/vendor/lowrisc_ibex/dv/uvm/riscv_dv_extension/ibex_log_to_trace_csv.py
@@ -11,6 +11,7 @@
sys.path.insert(0, "../../vendor/google_riscv-dv/scripts")
from riscv_trace_csv import *
+from lib import *
def process_ibex_sim_log(ibex_log, csv):
@@ -19,7 +20,7 @@
Extract instruction and affected register information from ibex simulation
log and save to a standard CSV format.
"""
- print("Processing ibex log : %s" % ibex_log)
+ logging.info("Processing ibex log : %s" % ibex_log)
instr_cnt = 0
ibex_instr = ""
@@ -29,10 +30,10 @@
for line in f:
if re.search("ecall", line):
break
- # Extract instruction infromation
- m = re.search(r"^\s*(?P<time>\d+)\s+(?P<cycle>\d+) " \
- "(?P<pc>[0-9a-f]+) (?P<bin>[0-9a-f]+) (?P<instr>.*)" \
- "x(?P<rd>\d+)=0x(?P<val>[0-9a-f]+)", line)
+ # Extract instruction information
+ m = re.search(r"^\s*(?P<time>\d+)\s+(?P<cycle>\d+)\s+" \
+ "(?P<pc>[0-9a-f]+)\s+(?P<bin>[0-9a-f]+)\s+(?P<instr>.*)" \
+ ".*x(?P<rd>[1-9]\d*)=0x(?P<val>[0-9a-f]+)", line)
if m:
# Write the extracted instruction to a csvcol buffer file
rv_instr_trace = RiscvInstructiontTraceEntry()
@@ -44,7 +45,7 @@
trace_csv.write_trace_entry(rv_instr_trace)
instr_cnt += 1
- print("Processed instruction count : %d" % instr_cnt)
+ logging.info("Processed instruction count : %d" % instr_cnt)
def check_ibex_uvm_log(uvm_log, core_name, test_name, report, write=True):
diff --git a/hw/vendor/lowrisc_ibex/dv/uvm/riscv_dv_extension/riscv_core_setting.sv b/hw/vendor/lowrisc_ibex/dv/uvm/riscv_dv_extension/riscv_core_setting.sv
new file mode 100644
index 0000000..621aeee
--- /dev/null
+++ b/hw/vendor/lowrisc_ibex/dv/uvm/riscv_dv_extension/riscv_core_setting.sv
@@ -0,0 +1,158 @@
+/*
+ * Copyright 2019 Google LLC
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+//-----------------------------------------------------------------------------
+// Processor feature configuration
+//-----------------------------------------------------------------------------
+// XLEN
+parameter int XLEN = 32;
+
+// Parameter for SATP mode, set to BARE if address translation is not supported
+parameter satp_mode_t SATP_MODE = BARE;
+
+// Supported Privileged mode
+privileged_mode_t supported_privileged_mode[] = {MACHINE_MODE};
+
+// Unsupported instructions
+// Avoid generating these instructions in regular regression
+// FENCE.I is intentionally treated as illegal instruction by ibex core
+riscv_instr_name_t unsupported_instr[] = {FENCE_I};
+
+// ISA supported by the processor
+riscv_instr_group_t supported_isa[$] = {RV32I, RV32M, RV32C};
+
+// Interrupt mode support
+mtvec_mode_t supported_interrupt_mode[$] = {VECTORED};
+
+// The number of interrupt vectors to be generated, only used if VECTORED interrupt mode is
+// supported
+int max_interrupt_vector_num = 32;
+
+// Debug mode support
+bit support_debug_mode = 1;
+
+// Support delegate trap to user mode
+bit support_umode_trap = 0;
+
+// Support sfence.vma instruction
+bit support_sfence = 0;
+
+//-----------------------------------------------------------------------------
+// Kernel section setting, used by supervisor mode programs
+//-----------------------------------------------------------------------------
+
+// Number of kernel data pages
+int num_of_kernel_data_pages = 2;
+
+// Byte size of kernel data pages
+int kernel_data_page_size = 4096;
+
+// Kernel Stack section word length
+int kernel_stack_len = 5000;
+
+// Number of instructions for each kernel program
+int kernel_program_instr_cnt = 400;
+
+// ----------------------------------------------------------------------------
+// Previleged CSR implementation
+// ----------------------------------------------------------------------------
+
+// Implemented previlieged CSR list
+parameter privileged_reg_t implemented_csr[] = {
+ // Machine mode mode CSR
+ MVENDORID, // Vendor ID
+ MARCHID, // Architecture ID
+ MHARTID, // Hardware thread ID
+ MSTATUS, // Machine status
+ MISA, // ISA and extensions
+ MTVEC, // Machine trap-handler base address
+ MEPC, // Machine exception program counter
+ MCAUSE, // Machine trap cause
+ MTVAL, // Machine bad address or instruction
+ MIE, // Machine interrupt enable
+ MCYCLE, // Machine cycle counter (lower 32 bits)
+ MCYCLEH, // Machine cycle counter (upper 32 bits)
+ MINSTRET, // Machine instructions retired counter (lower 32 bits)
+ MINSTRETH, // Machine instructions retired counter (upper 32 bits)
+ MCOUNTINHIBIT, // Machine counter inhibit register
+ MHPMEVENT3, // Machine performance monitoring event selector
+ MHPMEVENT4, // Machine performance monitoring event selector
+ MHPMEVENT5, // Machine performance monitoring event selector
+ MHPMEVENT6, // Machine performance monitoring event selector
+ MHPMEVENT7, // Machine performance monitoring event selector
+ MHPMEVENT8, // Machine performance monitoring event selector
+ MHPMEVENT9, // Machine performance monitoring event selector
+ MHPMEVENT10, // Machine performance monitoring event selector
+ MHPMCOUNTER3, // Machine performance monitoring counter (lower 32 bits)
+ MHPMCOUNTER4, // Machine performance monitoring counter (lower 32 bits)
+ MHPMCOUNTER5, // Machine performance monitoring counter (lower 32 bits)
+ MHPMCOUNTER6, // Machine performance monitoring counter (lower 32 bits)
+ MHPMCOUNTER7, // Machine performance monitoring counter (lower 32 bits)
+ MHPMCOUNTER8, // Machine performance monitoring counter (lower 32 bits)
+ MHPMCOUNTER9, // Machine performance monitoring counter (lower 32 bits)
+ MHPMCOUNTER10, // Machine performance monitoring counter (lower 32 bits)
+ MHPMCOUNTER3H, // Machine performance monitoring counter (upper 32 bits)
+ MHPMCOUNTER4H, // Machine performance monitoring counter (upper 32 bits)
+ MHPMCOUNTER5H, // Machine performance monitoring counter (upper 32 bits)
+ MHPMCOUNTER6H, // Machine performance monitoring counter (upper 32 bits)
+ MHPMCOUNTER7H, // Machine performance monitoring counter (upper 32 bits)
+ MHPMCOUNTER8H, // Machine performance monitoring counter (upper 32 bits)
+ MHPMCOUNTER9H, // Machine performance monitoring counter (upper 32 bits)
+ MHPMCOUNTER10H, // Machine performance monitoring counter (upper 32 bits)
+ PMPCFG0, // PMP configuration register
+ PMPCFG1, // PMP configuration register
+ PMPCFG2, // PMP configuration register
+ PMPCFG3, // PMP configuration register
+ PMPADDR0, // PMP address register
+ PMPADDR1, // PMP address register
+ PMPADDR2, // PMP address register
+ PMPADDR3, // PMP address register
+ PMPADDR4, // PMP address register
+ PMPADDR5, // PMP address register
+ PMPADDR6, // PMP address register
+ PMPADDR7, // PMP address register
+ PMPADDR8, // PMP address register
+ PMPADDR9, // PMP address register
+ PMPADDR10, // PMP address register
+ PMPADDR11, // PMP address register
+ PMPADDR12, // PMP address register
+ PMPADDR13, // PMP address register
+ PMPADDR14, // PMP address register
+ PMPADDR15, // PMP address register
+ DCSR, // Debug control and status register
+ DPC, // Debug PC
+ DSCRATCH0, // Debug scratch register 0
+ DSCRATCH1 // Debug scratch register 1
+};
+
+// --------------------------------------------------------------------------
+// Supported interrupt/exception setting, used for functional coverage
+// --------------------------------------------------------------------------
+
+parameter interrupt_cause_t implemented_interrupt[] = {
+ M_SOFTWARE_INTR,
+ M_TIMER_INTR,
+ M_EXTERNAL_INTR
+};
+
+parameter exception_cause_t implemented_exception[] = {
+ INSTRUCTION_ACCESS_FAULT,
+ ILLEGAL_INSTRUCTION,
+ BREAKPOINT,
+ LOAD_ACCESS_FAULT,
+ STORE_AMO_ACCESS_FAULT,
+ ECALL_MMODE
+};
diff --git a/hw/vendor/lowrisc_ibex/dv/uvm/riscv_dv_extension/testlist.yaml b/hw/vendor/lowrisc_ibex/dv/uvm/riscv_dv_extension/testlist.yaml
index d21b79e..7f92fbc 100644
--- a/hw/vendor/lowrisc_ibex/dv/uvm/riscv_dv_extension/testlist.yaml
+++ b/hw/vendor/lowrisc_ibex/dv/uvm/riscv_dv_extension/testlist.yaml
@@ -9,8 +9,8 @@
+instr_cnt=10000
+num_of_sub_program=0
+no_fence=1
- +no_data_page=1'b1
- +no_branch_jump=1'b1
+ +no_data_page=1
+ +no_branch_jump=1
+boot_mode=m
iterations: 10
gen_test: riscv_instr_base_test
@@ -35,12 +35,6 @@
gen_opts: >
+instr_cnt=10000
+num_of_sub_program=5
- +directed_instr_0=riscv_load_store_rand_instr_stream,4
- +directed_instr_1=riscv_loop_instr,4
- +directed_instr_2=riscv_hazard_instr_stream,4
- +directed_instr_3=riscv_load_store_hazard_instr_stream,4
- +directed_instr_4=riscv_cache_line_stress_instr_stream,4
- +directed_instr_5=riscv_multi_page_load_store_instr_stream,4
rtl_test: core_ibex_base_test
- test: riscv_rand_jump_test
@@ -65,8 +59,7 @@
+num_of_sub_program=5
+directed_instr_0=riscv_load_store_rand_instr_stream,40
+directed_instr_1=riscv_load_store_hazard_instr_stream,40
- +directed_instr_2=riscv_cache_line_stress_instr_stream,40
- +directed_instr_3=riscv_multi_page_load_store_instr_stream,40
+ +directed_instr_2=riscv_multi_page_load_store_instr_stream,40
rtl_test: core_ibex_base_test
- test: riscv_illegal_instr_test
@@ -78,7 +71,7 @@
iterations: 10
gen_test: riscv_rand_instr_test
gen_opts: >
- +enable_illegal_instruction=1
+ +illegal_instr_ratio=5
rtl_test: core_ibex_base_test
- test: riscv_hint_instr_test
@@ -88,7 +81,7 @@
iterations: 10
gen_test: riscv_rand_instr_test
gen_opts: >
- +enable_hint_instruction=1
+ +hint_instr_ratio=5
rtl_test: core_ibex_base_test
- test: riscv_ebreak_test
@@ -116,6 +109,7 @@
+no_csr_instr=1
+no_fence=1
+num_of_sub_program=0
+ +randomize_csr=1
rtl_test: core_ibex_debug_intr_basic_test
sim_opts: >
+require_signature_addr=1
@@ -158,11 +152,12 @@
+no_csr_instr=1
+no_fence=1
+num_of_sub_program=0
- +num_debug_sub_program=3
+ +num_debug_sub_program=2
+ +randomize_csr=1
rtl_test: core_ibex_debug_intr_basic_test
sim_opts: >
+require_signature_addr=1
- +max_interval=2000
+ +max_interval=3000
+enable_debug_stress_seq=1
compare_opts:
compare_final_value_only: 1
@@ -177,10 +172,12 @@
+require_signature_addr=1
+gen_debug_section=1
+no_ebreak=1
- +instr_cnt=3000
+ +instr_cnt=6000
+no_csr_instr=1
+no_fence=1
+no_wfi=0
+ +randomize_csr=1
+ +num_of_sub_program=0
rtl_test: core_ibex_debug_wfi_test
sim_opts: >
+require_signature_addr=1
@@ -203,16 +200,6 @@
sim_opts: >
+require_signature_addr=1
-- test: riscv_ebreak_test
- description: >
- Ebreak instructions will be inserted into the M mode code, ibex should handle them normally.
- iterations: 5
- gen_test: riscv_rand_instr_test
- gen_opts: >
- +no_ebreak=0
- +instr_cnt=6000
- rtl_test: core_ibex_base_test
-
- test: riscv_debug_ebreak_test
description: >
A directed ebreak sequence will be inserted into the debug rom, upon encountering it,
@@ -229,6 +216,7 @@
+no_wfi=1
+no_ebreak=0
+instr_cnt=6000
+ +randomize_csr=1
rtl_test: core_ibex_debug_ebreak_test
sim_opts: >
+require_signature_addr=1
@@ -251,6 +239,8 @@
+no_fence=1
+no_wfi=1
+instr_cnt=6000
+ +randomize_csr=1
+ +num_of_sub_program=0
rtl_test: core_ibex_debug_ebreakm_test
sim_opts: >
+require_signature_addr=1
@@ -261,14 +251,17 @@
- test: riscv_interrupt_test
description: >
Random instruction test with complete interrupt handling
- iterations: 0
+ iterations: 10
gen_test: riscv_rand_instr_test
gen_opts: >
+ +instr_cnt=6000
+require_signature_addr=1
+ +enable_interrupt=1
+ +randomize_csr=1
rtl_test: core_ibex_debug_intr_basic_test
sim_opts: >
+require_signature_addr=1
- +enable_irq_stress_seq=1
+ +enable_irq_seq=1
compare_opts:
compare_final_value_only: 1
@@ -290,7 +283,59 @@
+num_of_sub_program=5
+directed_instr_0=riscv_load_store_rand_instr_stream,20
+directed_instr_1=riscv_load_store_hazard_instr_stream,20
- +directed_instr_2=riscv_cache_line_stress_instr_stream,20
- +directed_instr_3=riscv_multi_page_load_store_instr_stream,20
+ +directed_instr_2=riscv_multi_page_load_store_instr_stream,20
+enable_unaligned_load_store=1
rtl_test: core_ibex_base_test
+
+- test: riscv_mem_error_test
+ description: >
+ Normal random instruction test, but randomly insert instruction fetch or memory load/store errors
+ iterations: 5
+ gen_test: riscv_rand_instr_test
+ gen_opts: >
+ +require_signature_addr=1
+ +instr_cnt=10000
+ +randomize_csr=1
+ rtl_test: core_ibex_mem_error_test
+ sim_opts: >
+ +require_signature_addr=1
+ compare_opts:
+ compare_final_value_only: 1
+
+- test: riscv_perf_counter_test
+ description: >
+ Dump performance counters at EOT for any analysis
+ iterations: 5
+ gen_test: riscv_rand_instr_test
+ gen_opts: >
+ +require_signature_addr=1
+ +instr_cnt=10000
+ +num_of_sub_program=5
+ rtl_test: core_ibex_perf_test
+ sim_opts: >
+ +require_signature_addr=1
+
+- test: riscv_debug_single_step_test
+ description: >
+ Randomly assert debug_req_i, and set dcsr.step to make ibex execute one isntruction and then re-enter debug mode
+ iterations: 5
+ gen_test: riscv_instr_base_test
+ gen_opts: >
+ +require_signature_addr=1
+ +gen_debug_section=1
+ +no_ebreak=1
+ +no_branch_jump=1
+ +instr_cnt=6000
+ +no_csr_instr=1
+ +no_fence=1
+ +num_of_sub_program=0
+ +randomize_csr=1
+ +enable_debug_single_step=1
+ rtl_test: core_ibex_debug_single_step_test
+ sim_opts: >
+ +require_signature_addr=1
+ +max_interval=1500
+ +enable_debug_single_seq=1
+ compare_opts:
+ compare_final_value_only: 1
+ verbose: 1
diff --git a/hw/vendor/lowrisc_ibex/dv/uvm/riscv_dv_extension/flist b/hw/vendor/lowrisc_ibex/dv/uvm/riscv_dv_extension/user_extension.svh
similarity index 100%
rename from hw/vendor/lowrisc_ibex/dv/uvm/riscv_dv_extension/flist
rename to hw/vendor/lowrisc_ibex/dv/uvm/riscv_dv_extension/user_extension.svh
diff --git a/hw/vendor/lowrisc_ibex/dv/uvm/sim.py b/hw/vendor/lowrisc_ibex/dv/uvm/sim.py
index 02c501b..c3ea22d 100644
--- a/hw/vendor/lowrisc_ibex/dv/uvm/sim.py
+++ b/hw/vendor/lowrisc_ibex/dv/uvm/sim.py
@@ -32,6 +32,7 @@
from ovpsim_log_to_trace_csv import *
from instr_trace_compare import *
+
def process_cmd(keyword, cmd, opts, enable):
""" Process the compile and simulation command
@@ -63,27 +64,36 @@
compile_cmd : RTL simulator command to compile the instruction generator
sim_cmd : RTL simulator command to run the instruction generator
"""
- print("Processing simulator setup file : %s" % simulator_yaml)
+ logging.info("Processing simulator setup file : %s" % simulator_yaml)
yaml_data = read_yaml(simulator_yaml)
# Search for matched simulator
for entry in yaml_data:
if entry['tool'] == simulator:
- print("Found matching simulator: %s" % entry['tool'])
+ logging.info("Found matching simulator: %s" % entry['tool'])
compile_cmd = entry['compile']['cmd']
for i in range(len(compile_cmd)):
- compile_cmd[i] = process_cmd("<cov_opts>", compile_cmd[i],
- entry['compile']['cov_opts'], en_cov)
- compile_cmd[i] = process_cmd("<wave_opts>", compile_cmd[i],
- entry['compile']['wave_opts'], en_wave)
+ if 'cov_opts' in entry['compile']:
+ compile_cmd[i] = process_cmd("<cov_opts>", compile_cmd[i],
+ entry['compile']['cov_opts'], en_cov)
+ if 'wave_opts' in entry['compile']:
+ compile_cmd[i] = process_cmd("<wave_opts>", compile_cmd[i],
+ entry['compile']['wave_opts'], en_wave)
sim_cmd = entry['sim']['cmd']
- sim_cmd = process_cmd("<cov_opts>", sim_cmd, entry['sim']['cov_opts'], en_cov)
- sim_cmd = process_cmd("<wave_opts>", sim_cmd, entry['sim']['wave_opts'], en_wave)
+ if 'cov_opts' in entry['sim']:
+ sim_cmd = process_cmd("<cov_opts>", sim_cmd, entry['sim']['cov_opts'], en_cov)
+ if 'wave_opts' in entry['sim']:
+ sim_cmd = process_cmd("<wave_opts>", sim_cmd, entry['sim']['wave_opts'], en_wave)
+ if 'env_var' in entry:
+ for env_var in entry['env_var'].split(','):
+ for i in range(len(compile_cmd)):
+ compile_cmd[i] = re.sub("<"+env_var+">", get_env_var(env_var), compile_cmd[i])
+ sim_cmd = re.sub("<"+env_var+">", get_env_var(env_var), sim_cmd)
return compile_cmd, sim_cmd
- print ("Cannot find RTL simulator %0s" % simulator)
+ logging.info("Cannot find RTL simulator %0s" % simulator)
sys.exit(1)
-def rtl_compile(compile_cmd, test_list, output_dir, lsf_cmd, opts, verbose):
+def rtl_compile(compile_cmd, test_list, output_dir, lsf_cmd, opts):
"""Run the instruction generator
Args:
@@ -92,21 +102,17 @@
output_dir : Output directory of the ELF files
lsf_cmd : LSF command to run compilation
opts : Compile options for the generator
- verbose : Verbose logging
"""
# Compile the TB
- print ("Compiling TB")
+ logging.info("Compiling TB")
for cmd in compile_cmd:
cmd = re.sub("<out>", output_dir, cmd)
cmd = re.sub("<cmp_opts>", opts, cmd)
- if verbose:
- print("Compile command: %s" % cmd)
- output = run_cmd(cmd)
- if verbose:
- print(output)
+ logging.debug("Compile command: %s" % cmd)
+ run_cmd(cmd)
-def rtl_sim(sim_cmd, test_list, output_dir, bin_dir, lsf_cmd, seed, opts, verbose):
+def rtl_sim(sim_cmd, test_list, output_dir, bin_dir, lsf_cmd, seed, opts):
"""Run the instruction generator
Args:
@@ -117,37 +123,37 @@
lsf_cmd : LSF command to run simulation
seed : Seed of RTL simulation
opts : Simulation options
- verbose : Verbose logging
"""
# Run the RTL simulation
sim_cmd = re.sub("<out>", output_dir, sim_cmd)
sim_cmd = re.sub("<sim_opts>", opts, sim_cmd)
sim_cmd = re.sub("<cwd>", cwd, sim_cmd)
- print ("Running RTL simulation...")
+ logging.info("Running RTL simulation...")
cmd_list = []
for test in test_list:
for i in range(test['iterations']):
rand_seed = get_seed(seed)
test_sim_cmd = re.sub("<seed>", str(rand_seed), sim_cmd)
if "sim_opts" in test:
+ test_sim_cmd += ' '
test_sim_cmd += test['sim_opts']
- print(test_sim_cmd)
sim_dir = output_dir + ("/%s.%d" %(test['test'], i))
run_cmd(("mkdir -p %s" % sim_dir))
os.chdir(sim_dir)
- if verbose:
- print("Run dir: %s" % sim_dir)
- binary = ("%s/%s.%d.bin" % (bin_dir, test['test'], i))
- cmd = lsf_cmd + " " + test_sim_cmd.rstrip() + \
+ binary = ("%s/%s_%d.bin" % (bin_dir, test['test'], i))
+ cmd = lsf_cmd + " " + test_sim_cmd + \
(" +UVM_TESTNAME=%s " % test['rtl_test']) + \
(" +bin=%s " % binary) + \
(" -l sim.log ")
- print("Running %s with %s" % (test['rtl_test'], binary))
- if verbose:
- print(cmd)
- output = run_cmd(' '.join(cmd.split()))
- if verbose:
- print(output)
+ cmd = re.sub('\n', '', cmd)
+ if lsf_cmd == "":
+ logging.info("Running %s with %s" % (test['rtl_test'], binary))
+ run_cmd(cmd, 300)
+ else:
+ cmd_list.append(cmd)
+ if lsf_cmd != "":
+ logging.info("Running %0d simulation jobs." % len(cmd_list))
+ run_parallel_cmd(cmd_list, 600)
def compare(test_list, iss, output_dir, verbose):
@@ -161,9 +167,15 @@
"""
report = ("%s/regr.log" % output_dir).rstrip()
for test in test_list:
+ compare_opts = test.get('compare_opts', {})
+ in_order_mode = compare_opts.get('in_order_mode', 1)
+ coalescing_limit = compare_opts.get('coalescing_limit', 0)
+ verbose = compare_opts.get('verbose', 0)
+ mismatch = compare_opts.get('mismatch_print_limit', 5)
+ compare_final = compare_opts.get('compare_final_value_only', 0)
for i in range(0, test['iterations']):
elf = ("%s/asm_tests/%s.%d.o" % (output_dir, test['test'], i))
- print("Comparing %s/DUT sim result : %s" % (iss, elf))
+ logging.info("Comparing %s/DUT sim result : %s" % (iss, elf))
run_cmd(("echo 'Test binary: %s' >> %s" % (elf, report)))
uvm_log = ("%s/rtl_sim/%s.%d/sim.log" % (output_dir, test['test'], i))
rtl_log = ("%s/rtl_sim/%s.%d/trace_core_00000000.log" % (output_dir, test['test'], i))
@@ -180,19 +192,13 @@
elif iss == "ovpsim":
process_ovpsim_sim_log(iss_log, iss_csv)
else:
- print("Unsupported ISS" % iss)
+ logging.info("Unsupported ISS" % iss)
sys.exit(1)
uvm_result = check_ibex_uvm_log(uvm_log, "ibex", test_name, report, False)
if not uvm_result:
check_ibex_uvm_log(uvm_log, "ibex", test_name, report)
else:
if 'compare_opts' in test:
- compare_opts = test.get('compare_opts')
- in_order_mode = compare_opts.get('in_order_mode', 1)
- coalescing_limit = compare_opts.get('coalescing_limit', 0)
- verbose = compare_opts.get('verbose', 0)
- mismatch = compare_opts.get('mismatch_print_limit', 5)
- compare_final = compare_opts.get('compare_final_value_only', 0)
compare_trace_csv(rtl_csv, iss_csv, "ibex", iss, report,
in_order_mode, coalescing_limit, verbose,
mismatch, compare_final)
@@ -201,9 +207,9 @@
passed_cnt = run_cmd("grep PASSED %s | wc -l" % report).strip()
failed_cnt = run_cmd("grep FAILED %s | wc -l" % report).strip()
summary = ("%s PASSED, %s FAILED" % (passed_cnt, failed_cnt))
- print(summary)
+ logging.info(summary)
run_cmd(("echo %s >> %s" % (summary, report)))
- print("RTL & ISS regression report is saved to %s" % report)
+ logging.info("RTL & ISS regression report is saved to %s" % report)
# Parse input arguments
@@ -242,6 +248,7 @@
command is not specified")
args = parser.parse_args()
+setup_logging(args.verbose)
parser.set_defaults(verbose=False)
cwd = os.path.dirname(os.path.realpath(__file__))
@@ -263,13 +270,12 @@
args.en_cov, args.en_wave)
# Compile TB
if args.steps == "all" or re.match("compile", args.steps):
- rtl_compile(compile_cmd, matched_list, output_dir,
- args.lsf_cmd, args.cmp_opts, args.verbose)
+ rtl_compile(compile_cmd, matched_list, output_dir, args.lsf_cmd, args.cmp_opts)
# Run RTL simulation
if args.steps == "all" or re.match("sim", args.steps):
rtl_sim(sim_cmd, matched_list, output_dir, bin_dir, args.lsf_cmd,
- args.seed, args.sim_opts, args.verbose)
+ args.seed, args.sim_opts)
# Compare RTL & ISS simulation result.;
if args.steps == "all" or re.match("compare", args.steps):
diff --git a/hw/vendor/lowrisc_ibex/dv/uvm/tb/core_ibex_tb_top.sv b/hw/vendor/lowrisc_ibex/dv/uvm/tb/core_ibex_tb_top.sv
index 251ea86..9d8b064 100644
--- a/hw/vendor/lowrisc_ibex/dv/uvm/tb/core_ibex_tb_top.sv
+++ b/hw/vendor/lowrisc_ibex/dv/uvm/tb/core_ibex_tb_top.sv
@@ -5,18 +5,24 @@
module core_ibex_tb_top;
import uvm_pkg::*;
+ import core_ibex_test_pkg::*;
logic clk;
logic rst_n;
logic fetch_enable;
- logic debug_req;
- clk_if ibex_clk_if(.clk(clk));
- irq_if irq_vif();
+ clk_if ibex_clk_if(.clk(clk));
+ irq_if irq_vif();
+ ibex_mem_intf data_mem_vif();
+ ibex_mem_intf instr_mem_vif();
+
// DUT probe interface
core_ibex_dut_probe_if dut_if(.clk(clk));
+ // RVFI interface
+ core_ibex_rvfi_if rvfi_if(.clk(clk));
+
// TODO(taliu) Resolve the tied-off ports
ibex_core_tracing #(.DmHaltAddr(`BOOT_ADDR + 'h0),
.DmExceptionAddr(`BOOT_ADDR + 'h4)) dut (
@@ -25,59 +31,75 @@
.test_en_i(1'b1),
.hart_id_i(32'b0),
.boot_addr_i(`BOOT_ADDR), // align with spike boot address
- .debug_req_i(debug_req),
- .irq_software_i(irq_if.irq_software),
- .irq_timer_i(irq_if.irq_timer),
- .irq_external_i(irq_if.irq_external),
- .irq_fast_i(irq_if.irq_fast),
- .irq_nm_i(irq_if.irq_nm),
+ .irq_software_i(irq_vif.irq_software),
+ .irq_timer_i(irq_vif.irq_timer),
+ .irq_external_i(irq_vif.irq_external),
+ .irq_fast_i(irq_vif.irq_fast),
+ .irq_nm_i(irq_vif.irq_nm),
.fetch_enable_i(dut_if.fetch_enable),
- .debug_req_i(dut_if.debug_req)
+ .debug_req_i(dut_if.debug_req),
+ .data_gnt_i(data_mem_vif.grant),
+ .data_rvalid_i(data_mem_vif.rvalid),
+ .data_rdata_i(data_mem_vif.rdata),
+ .data_err_i(data_mem_vif.error),
+ .instr_gnt_i(instr_mem_vif.grant),
+ .instr_rvalid_i(instr_mem_vif.rvalid),
+ .instr_rdata_i(instr_mem_vif.rdata),
+ .instr_err_i(instr_mem_vif.error)
);
- ibex_mem_intf data_mem_vif();
- ibex_mem_intf instr_mem_vif();
-
- initial begin
- // Data load/store vif connection
- force data_mem_vif.clock = clk;
- force data_mem_vif.reset = ~rst_n;
- force data_mem_vif.request = dut.data_req_o;
- force dut.data_gnt_i = data_mem_vif.grant;
- force dut.data_rvalid_i = data_mem_vif.rvalid;
- force data_mem_vif.we = dut.data_we_o;
- force data_mem_vif.be = dut.data_be_o;
- force data_mem_vif.addr = dut.data_addr_o;
- force data_mem_vif.wdata = dut.data_wdata_o;
- force dut.data_rdata_i = data_mem_vif.rdata;
- force dut.data_err_i = 0; // TODO(taliu) Support interface error
- // Instruction fetch vif connnection
- force instr_mem_vif.clock = clk;
- force instr_mem_vif.reset = ~rst_n;
- force instr_mem_vif.request = dut.instr_req_o;
- force dut.instr_gnt_i = instr_mem_vif.grant;
- force instr_mem_vif.we = 0;
- force instr_mem_vif.be = 0;
- force instr_mem_vif.wdata = 0;
- force dut.instr_rvalid_i = instr_mem_vif.rvalid;
- force instr_mem_vif.addr = dut.instr_addr_o;
- force dut.instr_rdata_i = instr_mem_vif.rdata;
- force dut.instr_err_i = 0; // TODO(taliu) Support interface error
- // IRQ interface
- force irq_vif.clock = clk;
- force irq_vif.reset = ~rst_n;
- end
-
- assign dut_if.ecall = dut.u_ibex_core.id_stage_i.ecall_insn_dec;
- assign dut_if.wfi = dut.u_ibex_core.id_stage_i.wfi_insn_dec;
- assign dut_if.ebreak = dut.u_ibex_core.id_stage_i.ebrk_insn;
- assign dut_if.dret = dut.u_ibex_core.id_stage_i.dret_insn_dec;
- assign dut_if.mret = dut.u_ibex_core.id_stage_i.mret_insn_dec;
+ // Data load/store vif connection
+ assign data_mem_vif.clock = clk;
+ assign data_mem_vif.reset = ~rst_n;
+ assign data_mem_vif.request = dut.data_req_o;
+ assign data_mem_vif.we = dut.data_we_o;
+ assign data_mem_vif.be = dut.data_be_o;
+ assign data_mem_vif.addr = dut.data_addr_o;
+ assign data_mem_vif.wdata = dut.data_wdata_o;
+ // Instruction fetch vif connnection
+ assign instr_mem_vif.clock = clk;
+ assign instr_mem_vif.reset = ~rst_n;
+ assign instr_mem_vif.request = dut.instr_req_o;
+ assign instr_mem_vif.we = 0;
+ assign instr_mem_vif.be = 0;
+ assign instr_mem_vif.wdata = 0;
+ assign instr_mem_vif.addr = dut.instr_addr_o;
+ // RVFI interface connections
+ assign rvfi_if.valid = dut.rvfi_valid;
+ assign rvfi_if.order = dut.rvfi_order;
+ assign rvfi_if.insn = dut.rvfi_insn;
+ assign rvfi_if.trap = dut.rvfi_trap;
+ assign rvfi_if.intr = dut.rvfi_intr;
+ assign rvfi_if.mode = dut.rvfi_mode;
+ assign rvfi_if.rs1_addr = dut.rvfi_rs1_addr;
+ assign rvfi_if.rs2_addr = dut.rvfi_rs2_addr;
+ assign rvfi_if.rs1_rdata = dut.rvfi_rs1_rdata;
+ assign rvfi_if.rs2_rdata = dut.rvfi_rs2_rdata;
+ assign rvfi_if.rd_addr = dut.rvfi_rd_addr;
+ assign rvfi_if.rd_wdata = dut.rvfi_rd_wdata;
+ assign rvfi_if.pc_rdata = dut.rvfi_pc_rdata;
+ assign rvfi_if_pc_wdata = dut.rvfi_pc_wdata;
+ assign rvfi_if.mem_addr = dut.rvfi_mem_addr;
+ assign rvfi_if.mem_rmask = dut.rvfi_mem_rmask;
+ assign rvfi_if.mem_rdata = dut.rvfi_mem_rdata;
+ assign rvfi_if.mem_wdata = dut.rvfi_mem_wdata;
+ // Irq interface connections
+ assign irq_vif.clock = clk;
+ assign irq_vif.reset = ~rst_n;
+ // Dut_if interface connections
+ assign dut_if.ecall = dut.u_ibex_core.id_stage_i.ecall_insn_dec;
+ assign dut_if.wfi = dut.u_ibex_core.id_stage_i.wfi_insn_dec;
+ assign dut_if.ebreak = dut.u_ibex_core.id_stage_i.ebrk_insn;
+ assign dut_if.illegal_instr = dut.u_ibex_core.id_stage_i.illegal_insn_dec;
+ assign dut_if.dret = dut.u_ibex_core.id_stage_i.dret_insn_dec;
+ assign dut_if.mret = dut.u_ibex_core.id_stage_i.mret_insn_dec;
+ assign dut_if.core_sleep = dut.u_ibex_core.core_sleep_o;
initial begin
uvm_config_db#(virtual clk_if)::set(null, "*", "clk_if", ibex_clk_if);
uvm_config_db#(virtual core_ibex_dut_probe_if)::set(null, "*", "dut_if", dut_if);
+ uvm_config_db#(virtual core_ibex_rvfi_if)::set(null, "*", "rvfi_if", rvfi_if);
uvm_config_db#(virtual ibex_mem_intf)::set(null, "*data_if_slave*", "vif", data_mem_vif);
uvm_config_db#(virtual ibex_mem_intf)::set(null, "*instr_if_slave*", "vif", instr_mem_vif);
uvm_config_db#(virtual irq_if)::set(null, "*", "vif", irq_vif);
@@ -97,6 +119,7 @@
rst_n = 1'b0;
repeat(100) @(posedge clk);
rst_n = 1'b1;
+ dut_if.debug_req = 1'b0;
end
endmodule
diff --git a/hw/vendor/lowrisc_ibex/dv/uvm/tests/core_ibex_base_test.sv b/hw/vendor/lowrisc_ibex/dv/uvm/tests/core_ibex_base_test.sv
index 54cd279..6bd5635 100644
--- a/hw/vendor/lowrisc_ibex/dv/uvm/tests/core_ibex_base_test.sv
+++ b/hw/vendor/lowrisc_ibex/dv/uvm/tests/core_ibex_base_test.sv
@@ -10,8 +10,7 @@
virtual core_ibex_dut_probe_if dut_vif;
mem_model_pkg::mem_model mem;
core_ibex_vseq vseq;
- irq_seq irq_seq_h;
- int unsigned timeout_in_cycles = 3000000;
+ int unsigned timeout_in_cycles = 5000000;
// If no signature_addr handshake functionality is desired between the testbench and the generated
// code, the test will wait for the specifield number of cycles before starting stimulus
// sequences (irq and debug)
@@ -19,6 +18,7 @@
bit[ibex_mem_intf_agent_pkg::DATA_WIDTH-1:0] signature_data_q[$];
bit[ibex_mem_intf_agent_pkg::DATA_WIDTH-1:0] signature_data;
uvm_tlm_analysis_fifo #(ibex_mem_intf_seq_item) item_collected_port;
+ uvm_tlm_analysis_fifo #(irq_seq_item) irq_collected_port;
`uvm_component_utils(core_ibex_base_test)
@@ -28,6 +28,7 @@
ibex_report_server = new();
uvm_report_server::set_server(ibex_report_server);
item_collected_port = new("item_collected_port_test", this);
+ irq_collected_port = new("irq_collected_port_test", this);
endfunction
virtual function void build_phase(uvm_phase phase);
@@ -52,6 +53,9 @@
virtual function void connect_phase(uvm_phase phase);
super.connect_phase(phase);
env.data_if_slave_agent.monitor.item_collected_port.connect(this.item_collected_port.analysis_export);
+ if (cfg.enable_irq_seq) begin
+ env.irq_agent.monitor.irq_port.connect(this.irq_collected_port.analysis_export);
+ end
endfunction
virtual task run_phase(uvm_phase phase);
@@ -73,6 +77,9 @@
vseq.start(env.vseqr);
endtask
+ virtual task check_perf_stats();
+ endtask
+
function void load_binary_to_mem();
string bin;
bit [7:0] r8;
@@ -105,8 +112,11 @@
`uvm_info(`gfn, "ECALL instruction is detected, test done", UVM_LOW)
// De-assert fetch enable to finish the test
dut_vif.fetch_enable = 1'b0;
- // Wait some time for the remaining instruction to finish
- clk_vif.wait_clks(100);
+ fork
+ check_perf_stats();
+ // Wait some time for the remaining instruction to finish
+ clk_vif.wait_clks(3000);
+ join
end
begin
clk_vif.wait_clks(timeout_in_cycles);
@@ -165,12 +175,10 @@
// Gets the next CORE_STATUS signature write and compares it against the provided core_status
// type, throws uvm_error on mismatch
- virtual task check_next_core_status(core_status_t core_status, error_msg="");
+ virtual task check_next_core_status(core_status_t core_status, string error_msg = "");
wait_for_mem_txn(cfg.signature_addr, CORE_STATUS);
signature_data = signature_data_q.pop_front();
- if (signature_data != core_status) begin
- `uvm_error(`gfn, error_msg)
- end
+ `DV_CHECK_EQ_FATAL(signature_data, core_status, error_msg);
endtask
// Waits for a write to the address of the specified CSR and retrieves the csr data
diff --git a/hw/vendor/lowrisc_ibex/dv/uvm/tests/core_ibex_seq_lib.sv b/hw/vendor/lowrisc_ibex/dv/uvm/tests/core_ibex_seq_lib.sv
index 0170a47..a27f1f0 100644
--- a/hw/vendor/lowrisc_ibex/dv/uvm/tests/core_ibex_seq_lib.sv
+++ b/hw/vendor/lowrisc_ibex/dv/uvm/tests/core_ibex_seq_lib.sv
@@ -61,17 +61,38 @@
endclass
-// Interrupt sequence
-class irq_seq extends core_base_seq#(irq_seq_item);
+// Interrupt sequences
+class irq_raise_single_seq extends core_base_seq#(irq_seq_item);
- `uvm_object_utils(irq_seq)
+ `uvm_object_utils(irq_raise_single_seq)
`uvm_object_new
virtual task send_req();
irq_seq_item irq;
- irq = irq_seq_item::type_id::create($sformatf("irq[%0d]", iteration_cnt));
+ irq = irq_seq_item::type_id::create($sformatf("irq_raise_single[%0d]", iteration_cnt));
start_item(irq);
- `DV_CHECK_RANDOMIZE_FATAL(irq)
+ // TODO(udinator) - constrain irq_timer to 0 for now due to timer interrupt causing spike
+ // simulator to trap to irq handler
+ `DV_CHECK_RANDOMIZE_WITH_FATAL(irq, irq_timer==0;)
+ finish_item(irq);
+ get_response(irq);
+ endtask
+
+endclass
+
+// Irq sequence to deassert all interrupt lines, since Ibex interrupts are level sensitive
+class irq_drop_seq extends core_base_seq#(irq_seq_item);
+
+ `uvm_object_utils(irq_drop_seq)
+ `uvm_object_new
+
+ // TODO(udinator) - for nested interrupt tests, test scenarios where a random number of interrupts
+ // are dropped
+ virtual task send_req();
+ irq_seq_item irq;
+ irq = irq_seq_item::type_id::create($sformatf("irq_drop[%0d]", iteration_cnt));
+ start_item(irq);
+ `DV_CHECK_RANDOMIZE_WITH_FATAL(irq, num_of_interrupt == 0;)
finish_item(irq);
get_response(irq);
endtask
@@ -98,7 +119,7 @@
virtual task send_req();
`uvm_info(get_full_name(), "Sending debug request", UVM_HIGH)
dut_vif.debug_req <= 1'b1;
- clk_vif.wait_clks($urandom_range(10, 30));
+ clk_vif.wait_clks(50);
dut_vif.debug_req <= 1'b0;
endtask
diff --git a/hw/vendor/lowrisc_ibex/dv/uvm/tests/core_ibex_test_lib.sv b/hw/vendor/lowrisc_ibex/dv/uvm/tests/core_ibex_test_lib.sv
index c306e5b..c3c0b0d 100644
--- a/hw/vendor/lowrisc_ibex/dv/uvm/tests/core_ibex_test_lib.sv
+++ b/hw/vendor/lowrisc_ibex/dv/uvm/tests/core_ibex_test_lib.sv
@@ -31,12 +31,95 @@
endclass
+// Performance counter test class
+class core_ibex_perf_test extends core_ibex_base_test;
+
+ `uvm_component_utils(core_ibex_perf_test)
+ `uvm_component_new
+
+ virtual task check_perf_stats();
+ bit [63:0] num_cycles, num_instr_ret, num_cycles_lsu, num_cycles_if, num_loads, num_stores,
+ num_jumps, num_branches, num_branches_taken, num_instr_ret_c;
+ wait_for_csr_write(CSR_MCYCLE);
+ num_cycles[31:0] = signature_data;
+ wait_for_csr_write(CSR_MCYCLEH);
+ num_cycles[63:32] = signature_data;
+ wait_for_csr_write(CSR_MINSTRET);
+ num_instr_ret[31:0] = signature_data;
+ wait_for_csr_write(CSR_MINSTRETH);
+ num_instr_ret[63:32] = signature_data;
+ // mhpmcounter3
+ wait_for_csr_write(12'hB03);
+ num_cycles_lsu[31:0] = signature_data;
+ // mhpmcounter4
+ wait_for_csr_write(12'hB04);
+ num_cycles_if[31:0] = signature_data;
+ // mhpmcounter5
+ wait_for_csr_write(12'hB05);
+ num_loads[31:0] = signature_data;
+ // mhpmcounter6
+ wait_for_csr_write(12'hB06);
+ num_stores[31:0] = signature_data;
+ // mhpmcounter7
+ wait_for_csr_write(12'hB07);
+ num_jumps[31:0] = signature_data;
+ // mhpmcounter8
+ wait_for_csr_write(12'hB08);
+ num_branches[31:0] = signature_data;
+ // mhpmcounter9
+ wait_for_csr_write(12'hB09);
+ num_branches_taken[31:0] = signature_data;
+ // mhpmcounter10
+ wait_for_csr_write(12'hB0A);
+ num_instr_ret_c[31:0] = signature_data;
+ // mhpmcounterh3
+ wait_for_csr_write(12'hB83);
+ num_cycles_lsu[63:32] = signature_data;
+ // mhpmcounterh4
+ wait_for_csr_write(12'hB84);
+ num_cycles_if[63:32] = signature_data;
+ // mhpmcounterh5
+ wait_for_csr_write(12'hB85);
+ num_loads[63:32] = signature_data;
+ // mhpmcounterh6
+ wait_for_csr_write(12'hB86);
+ num_stores[63:32] = signature_data;
+ // mhpmcounterh7
+ wait_for_csr_write(12'hB87);
+ num_jumps[63:32] = signature_data;
+ // mhpmcounterh8
+ wait_for_csr_write(12'hB88);
+ num_branches[63:32] = signature_data;
+ // mhpmcounterh9
+ wait_for_csr_write(12'hB89);
+ num_branches_taken[63:32] = signature_data;
+ // mhpmcounterh10
+ wait_for_csr_write(12'hB8A);
+ num_instr_ret_c[63:32] = signature_data;
+ `uvm_info(`gfn, $sformatf("NUM_CYCLES: 0x%0x", num_cycles), UVM_LOW)
+ `uvm_info(`gfn, $sformatf("NUM_INSTR_RET: 0x%0x", num_instr_ret), UVM_LOW)
+ `uvm_info(`gfn, $sformatf("NUM_CYCLES_LSU: 0x%0x", num_cycles_lsu), UVM_LOW)
+ `uvm_info(`gfn, $sformatf("NUM_CYCLES_IF: 0x%0x", num_cycles_if), UVM_LOW)
+ `uvm_info(`gfn, $sformatf("NUM_LOADS: 0x%0x", num_loads), UVM_LOW)
+ `uvm_info(`gfn, $sformatf("NUM_STORES: 0x%0x", num_stores), UVM_LOW)
+ `uvm_info(`gfn, $sformatf("NUM_JUMPS: 0x%0x", num_jumps), UVM_LOW)
+ `uvm_info(`gfn, $sformatf("NUM_BRANCHES: 0x%0x", num_branches), UVM_LOW)
+ `uvm_info(`gfn, $sformatf("NUM_BRANCHES_TAKEN: 0x%0x", num_branches_taken), UVM_LOW)
+ `uvm_info(`gfn, $sformatf("NUM_INSTR_RET_COMPRESSED: 0x%0x", num_instr_ret_c), UVM_LOW)
+ endtask
+
+endclass
+
// Debug test class
class core_ibex_debug_intr_basic_test extends core_ibex_base_test;
`uvm_component_utils(core_ibex_debug_intr_basic_test)
`uvm_component_new
+ bit [ibex_mem_intf_agent_pkg::DATA_WIDTH-1:0] core_init_mstatus;
+ bit [ibex_mem_intf_agent_pkg::DATA_WIDTH-1:0] core_init_mie;
+ bit [$clog2(irq_agent_pkg::DATA_WIDTH)-1:0] irq_id;
+
virtual task send_stimulus();
fork
begin
@@ -44,7 +127,7 @@
end
begin
if (cfg.require_signature_addr) begin
- wait_for_core_status(INITIALIZED);
+ wait_for_core_setup();
end else begin
// If no signature_addr functionality is desired, then the test will simply wait for an
// adequate number of cycles
@@ -52,13 +135,15 @@
end
fork
begin
- if (cfg.enable_irq_stress_seq) begin
- vseq.start_irq_stress_seq();
+ if (cfg.enable_irq_seq) begin
+ forever begin
+ send_irq_stimulus();
+ end
end
end
begin
if (cfg.enable_debug_stress_seq) begin
- vseq.start_debug_stress_seq();
+ send_debug_stimulus();
end
end
join_none
@@ -66,10 +151,119 @@
join_none
endtask
+ virtual task wait_for_core_setup();
+ wait_for_csr_write(CSR_MSTATUS);
+ core_init_mstatus = signature_data;
+ wait_for_csr_write(CSR_MIE);
+ core_init_mie = signature_data;
+ check_next_core_status(INITIALIZED, "Core initialization handshake failure");
+ endtask
+
+ // TODO(udi) - much of this checking logic is based on the current design only implementing
+ // MACHINE_MODE, the checking will have to be modified once USER_MODE is implemented and merged,
+ // e.g. need to also check mideleg for correct privilege mode context switch
+ virtual task send_irq_stimulus();
+ irq_seq_item irq_txn;
+ bit [irq_agent_pkg::DATA_WIDTH-1:0] irq;
+ bit [ibex_mem_intf_agent_pkg::DATA_WIDTH-1:0] mstatus;
+ bit [ibex_mem_intf_agent_pkg::DATA_WIDTH-1:0] mcause;
+ bit [ibex_mem_intf_agent_pkg::DATA_WIDTH-1:0] mip;
+ bit [ibex_mem_intf_agent_pkg::DATA_WIDTH-1:0] mie;
+ // send the interrupt
+ vseq.start_irq_single_seq();
+ irq_collected_port.get(irq_txn);
+ irq = {irq_txn.irq_nm, irq_txn.irq_fast, 4'b0, irq_txn.irq_external, 3'b0,
+ irq_txn.irq_timer, 3'b0, irq_txn.irq_software, 3'b0};
+ // Get the bit position of the highest priority interrupt - ibex will only handle this one if
+ // there are multiple irqs asserted at once
+ irq_id = get_max_irq_id(irq);
+ // If the interrupt is maskable, and the corresponding bit in MIE is not set, skip the next
+ // checks, as it means the interrupt in question is not enabled by Ibex, and drop the interrupt
+ // lines to avoid locking up the simulation
+ if (!irq_txn.irq_nm && !core_init_mie[irq_id]) begin
+ vseq.start_irq_drop_seq();
+ irq_collected_port.get(irq_txn);
+ irq = {irq_txn.irq_nm, irq_txn.irq_fast, 4'b0, irq_txn.irq_external, 3'b0,
+ irq_txn.irq_timer, 3'b0, irq_txn.irq_software, 3'b0};
+ `DV_CHECK_EQ_FATAL(irq, 0, "Interrupt lines have not been dropped")
+ return;
+ end
+ check_next_core_status(HANDLING_IRQ, "Core did not jump to vectored interrupt handler");
+ // check mstatus
+ wait_for_csr_write(CSR_MSTATUS);
+ mstatus = signature_data;
+ `DV_CHECK_EQ_FATAL(mstatus[12:11], PRIV_LVL_M, "Incorrect privilege mode")
+ `DV_CHECK_EQ_FATAL(mstatus[7], 1'b1, "mstatus.mpie was not set to 1'b1 after entering handler")
+ `DV_CHECK_EQ_FATAL(mstatus[3], 1'b0, "mstatus.mie was not set to 1'b0 after entering handler")
+ // check mcause against the interrupt id
+ wait_for_csr_write(CSR_MCAUSE);
+ mcause = signature_data;
+ // check that mcause.interrupt is set
+ `DV_CHECK_EQ_FATAL(mcause[ibex_mem_intf_agent_pkg::DATA_WIDTH-1], 1'b1,
+ "mcause.interrupt is not set to 1'b1")
+ // check that mcause.exception_code matches the current interrupt's ID
+ `DV_CHECK_EQ_FATAL(mcause[ibex_mem_intf_agent_pkg::DATA_WIDTH-2:0], irq_id,
+ "mcause.exception_code is encoding the wrong interrupt type")
+ // Wait for MIE and MIP to be written regardless of what interrupt ibex is dealing with, to
+ // prevent the case where MIP/MIE stays at 0 due to a nonmaskable interrupt, which will falsely
+ // trigger the following call of check_next_core_status()
+ wait_for_csr_write(CSR_MIE);
+ mie = signature_data;
+ wait_for_csr_write(CSR_MIP);
+ mip = signature_data;
+ // only check mip, and mie if the interrupt is not irq_nm, as Ibex's implementation of MIP and
+ // MIE CSRs do not contain a bit for irq_nm
+ if (!irq_txn.irq_nm) begin
+ // check that the proper bit in MIE is high
+ `DV_CHECK_EQ_FATAL(mie[irq_id], 1'b1,
+ $sformatf("mie[%0d] is not set, but core responded to corresponding interrupt", irq_id))
+ // check that the proper bit in MIP is high
+ `DV_CHECK_EQ_FATAL(mip[irq_id], 1'b1,
+ $sformatf("mip[%0d] is not set, but core responded to corresponding interrupt", irq_id))
+ end
+ // As Ibex interrupts are level sensitive, core must write to memory mapped address to
+ // indicate that irq stimulus be dropped
+ check_next_core_status(FINISHED_IRQ, "Core did not signal end of interrupt properly");
+ // Will receive irq_seq_item indicating that lines have been dropped
+ vseq.start_irq_drop_seq();
+ irq_collected_port.get(irq_txn);
+ irq = {irq_txn.irq_nm, irq_txn.irq_fast, 4'b0, irq_txn.irq_external, 3'b0,
+ irq_txn.irq_timer, 3'b0, irq_txn.irq_software, 3'b0};
+ `DV_CHECK_EQ_FATAL(irq, 0, "Interrupt lines have not been dropped")
+ wait (dut_vif.mret === 1'b1);
+ endtask
+
+ function int get_max_irq_id(bit [irq_agent_pkg::DATA_WIDTH-1:0] irq);
+ int i;
+ for (i = irq_agent_pkg::DATA_WIDTH-1; i >= 0; i = i - 1) begin
+ if (irq[i] === 1'b1) begin
+ return i;
+ break;
+ end
+ end
+ endfunction
+
+ // Basic debug stimulus check for Ibex for debug stimulus stress tests: check that Ibex enters
+ // debug mode properly after stimulus is sent and then check that a dret is encountered signifying
+ // the end of debug mode.
+ virtual task send_debug_stimulus();
+ fork
+ begin
+ vseq.start_debug_stress_seq();
+ end
+ begin
+ forever begin
+ wait_for_core_status(IN_DEBUG_MODE);
+ wait(dut_vif.dret === 1'b1);
+ end
+ end
+ join_none
+ endtask
+
endclass
// Base class for directed debug and irq test scenarios
-class core_ibex_directed_test extends core_ibex_base_test;
+class core_ibex_directed_test extends core_ibex_debug_intr_basic_test;
`uvm_component_utils(core_ibex_directed_test)
`uvm_component_new
@@ -84,23 +278,33 @@
clk_vif.wait_clks(stimulus_delay);
fork
begin
- if (cfg.enable_irq_stress_seq) begin
- vseq.start_irq_stress_seq();
+ if (cfg.enable_irq_seq) begin
+ forever begin
+ send_irq_stimulus();
+ end
end
end
begin
if (cfg.enable_debug_stress_seq) begin
- vseq.start_debug_stress_seq();
+ send_debug_stimulus();
end
end
join_none
end else begin
// Wait for core initialization before starting the stimulus check loop - first write
// to signature address is guaranteed to be core initialization info
- check_next_core_status(INITIALIZED, "Core initialization handshake failure");
+ wait_for_core_setup();
// Should be extended by derived classes.
// DO NOT use this test class directly.
- check_stimulus();
+ fork
+ begin : stimulus
+ check_stimulus();
+ end : stimulus
+ begin
+ wait(dut_vif.ecall === 1'b1);
+ disable stimulus;
+ end
+ join
end
end
join_none
@@ -150,6 +354,7 @@
// is detected, and before any stimulus is sent to the core
forever begin
wait (dut_vif.wfi === 1'b1);
+ wait (dut_vif.core_sleep === 1'b1);
clk_vif.wait_clks($urandom_range(100));
vseq.start_debug_single_seq();
// After assserting this signal, core should wake up and jump into debug mode from WFI state
@@ -181,7 +386,8 @@
check_next_core_status(HANDLING_EXCEPTION, "Core did not jump to vectored exception handler");
// The core will receive an illegal instruction handshake after jumping from the vectored trap
// handler to the illegal instruction exception handler
- check_next_core_status(ILLEGAL_INSTR_EXCEPTION, "Core did not treat dret like illegal instruction");
+ check_next_core_status(ILLEGAL_INSTR_EXCEPTION,
+ "Core did not treat dret like illegal instruction");
end
endtask
@@ -200,7 +406,8 @@
forever begin
wait (dut_vif.ebreak === 1'b1);
check_next_core_status(HANDLING_EXCEPTION, "Core did not jump to exception handler");
- check_next_core_status(EBREAK_EXCEPTION, "Core did not jump from exception handler to ebreak handler");
+ check_next_core_status(EBREAK_EXCEPTION,
+ "Core did not jump from exception handler to ebreak handler");
wait (dut_vif.mret === 1'b1);
// Want to wait until after the ebreak handler has finished to send debug stimulus, to avoid
// nested trap scenarios
@@ -218,9 +425,11 @@
wait (dut_vif.ebreak === 1'b1);
// compare the second writes of dcsr and dpc against the captured values
wait_for_csr_write(CSR_DCSR);
- `DV_CHECK_EQ_FATAL(dcsr, signature_data, "ebreak inside the debug rom has changed the value of DCSR")
+ `DV_CHECK_EQ_FATAL(dcsr, signature_data,
+ "ebreak inside the debug rom has changed the value of DCSR")
wait_for_csr_write(CSR_DPC);
- `DV_CHECK_EQ_FATAL(dpc, signature_data, "ebreak inside the debug rom has changed the value of DPC")
+ `DV_CHECK_EQ_FATAL(dpc, signature_data,
+ "ebreak inside the debug rom has changed the value of DPC")
wait (dut_vif.dret === 1'b1);
end
endtask
@@ -236,7 +445,8 @@
virtual task check_stimulus();
// send a single debug request after core initialization to configure dcsr
vseq.start_debug_single_seq();
- check_next_core_status(IN_DEBUG_MODE, "Core did not enter debug mode after debug_req stimulus");
+ check_next_core_status(IN_DEBUG_MODE,
+ "Core did not enter debug mode after debug_req stimulus");
// Read dcsr and verify the appropriate ebreak(m/s/u) bit has been set based on the prv field,
// as well as the cause field
wait_for_csr_write(CSR_DCSR);
@@ -245,7 +455,8 @@
wait (dut_vif.dret === 1'b1);
forever begin
wait (dut_vif.ebreak === 1'b1);
- check_next_core_status(IN_DEBUG_MODE, "Core did not enter debug mode after execution of ebreak");
+ check_next_core_status(IN_DEBUG_MODE,
+ "Core did not enter debug mode after execution of ebreak");
// Read dcsr and verify the appropriate ebreak(m/s/u) bit has been set based on the prv field
wait_for_csr_write(CSR_DCSR);
check_dcsr_ebreak();
@@ -255,3 +466,121 @@
endtask
endclass
+
+// Debug single step test
+class core_ibex_debug_single_step_test extends core_ibex_directed_test;
+
+ `uvm_component_utils(core_ibex_debug_single_step_test)
+ `uvm_component_new
+
+ virtual task check_stimulus();
+ bit[ibex_mem_intf_agent_pkg::DATA_WIDTH-1:0] ret_pc;
+ bit [ibex_mem_intf_agent_pkg::DATA_WIDTH-1:0] counter = 0;
+ bit [ibex_mem_intf_agent_pkg::DATA_WIDTH-1:0] next_counter = 0;
+ forever begin
+ vseq.start_debug_single_seq();
+ check_next_core_status(IN_DEBUG_MODE,
+ "Core did not enter debug mode after debug stimulus");
+ wait_for_csr_write(CSR_DPC);
+ ret_pc = signature_data;
+ wait_for_csr_write(CSR_DSCRATCH0);
+ next_counter = signature_data;
+ wait_for_csr_write(CSR_DCSR);
+ check_dcsr_cause(DBG_CAUSE_HALTREQ);
+ `DV_CHECK_EQ_FATAL(signature_data[1], 1'b1, "dcsr.step is not set")
+ wait(dut_vif.dret === 1'b1);
+ // now we loop on the counter until we are done single stepping
+ while (counter >= 0) begin
+ counter = next_counter;
+ check_next_core_status(IN_DEBUG_MODE,
+ "Core did not enter debug mode after debug stimulus");
+ wait_for_csr_write(CSR_DPC);
+ if (signature_data - ret_pc !== 'h2 &&
+ signature_data - ret_pc !== 'h4) begin
+ `uvm_fatal(`gfn, $sformatf("DPC value [0x%0x] is not the next instruction after ret_pc [0x%0x]",
+ signature_data, ret_pc))
+ end
+ ret_pc = signature_data;
+ wait_for_csr_write(CSR_DSCRATCH0);
+ next_counter = signature_data;
+ wait_for_csr_write(CSR_DCSR);
+ check_dcsr_cause(DBG_CAUSE_STEP);
+ if (counter === 0) begin
+ `DV_CHECK_EQ_FATAL(signature_data[2], 1'b0, "dcsr.step is set")
+ end else begin
+ `DV_CHECK_EQ_FATAL(signature_data[2], 1'b1, "dcsr.step is not set")
+ end
+ wait(dut_vif.dret === 1'b1);
+ if (counter === 0) break;
+ end
+ clk_vif.wait_clks(2000);
+ end
+ endtask
+
+endclass
+
+// Memory interface error test class
+class core_ibex_mem_error_test extends core_ibex_directed_test;
+
+ `uvm_component_utils(core_ibex_mem_error_test)
+ `uvm_component_new
+
+ int err_delay;
+
+ // check memory error inputs and verify that core jumps to correct exception handler
+ // TODO(udinator) - add checks for the RVFI interface
+ virtual task check_stimulus();
+ forever begin
+ while (!vseq.data_intf_seq.get_error_synch()) begin
+ clk_vif.wait_clks(1);
+ end
+ vseq.data_intf_seq.inject_error();
+ `uvm_info(`gfn, "Injected dmem error", UVM_LOW)
+ // Dmem interface error could be either a load or store operation
+ check_mem_fault(1'b1);
+ // Random delay before injecting instruction fetch fault
+ `DV_CHECK_STD_RANDOMIZE_WITH_FATAL(err_delay, err_delay inside { [25:100] };)
+ clk_vif.wait_clks(err_delay);
+ while (!vseq.instr_intf_seq.get_error_synch()) begin
+ clk_vif.wait_clks(1);
+ end
+ `uvm_info(`gfn, "Injecting imem fault", UVM_LOW)
+ vseq.instr_intf_seq.inject_error();
+ check_mem_fault(1'b0);
+ // Random delay before injecting this series of errors again
+ `DV_CHECK_STD_RANDOMIZE_WITH_FATAL(err_delay, err_delay inside { [250:750] };)
+ clk_vif.wait_clks(err_delay);
+ end
+ endtask
+
+ virtual task check_mem_fault(bit imem_or_dmem);
+ bit[ibex_mem_intf_agent_pkg::DATA_WIDTH-1:0] mcause;
+ core_status_t mem_status;
+ ibex_pkg::exc_cause_e exc_type;
+ check_next_core_status(HANDLING_EXCEPTION, "Core did not jump to exception handler");
+ if (imem_or_dmem) begin
+ // Next write of CORE_STATUS will be the load/store fault type
+ wait_for_mem_txn(cfg.signature_addr, CORE_STATUS);
+ mem_status = signature_data_q.pop_front();
+ if (mem_status == LOAD_FAULT_EXCEPTION) begin
+ exc_type = EXC_CAUSE_LOAD_ACCESS_FAULT;
+ end else if (mem_status == STORE_FAULT_EXCEPTION) begin
+ exc_type = EXC_CAUSE_STORE_ACCESS_FAULT;
+ end
+ `uvm_info(`gfn, $sformatf("0x%0x", exc_type), UVM_LOW)
+ end else begin
+ check_next_core_status(INSTR_FAULT_EXCEPTION, "Core did not register correct memory fault type");
+ exc_type = EXC_CAUSE_INSTR_ACCESS_FAULT;
+ end
+ wait_for_csr_write(CSR_MCAUSE);
+ mcause = signature_data;
+ `DV_CHECK_EQ_FATAL(mcause[ibex_mem_intf_agent_pkg::DATA_WIDTH-1], 1'b0,
+ "mcause interrupt is not set to 1'b0")
+ `DV_CHECK_EQ_FATAL(mcause[ibex_mem_intf_agent_pkg::DATA_WIDTH-2:0],
+ exc_type,
+ "mcause.exception_code is encoding the wrong exception type")
+ wait(dut_vif.mret === 1'b1);
+ `uvm_info(`gfn, "exiting mem fault checker", UVM_LOW)
+ endtask
+
+endclass
diff --git a/hw/vendor/lowrisc_ibex/dv/uvm/tests/core_ibex_vseq.sv b/hw/vendor/lowrisc_ibex/dv/uvm/tests/core_ibex_vseq.sv
index 53ccc75..2a754c6 100644
--- a/hw/vendor/lowrisc_ibex/dv/uvm/tests/core_ibex_vseq.sv
+++ b/hw/vendor/lowrisc_ibex/dv/uvm/tests/core_ibex_vseq.sv
@@ -11,8 +11,8 @@
ibex_mem_intf_slave_seq instr_intf_seq;
ibex_mem_intf_slave_seq data_intf_seq;
mem_model_pkg::mem_model mem;
- irq_seq irq_seq_stress_h;
- irq_seq irq_seq_single_h;
+ irq_raise_single_seq irq_single_seq_h;
+ irq_drop_seq irq_drop_seq_h;
debug_seq debug_seq_stress_h;
debug_seq debug_seq_single_h;
core_ibex_env_cfg cfg;
@@ -25,17 +25,18 @@
virtual task body();
instr_intf_seq = ibex_mem_intf_slave_seq::type_id::create("instr_intf_seq");
data_intf_seq = ibex_mem_intf_slave_seq::type_id::create("data_intf_seq");
- if (cfg.enable_irq_stress_seq) begin
- irq_seq_stress_h = irq_seq::type_id::create("irq_seq_stress_h");
- irq_seq_stress_h.max_interval = cfg.max_interval;
- end
- if (cfg.enable_irq_single_seq) begin
- irq_seq_single_h = irq_seq::type_id::create("irq_seq_single_h");
- irq_seq_single_h.num_of_iterations = 1;
- irq_seq_single_h.max_interval = 1;
- irq_seq_single_h.max_delay = 1;
- irq_seq_single_h.interval.rand_mode(0);
- irq_seq_single_h.interval = 0;
+ if (cfg.enable_irq_seq) begin
+ irq_single_seq_h = irq_raise_single_seq::type_id::create("irq_seq_single_h");
+ irq_single_seq_h.num_of_iterations = 1;
+ irq_single_seq_h.max_interval = 1;
+ irq_single_seq_h.max_delay = 500;
+ irq_single_seq_h.interval = 0;
+
+ irq_drop_seq_h = irq_drop_seq::type_id::create("irq_drop_seq_h");
+ irq_drop_seq_h.num_of_iterations = 1;
+ irq_drop_seq_h.max_interval = 1;
+ irq_drop_seq_h.max_delay = 1;
+ irq_drop_seq_h.interval = 0;
end
if (cfg.enable_debug_stress_seq) begin
debug_seq_stress_h = debug_seq::type_id::create("debug_seq_stress_h");
@@ -58,11 +59,9 @@
endtask
virtual task stop();
- if (cfg.enable_irq_stress_seq) begin
- irq_seq_stress_h.stop();
- end
- if (cfg.enable_irq_single_seq) begin
- irq_seq_single_h.stop();
+ if (cfg.enable_irq_seq) begin
+ irq_single_seq_h.stop();
+ irq_drop_seq_h.stop();
end
if (cfg.enable_debug_stress_seq) begin
debug_seq_stress_h.stop();
@@ -82,12 +81,12 @@
debug_seq_single_h.start(null);
endtask
- virtual task start_irq_stress_seq();
- irq_seq_stress_h.start(p_sequencer.irq_seqr);
+ virtual task start_irq_single_seq();
+ irq_single_seq_h.start(p_sequencer.irq_seqr);
endtask
- virtual task start_irq_single_seq();
- irq_seq_single_h.start(p_sequencer.irq_seqr);
+ virtual task start_irq_drop_seq();
+ irq_drop_seq_h.start(p_sequencer.irq_seqr);
endtask
endclass
diff --git a/hw/vendor/lowrisc_ibex/dv/uvm/yaml/rtl_simulation.yaml b/hw/vendor/lowrisc_ibex/dv/uvm/yaml/rtl_simulation.yaml
index ea7037f..de497d8 100644
--- a/hw/vendor/lowrisc_ibex/dv/uvm/yaml/rtl_simulation.yaml
+++ b/hw/vendor/lowrisc_ibex/dv/uvm/yaml/rtl_simulation.yaml
@@ -45,3 +45,22 @@
-cm_name test_<seed>
wave_opts: >
-ucli -do <cwd>/vcs.tcl
+
+- tool: dsim
+ env_var: DSIM,DSIM_LIB_PATH
+ compile:
+ cmd:
+ - "mkdir -p <out>/dsim"
+ - "<DSIM> -sv -work <out>/dsim
+ -genimage image
+ +incdir+$UVM_HOME/src
+ $UVM_HOME/src/uvm_pkg.sv
+ +define+DSIM
+ +acc+rwb
+ -f ibex_dv.f
+ -l <out>/dsim/compile.log"
+ sim:
+ cmd: >
+ <DSIM> <sim_opts> -sv_seed <seed> -pli_lib <DSIM_LIB_PATH>/libuvm_dpi.so +acc+rwb -image image -work <out>/dsim <wave_opts>
+ wave_opts: >
+ -waves waves.vcd
diff --git a/hw/vendor/lowrisc_ibex/dv/verilator/simutil_verilator/cpp/verilated_toplevel.h b/hw/vendor/lowrisc_ibex/dv/verilator/simutil_verilator/cpp/verilated_toplevel.h
deleted file mode 100644
index 8b13671..0000000
--- a/hw/vendor/lowrisc_ibex/dv/verilator/simutil_verilator/cpp/verilated_toplevel.h
+++ /dev/null
@@ -1,123 +0,0 @@
-// Copyright lowRISC contributors.
-// Licensed under the Apache License, Version 2.0, see LICENSE for details.
-// SPDX-License-Identifier: Apache-2.0
-
-#ifndef VERILATED_TOPLEVEL_H_
-#define VERILATED_TOPLEVEL_H_
-
-#include <verilated.h>
-
-// VM_TRACE_FMT_FST must be set by the user when calling Verilator with
-// --trace-fst. VM_TRACE is set by Verilator itself.
-#if VM_TRACE == 1
-# ifdef VM_TRACE_FMT_FST
-# include "verilated_fst_c.h"
-# define VM_TRACE_CLASS_NAME VerilatedFstC
-# else
-# include "verilated_vcd_c.h"
-# define VM_TRACE_CLASS_NAME VerilatedVcdC
-# endif
-#endif
-
-#if VM_TRACE == 1
-/**
- * "Base" for all tracers in Verilator with common functionality
- *
- * This class is (like the VerilatedToplevel class) a workaround for the
- * insufficient class hierarchy in Verilator-generated C++ code.
- *
- * Once Verilator is improved to support this functionality natively this class
- * should go away.
- */
-class VerilatedTracer {
- public:
- VerilatedTracer() : impl_(nullptr) { impl_ = new VM_TRACE_CLASS_NAME(); };
-
- ~VerilatedTracer() { delete impl_; }
-
- bool isOpen() const { return impl_->isOpen(); };
-
- void open(const char *filename) { impl_->open(filename); };
-
- void close() { impl_->close(); };
-
- void dump(vluint64_t timeui) { impl_->dump(timeui); }
-
- operator VM_TRACE_CLASS_NAME *() const {
- assert(impl_);
- return impl_;
- }
-
- private:
- VM_TRACE_CLASS_NAME *impl_;
-};
-#else
-/**
- * No-op tracer interface
- */
-class VerilatedTracer {
- public:
- VerilatedTracer(){};
- ~VerilatedTracer() {}
- bool isOpen() const { return false; };
- void open(const char *filename){};
- void close(){};
- void dump(vluint64_t timeui) {}
-};
-#endif // VM_TRACE == 1
-
-/**
- * Pure abstract class (interface) for verilated toplevel modules
- *
- * Verilator-produced toplevel modules do not have a common base class defining
- * the methods such as eval(); instead, they are only inheriting from the
- * generic VerilatedModule class, which doesn't have toplevel-specific
- * functionality. This makes it impossible to write code which accepts any
- * toplevel module as input by specifying the common "toplevel base class".
- *
- * This class, VerilatedToplevel, fills this gap by defining an abstract base
- * class for verilated toplevel modules. This class should be used together with
- * the VERILATED_TOPLEVEL macro.
- *
- * Note that this function is a workaround until Verilator gains this
- * functionality natively.
- *
- * To support the different tracing implementations (VCD, FST or no tracing),
- * the trace() function is modified to take a VerilatedTracer argument instead
- * of the tracer-specific class.
- */
-class VerilatedToplevel {
- public:
- VerilatedToplevel(){};
- virtual ~VerilatedToplevel(){};
-
- virtual void eval() = 0;
- virtual void final() = 0;
- virtual const char *name() const = 0;
- virtual void trace(VerilatedTracer &tfp, int levels, int options) = 0;
-};
-
-#define STR(s) #s
-
-#if VM_TRACE == 1
-# define VERILATED_TOPLEVEL_TRACE_CALL(topname) \
- V##topname::trace(static_cast<VM_TRACE_CLASS_NAME *>(tfp), levels, options);
-#else
-# define VERILATED_TOPLEVEL_TRACE_CALL(topname) \
- assert(0 && "Tracing not enabled.");
-#endif
-
-#define VERILATED_TOPLEVEL(topname) \
- class topname : public V##topname, public VerilatedToplevel { \
- public: \
- topname(const char *name = "TOP") \
- : V##topname(name), VerilatedToplevel() {} \
- const char *name() const { return STR(topname); } \
- void eval() { V##topname::eval(); } \
- void final() { V##topname::final(); } \
- void trace(VerilatedTracer &tfp, int levels, int options = 0) { \
- VERILATED_TOPLEVEL_TRACE_CALL(topname) \
- } \
- };
-
-#endif // VERILATED_TOPLEVEL_H_
diff --git a/hw/vendor/lowrisc_ibex/dv/verilator/simutil_verilator/cpp/verilator_sim_ctrl.cc b/hw/vendor/lowrisc_ibex/dv/verilator/simutil_verilator/cpp/verilator_sim_ctrl.cc
deleted file mode 100644
index d9aae69..0000000
--- a/hw/vendor/lowrisc_ibex/dv/verilator/simutil_verilator/cpp/verilator_sim_ctrl.cc
+++ /dev/null
@@ -1,380 +0,0 @@
-// Copyright lowRISC contributors.
-// Licensed under the Apache License, Version 2.0, see LICENSE for details.
-// SPDX-License-Identifier: Apache-2.0
-
-#include "verilator_sim_ctrl.h"
-
-#include <getopt.h>
-#include <sys/stat.h>
-#include <unistd.h>
-#include <vltstd/svdpi.h>
-
-#include <iostream>
-
-// This is defined by Verilator and passed through the command line
-#ifndef VM_TRACE
-#define VM_TRACE 0
-#endif
-
-// DPI Exports
-extern "C" {
-extern void simutil_verilator_memload(const char *file);
-}
-
-VerilatorSimCtrl::VerilatorSimCtrl(VerilatedToplevel *top, CData &sig_clk,
- CData &sig_rst, VerilatorSimCtrlFlags flags)
- : top_(top),
- sig_clk_(sig_clk),
- sig_rst_(sig_rst),
- flags_(flags),
- time_(0),
- init_rom_(false),
- init_ram_(false),
- init_flash_(false),
- tracing_enabled_(false),
- tracing_enabled_changed_(false),
- tracing_ever_enabled_(false),
- tracing_possible_(VM_TRACE),
- initial_reset_delay_cycles_(2),
- reset_duration_cycles_(2),
- request_stop_(false),
- tracer_(VerilatedTracer()),
- term_after_cycles_(0) {}
-
-void VerilatorSimCtrl::RequestStop() { request_stop_ = true; }
-
-bool VerilatorSimCtrl::TraceOn() {
- bool old_tracing_enabled = tracing_enabled_;
-
- tracing_enabled_ = tracing_possible_;
- tracing_ever_enabled_ = tracing_enabled_;
-
- if (old_tracing_enabled != tracing_enabled_) {
- tracing_enabled_changed_ = true;
- }
- return tracing_enabled_;
-}
-
-bool VerilatorSimCtrl::TraceOff() {
- if (tracing_enabled_) {
- tracing_enabled_changed_ = true;
- }
- tracing_enabled_ = false;
- return tracing_enabled_;
-}
-
-void VerilatorSimCtrl::PrintHelp() const {
- std::cout << "Execute a simulation model for " << top_->name()
- << "\n"
- "\n";
- if (tracing_possible_) {
- std::cout << "-t|--trace Write a trace file from the start\n";
- }
- std::cout << "-r|--rominit=VMEMFILE Initialize the ROM with VMEMFILE\n"
- "-m|--raminit=VMEMFILE Initialize the RAM with VMEMFILE\n"
- "-f|--flashinit=VMEMFILE Initialize the FLASH with VMEMFILE\n"
- "-h|--help Show help\n"
- "\n"
- "All further arguments are passed to the design and can be used "
- "in the \n"
- "design, e.g. by DPI modules.\n";
-}
-
-void VerilatorSimCtrl::InitRom(std::string rom) {
- if (!init_rom_) {
- return;
- }
-
- svScope scope;
-
- scope = svGetScopeFromName(rom.data());
- if (!scope) {
- std::cerr << "ERROR: No ROM found at " << rom << std::endl;
- exit(1);
- }
- svSetScope(scope);
-
- simutil_verilator_memload(rom_init_file_.data());
-
- std::cout << std::endl
- << "Rom initialized with program at " << rom_init_file_
- << std::endl;
-}
-
-void VerilatorSimCtrl::InitRam(std::string ram) {
- if (!init_ram_) {
- return;
- }
-
- svScope scope;
-
- scope = svGetScopeFromName(ram.data());
- if (!scope) {
- std::cerr << "ERROR: No RAM found at " << ram << std::endl;
- exit(1);
- }
- svSetScope(scope);
-
- simutil_verilator_memload(ram_init_file_.data());
-
- std::cout << std::endl
- << "Ram initialized with program at " << ram_init_file_
- << std::endl;
-}
-
-void VerilatorSimCtrl::InitFlash(std::string flash) {
- if (!init_flash_) {
- return;
- }
-
- svScope scope;
-
- scope = svGetScopeFromName(flash.data());
- if (!scope) {
- std::cerr << "ERROR: No FLASH found at " << flash << std::endl;
- exit(1);
- }
- svSetScope(scope);
-
- simutil_verilator_memload(flash_init_file_.data());
-
- std::cout << std::endl
- << "Flash initialized with program at " << flash_init_file_
- << std::endl;
-}
-
-bool VerilatorSimCtrl::ParseCommandArgs(int argc, char **argv, int &retcode) {
- const struct option long_options[] = {
- {"rominit", required_argument, nullptr, 'r'},
- {"raminit", required_argument, nullptr, 'm'},
- {"flashinit", required_argument, nullptr, 'f'},
- {"term-after-cycles", required_argument, nullptr, 'c'},
- {"trace", no_argument, nullptr, 't'},
- {"help", no_argument, nullptr, 'h'},
- {nullptr, no_argument, nullptr, 0}};
-
- while (1) {
- int c = getopt_long(argc, argv, ":r:m:f:th", long_options, nullptr);
- if (c == -1) {
- break;
- }
-
- // Disable error reporting by getopt
- opterr = 0;
-
- switch (c) {
- case 0:
- break;
- case 'r':
- rom_init_file_ = optarg;
- init_rom_ = true;
- if (!IsFileReadable(rom_init_file_)) {
- std::cerr << "ERROR: ROM initialization file "
- << "'" << rom_init_file_ << "'"
- << " is not readable." << std::endl;
- return false;
- }
- break;
- case 'm':
- ram_init_file_ = optarg;
- init_ram_ = true;
- if (!IsFileReadable(ram_init_file_)) {
- std::cerr << "ERROR: Memory initialization file "
- << "'" << ram_init_file_ << "'"
- << " is not readable." << std::endl;
- return false;
- }
- break;
- case 'f':
- flash_init_file_ = optarg;
- init_flash_ = true;
- if (!IsFileReadable(flash_init_file_)) {
- std::cerr << "ERROR: FLASH initialization file "
- << "'" << flash_init_file_ << "'"
- << " is not readable." << std::endl;
- return false;
- }
- break;
- case 't':
- if (!tracing_possible_) {
- std::cerr << "ERROR: Tracing has not been enabled at compile time."
- << std::endl;
- return false;
- }
- TraceOn();
- break;
- case 'c':
- term_after_cycles_ = atoi(optarg);
- break;
- case 'h':
- PrintHelp();
- return false;
- case ':': // missing argument
- std::cerr << "ERROR: Missing argument." << std::endl;
- PrintHelp();
- return false;
- case '?':
- default:;
- // Ignore unrecognized options since they might be consumed by
- // Verilator's built-in parsing below.
- }
- }
-
- Verilated::commandArgs(argc, argv);
- return true;
-}
-
-void VerilatorSimCtrl::Trace() {
- // We cannot output a message when calling TraceOn()/TraceOff() as these
- // functions can be called from a signal handler. Instead we print the message
- // here from the main loop.
- if (tracing_enabled_changed_) {
- if (TracingEnabled()) {
- std::cout << "Tracing enabled." << std::endl;
- } else {
- std::cout << "Tracing disabled." << std::endl;
- }
- tracing_enabled_changed_ = false;
- }
-
- if (!TracingEnabled()) {
- return;
- }
-
- if (!tracer_.isOpen()) {
- tracer_.open(GetSimulationFileName());
- std::cout << "Writing simulation traces to " << GetSimulationFileName()
- << std::endl;
- }
-
- tracer_.dump(GetTime());
-}
-
-const char *VerilatorSimCtrl::GetSimulationFileName() const {
-#ifdef VM_TRACE_FMT_FST
- return "sim.fst";
-#else
- return "sim.vcd";
-#endif
-}
-
-void VerilatorSimCtrl::Run() {
- // We always need to enable this as tracing can be enabled at runtime
- if (tracing_possible_) {
- Verilated::traceEverOn(true);
- top_->trace(tracer_, 99, 0);
- }
-
- // Evaluate all initial blocks, including the DPI setup routines
- top_->eval();
-
- std::cout << std::endl
- << "Simulation running, end by pressing CTRL-c." << std::endl;
-
- time_begin_ = std::chrono::steady_clock::now();
- UnsetReset();
- Trace();
- while (1) {
- if (time_ >= initial_reset_delay_cycles_ * 2) {
- SetReset();
- }
- if (time_ >= reset_duration_cycles_ * 2 + initial_reset_delay_cycles_ * 2) {
- UnsetReset();
- }
-
- sig_clk_ = !sig_clk_;
-
- top_->eval();
- time_++;
-
- Trace();
-
- if (request_stop_) {
- std::cout << "Received stop request, shutting down simulation."
- << std::endl;
- break;
- }
- if (Verilated::gotFinish()) {
- std::cout << "Received $finish() from Verilog, shutting down simulation."
- << std::endl;
- break;
- }
- if (term_after_cycles_ && time_ > term_after_cycles_) {
- std::cout << "Simulation timeout of " << term_after_cycles_
- << " cycles reached, shutting down simulation." << std::endl;
- break;
- }
- }
-
- top_->final();
- time_end_ = std::chrono::steady_clock::now();
-
- if (TracingEverEnabled()) {
- tracer_.close();
- }
-}
-
-void VerilatorSimCtrl::SetReset() {
- if (flags_ & ResetPolarityNegative) {
- sig_rst_ = 0;
- } else {
- sig_rst_ = 1;
- }
-}
-
-void VerilatorSimCtrl::UnsetReset() {
- if (flags_ & ResetPolarityNegative) {
- sig_rst_ = 1;
- } else {
- sig_rst_ = 0;
- }
-}
-
-void VerilatorSimCtrl::SetInitialResetDelay(unsigned int cycles) {
- initial_reset_delay_cycles_ = cycles;
-}
-
-void VerilatorSimCtrl::SetResetDuration(unsigned int cycles) {
- reset_duration_cycles_ = cycles;
-}
-
-bool VerilatorSimCtrl::IsFileReadable(std::string filepath) {
- struct stat statbuf;
- return stat(filepath.data(), &statbuf) == 0;
-}
-
-bool VerilatorSimCtrl::FileSize(std::string filepath, int &size_byte) {
- struct stat statbuf;
- if (stat(filepath.data(), &statbuf) != 0) {
- size_byte = 0;
- return false;
- }
-
- size_byte = statbuf.st_size;
- return true;
-}
-
-unsigned int VerilatorSimCtrl::GetExecutionTimeMs() {
- return std::chrono::duration_cast<std::chrono::milliseconds>(time_end_ -
- time_begin_)
- .count();
-}
-
-void VerilatorSimCtrl::PrintStatistics() {
- double speed_hz = time_ / 2 / (GetExecutionTimeMs() / 1000.0);
- double speed_khz = speed_hz / 1000.0;
-
- std::cout << std::endl
- << "Simulation statistics" << std::endl
- << "=====================" << std::endl
- << "Executed cycles: " << time_ / 2 << std::endl
- << "Wallclock time: " << GetExecutionTimeMs() / 1000.0 << " s"
- << std::endl
- << "Simulation speed: " << speed_hz << " cycles/s "
- << "(" << speed_khz << " kHz)" << std::endl;
-
- int trace_size_byte;
- if (tracing_enabled_ && FileSize(GetSimulationFileName(), trace_size_byte)) {
- std::cout << "Trace file size: " << trace_size_byte << " B" << std::endl;
- }
-}
diff --git a/hw/vendor/lowrisc_ibex/dv/verilator/simutil_verilator/cpp/verilator_sim_ctrl.h b/hw/vendor/lowrisc_ibex/dv/verilator/simutil_verilator/cpp/verilator_sim_ctrl.h
deleted file mode 100644
index 183939f..0000000
--- a/hw/vendor/lowrisc_ibex/dv/verilator/simutil_verilator/cpp/verilator_sim_ctrl.h
+++ /dev/null
@@ -1,157 +0,0 @@
-// Copyright lowRISC contributors.
-// Licensed under the Apache License, Version 2.0, see LICENSE for details.
-// SPDX-License-Identifier: Apache-2.0
-
-#ifndef VERILATOR_SIM_CTRL_H_
-#define VERILATOR_SIM_CTRL_H_
-
-#include <verilated.h>
-
-#include <chrono>
-#include <string>
-
-#include "verilated_toplevel.h"
-
-enum VerilatorSimCtrlFlags {
- Defaults = 0,
- ResetPolarityNegative = 1,
-};
-
-class VerilatorSimCtrl {
- public:
- VerilatorSimCtrl(VerilatedToplevel *top, CData &clk, CData &rst_n,
- VerilatorSimCtrlFlags flags = Defaults);
-
- /**
- * Print help how to use this tool
- */
- void PrintHelp() const;
-
- /**
- * Parse command line arguments
- *
- * This removes all recognized command-line arguments from argc/argv.
- *
- * The return value of this method indicates if the program should exit with
- * retcode: if this method returns true, do *not* exit; if it returns *false*,
- * do exit.
- */
- bool ParseCommandArgs(int argc, char **argv, int &retcode);
-
- /**
- * Run the main loop of the simulation
- *
- * This function blocks until the simulation finishes.
- */
- void Run();
-
- /**
- * Initialize Rom
- */
- void InitRom(const std::string mem);
-
- /**
- * Initialize Ram
- */
- void InitRam(const std::string mem);
-
- /**
- * Initialize Flash
- */
- void InitFlash(const std::string mem);
-
- /**
- * Get the current time in ticks
- */
- unsigned long GetTime() { return time_; }
-
- /**
- * Set the number of clock cycles (periods) before the reset signal is
- * activated
- */
- void SetInitialResetDelay(unsigned int cycles);
-
- /**
- * Set the number of clock cycles (periods) the reset signal is activated
- */
- void SetResetDuration(unsigned int cycles);
-
- /**
- * Request the simulation to stop
- */
- void RequestStop();
-
- /**
- * Enable tracing (if possible)
- *
- * Enabling tracing can fail if no tracing support has been compiled into the
- * simulation.
- *
- * @return Is tracing enabled?
- */
- bool TraceOn();
-
- /**
- * Disable tracing
- *
- * @return Is tracing enabled?
- */
- bool TraceOff();
-
- /**
- * Is tracing currently enabled?
- */
- bool TracingEnabled() { return tracing_enabled_; }
-
- /**
- * Has tracing been ever enabled during the run?
- *
- * Tracing can be enabled and disabled at runtime.
- */
- bool TracingEverEnabled() { return tracing_ever_enabled_; }
-
- /**
- * Is tracing support compiled into the simulation?
- */
- bool TracingPossible() { return tracing_possible_; }
-
- /**
- * Print statistics about the simulation run
- */
- void PrintStatistics();
-
- const char *GetSimulationFileName() const;
-
- private:
- VerilatedToplevel *top_;
- CData &sig_clk_;
- CData &sig_rst_;
- VerilatorSimCtrlFlags flags_;
- unsigned long time_;
- bool init_rom_;
- bool init_ram_;
- bool init_flash_;
- std::string rom_init_file_;
- std::string ram_init_file_;
- std::string flash_init_file_;
- bool tracing_enabled_;
- bool tracing_enabled_changed_;
- bool tracing_ever_enabled_;
- bool tracing_possible_;
- unsigned int initial_reset_delay_cycles_;
- unsigned int reset_duration_cycles_;
- volatile unsigned int request_stop_;
- std::chrono::steady_clock::time_point time_begin_;
- std::chrono::steady_clock::time_point time_end_;
- VerilatedTracer tracer_;
- int term_after_cycles_;
-
- unsigned int GetExecutionTimeMs();
- void SetReset();
- void UnsetReset();
- bool IsFileReadable(std::string filepath);
- bool FileSize(std::string filepath, int &size_byte);
- void Trace();
-};
-
-#endif // VERILATOR_SIM_CTRL_H_
diff --git a/hw/vendor/lowrisc_ibex/dv/verilator/simutil_verilator/simutil_verilator.core b/hw/vendor/lowrisc_ibex/dv/verilator/simutil_verilator/simutil_verilator.core
deleted file mode 100644
index 28b45f1..0000000
--- a/hw/vendor/lowrisc_ibex/dv/verilator/simutil_verilator/simutil_verilator.core
+++ /dev/null
@@ -1,19 +0,0 @@
-CAPI=2:
-# Copyright lowRISC contributors.
-# Licensed under the Apache License, Version 2.0, see LICENSE for details.
-# SPDX-License-Identifier: Apache-2.0
-
-name: "lowrisc:dv_verilator:simutil_verilator"
-description: "Verilator simulator support"
-filesets:
- files_cpp:
- files:
- - cpp/verilator_sim_ctrl.cc
- - cpp/verilator_sim_ctrl.h: { is_include_file: true }
- - cpp/verilated_toplevel.h: { is_include_file: true }
- file_type: cppSource
-
-targets:
- default:
- filesets:
- - files_cpp
diff --git a/hw/vendor/lowrisc_ibex/examples/sim/README.md b/hw/vendor/lowrisc_ibex/examples/sim/README.md
deleted file mode 100644
index 8b310a8..0000000
--- a/hw/vendor/lowrisc_ibex/examples/sim/README.md
+++ /dev/null
@@ -1,26 +0,0 @@
-# Example: Ibex with enabled instruction tracing for simulation
-
-## Overview
-
-This examples shows the usage of the module `ibex_core_tracing` which forwards
-all port signals to the `ibex_core` and a subset of signals to `ibex_tracer`.
-The tracer will create a file with a stream of executed instructions.
-
-## Prerequisites
-
-For this example, `modelsim` must be available and the following environment
-variable must point to the path of installation:
-
-```
-export MODEL_TECH=/path/to/modelsim/bin
-```
-
-## Usage
-
-Run the following command in the top level directory.
-
-```
-fusesoc --cores-root=. run --target=sim lowrisc:ibex:top_tracing_sim
-```
-
-The trace output can be found in `build/lowrisc_ibex_top_tracing_sim_0.1/sim-modelsim/trace_core_00_0.log`.
diff --git a/hw/vendor/lowrisc_ibex/examples/sim/rtl/prim_clock_gating.sv b/hw/vendor/lowrisc_ibex/examples/sim/rtl/prim_clock_gating.sv
deleted file mode 100644
index ed13f44..0000000
--- a/hw/vendor/lowrisc_ibex/examples/sim/rtl/prim_clock_gating.sv
+++ /dev/null
@@ -1,24 +0,0 @@
-// Copyright lowRISC contributors.
-// Licensed under the Apache License, Version 2.0, see LICENSE for details.
-// SPDX-License-Identifier: Apache-2.0
-//
-// Dummy clock gating module
-
-module prim_clock_gating (
- input clk_i,
- input en_i,
- input test_en_i,
- output logic clk_o
-);
-
- logic clk_en;
-
- always_latch begin
- if (clk_i == 1'b0) begin
- clk_en <= en_i | test_en_i;
- end
- end
-
- assign clk_o = clk_i & clk_en;
-
-endmodule
diff --git a/hw/vendor/lowrisc_ibex/examples/sim/tb/ibex_tracing_tb.sv b/hw/vendor/lowrisc_ibex/examples/sim/tb/ibex_tracing_tb.sv
deleted file mode 100644
index 59d4d9a..0000000
--- a/hw/vendor/lowrisc_ibex/examples/sim/tb/ibex_tracing_tb.sv
+++ /dev/null
@@ -1,117 +0,0 @@
-// Copyright lowRISC contributors.
-// Licensed under the Apache License, Version 2.0, see LICENSE for details.
-// SPDX-License-Identifier: Apache-2.0
-//
-// Sample testbench for Ibex with tracing enabled
-// The `nop` instruction is the only input
-
-module ibex_tracing_tb;
- logic clk = 1'b0;
- logic rst_n = 1'b0;
- logic [31:0] instr_rdata = 32'h00000013;
- logic [31:0] data_rdata = 32'h00000000;
- logic instr_gnt = 1'b0;
- logic instr_rvalid = 1'b0;
-
- initial begin: clock_gen
- forever begin
- #5ns clk = 1'b0;
- #5ns clk = 1'b1;
- end
- end
-
- initial begin: reset_gen
- rst_n = 1'b0;
- #160ns rst_n = 1'b1;
- #400ns $finish;
- end
-
- initial begin: instr_gen
- #200ns instr_rdata = 32'h81868106;
- instr_rvalid = 1'b0;
- instr_gnt = 1'b1;
- #10ns instr_rvalid = 1'b1;
- instr_gnt = 1'b0;
- #10ns instr_rvalid = 1'b0;
- #30ns instr_rdata = 32'h00400113;
- instr_rvalid = 1'b0;
- instr_gnt = 1'b1;
- #10ns instr_rvalid = 1'b1;
- instr_gnt = 1'b0;
- #10ns instr_rvalid = 1'b0;
- instr_rdata = 32'hff810113;
- instr_gnt = 1'b1;
- #10ns instr_rvalid = 1'b1;
- instr_gnt = 1'b0;
- #10ns instr_rvalid = 1'b0;
- instr_rdata = 32'h4000006f;
- instr_gnt = 1'b1;
- #10ns instr_rvalid = 1'b1;
- instr_gnt = 1'b0;
- #10ns instr_rvalid = 1'b0;
- #10ns instr_rdata = 32'h039597b3;
- instr_gnt = 1'b1;
- #10ns instr_rvalid = 1'b1;
- instr_gnt = 1'b1;
- #10ns instr_rdata = 32'h13410d13;
- #10ns instr_rdata = 32'he1070713;
- #10ns instr_rdata = 32'hfff7c793;
- #10ns instr_rdata = 32'h00000013;
- #10ns instr_rdata = 32'h002d2c23;
- #10ns instr_rdata = 32'h00000013;
- #10ns instr_rdata = 32'h000d2083;
- data_rdata = 32'h12345678;
- #10ns instr_rdata = 32'h60008113;
- #10ns instr_rdata = 32'h00000013;
- #10ns instr_rdata = 32'h002d2023;
- #20ns instr_rdata = 32'h0000000f;
- #10ns instr_rdata = 32'h00000113;
- #30ns instr_rdata = 32'h00000013;
- #10ns instr_rdata = 32'h0000000f;
- end
-
- ibex_core_tracing ibex_i (
- .clk_i (clk),
- .rst_ni (rst_n),
-
- .test_en_i (1'b0),
-
- // Core ID, Cluster ID and boot address are considered more or less static
- .hart_id_i (32'b0),
- .boot_addr_i (32'b0),
-
- // Instruction memory interface
- .instr_req_o (),
- .instr_gnt_i (instr_gnt),
- .instr_rvalid_i (instr_rvalid),
- .instr_addr_o (),
- .instr_rdata_i (instr_rdata),
- .instr_err_i (1'b0),
-
- // Data memory interface
- .data_req_o (),
- .data_gnt_i (1'b1),
- .data_rvalid_i (1'b1),
- .data_we_o (),
- .data_be_o (),
- .data_addr_o (),
- .data_wdata_o (),
- .data_rdata_i (data_rdata),
- .data_err_i (1'b0),
-
- // Interrupt inputs
- .irq_software_i (1'b0),
- .irq_timer_i (1'b0),
- .irq_external_i (1'b0),
- .irq_fast_i (15'b0),
- .irq_nm_i (1'b0),
-
- // Debug Interface
- .debug_req_i (1'b0),
-
- // CPU Control Signals
- .fetch_enable_i (1'b1),
- .core_sleep_o ()
- );
-
-endmodule
diff --git a/hw/vendor/lowrisc_ibex/examples/sim/top_tracing_sim.core b/hw/vendor/lowrisc_ibex/examples/sim/top_tracing_sim.core
deleted file mode 100644
index d318bcc..0000000
--- a/hw/vendor/lowrisc_ibex/examples/sim/top_tracing_sim.core
+++ /dev/null
@@ -1,25 +0,0 @@
-CAPI=2:
-# Copyright lowRISC contributors.
-# Licensed under the Apache License, Version 2.0, see LICENSE for details.
-# SPDX-License-Identifier: Apache-2.0
-name: "lowrisc:ibex:top_tracing_sim:0.1"
-description: "Ibex with tracing enabled (ModelSim only right now)"
-filesets:
- files_tb:
- depend:
- - lowrisc:ibex:ibex_core_tracing
- files:
- - rtl/prim_clock_gating.sv
- - tb/ibex_tracing_tb.sv
- file_type: systemVerilogSource
-
-targets:
- sim:
- default_tool: modelsim
- filesets:
- - files_tb
- toplevel:
- - ibex_tracing_tb
- tools:
- modelsim:
- vlog_options: [-timescale 1ns/1ns]
diff --git a/hw/vendor/lowrisc_ibex/ibex_core.core b/hw/vendor/lowrisc_ibex/ibex_core.core
index 48c0e9a..1ab080a 100644
--- a/hw/vendor/lowrisc_ibex/ibex_core.core
+++ b/hw/vendor/lowrisc_ibex/ibex_core.core
@@ -46,6 +46,14 @@
datatype: bool
paramtype: vlogdefine
+ RV32E:
+ datatype: bool
+ paramtype: vlogparam
+
+ RV32M:
+ datatype: bool
+ paramtype: vlogparam
+
targets:
default:
filesets:
@@ -61,6 +69,7 @@
- files_lint
parameters:
- SYNTHESIS=true
+ - RVFI=true
default_tool: verilator
toplevel: ibex_core
tools:
diff --git a/hw/vendor/lowrisc_ibex/ibex_core_tracing.core b/hw/vendor/lowrisc_ibex/ibex_core_tracing.core
index 0b9c897..f1cc613 100644
--- a/hw/vendor/lowrisc_ibex/ibex_core_tracing.core
+++ b/hw/vendor/lowrisc_ibex/ibex_core_tracing.core
@@ -13,6 +13,14 @@
- rtl/ibex_core_tracing.sv
file_type: systemVerilogSource
+ files_lint:
+ files:
+ - dv/uvm/tb/prim_clock_gating.sv: {file_type: systemVerilogSource}
+
+ files_lint_verilator:
+ files:
+ - lint/verilator_waiver.vlt: {file_type: vlt}
+
parameters:
# The tracer uses the RISC-V Formal Interface (RVFI) to collect trace signals.
RVFI:
@@ -20,9 +28,42 @@
paramtype: vlogdefine
default: true
+ SYNTHESIS:
+ datatype: bool
+ paramtype: vlogdefine
+
+ RV32E:
+ datatype: bool
+ paramtype: vlogparam
+
+ RV32M:
+ datatype: bool
+ paramtype: vlogparam
+
+
+
targets:
default:
filesets:
- files_rtl
parameters:
- RVFI=true
+
+ lint:
+ filesets:
+ # Note on Verilator waivers:
+ # You *must* include the waiver file first, otherwise only global waivers
+ # are applied, but not file-specific waivers.
+ - tool_verilator ? (files_lint_verilator)
+ - files_rtl
+ - files_lint
+ parameters:
+ - RVFI=true
+ - SYNTHESIS=true
+ default_tool: verilator
+ toplevel: ibex_core_tracing
+ tools:
+ verilator:
+ mode: lint-only
+ verilator_options:
+ - "-Wall"
diff --git a/hw/vendor/lowrisc_ibex/lint/verilator_waiver.vlt b/hw/vendor/lowrisc_ibex/lint/verilator_waiver.vlt
index 22c77bd..fca9dc9 100644
--- a/hw/vendor/lowrisc_ibex/lint/verilator_waiver.vlt
+++ b/hw/vendor/lowrisc_ibex/lint/verilator_waiver.vlt
@@ -56,22 +56,22 @@
// Signal is not used: csr_pmp_addr
// Signal not connected when PMP is not configured
-lint_off -msg UNUSED -file "*/rtl/ibex_core.sv" -lines 185
+lint_off -msg UNUSED -file "*/rtl/ibex_core.sv" -lines 186
// Signal is not used: csr_pmp_cfg
// Signal not connected when PMP is not configured
-lint_off -msg UNUSED -file "*/rtl/ibex_core.sv" -lines 186
+lint_off -msg UNUSED -file "*/rtl/ibex_core.sv" -lines 187
// Signal is not used: priv_mode
// Signal not connected when PMP is not configured
-lint_off -msg UNUSED -file "*/rtl/ibex_core.sv" -lines 198
+lint_off -msg UNUSED -file "*/rtl/ibex_core.sv" -lines 199
// Signal unoptimizable: Feedback to clock or circular logic:
// ibex_core.id_stage_i.controller_i.ctrl_fsm_cs
// Issue lowrisc/ibex#211
-lint_off -msg UNOPTFLAT -file "*/rtl/ibex_controller.sv" -lines 98
+lint_off -msg UNOPTFLAT -file "*/rtl/ibex_controller.sv" -lines 100
// Signal unoptimizable: Feedback to clock or circular logic:
// ibex_core.cs_registers_i.mie_q
// Issue lowrisc/ibex#212
-lint_off -msg UNOPTFLAT -file "*/rtl/ibex_cs_registers.sv" -lines 149
+lint_off -msg UNOPTFLAT -file "*/rtl/ibex_cs_registers.sv" -lines 162
diff --git a/hw/vendor/lowrisc_ibex/rtl/ibex_controller.sv b/hw/vendor/lowrisc_ibex/rtl/ibex_controller.sv
index 5a8fc54..c521e9b 100644
--- a/hw/vendor/lowrisc_ibex/rtl/ibex_controller.sv
+++ b/hw/vendor/lowrisc_ibex/rtl/ibex_controller.sv
@@ -74,6 +74,8 @@
output logic csr_restore_mret_id_o,
output logic csr_save_cause_o,
output logic [31:0] csr_mtval_o,
+ input ibex_pkg::priv_lvl_e priv_mode_i,
+ input logic csr_mstatus_tw_i,
// stall signals
input logic stall_lsu_i,
@@ -101,13 +103,14 @@
logic debug_mode_q, debug_mode_d;
logic load_err_q, load_err_d;
logic store_err_q, store_err_d;
+ logic exc_req_q, exc_req_d;
+ logic illegal_insn_q, illegal_insn_d;
logic stall;
logic halt_if;
- logic halt_id;
+ logic flush_id;
logic illegal_dret;
- logic illegal_insn;
- logic exc_req;
+ logic illegal_umode;
logic exc_req_lsu;
logic special_req;
logic enter_debug_mode;
@@ -116,13 +119,21 @@
logic [3:0] mfip_id;
logic unused_csr_mtip;
+ logic ecall_insn;
+ logic mret_insn;
+ logic dret_insn;
+ logic wfi_insn;
+ logic ebrk_insn;
+ logic csr_pipe_flush;
+ logic instr_fetch_err;
+
`ifndef SYNTHESIS
// synopsys translate_off
// make sure we are called later so that we do not generate messages for
// glitches
always_ff @(negedge clk_i) begin
// print warning in case of decoding errors
- if ((ctrl_fsm_cs == DECODE) && instr_valid_i && illegal_insn) begin
+ if ((ctrl_fsm_cs == DECODE) && instr_valid_i && !instr_fetch_err_i && illegal_insn_d) begin
$display("%t: Illegal instruction (hart %0x) at PC 0x%h: 0x%h", $time, ibex_core.hart_id_i,
ibex_id_stage.pc_id_i, ibex_id_stage.instr_rdata_i);
end
@@ -137,20 +148,43 @@
assign load_err_d = load_err_i;
assign store_err_d = store_err_i;
+ // Decoder doesn't take instr_valid into account, factor it in here.
+ assign ecall_insn = ecall_insn_i & instr_valid_i;
+ assign mret_insn = mret_insn_i & instr_valid_i;
+ assign dret_insn = dret_insn_i & instr_valid_i;
+ assign wfi_insn = wfi_insn_i & instr_valid_i;
+ assign ebrk_insn = ebrk_insn_i & instr_valid_i;
+ assign csr_pipe_flush = csr_pipe_flush_i & instr_valid_i;
+ assign instr_fetch_err = instr_fetch_err_i & instr_valid_i;
+
// "Executing DRET outside of Debug Mode causes an illegal instruction exception."
// [Debug Spec v0.13.2, p.41]
- assign illegal_dret = dret_insn_i & ~debug_mode_q;
- assign illegal_insn = illegal_insn_i | illegal_dret;
+ assign illegal_dret = dret_insn & ~debug_mode_q;
+
+ // Some instructions can only be executed in M-Mode
+ assign illegal_umode = (priv_mode_i != PRIV_LVL_M) &
+ // MRET must be in M-Mode. TW means trap WFI to M-Mode.
+ (mret_insn | (csr_mstatus_tw_i & wfi_insn));
+
+ // This is recorded in the illegal_insn_q flop to help timing. Specifically
+ // it is needed to break the path from ibex_cs_registers/illegal_csr_insn_o
+ // to pc_set_o. Clear when controller is in FLUSH so it won't remain set
+ // once illegal instruction is handled.
+ assign illegal_insn_d = (illegal_insn_i | illegal_dret | illegal_umode) & (ctrl_fsm_cs != FLUSH);
// exception requests
- assign exc_req = ecall_insn_i | ebrk_insn_i | illegal_insn | instr_fetch_err_i;
+ // requests are flopped in exc_req_q. This is cleared when controller is in
+ // the FLUSH state so the cycle following exc_req_q won't remain set for an
+ // exception request that has just been handled.
+ assign exc_req_d = (ecall_insn | ebrk_insn | illegal_insn_d | instr_fetch_err) &
+ (ctrl_fsm_cs != FLUSH);
// LSU exception requests
assign exc_req_lsu = store_err_i | load_err_i;
// special requests: special instructions, pipeline flushes, exceptions...
- assign special_req = mret_insn_i | dret_insn_i | wfi_insn_i | csr_pipe_flush_i |
- exc_req | exc_req_lsu;
+ assign special_req = mret_insn | dret_insn | wfi_insn | csr_pipe_flush |
+ exc_req_d | exc_req_lsu;
////////////////
// Interrupts //
@@ -210,7 +244,7 @@
first_fetch_o = 1'b0;
halt_if = 1'b0;
- halt_id = 1'b0;
+ flush_id = 1'b0;
debug_csr_save_o = 1'b0;
debug_cause_o = DBG_CAUSE_EBREAK;
@@ -244,7 +278,7 @@
ctrl_busy_o = 1'b0;
instr_req_o = 1'b0;
halt_if = 1'b1;
- halt_id = 1'b1;
+ flush_id = 1'b1;
ctrl_fsm_ns = SLEEP;
end
@@ -254,7 +288,7 @@
ctrl_busy_o = 1'b0;
instr_req_o = 1'b0;
halt_if = 1'b1;
- halt_id = 1'b1;
+ flush_id = 1'b1;
// normal execution flow
// in debug mode or single step mode we leave immediately (wfi=nop)
@@ -276,14 +310,14 @@
// going to sleep.
ctrl_fsm_ns = IRQ_TAKEN;
halt_if = 1'b1;
- halt_id = 1'b1;
+ flush_id = 1'b1;
end
// enter debug mode
if (enter_debug_mode) begin
ctrl_fsm_ns = DBG_TAKEN_IF;
halt_if = 1'b1;
- halt_id = 1'b1;
+ flush_id = 1'b1;
end
end
@@ -296,21 +330,23 @@
if (instr_valid_i) begin
+ // get ready for special instructions, exceptions, pipeline flushes
+ if (special_req) begin
+ // Halt IF but don't flush ID. This leaves a valid instruction in
+ // ID so controller can determine appropriate action in the
+ // FLUSH state.
+ ctrl_fsm_ns = FLUSH;
+ halt_if = 1'b1;
// set PC in IF stage to branch or jump target
- if (branch_set_i || jump_set_i) begin
+ end else if (branch_set_i || jump_set_i) begin
pc_mux_o = PC_JUMP;
pc_set_o = 1'b1;
perf_tbranch_o = branch_set_i;
perf_jump_o = jump_set_i;
-
- // get ready for special instructions, exceptions, pipeline flushes
- end else if (special_req) begin
- ctrl_fsm_ns = FLUSH;
- halt_if = 1'b1;
- halt_id = 1'b1;
end
+
// stall IF stage to not starve debug and interrupt requests, these just
// need to wait until after the current (multicycle) instruction
if ((enter_debug_mode || handle_irq) && stall) begin
@@ -334,13 +370,13 @@
// enter debug mode
ctrl_fsm_ns = DBG_TAKEN_IF;
halt_if = 1'b1;
- halt_id = 1'b1;
+ flush_id = 1'b1;
end else if (handle_irq) begin
// handle interrupt (not in debug mode)
ctrl_fsm_ns = IRQ_TAKEN;
halt_if = 1'b1;
- halt_id = 1'b1;
+ flush_id = 1'b1;
end
end
@@ -410,7 +446,7 @@
//
// for 1. do not update dcsr and dpc, for 2. do so [Debug Spec v0.13.2, p.39]
// jump to debug exception handler in debug memory
- if (ebrk_insn_i) begin
+ if (ebrk_insn) begin
pc_mux_o = PC_EXC;
pc_set_o = 1'b1;
exc_pc_mux_o = EXC_PC_DBD;
@@ -437,12 +473,12 @@
FLUSH: begin
// flush the pipeline
halt_if = 1'b1;
- halt_id = 1'b1;
+ flush_id = 1'b1;
ctrl_fsm_ns = DECODE;
// exceptions: set exception PC, save PC and exception cause
// exc_req_lsu is high for one clock cycle only (in DECODE)
- if (exc_req || store_err_q || load_err_q) begin
+ if (exc_req_q || store_err_q || load_err_q) begin
pc_set_o = 1'b1;
pc_mux_o = PC_EXC;
exc_pc_mux_o = debug_mode_q ? EXC_PC_DBG_EXC : EXC_PC_EXC;
@@ -450,18 +486,19 @@
csr_save_cause_o = 1'b1;
// set exception registers, priorities according to Table 3.7 of Privileged Spec v1.11
- if (instr_fetch_err_i) begin
+ if (instr_fetch_err) begin
exc_cause_o = EXC_CAUSE_INSTR_ACCESS_FAULT;
csr_mtval_o = pc_id_i;
- end else if (illegal_insn) begin
+ end else if (illegal_insn_q) begin
exc_cause_o = EXC_CAUSE_ILLEGAL_INSN;
csr_mtval_o = instr_is_compressed_i ? {16'b0, instr_compressed_i} : instr_i;
- end else if (ecall_insn_i) begin
- exc_cause_o = EXC_CAUSE_ECALL_MMODE;
+ end else if (ecall_insn) begin
+ exc_cause_o = (priv_mode_i == PRIV_LVL_M) ? EXC_CAUSE_ECALL_MMODE :
+ EXC_CAUSE_ECALL_UMODE;
- end else if (ebrk_insn_i) begin
+ end else if (ebrk_insn) begin
if (debug_mode_q) begin
/*
* EBREAK in debug mode re-enters debug mode
@@ -508,24 +545,24 @@
end else begin
// special instructions and pipeline flushes
- if (mret_insn_i) begin
+ if (mret_insn) begin
pc_mux_o = PC_ERET;
pc_set_o = 1'b1;
csr_restore_mret_id_o = 1'b1;
if (nmi_mode_q) begin
nmi_mode_d = 1'b0; // exit NMI mode
end
- end else if (dret_insn_i) begin
+ end else if (dret_insn) begin
pc_mux_o = PC_DRET;
pc_set_o = 1'b1;
debug_mode_d = 1'b0;
- end else if (wfi_insn_i) begin
+ end else if (wfi_insn) begin
ctrl_fsm_ns = WAIT_SLEEP;
- end else if (csr_pipe_flush_i && handle_irq) begin
+ end else if (csr_pipe_flush && handle_irq) begin
// start handling IRQs when doing CSR-related pipeline flushes
ctrl_fsm_ns = IRQ_TAKEN;
end
- end // exc_req
+ end // exc_req_q
// single stepping
// set exception registers, but do not jump into handler [Debug Spec v0.13.2, p.44]
@@ -559,22 +596,29 @@
// kill instr in IF-ID pipeline reg that are done, or if a
// multicycle instr causes an exception for example
- assign instr_valid_clear_o = ~stall | halt_id;
+ // halt_if is another kind of stall, where the instr_valid bit must remain
+ // set (unless flush_id is set also). It cannot be factored directly into
+ // stall as this causes a combinational loop.
+ assign instr_valid_clear_o = ~(stall | halt_if) | flush_id;
// update registers
always_ff @(posedge clk_i or negedge rst_ni) begin : update_regs
if (!rst_ni) begin
- ctrl_fsm_cs <= RESET;
- nmi_mode_q <= 1'b0;
- debug_mode_q <= 1'b0;
- load_err_q <= 1'b0;
- store_err_q <= 1'b0;
+ ctrl_fsm_cs <= RESET;
+ nmi_mode_q <= 1'b0;
+ debug_mode_q <= 1'b0;
+ load_err_q <= 1'b0;
+ store_err_q <= 1'b0;
+ exc_req_q <= 1'b0;
+ illegal_insn_q <= 1'b0;
end else begin
- ctrl_fsm_cs <= ctrl_fsm_ns;
- nmi_mode_q <= nmi_mode_d;
- debug_mode_q <= debug_mode_d;
- load_err_q <= load_err_d;
- store_err_q <= store_err_d;
+ ctrl_fsm_cs <= ctrl_fsm_ns;
+ nmi_mode_q <= nmi_mode_d;
+ debug_mode_q <= debug_mode_d;
+ load_err_q <= load_err_d;
+ store_err_q <= store_err_d;
+ exc_req_q <= exc_req_d;
+ illegal_insn_q <= illegal_insn_d;
end
end
diff --git a/hw/vendor/lowrisc_ibex/rtl/ibex_core.sv b/hw/vendor/lowrisc_ibex/rtl/ibex_core.sv
index 4f5bafd..303f533 100644
--- a/hw/vendor/lowrisc_ibex/rtl/ibex_core.sv
+++ b/hw/vendor/lowrisc_ibex/rtl/ibex_core.sv
@@ -11,13 +11,13 @@
* Top level module of the ibex RISC-V core
*/
module ibex_core #(
- parameter bit PMPEnable = 0,
+ parameter bit PMPEnable = 1'b0,
parameter int unsigned PMPGranularity = 0,
parameter int unsigned PMPNumRegions = 4,
parameter int unsigned MHPMCounterNum = 0,
parameter int unsigned MHPMCounterWidth = 40,
- parameter bit RV32E = 0,
- parameter bit RV32M = 1,
+ parameter bit RV32E = 1'b0,
+ parameter bit RV32M = 1'b1,
parameter int unsigned DmHaltAddr = 32'h1A110800,
parameter int unsigned DmExceptionAddr = 32'h1A110808
) (
@@ -147,6 +147,7 @@
// CSR control
logic csr_access;
+ logic valid_csr_id;
csr_op_e csr_op;
csr_num_e csr_addr;
logic [31:0] csr_rdata;
@@ -195,7 +196,10 @@
logic csr_mtvec_init;
logic [31:0] csr_mtvec;
logic [31:0] csr_mtval;
- priv_lvl_e priv_mode;
+ logic csr_mstatus_tw;
+ priv_lvl_e priv_mode_id;
+ priv_lvl_e priv_mode_if;
+ priv_lvl_e priv_mode_lsu;
// debug mode and dcsr configuration
logic debug_mode;
@@ -411,6 +415,8 @@
.csr_restore_mret_id_o ( csr_restore_mret_id ), // restore mstatus upon MRET
.csr_save_cause_o ( csr_save_cause ),
.csr_mtval_o ( csr_mtval ),
+ .priv_mode_i ( priv_mode_id ),
+ .csr_mstatus_tw_i ( csr_mstatus_tw ),
.illegal_csr_insn_i ( illegal_csr_insn_id ),
// LSU
@@ -554,9 +560,13 @@
assign perf_load = data_req_o & data_gnt_i & (~data_we_o);
assign perf_store = data_req_o & data_gnt_i & data_we_o;
+ // CSR access is qualified by instruction fetch error
+ assign valid_csr_id = instr_new_id & ~instr_fetch_err;
+
ibex_cs_registers #(
.MHPMCounterNum ( MHPMCounterNum ),
.MHPMCounterWidth ( MHPMCounterWidth ),
+ .PMPEnable ( PMPEnable ),
.PMPGranularity ( PMPGranularity ),
.PMPNumRegions ( PMPNumRegions ),
.RV32E ( RV32E ),
@@ -567,7 +577,9 @@
// Hart ID from outside
.hart_id_i ( hart_id_i ),
- .priv_mode_o ( priv_mode ),
+ .priv_mode_id_o ( priv_mode_id ),
+ .priv_mode_if_o ( priv_mode_if ),
+ .priv_mode_lsu_o ( priv_mode_lsu ),
// mtvec
.csr_mtvec_o ( csr_mtvec ),
@@ -592,6 +604,7 @@
.csr_meip_o ( csr_meip ),
.csr_mfip_o ( csr_mfip ),
.csr_mstatus_mie_o ( csr_mstatus_mie ),
+ .csr_mstatus_tw_o ( csr_mstatus_tw ),
.csr_mepc_o ( csr_mepc ),
// PMP
@@ -617,7 +630,7 @@
.csr_mtval_i ( csr_mtval ),
.illegal_csr_insn_o ( illegal_csr_insn_id ),
- .instr_new_id_i ( instr_new_id ),
+ .instr_new_id_i ( valid_csr_id ),
// performance counter related signals
.instr_ret_i ( instr_ret ),
@@ -635,11 +648,14 @@
if (PMPEnable) begin : g_pmp
logic [33:0] pmp_req_addr [PMP_NUM_CHAN];
pmp_req_e pmp_req_type [PMP_NUM_CHAN];
+ priv_lvl_e pmp_priv_lvl [PMP_NUM_CHAN];
assign pmp_req_addr[PMP_I] = {2'b00,instr_addr_o[31:0]};
assign pmp_req_type[PMP_I] = PMP_ACC_EXEC;
+ assign pmp_priv_lvl[PMP_I] = priv_mode_if;
assign pmp_req_addr[PMP_D] = {2'b00,data_addr_o[31:0]};
assign pmp_req_type[PMP_D] = data_we_o ? PMP_ACC_WRITE : PMP_ACC_READ;
+ assign pmp_priv_lvl[PMP_D] = priv_mode_lsu;
ibex_pmp #(
.PMPGranularity ( PMPGranularity ),
@@ -651,13 +667,18 @@
// Interface to CSRs
.csr_pmp_cfg_i ( csr_pmp_cfg ),
.csr_pmp_addr_i ( csr_pmp_addr ),
- .priv_mode_i ( priv_mode ),
+ .priv_mode_i ( pmp_priv_lvl ),
// Access checking channels
.pmp_req_addr_i ( pmp_req_addr ),
.pmp_req_type_i ( pmp_req_type ),
.pmp_req_err_o ( pmp_req_err )
);
end else begin : g_no_pmp
+ // Unused signal tieoff
+ priv_lvl_e unused_priv_lvl_if, unused_priv_lvl_ls;
+ assign unused_priv_lvl_if = priv_mode_if;
+ assign unused_priv_lvl_ls = priv_mode_lsu;
+ // Output tieoff
assign pmp_req_err[PMP_I] = 1'b0;
assign pmp_req_err[PMP_D] = 1'b0;
end
@@ -670,7 +691,7 @@
rvfi_intr <= '0;
rvfi_order <= '0;
rvfi_insn <= '0;
- rvfi_mode <= '0;
+ rvfi_mode <= {PRIV_LVL_M};
rvfi_rs1_addr <= '0;
rvfi_rs2_addr <= '0;
rvfi_pc_rdata <= '0;
@@ -689,9 +710,9 @@
rvfi_halt <= '0;
rvfi_trap <= illegal_insn_id;
rvfi_intr <= rvfi_intr_d;
- rvfi_order <= rvfi_order + rvfi_valid;
+ rvfi_order <= rvfi_order + 64'(rvfi_valid);
rvfi_insn <= rvfi_insn_id;
- rvfi_mode <= PRIV_LVL_M; // TODO: Update for user mode support
+ rvfi_mode <= {priv_mode_id};
rvfi_rs1_addr <= rvfi_rs1_addr_id;
rvfi_rs2_addr <= rvfi_rs2_addr_id;
rvfi_pc_rdata <= pc_id;
@@ -779,7 +800,7 @@
rvfi_rd_wdata_d = '0;
end else begin
rvfi_rd_addr_d = rvfi_rd_addr_id;
- if (!rvfi_rd_addr_id) begin
+ if (rvfi_rd_addr_id == 5'h0) begin
rvfi_rd_wdata_d = '0;
end else begin
rvfi_rd_wdata_d = rvfi_rd_wdata_id;
diff --git a/hw/vendor/lowrisc_ibex/rtl/ibex_core_tracing.sv b/hw/vendor/lowrisc_ibex/rtl/ibex_core_tracing.sv
index 7331923..bd87ef0 100644
--- a/hw/vendor/lowrisc_ibex/rtl/ibex_core_tracing.sv
+++ b/hw/vendor/lowrisc_ibex/rtl/ibex_core_tracing.sv
@@ -7,10 +7,13 @@
* Top level module of the ibex RISC-V core with tracing enabled
*/
module ibex_core_tracing #(
+ parameter bit PMPEnable = 1'b0,
+ parameter int unsigned PMPGranularity = 0,
+ parameter int unsigned PMPNumRegions = 4,
parameter int unsigned MHPMCounterNum = 8,
parameter int unsigned MHPMCounterWidth = 40,
- parameter bit RV32E = 0,
- parameter bit RV32M = 1,
+ parameter bit RV32E = 1'b0,
+ parameter bit RV32M = 1'b1,
parameter int unsigned DmHaltAddr = 32'h1A110800,
parameter int unsigned DmExceptionAddr = 32'h1A110808
) (
@@ -62,7 +65,7 @@
// ibex_tracer relies on the signals from the RISC-V Formal Interface
`ifndef RVFI
- Fatal error: RVFI needs to be defined globally.
+ $fatal("Fatal error: RVFI needs to be defined globally.");
`endif
logic rvfi_valid;
@@ -87,6 +90,9 @@
logic [31:0] rvfi_mem_wdata;
ibex_core #(
+ .PMPEnable(PMPEnable),
+ .PMPGranularity(PMPGranularity),
+ .PMPNumRegions(PMPNumRegions),
.MHPMCounterNum(MHPMCounterNum),
.MHPMCounterWidth(MHPMCounterWidth),
.RV32E(RV32E),
@@ -152,28 +158,33 @@
.core_sleep_o
);
+ ibex_tracer
+ u_ibex_tracer (
+ .clk_i,
+ .rst_ni,
-`ifndef VERILATOR
- ibex_tracer u_ibex_tracer (
- .clk_i ( clk_i ),
- .rst_ni ( rst_ni ),
+ .hart_id_i,
- .fetch_enable_i ( fetch_enable_i ),
- .hart_id_i ( hart_id_i ),
-
- .valid_i ( rvfi_valid ),
- .pc_i ( rvfi_pc_rdata ),
- .instr_i ( rvfi_insn ),
- .rs1_value_i ( rvfi_rs1_rdata ),
- .rs2_value_i ( rvfi_rs2_rdata ),
- .ex_reg_addr_i ( rvfi_rd_addr ),
- .ex_reg_wdata_i ( rvfi_rd_wdata ),
- .ex_data_addr_i ( rvfi_mem_addr ),
- .ex_data_wdata_i ( rvfi_mem_wdata ),
- .ex_data_rdata_i ( rvfi_mem_rdata )
+ .rvfi_valid,
+ .rvfi_order,
+ .rvfi_insn,
+ .rvfi_trap,
+ .rvfi_halt,
+ .rvfi_intr,
+ .rvfi_mode,
+ .rvfi_rs1_addr,
+ .rvfi_rs2_addr,
+ .rvfi_rs1_rdata,
+ .rvfi_rs2_rdata,
+ .rvfi_rd_addr,
+ .rvfi_rd_wdata,
+ .rvfi_pc_rdata,
+ .rvfi_pc_wdata,
+ .rvfi_mem_addr,
+ .rvfi_mem_rmask,
+ .rvfi_mem_wmask,
+ .rvfi_mem_rdata,
+ .rvfi_mem_wdata
);
-`else
- // ibex_tracer uses language constructs which Verilator doesn't understand.
-`endif
endmodule
diff --git a/hw/vendor/lowrisc_ibex/rtl/ibex_cs_registers.sv b/hw/vendor/lowrisc_ibex/rtl/ibex_cs_registers.sv
index d7763df..61e6690 100644
--- a/hw/vendor/lowrisc_ibex/rtl/ibex_cs_registers.sv
+++ b/hw/vendor/lowrisc_ibex/rtl/ibex_cs_registers.sv
@@ -24,7 +24,12 @@
// Hart ID
input logic [31:0] hart_id_i,
- output ibex_pkg::priv_lvl_e priv_mode_o,
+
+ // Privilege mode
+ output ibex_pkg::priv_lvl_e priv_mode_id_o,
+ output ibex_pkg::priv_lvl_e priv_mode_if_o,
+ output ibex_pkg::priv_lvl_e priv_mode_lsu_o,
+ output logic csr_mstatus_tw_o,
// mtvec
output logic [31:0] csr_mtvec_o,
@@ -112,8 +117,15 @@
logic mie;
logic mpie;
priv_lvl_e mpp;
+ logic mprv;
+ logic tw;
} Status_t;
+ typedef struct packed {
+ logic mpie;
+ priv_lvl_e mpp;
+ } StatusStk_t;
+
// struct for mip/mie CSRs
typedef struct packed {
logic irq_software;
@@ -145,6 +157,7 @@
logic [31:0] exception_pc;
// CSRs
+ priv_lvl_e priv_lvl_q, priv_lvl_d;
Status_t mstatus_q, mstatus_d;
Interrupts_t mie_q, mie_d;
logic [31:0] mscratch_q, mscratch_d;
@@ -160,7 +173,7 @@
// CSRs for recoverable NMIs
// NOTE: these CSRS are nonstandard, see https://github.com/riscv/riscv-isa-manual/issues/261
- Status_t mstack_q, mstack_d;
+ StatusStk_t mstack_q, mstack_d;
logic [31:0] mstack_epc_q, mstack_epc_d;
logic [5:0] mstack_cause_q, mstack_cause_d;
@@ -204,11 +217,12 @@
assign csr_addr = {csr_addr_i};
assign mhpmcounter_idx = csr_addr[4:0];
- assign illegal_csr_priv = 1'b0; // we only support M-mode
+ // See RISC-V Privileged Specification, version 1.11, Section 2.1
+ assign illegal_csr_priv = (csr_addr[9:8] > {priv_lvl_q});
assign illegal_csr_write = (csr_addr[11:10] == 2'b11) && csr_wreq;
- assign illegal_csr_insn_o = illegal_csr | illegal_csr_write | illegal_csr_priv;
+ assign illegal_csr_insn_o = csr_access_i & (illegal_csr | illegal_csr_write | illegal_csr_priv);
- // mip CSR is purely combintational - must be able to re-enable the clock upon WFI
+ // mip CSR is purely combinational - must be able to re-enable the clock upon WFI
assign mip.irq_software = irq_software_i & mie_q.irq_software;
assign mip.irq_timer = irq_timer_i & mie_q.irq_timer;
assign mip.irq_external = irq_external_i & mie_q.irq_external;
@@ -229,6 +243,7 @@
csr_rdata_int[CSR_MSTATUS_MIE_BIT] = mstatus_q.mie;
csr_rdata_int[CSR_MSTATUS_MPIE_BIT] = mstatus_q.mpie;
csr_rdata_int[CSR_MSTATUS_MPP_BIT_HIGH:CSR_MSTATUS_MPP_BIT_LOW] = mstatus_q.mpp;
+ csr_rdata_int[CSR_MSTATUS_MPRV_BIT] = mstatus_q.mprv;
end
// misa
@@ -323,7 +338,7 @@
if ((csr_addr[4:0] == 5'b00000) || // CSR_MCOUNTINHIBIT
(csr_addr[4:0] == 5'b00001) ||
(csr_addr[4:0] == 5'b00010)) begin
- illegal_csr = csr_access_i;
+ illegal_csr = 1'b1;
end
end else if ((csr_addr & CSR_MASK_MCOUNTER) == CSR_OFF_MCOUNTER) begin
@@ -332,7 +347,7 @@
if ((csr_addr[4:0] == 5'b00000) || // CSR_MCYCLE
(csr_addr[4:0] == 5'b00001) ||
(csr_addr[4:0] == 5'b00010)) begin // CSR_MINSTRET
- illegal_csr = csr_access_i;
+ illegal_csr = 1'b1;
end
end else if ((csr_addr & CSR_MASK_MCOUNTER) == CSR_OFF_MCOUNTERH) begin
@@ -341,10 +356,10 @@
if ((csr_addr[4:0] == 5'b00000) || // CSR_MCYCLEH
(csr_addr[4:0] == 5'b00001) ||
(csr_addr[4:0] == 5'b00010)) begin // CSR_MINSTRETH
- illegal_csr = csr_access_i;
+ illegal_csr = 1'b1;
end
end else begin
- illegal_csr = csr_access_i;
+ illegal_csr = 1'b1;
end
end
endcase
@@ -354,6 +369,7 @@
always_comb begin
exception_pc = pc_id_i;
+ priv_lvl_d = priv_lvl_q;
mstatus_d = mstatus_q;
mie_d = mie_q;
mscratch_d = mscratch_q;
@@ -374,49 +390,54 @@
mhpmcounter_we = '0;
mhpmcounterh_we = '0;
- unique case (csr_addr_i)
- // mstatus: IE bit
- CSR_MSTATUS: begin
- if (csr_we_int) begin
+ if (csr_we_int) begin
+ unique case (csr_addr_i)
+ // mstatus: IE bit
+ CSR_MSTATUS: begin
mstatus_d = '{
mie: csr_wdata_int[CSR_MSTATUS_MIE_BIT],
mpie: csr_wdata_int[CSR_MSTATUS_MPIE_BIT],
- mpp: PRIV_LVL_M
+ mpp: priv_lvl_e'(csr_wdata_int[CSR_MSTATUS_MPP_BIT_HIGH:CSR_MSTATUS_MPP_BIT_LOW]),
+ mprv: csr_wdata_int[CSR_MSTATUS_MPRV_BIT],
+ tw: csr_wdata_int[CSR_MSTATUS_TW_BIT]
};
+ // Convert illegal values to M-mode
+ if ((mstatus_d.mpp != PRIV_LVL_M) && (mstatus_d.mpp != PRIV_LVL_U)) begin
+ mstatus_d.mpp = PRIV_LVL_M;
+ end
end
- end
- // interrupt enable
- CSR_MIE: begin
- if (csr_we_int) begin
+ // interrupt enable
+ CSR_MIE: begin
mie_d.irq_software = csr_wdata_int[CSR_MSIX_BIT];
mie_d.irq_timer = csr_wdata_int[CSR_MTIX_BIT];
mie_d.irq_external = csr_wdata_int[CSR_MEIX_BIT];
mie_d.irq_fast = csr_wdata_int[CSR_MFIX_BIT_HIGH:CSR_MFIX_BIT_LOW];
end
- end
- CSR_MSCRATCH: if (csr_we_int) mscratch_d = csr_wdata_int;
+ CSR_MSCRATCH: mscratch_d = csr_wdata_int;
- // mepc: exception program counter
- CSR_MEPC: if (csr_we_int) mepc_d = {csr_wdata_int[31:1], 1'b0};
+ // mepc: exception program counter
+ CSR_MEPC: mepc_d = {csr_wdata_int[31:1], 1'b0};
- // mcause
- CSR_MCAUSE: if (csr_we_int) mcause_d = {csr_wdata_int[31], csr_wdata_int[4:0]};
+ // mcause
+ CSR_MCAUSE: mcause_d = {csr_wdata_int[31], csr_wdata_int[4:0]};
- // mtval: trap value
- CSR_MTVAL: if (csr_we_int) mtval_d = csr_wdata_int;
+ // mtval: trap value
+ CSR_MTVAL: mtval_d = csr_wdata_int;
- // mtvec
- // mtvec.MODE set to vectored
- // mtvec.BASE must be 256-byte aligned
- CSR_MTVEC: if (csr_we_int) mtvec_d = {csr_wdata_int[31:8], 6'b0, 2'b01};
+ // mtvec
+ // mtvec.MODE set to vectored
+ // mtvec.BASE must be 256-byte aligned
+ CSR_MTVEC: mtvec_d = {csr_wdata_int[31:8], 6'b0, 2'b01};
- CSR_DCSR: begin
- if (csr_we_int) begin
+ CSR_DCSR: begin
dcsr_d = csr_wdata_int;
dcsr_d.xdebugver = XDEBUGVER_STD;
- dcsr_d.prv = PRIV_LVL_M; // only M-mode is supported
+ // Change to PRIV_LVL_M if sofware writes an unsupported value
+ if ((dcsr_d.prv != PRIV_LVL_M) && (dcsr_d.prv != PRIV_LVL_U)) begin
+ dcsr_d.prv = PRIV_LVL_M;
+ end
// currently not supported:
dcsr_d.nmip = 1'b0;
@@ -429,59 +450,24 @@
dcsr_d.zero1 = 1'b0;
dcsr_d.zero2 = 12'h0;
end
- end
- CSR_DPC: begin
- // Only valid PC addresses are allowed (half-word aligned with C ext.)
- if (csr_we_int && csr_wdata_int[0] == 1'b0) begin
- depc_d = csr_wdata_int;
+ CSR_DPC: begin
+ // Only valid PC addresses are allowed (half-word aligned with C ext.)
+ if (csr_wdata_int[0] == 1'b0) begin
+ depc_d = csr_wdata_int;
+ end
end
- end
- CSR_DSCRATCH0: begin
- if (csr_we_int) begin
- dscratch0_d = csr_wdata_int;
- end
- end
+ CSR_DSCRATCH0: dscratch0_d = csr_wdata_int;
+ CSR_DSCRATCH1: dscratch1_d = csr_wdata_int;
- CSR_DSCRATCH1: begin
- if (csr_we_int) begin
- dscratch1_d = csr_wdata_int;
- end
- end
+ CSR_MCOUNTINHIBIT: mcountinhibit_we = 1'b1;
+ CSR_MCYCLE: mhpmcounter_we[0] = 1'b1;
+ CSR_MCYCLEH: mhpmcounterh_we[0] = 1'b1;
+ CSR_MINSTRET: mhpmcounter_we[2] = 1'b1;
+ CSR_MINSTRETH: mhpmcounterh_we[2] = 1'b1;
- CSR_MCOUNTINHIBIT: begin
- if (csr_we_int) begin
- mcountinhibit_we = 1'b1;
- end
- end
-
- CSR_MCYCLE: begin
- if (csr_we_int) begin
- mhpmcounter_we[0] = 1'b1;
- end
- end
-
- CSR_MCYCLEH: begin
- if (csr_we_int) begin
- mhpmcounterh_we[0] = 1'b1;
- end
- end
-
- CSR_MINSTRET: begin
- if (csr_we_int) begin
- mhpmcounter_we[2] = 1'b1;
- end
- end
-
- CSR_MINSTRETH: begin
- if (csr_we_int) begin
- mhpmcounterh_we[2] = 1'b1;
- end
- end
-
- default: begin
- if (csr_we_int == 1'b1) begin
+ default: begin
// performance counters and event selector
if ((csr_addr & CSR_MASK_MCOUNTER) == CSR_OFF_MCOUNTER) begin
mhpmcounter_we[mhpmcounter_idx] = 1'b1;
@@ -489,8 +475,8 @@
mhpmcounterh_we[mhpmcounter_idx] = 1'b1;
end
end
- end
- endcase
+ endcase
+ end
// exception controller gets priority over other writes
unique case (1'b1)
@@ -509,15 +495,16 @@
if (debug_csr_save_i) begin
// all interrupts are masked
// do not update cause, epc, tval, epc and status
- dcsr_d.prv = PRIV_LVL_M;
+ dcsr_d.prv = priv_lvl_q;
dcsr_d.cause = debug_cause_i;
depc_d = exception_pc;
end else begin
+ priv_lvl_d = PRIV_LVL_M;
mtval_d = csr_mtval_i;
mstatus_d.mie = 1'b0; // disable interrupts
// save current status
mstatus_d.mpie = mstatus_q.mie;
- mstatus_d.mpp = PRIV_LVL_M;
+ mstatus_d.mpp = priv_lvl_q;
mepc_d = exception_pc;
mcause_d = {csr_mcause_i};
// save previous status for recoverable NMI
@@ -529,12 +516,15 @@
end // csr_save_cause_i
csr_restore_mret_i: begin // MRET
+ priv_lvl_d = mstatus_q.mpp;
mstatus_d.mie = mstatus_q.mpie; // re-enable interrupts
// restore previous status for recoverable NMI
mstatus_d.mpie = mstack_q.mpie;
mstatus_d.mpp = mstack_q.mpp;
mepc_d = mstack_epc_q;
mcause_d = mstack_cause_q;
+ mstack_d.mpie = 1'b1;
+ mstack_d.mpp = PRIV_LVL_U;
end // csr_restore_mret_i
default:;
@@ -576,6 +566,7 @@
assign csr_mtvec_o = mtvec_q;
assign csr_mstatus_mie_o = mstatus_q.mie;
+ assign csr_mstatus_tw_o = mstatus_q.tw;
assign debug_single_step_o = dcsr_q.step;
assign debug_ebreakm_o = dcsr_q.ebreakm;
@@ -584,10 +575,13 @@
// actual registers
always_ff @(posedge clk_i or negedge rst_ni) begin
if (!rst_ni) begin
+ priv_lvl_q <= PRIV_LVL_M;
mstatus_q <= '{
mie: 1'b0,
- mpie: 1'b0,
- mpp: PRIV_LVL_M
+ mpie: 1'b1,
+ mpp: PRIV_LVL_U,
+ mprv: 1'b0,
+ tw: 1'b0
};
mie_q <= '0;
mscratch_q <= '0;
@@ -606,15 +600,15 @@
dscratch1_q <= '0;
mstack_q <= '{
- mie: 1'b0,
- mpie: 1'b0,
- mpp: PRIV_LVL_M
+ mpie: 1'b1,
+ mpp: PRIV_LVL_U
};
mstack_epc_q <= '0;
mstack_cause_q <= '0;
end else begin
// update CSRs
+ priv_lvl_q <= priv_lvl_d;
mstatus_q <= mstatus_d;
mie_q <= mie_d;
mscratch_q <= mscratch_d;
@@ -634,7 +628,12 @@
end
end
- assign priv_mode_o = mstatus_q.mpp;
+ // Send current priv level to the decoder
+ assign priv_mode_id_o = priv_lvl_q;
+ // New instruction fetches need to account for updates to priv_lvl_q this cycle
+ assign priv_mode_if_o = priv_lvl_d;
+ // Load/store instructions must factor in MPRV for PMP checking
+ assign priv_mode_lsu_o = mstatus_q.mprv ? mstatus_q.mpp : priv_lvl_q;
// -----------------
// PMP registers
diff --git a/hw/vendor/lowrisc_ibex/rtl/ibex_fetch_fifo.sv b/hw/vendor/lowrisc_ibex/rtl/ibex_fetch_fifo.sv
index 6d4fba9..e2e5639 100644
--- a/hw/vendor/lowrisc_ibex/rtl/ibex_fetch_fifo.sv
+++ b/hw/vendor/lowrisc_ibex/rtl/ibex_fetch_fifo.sv
@@ -9,7 +9,9 @@
* input port: send address and data to the FIFO
* clear_i clears the FIFO for the following cycle, including any new request
*/
-module ibex_fetch_fifo (
+module ibex_fetch_fifo #(
+ parameter int unsigned NUM_REQS = 2
+) (
input logic clk_i,
input logic rst_ni,
@@ -31,10 +33,9 @@
output logic out_err_o
);
- localparam int unsigned DEPTH = 3; // must be 3 or greater
+ localparam int unsigned DEPTH = NUM_REQS+1;
// index 0 is used for output
- logic [DEPTH-1:0] [31:2] addr_d, addr_q;
logic [DEPTH-1:0] [31:0] rdata_d, rdata_q;
logic [DEPTH-1:0] err_d, err_q;
logic [DEPTH-1:0] valid_d, valid_q;
@@ -47,9 +48,11 @@
logic err, err_unaligned;
logic valid, valid_unaligned;
- logic entry0_unaligned_d, entry0_unaligned_q;
logic aligned_is_compressed, unaligned_is_compressed;
-
+
+ logic addr_incr_two;
+ logic [31:1] instr_addr_d, instr_addr_q;
+ logic instr_addr_en;
logic unused_addr_in;
/////////////////
@@ -70,21 +73,6 @@
// The FIFO also has a direct bypass path, so a complete instruction might be made up of data
// from the FIFO and new incoming data.
//
- // Additionally, branches can cause a fetch from an unaligned address. The full data word will be
- // fetched, but the FIFO must output the unaligned instruction as the first valid data.
-
- // Alignment is tracked with a flag, this records whether entry[0] of the FIFO has become unaligned.
- // The flag is set once any compressed instruction enters the FIFO and is only cleared once a
- // a compressed instruction realigns the FIFO, or the FIFO is cleared.
-
- // New incoming unaligned request (must be a branch) or already unaligned
- assign entry0_unaligned_d = ((((in_valid_i & in_addr_i[1]) | entry0_unaligned_q) &
- // cleared by a compressed unaligned instruction
- ~(out_ready_i & unaligned_is_compressed)) |
- // Also set when a new aligned compressed instruction is driven
- (valid & out_ready_i & ~out_addr_o[1] & aligned_is_compressed)) &
- // reset by a FIFO clear
- ~clear_i;
// Construct the output data for an unaligned instruction
assign rdata_unaligned = valid_q[1] ? {rdata_q[1][15:0], rdata[31:16]} :
@@ -129,8 +117,29 @@
end
end
- assign out_addr_o[31:2] = valid_q[0] ? addr_q[0] : in_addr_i[31:2];
- assign out_addr_o[1] = valid_q[0] ? entry0_unaligned_q : in_addr_i[1];
+ /////////////////////////
+ // Instruction address //
+ /////////////////////////
+
+ // Update the address on branches and every time an instruction is driven
+ assign instr_addr_en = clear_i | (out_ready_i & out_valid_o);
+
+ // Increment the address by two every time a compressed instruction is popped
+ assign addr_incr_two = instr_addr_q[1] ? unaligned_is_compressed :
+ aligned_is_compressed;
+
+ assign instr_addr_d = clear_i ? in_addr_i[31:1] :
+ (instr_addr_q[31:1] +
+ // Increment address by 4 or 2
+ {29'd0,~addr_incr_two,addr_incr_two});
+
+ always_ff @(posedge clk_i) begin
+ if (instr_addr_en) begin
+ instr_addr_q <= instr_addr_d;
+ end
+ end
+
+ assign out_addr_o[31:1] = instr_addr_q[31:1];
assign out_addr_o[0] = 1'b0;
// The LSB of the address is unused, since all addresses are halfword aligned
@@ -140,10 +149,10 @@
// input port //
////////////////
- // we accept data as long as our FIFO is not full
- // we don't care about clear here as the data will be received one cycle
- // later anyway
- assign in_ready_o = ~valid_q[DEPTH-2];
+ // Accept data as long as our FIFO has space to accept the maximum number of outstanding
+ // requests. Note that the prefetch buffer does not count how many requests are actually
+ // outstanding, so space must be reserved for the maximum number.
+ assign in_ready_o = ~valid_q[DEPTH-NUM_REQS];
/////////////////////
// FIFO management //
@@ -157,7 +166,7 @@
if (i == 0) begin : g_ent0
assign lowest_free_entry[i] = ~valid_q[i];
end else begin : g_ent_others
- assign lowest_free_entry[i] = ~valid_q[i] & (&valid_q[i-1:0]);
+ assign lowest_free_entry[i] = ~valid_q[i] & valid_q[i-1];
end
// An entry is set when an incoming request chooses the lowest available entry
@@ -174,17 +183,15 @@
(in_valid_i & lowest_free_entry[i] & ~pop_fifo);
// take the next entry or the incoming data
- assign addr_d [i] = valid_q[i+1] ? addr_q [i+1] : in_addr_i[31:2];
assign rdata_d[i] = valid_q[i+1] ? rdata_q[i+1] : in_rdata_i;
assign err_d [i] = valid_q[i+1] ? err_q [i+1] : in_err_i;
end
// The top entry is similar but with simpler muxing
- assign lowest_free_entry[DEPTH-1] = ~valid_q[DEPTH-1] & (&valid_q[DEPTH-2:0]);
+ assign lowest_free_entry[DEPTH-1] = ~valid_q[DEPTH-1] & valid_q[DEPTH-2];
assign valid_pushed [DEPTH-1] = valid_q[DEPTH-1] | (in_valid_i & lowest_free_entry[DEPTH-1]);
assign valid_popped [DEPTH-1] = pop_fifo ? 1'b0 : valid_pushed[DEPTH-1];
assign valid_d [DEPTH-1] = valid_popped[DEPTH-1] & ~clear_i;
assign entry_en[DEPTH-1] = in_valid_i & lowest_free_entry[DEPTH-1];
- assign addr_d [DEPTH-1] = in_addr_i[31:2];
assign rdata_d [DEPTH-1] = in_rdata_i;
assign err_d [DEPTH-1] = in_err_i;
@@ -194,18 +201,15 @@
always_ff @(posedge clk_i or negedge rst_ni) begin
if (!rst_ni) begin
- valid_q <= '0;
- entry0_unaligned_q <= '0;
+ valid_q <= '0;
end else begin
- valid_q <= valid_d;
- entry0_unaligned_q <= entry0_unaligned_d;
+ valid_q <= valid_d;
end
end
for (genvar i = 0; i < DEPTH; i++) begin : g_fifo_regs
always_ff @(posedge clk_i) begin
if (entry_en[i]) begin
- addr_q[i] <= addr_d[i];
rdata_q[i] <= rdata_d[i];
err_q[i] <= err_d[i];
end
diff --git a/hw/vendor/lowrisc_ibex/rtl/ibex_id_stage.sv b/hw/vendor/lowrisc_ibex/rtl/ibex_id_stage.sv
index 45f2446..71b7a0c 100644
--- a/hw/vendor/lowrisc_ibex/rtl/ibex_id_stage.sv
+++ b/hw/vendor/lowrisc_ibex/rtl/ibex_id_stage.sv
@@ -75,6 +75,8 @@
output logic csr_restore_mret_id_o,
output logic csr_save_cause_o,
output logic [31:0] csr_mtval_o,
+ input ibex_pkg::priv_lvl_e priv_mode_i,
+ input logic csr_mstatus_tw_i,
input logic illegal_csr_insn_i,
// Interface to load store unit
@@ -376,7 +378,7 @@
// Controller //
////////////////
- assign illegal_insn_o = illegal_insn_dec | illegal_csr_insn_i;
+ assign illegal_insn_o = instr_valid_i & (illegal_insn_dec | illegal_csr_insn_i);
ibex_controller controller_i (
.clk_i ( clk_i ),
@@ -438,6 +440,8 @@
.csr_restore_mret_id_o ( csr_restore_mret_id_o ),
.csr_save_cause_o ( csr_save_cause_o ),
.csr_mtval_o ( csr_mtval_o ),
+ .priv_mode_i ( priv_mode_i ),
+ .csr_mstatus_tw_i ( csr_mstatus_tw_i ),
// Debug Signal
.debug_mode_o ( debug_mode_o ),
@@ -469,7 +473,9 @@
// being executed. This is the case if the current instr is either:
// - a new instr (not yet done)
// - a multicycle instr that is not yet done
- assign instr_executing = instr_new_i | (instr_multicycle & ~instr_multicycle_done_q);
+ // An instruction error will suppress any requests or register writes
+ assign instr_executing = (instr_new_i | (instr_multicycle & ~instr_multicycle_done_q)) &
+ ~instr_fetch_err_i;
assign data_req_id = instr_executing ? data_req_dec : 1'b0;
assign mult_en_id = instr_executing ? mult_en_dec : 1'b0;
assign div_en_id = instr_executing ? div_en_dec : 1'b0;
@@ -536,7 +542,7 @@
IDLE: begin
// only detect multicycle when instruction is new, do not re-detect after
// execution (when waiting for next instruction from IF stage)
- if (instr_new_i) begin
+ if (instr_new_i & ~instr_fetch_err_i) begin
unique case (1'b1)
data_req_dec: begin
// LSU operation
diff --git a/hw/vendor/lowrisc_ibex/rtl/ibex_pkg.sv b/hw/vendor/lowrisc_ibex/rtl/ibex_pkg.sv
index 8df2f46..de6c299 100644
--- a/hw/vendor/lowrisc_ibex/rtl/ibex_pkg.sv
+++ b/hw/vendor/lowrisc_ibex/rtl/ibex_pkg.sv
@@ -180,6 +180,7 @@
EXC_CAUSE_BREAKPOINT = {1'b0, 5'd03},
EXC_CAUSE_LOAD_ACCESS_FAULT = {1'b0, 5'd05},
EXC_CAUSE_STORE_ACCESS_FAULT = {1'b0, 5'd07},
+ EXC_CAUSE_ECALL_UMODE = {1'b0, 5'd08},
EXC_CAUSE_ECALL_MMODE = {1'b0, 5'd11}
} exc_cause_e;
@@ -293,6 +294,8 @@
parameter int unsigned CSR_MSTATUS_MPIE_BIT = 7;
parameter int unsigned CSR_MSTATUS_MPP_BIT_LOW = 11;
parameter int unsigned CSR_MSTATUS_MPP_BIT_HIGH = 12;
+parameter int unsigned CSR_MSTATUS_MPRV_BIT = 17;
+parameter int unsigned CSR_MSTATUS_TW_BIT = 21;
// CSR interrupt pending/enable bits
parameter int unsigned CSR_MSIX_BIT = 3;
diff --git a/hw/vendor/lowrisc_ibex/rtl/ibex_pmp.sv b/hw/vendor/lowrisc_ibex/rtl/ibex_pmp.sv
index e54edab..0fee9b5 100644
--- a/hw/vendor/lowrisc_ibex/rtl/ibex_pmp.sv
+++ b/hw/vendor/lowrisc_ibex/rtl/ibex_pmp.sv
@@ -19,8 +19,7 @@
input ibex_pkg::pmp_cfg_t csr_pmp_cfg_i [PMPNumRegions],
input logic [33:0] csr_pmp_addr_i [PMPNumRegions],
- input ibex_pkg::priv_lvl_e priv_mode_i, // Current priv mode, assumed to
- // be the same for all channels
+ input ibex_pkg::priv_lvl_e priv_mode_i [PMPNumChan],
// Access checking channels
input logic [33:0] pmp_req_addr_i [PMPNumChan],
input ibex_pkg::pmp_req_e pmp_req_type_i [PMPNumChan],
@@ -28,7 +27,7 @@
);
- import ibex_pkg::*;
+ import ibex_pkg::*;
// Access Checking Signals
logic [33:0] region_start_addr [PMPNumRegions];
@@ -36,7 +35,6 @@
logic [PMPNumChan-1:0][PMPNumRegions-1:0] region_match_high;
logic [PMPNumChan-1:0][PMPNumRegions-1:0] region_match_low;
logic [PMPNumChan-1:0][PMPNumRegions-1:0] region_match_both;
- logic [PMPNumChan-1:0][PMPNumRegions-1:0] region_match_partial;
logic [PMPNumChan-1:0][PMPNumRegions-1:0] region_perm_check;
logic [PMPNumChan-1:0][PMPNumRegions-1:0] machine_access_fault;
logic [PMPNumChan-1:0][PMPNumRegions-1:0] user_access_allowed;
@@ -81,12 +79,9 @@
(region_start_addr[r][33:PMPGranularity+2] &
region_addr_mask[r]));
assign region_match_high[c][r] = (pmp_req_addr_i[c][33:PMPGranularity+2] <=
- (csr_pmp_addr_i[r][33:PMPGranularity+2] &
- region_addr_mask[r]));
+ csr_pmp_addr_i[r][33:PMPGranularity+2]);
assign region_match_both[c][r] = region_match_low[c][r] & region_match_high[c][r] &
(csr_pmp_cfg_i[r].mode != PMP_MODE_OFF);
- assign region_match_partial[c][r] = (region_match_low[c][r] ^ region_match_high[c][r]) &
- (csr_pmp_cfg_i[r].mode != PMP_MODE_OFF);
// Check specific required permissions
assign region_perm_check[c][r] =
((pmp_req_type_i[c] == PMP_ACC_EXEC) & csr_pmp_cfg_i[r].exec) |
@@ -95,17 +90,11 @@
// In machine mode, any match to a locked region without sufficient permissions is a fault
assign machine_access_fault[c][r] = region_match_both[c][r] & csr_pmp_cfg_i[r].lock &
~region_perm_check[c][r];
- if (r == 0) begin : g_region0
- // In any other mode, any access should fault unless is matches a region
- assign user_access_allowed[c][r] = region_match_both[c][r] & region_perm_check[c][r];
- end else begin : g_oth_regions
- assign user_access_allowed[c][r] = region_match_both[c][r] & region_perm_check[c][r] &
- // any higher priority (lower region number) partial match should also cause a fault
- ~|region_match_partial[c][r-1:0];
- end
+ // In any other mode, any access should fault unless is matches a region
+ assign user_access_allowed[c][r] = region_match_both[c][r] & region_perm_check[c][r];
end
- assign access_fault[c] = (priv_mode_i == PRIV_LVL_M) ? |machine_access_fault[c] :
- ~|user_access_allowed[c];
+ assign access_fault[c] = (priv_mode_i[c] == PRIV_LVL_M) ? |machine_access_fault[c] :
+ ~|user_access_allowed[c];
assign pmp_req_err_o[c] = access_fault[c];
end
diff --git a/hw/vendor/lowrisc_ibex/rtl/ibex_prefetch_buffer.sv b/hw/vendor/lowrisc_ibex/rtl/ibex_prefetch_buffer.sv
index 6446661..605010a 100644
--- a/hw/vendor/lowrisc_ibex/rtl/ibex_prefetch_buffer.sv
+++ b/hw/vendor/lowrisc_ibex/rtl/ibex_prefetch_buffer.sv
@@ -39,20 +39,21 @@
output logic busy_o
);
- // Changes to the address flops would be required for > 2 outstanding requests
- localparam int unsigned NUM_REQS = 2;
+ localparam int unsigned NUM_REQS = 2;
- logic valid_req;
+ logic valid_new_req, valid_req;
logic valid_req_d, valid_req_q;
- logic hold_addr_d, hold_addr_q;
+ logic discard_req_d, discard_req_q;
logic gnt_or_pmp_err, rvalid_or_pmp_err;
logic [NUM_REQS-1:0] rdata_outstanding_n, rdata_outstanding_s, rdata_outstanding_q;
- logic [NUM_REQS-1:0] branch_abort_n, branch_abort_s, branch_abort_q;
+ logic [NUM_REQS-1:0] branch_discard_n, branch_discard_s, branch_discard_q;
+ logic [NUM_REQS-1:0] rdata_pmp_err_n, rdata_pmp_err_s, rdata_pmp_err_q;
- logic [31:0] instr_addr_q, fetch_addr;
+ logic [31:0] stored_addr_d, stored_addr_q;
+ logic stored_addr_en;
+ logic [31:0] fetch_addr_d, fetch_addr_q;
+ logic fetch_addr_en;
logic [31:0] instr_addr, instr_addr_w_aligned;
- logic addr_valid;
- logic pmp_err_q;
logic instr_or_pmp_err;
logic fifo_valid;
@@ -71,19 +72,21 @@
// Instruction fetch errors are valid on the data phase of a request
// PMP errors are generated in the address phase, and registered into a fake data phase
- assign instr_or_pmp_err = instr_err_i | pmp_err_q;
+ assign instr_or_pmp_err = instr_err_i | rdata_pmp_err_q[0];
// A branch will invalidate any previously fetched instructions
assign fifo_clear = branch_i;
- ibex_fetch_fifo fifo_i (
+ ibex_fetch_fifo #(
+ .NUM_REQS (NUM_REQS)
+ ) fifo_i (
.clk_i ( clk_i ),
.rst_ni ( rst_ni ),
.clear_i ( fifo_clear ),
.in_valid_i ( fifo_valid ),
- .in_addr_i ( instr_addr_q ),
+ .in_addr_i ( addr_i ),
.in_rdata_i ( instr_rdata_i ),
.in_err_i ( instr_or_pmp_err ),
.in_ready_o ( fifo_ready ),
@@ -101,55 +104,72 @@
//////////////
// Make a new request any time there is space in the FIFO, and space in the request queue
- assign valid_req = valid_req_q | (req_i & (fifo_ready | branch_i) & (~&rdata_outstanding_q));
+ assign valid_new_req = req_i & (fifo_ready | branch_i) & ~rdata_outstanding_q[NUM_REQS-1];
+ assign valid_req = valid_req_q | valid_new_req;
// If a request address triggers a PMP error, the external bus request is suppressed. We might
// therefore never receive a grant for such a request. The grant is faked in this case to make
// sure the request proceeds and the error is pushed to the FIFO.
- // We always use the registered version of the signal since it will be held stable throughout
- // the request, and the penalty of waiting for an extra cycle to consume the error is irrelevant.
- // A branch could update the address (and therefore data_pmp_err_i) on the cycle a request is
- // issued, in which case we must ignore the registered version.
- assign gnt_or_pmp_err = instr_gnt_i | (pmp_err_q & ~branch_i);
+ assign gnt_or_pmp_err = instr_gnt_i | instr_pmp_err_i;
// As with the grant, the rvalid must be faked for a PMP error, since the request was suppressed.
- // Since the pmp_err_q flop is only updated when the address updates, it will always point to the
- // PMP error status of the oldest outstanding request
- assign rvalid_or_pmp_err = rdata_outstanding_q[0] & (instr_rvalid_i | pmp_err_q);
+ assign rvalid_or_pmp_err = rdata_outstanding_q[0] & (instr_rvalid_i | rdata_pmp_err_q[0]);
// Hold the request stable for requests that didn't get granted
- assign valid_req_d = valid_req & ~instr_gnt_i;
+ assign valid_req_d = valid_req & ~gnt_or_pmp_err;
- // Hold the address stable for requests that couldn't be issued, or didn't get granted.
- // This is different to valid_req_q since there are cases where we must use addr+4 for
- // an ungranted request rather than addr_q (where addr_q has not been updated).
- assign hold_addr_d = (branch_i | hold_addr_q) & ~(valid_req & instr_gnt_i);
+ // Record whether an outstanding bus request is cancelled by a branch
+ assign discard_req_d = valid_req_q & (branch_i | discard_req_q);
////////////////
// Fetch addr //
////////////////
- // The address flop is used to hold the address steady for ungranted requests and also to
- // push the address to the FIFO for completed requests. For this reason, the address is only
- // updated once a request is the oldest outstanding to ensure that newer requests do not
- // overwrite the addresses of older ones. Branches are an exception to this, since all older
- // addresses will be discarded due to the branch.
+ // Two addresses are tracked in the prefetch buffer:
+ // 1. stored_addr_q - This is the address issued on the bus. It stays stable until
+ // the request is granted.
+ // 2. fetch_addr_q - This is our next address to fetch from. It is updated on branches to
+ // capture the new address, and then for each new request issued.
+ // A third address is tracked in the fetch FIFO itself:
+ // 3. instr_addr_q - This is the address at the head of the FIFO, efectively our oldest fetched
+ // address. This address is updated on branches, and does its own increment
+ // each time the FIFO is popped.
- // Update the addr_q flop on any branch, or
- assign addr_valid = branch_i |
- // A new request which will be the oldest, or
- (valid_req & instr_gnt_i & ~rdata_outstanding_q[0]) |
- // each time a valid request becomes the oldest
- (rvalid_or_pmp_err & ~branch_abort_q[0] &
- ((valid_req & instr_gnt_i) | rdata_outstanding_q[1]));
+ // 1. stored_addr_q
- // Fetch the next word-aligned instruction address
- assign fetch_addr = {instr_addr_q[31:2], 2'b00} + 32'd4;
+ // Only update stored_addr_q for new ungranted requests
+ assign stored_addr_en = valid_new_req & ~valid_req_q & ~gnt_or_pmp_err;
+
+ // Store whatever address was issued on the bus
+ assign stored_addr_d = instr_addr;
+
+ // CPU resets with a branch, so no need to reset these addresses
+ always_ff @(posedge clk_i) begin
+ if (stored_addr_en) begin
+ stored_addr_q <= stored_addr_d;
+ end
+ end
+
+ // 2. fetch_addr_q
+
+ // Update on a branch or as soon as a request is issued
+ assign fetch_addr_en = branch_i | (valid_new_req & ~valid_req_q);
+
+ assign fetch_addr_d = (branch_i ? addr_i :
+ {fetch_addr_q[31:2], 2'b00}) +
+ // Current address + 4
+ {{29{1'b0}},(valid_new_req & ~valid_req_q),2'b00};
+
+ always_ff @(posedge clk_i) begin
+ if (fetch_addr_en) begin
+ fetch_addr_q <= fetch_addr_d;
+ end
+ end
// Address mux
- assign instr_addr = branch_i ? addr_i :
- hold_addr_q ? instr_addr_q :
- fetch_addr;
+ assign instr_addr = valid_req_q ? stored_addr_q :
+ branch_i ? addr_i :
+ fetch_addr_q;
assign instr_addr_w_aligned = {instr_addr[31:2], 2'b00};
@@ -161,31 +181,43 @@
// Request 0 (always the oldest outstanding request)
if (i == 0) begin : g_req0
// A request becomes outstanding once granted, and is cleared once the rvalid is received.
- // Outstanding requests shift down the queue towards entry 0. Entry 0 considers the PMP
- // error cases while newer entries do not (pmp_err_q is only valid for entry 0)
+ // Outstanding requests shift down the queue towards entry 0.
assign rdata_outstanding_n[i] = (valid_req & gnt_or_pmp_err) |
rdata_outstanding_q[i];
// If a branch is received at any point while a request is outstanding, it must be tracked
// to ensure we discard the data once received
- assign branch_abort_n[i] = (branch_i & rdata_outstanding_q[i]) | branch_abort_q[i];
+ assign branch_discard_n[i] = (valid_req & gnt_or_pmp_err & discard_req_d) |
+ (branch_i & rdata_outstanding_q[i]) | branch_discard_q[i];
+ // Record whether this request received a PMP error
+ assign rdata_pmp_err_n[i] = (valid_req & ~rdata_outstanding_q[i] & instr_pmp_err_i) |
+ rdata_pmp_err_q[i];
end else begin : g_reqtop
+ // Entries > 0 consider the FIFO fill state to calculate their next state (by checking
+ // whether the previous entry is valid)
- assign rdata_outstanding_n[i] = (valid_req & instr_gnt_i &
- (&rdata_outstanding_q[i-1:0])) |
+ assign rdata_outstanding_n[i] = (valid_req & gnt_or_pmp_err &
+ rdata_outstanding_q[i-1]) |
rdata_outstanding_q[i];
- assign branch_abort_n[i] = (branch_i & rdata_outstanding_q[i]) | branch_abort_q[i];
+ assign branch_discard_n[i] = (valid_req & gnt_or_pmp_err & discard_req_d &
+ rdata_outstanding_q[i-1]) |
+ (branch_i & rdata_outstanding_q[i]) | branch_discard_q[i];
+ assign rdata_pmp_err_n[i] = (valid_req & ~rdata_outstanding_q[i] & instr_pmp_err_i &
+ rdata_outstanding_q[i-1]) |
+ rdata_pmp_err_q[i];
end
end
// Shift the entries down on each instr_rvalid_i
assign rdata_outstanding_s = rvalid_or_pmp_err ? {1'b0,rdata_outstanding_n[NUM_REQS-1:1]} :
rdata_outstanding_n;
- assign branch_abort_s = rvalid_or_pmp_err ? {1'b0,branch_abort_n[NUM_REQS-1:1]} :
- branch_abort_n;
+ assign branch_discard_s = rvalid_or_pmp_err ? {1'b0,branch_discard_n[NUM_REQS-1:1]} :
+ branch_discard_n;
+ assign rdata_pmp_err_s = rvalid_or_pmp_err ? {1'b0,rdata_pmp_err_n[NUM_REQS-1:1]} :
+ rdata_pmp_err_n;
- // Push a new entry to the FIFO once complete (and not aborted by a branch)
- assign fifo_valid = rvalid_or_pmp_err & ~branch_abort_q[0];
+ // Push a new entry to the FIFO once complete (and not cancelled by a branch)
+ assign fifo_valid = rvalid_or_pmp_err & ~branch_discard_q[0];
///////////////
// Registers //
@@ -194,22 +226,16 @@
always_ff @(posedge clk_i or negedge rst_ni) begin
if (!rst_ni) begin
valid_req_q <= 1'b0;
- hold_addr_q <= 1'b0;
+ discard_req_q <= 1'b0;
rdata_outstanding_q <= 'b0;
- branch_abort_q <= 'b0;
+ branch_discard_q <= 'b0;
+ rdata_pmp_err_q <= 'b0;
end else begin
valid_req_q <= valid_req_d;
- hold_addr_q <= hold_addr_d;
+ discard_req_q <= discard_req_d;
rdata_outstanding_q <= rdata_outstanding_s;
- branch_abort_q <= branch_abort_s;
- end
- end
-
- // CPU resets with a branch, so no need to reset these
- always_ff @(posedge clk_i) begin
- if (addr_valid) begin
- instr_addr_q <= instr_addr;
- pmp_err_q <= instr_pmp_err_i;
+ branch_discard_q <= branch_discard_s;
+ rdata_pmp_err_q <= rdata_pmp_err_s;
end
end
@@ -217,18 +243,7 @@
// Outputs //
/////////////
- assign instr_req_o = valid_req;
- assign instr_addr_o = instr_addr_w_aligned;
-
- ////////////////
- // Assertions //
- ////////////////
-
-`ifndef VERILATOR
- // Code changes required to support > 2 outstanding requests
- assert property (
- @(posedge clk_i) disable iff (!rst_ni)
- (NUM_REQS <= 2) );
-`endif
+ assign instr_req_o = valid_req;
+ assign instr_addr_o = instr_addr_w_aligned;
endmodule
diff --git a/hw/vendor/lowrisc_ibex/rtl/ibex_tracer.sv b/hw/vendor/lowrisc_ibex/rtl/ibex_tracer.sv
index 69c096c..423b76d 100644
--- a/hw/vendor/lowrisc_ibex/rtl/ibex_tracer.sv
+++ b/hw/vendor/lowrisc_ibex/rtl/ibex_tracer.sv
@@ -1,579 +1,834 @@
// Copyright lowRISC contributors.
-// Copyright 2018 ETH Zurich and University of Bologna.
+// Copyright 2018 ETH Zurich and University of Bologna, see also CREDITS.md.
// Licensed under the Apache License, Version 2.0, see LICENSE for details.
// SPDX-License-Identifier: Apache-2.0
-// Source/Destination register instruction index
-`define REG_S1 19:15
-`define REG_S2 24:20
-`define REG_S3 29:25
-`define REG_D 11:07
-
/**
- * Traces the executed instructions
+ * Trace executed instructions in simulation
*
- * Note: Verilator does not support the language constructs used in this
- * module!
+ * This tracer takes execution information from the RISC-V Verification Interface (RVFI) and
+ * produces a text file with a human-readable trace.
+ *
+ * All traced instructions are written to a log file. By default, the log file is named
+ * trace_core_<HARTID>.log, with <HARTID> being the 8 digit hart ID of the core being traced.
+ *
+ * The file name base, defaulting to "trace_core" can be set using the "ibex_tracer_file_base"
+ * plusarg passed to the simulation, e.g. "+ibex_tracer_file_base=ibex_my_trace". The exact syntax
+ * of passing plusargs to a simulation depends on the simulator.
+ *
+ * The trace contains six columns, separated by tabs:
+ * - The simulation time
+ * - The clock cycle count since reset
+ * - The program counter (PC)
+ * - The instruction
+ * - The decoded instruction in the same format as objdump, together with the accessed registers and
+ * read/written memory values. Jumps and branches show the target address.
+ * This column may be omitted if the instruction does not decode into a long form.
+ * - Accessed registers and memory locations.
+ *
+ * Significant effort is spent to make the decoding produced by this tracer as similar as possible
+ * to the one produced by objdump. This simplifies the correlation between the static program
+ * information from the objdump-generated disassembly, and the runtime information from this tracer.
*/
-module ibex_tracer #(
- parameter int unsigned RegAddrWidth = 5
-) (
- // Clock and Reset
- input logic clk_i,
- input logic rst_ni,
+module ibex_tracer (
+ input logic clk_i,
+ input logic rst_ni,
- input logic fetch_enable_i,
- input logic [31:0] hart_id_i,
+ input logic [31:0] hart_id_i,
- input logic valid_i,
- input logic [31:0] pc_i,
- input logic [31:0] instr_i,
- input logic [31:0] rs1_value_i,
- input logic [31:0] rs2_value_i,
- input logic [(RegAddrWidth-1):0] ex_reg_addr_i,
- input logic [31:0] ex_reg_wdata_i,
- input logic [31:0] ex_data_addr_i,
- input logic [31:0] ex_data_wdata_i,
- input logic [31:0] ex_data_rdata_i
+ // RVFI as described at https://github.com/SymbioticEDA/riscv-formal/blob/master/docs/rvfi.md
+ // The standard interface does not have _i/_o suffixes. For consistency with the standard the
+ // signals in this module don't have the suffixes either.
+ input logic rvfi_valid,
+ input logic [63:0] rvfi_order,
+ input logic [31:0] rvfi_insn,
+ input logic rvfi_trap,
+ input logic rvfi_halt,
+ input logic rvfi_intr,
+ input logic [ 1:0] rvfi_mode,
+ input logic [ 4:0] rvfi_rs1_addr,
+ input logic [ 4:0] rvfi_rs2_addr,
+ input logic [31:0] rvfi_rs1_rdata,
+ input logic [31:0] rvfi_rs2_rdata,
+ input logic [ 4:0] rvfi_rd_addr,
+ input logic [31:0] rvfi_rd_wdata,
+ input logic [31:0] rvfi_pc_rdata,
+ input logic [31:0] rvfi_pc_wdata,
+ input logic [31:0] rvfi_mem_addr,
+ input logic [ 3:0] rvfi_mem_rmask,
+ input logic [ 3:0] rvfi_mem_wmask,
+ input logic [31:0] rvfi_mem_rdata,
+ input logic [31:0] rvfi_mem_wdata
);
+ // These signals are part of RVFI, but not used in this module currently.
+ // Keep them as part of the interface to change the tracer more easily in the future. Assigning
+ // these signals to unused_* signals marks them explicitly as unused, an annotation picked up by
+ // linters, including Verilator lint.
+ logic [63:0] unused_rvfi_order = rvfi_order;
+ logic unused_rvfi_trap = rvfi_trap;
+ logic unused_rvfi_halt = rvfi_halt;
+ logic unused_rvfi_intr = rvfi_intr;
+ logic [ 1:0] unused_rvfi_mode = rvfi_mode;
+
import ibex_pkg::*;
import ibex_tracer_pkg::*;
- integer f;
- string fn;
- integer cycles;
- logic [ 4:0] rd, rs1, rs2, rs3;
+ int file_handle;
+ string file_name;
- typedef struct {
- logic [(RegAddrWidth-1):0] addr;
- logic [31:0] value;
- } reg_t;
+ int unsigned cycle;
+ string decoded_str;
+ logic insn_is_compressed;
- typedef struct {
- logic [31:0] addr;
- logic we;
- logic [ 3:0] be;
- logic [31:0] wdata;
- logic [31:0] rdata;
- } mem_acc_t;
+ // Data items accessed during this instruction
+ localparam RS1 = (1 << 0);
+ localparam RS2 = (1 << 1);
+ localparam RD = (1 << 2);
+ localparam MEM = (1 << 3);
+ logic [3:0] data_accessed;
- class instr_trace_t;
- time simtime;
- integer cycles;
- logic [31:0] pc;
- logic [31:0] instr;
- string str;
- reg_t regs_read[$];
- reg_t regs_write[$];
- mem_acc_t mem_access[$];
+ function void printbuffer_dumpline();
+ string rvfi_insn_str;
- function new ();
- str = "";
- regs_read = {};
- regs_write = {};
- mem_access = {};
- endfunction
+ if (file_handle == 32'h0) begin
+ string file_name_base = "trace_core";
+ $value$plusargs("ibex_tracer_file_base=%s", file_name_base);
+ $sformat(file_name, "%s_%h.log", file_name_base, hart_id_i);
- function string regAddrToStr(input logic [(RegAddrWidth-1):0] addr);
- begin
- if (addr < 10) begin
- return $sformatf(" x%0d", addr);
- end else begin
- return $sformatf("x%0d", addr);
- end
+ $display("%m: Writing execution trace to %s", file_name);
+ file_handle = $fopen(file_name, "w");
+ $fwrite(file_handle, "Time\tCycle\tPC\tInsn\tDecoded instruction\tRegister and memory contents\n");
+ end
+
+ // Write compressed instructions as four hex digits (16 bit word), and
+ // uncompressed ones as 8 hex digits (32 bit words).
+ if (insn_is_compressed) begin
+ rvfi_insn_str = $sformatf("%h", rvfi_insn[15:0]);
+ end else begin
+ rvfi_insn_str = $sformatf("%h", rvfi_insn);
+ end
+
+ $fwrite(file_handle, "%15t\t%d\t%h\t%s\t%s\t", $time, cycle, rvfi_pc_rdata, rvfi_insn_str, decoded_str);
+
+ if ((data_accessed & RS1) != 0) begin
+ $fwrite(file_handle, " %s:0x%08x", reg_addr_to_str(rvfi_rs1_addr), rvfi_rs1_rdata);
+ end
+ if ((data_accessed & RS2) != 0) begin
+ $fwrite(file_handle, " %s:0x%08x", reg_addr_to_str(rvfi_rs2_addr), rvfi_rs2_rdata);
+ end
+ if ((data_accessed & RD) != 0) begin
+ $fwrite(file_handle, " %s=0x%08x", reg_addr_to_str(rvfi_rd_addr), rvfi_rd_wdata);
+ end
+ if ((data_accessed & MEM) != 0) begin
+ $fwrite(file_handle, " PA:0x%08x", rvfi_mem_addr);
+
+ if (rvfi_mem_rmask != 4'b000) begin
+ $fwrite(file_handle, " store:0x%08x", rvfi_mem_wdata);
end
- endfunction
-
- function void printInstrTrace();
- mem_acc_t mem_acc;
- begin
- $fwrite(f, "%t %15d %h %h %-36s", simtime,
- cycles,
- pc_i,
- instr_i,
- str);
-
- foreach(regs_write[i]) begin
- if (regs_write[i].addr != 0) begin
- $fwrite(f, " %s=0x%08x", regAddrToStr(regs_write[i].addr), regs_write[i].value);
- end
- end
-
- foreach(regs_read[i]) begin
- if (regs_read[i].addr != 0) begin
- $fwrite(f, " %s:0x%08x", regAddrToStr(regs_read[i].addr), regs_read[i].value);
- end
- end
-
- if (mem_access.size() > 0) begin
- mem_acc = mem_access.pop_front();
-
- $fwrite(f, " PA:0x%08x", mem_acc.addr);
-
- if (mem_acc.we == 1'b1) begin
- $fwrite(f, " store:0x%08x", mem_acc.wdata);
- end else begin
- $fwrite(f, " load:0x%08x", mem_acc.rdata);
- end
- end
-
- $fwrite(f, "\n");
+ if (rvfi_mem_wmask != 4'b000) begin
+ $fwrite(file_handle, " load:0x%08x", rvfi_mem_rdata);
end
- endfunction
+ end
- function void printMnemonic(input string mnemonic);
- begin
- str = mnemonic;
+ $fwrite(file_handle, "\n");
+ endfunction
+
+
+ // Format register address with "x" prefix, left-aligned to a fixed width of 3 characters.
+ function string reg_addr_to_str(input logic [4:0] addr);
+ if (addr < 10) begin
+ return $sformatf(" x%0d", addr);
+ end else begin
+ return $sformatf("x%0d", addr);
+ end
+ endfunction
+
+ // Get a CSR name for a CSR address.
+ function string get_csr_name(input logic [11:0] csr_addr);
+ unique case (csr_addr)
+ 12'd0: return "ustatus";
+ 12'd4: return "uie";
+ 12'd5: return "utvec";
+ 12'd64: return "uscratch";
+ 12'd65: return "uepc";
+ 12'd66: return "ucause";
+ 12'd67: return "utval";
+ 12'd68: return "uip";
+ 12'd1: return "fflags";
+ 12'd2: return "frm";
+ 12'd3: return "fcsr";
+ 12'd3072: return "cycle";
+ 12'd3073: return "time";
+ 12'd3074: return "instret";
+ 12'd3075: return "hpmcounter3";
+ 12'd3076: return "hpmcounter4";
+ 12'd3077: return "hpmcounter5";
+ 12'd3078: return "hpmcounter6";
+ 12'd3079: return "hpmcounter7";
+ 12'd3080: return "hpmcounter8";
+ 12'd3081: return "hpmcounter9";
+ 12'd3082: return "hpmcounter10";
+ 12'd3083: return "hpmcounter11";
+ 12'd3084: return "hpmcounter12";
+ 12'd3085: return "hpmcounter13";
+ 12'd3086: return "hpmcounter14";
+ 12'd3087: return "hpmcounter15";
+ 12'd3088: return "hpmcounter16";
+ 12'd3089: return "hpmcounter17";
+ 12'd3090: return "hpmcounter18";
+ 12'd3091: return "hpmcounter19";
+ 12'd3092: return "hpmcounter20";
+ 12'd3093: return "hpmcounter21";
+ 12'd3094: return "hpmcounter22";
+ 12'd3095: return "hpmcounter23";
+ 12'd3096: return "hpmcounter24";
+ 12'd3097: return "hpmcounter25";
+ 12'd3098: return "hpmcounter26";
+ 12'd3099: return "hpmcounter27";
+ 12'd3100: return "hpmcounter28";
+ 12'd3101: return "hpmcounter29";
+ 12'd3102: return "hpmcounter30";
+ 12'd3103: return "hpmcounter31";
+ 12'd3200: return "cycleh";
+ 12'd3201: return "timeh";
+ 12'd3202: return "instreth";
+ 12'd3203: return "hpmcounter3h";
+ 12'd3204: return "hpmcounter4h";
+ 12'd3205: return "hpmcounter5h";
+ 12'd3206: return "hpmcounter6h";
+ 12'd3207: return "hpmcounter7h";
+ 12'd3208: return "hpmcounter8h";
+ 12'd3209: return "hpmcounter9h";
+ 12'd3210: return "hpmcounter10h";
+ 12'd3211: return "hpmcounter11h";
+ 12'd3212: return "hpmcounter12h";
+ 12'd3213: return "hpmcounter13h";
+ 12'd3214: return "hpmcounter14h";
+ 12'd3215: return "hpmcounter15h";
+ 12'd3216: return "hpmcounter16h";
+ 12'd3217: return "hpmcounter17h";
+ 12'd3218: return "hpmcounter18h";
+ 12'd3219: return "hpmcounter19h";
+ 12'd3220: return "hpmcounter20h";
+ 12'd3221: return "hpmcounter21h";
+ 12'd3222: return "hpmcounter22h";
+ 12'd3223: return "hpmcounter23h";
+ 12'd3224: return "hpmcounter24h";
+ 12'd3225: return "hpmcounter25h";
+ 12'd3226: return "hpmcounter26h";
+ 12'd3227: return "hpmcounter27h";
+ 12'd3228: return "hpmcounter28h";
+ 12'd3229: return "hpmcounter29h";
+ 12'd3230: return "hpmcounter30h";
+ 12'd3231: return "hpmcounter31h";
+ 12'd256: return "sstatus";
+ 12'd258: return "sedeleg";
+ 12'd259: return "sideleg";
+ 12'd260: return "sie";
+ 12'd261: return "stvec";
+ 12'd262: return "scounteren";
+ 12'd320: return "sscratch";
+ 12'd321: return "sepc";
+ 12'd322: return "scause";
+ 12'd323: return "stval";
+ 12'd324: return "sip";
+ 12'd384: return "satp";
+ 12'd3857: return "mvendorid";
+ 12'd3858: return "marchid";
+ 12'd3859: return "mimpid";
+ 12'd3860: return "mhartid";
+ 12'd768: return "mstatus";
+ 12'd769: return "misa";
+ 12'd770: return "medeleg";
+ 12'd771: return "mideleg";
+ 12'd772: return "mie";
+ 12'd773: return "mtvec";
+ 12'd774: return "mcounteren";
+ 12'd832: return "mscratch";
+ 12'd833: return "mepc";
+ 12'd834: return "mcause";
+ 12'd835: return "mtval";
+ 12'd836: return "mip";
+ 12'd928: return "pmpcfg0";
+ 12'd929: return "pmpcfg1";
+ 12'd930: return "pmpcfg2";
+ 12'd931: return "pmpcfg3";
+ 12'd944: return "pmpaddr0";
+ 12'd945: return "pmpaddr1";
+ 12'd946: return "pmpaddr2";
+ 12'd947: return "pmpaddr3";
+ 12'd948: return "pmpaddr4";
+ 12'd949: return "pmpaddr5";
+ 12'd950: return "pmpaddr6";
+ 12'd951: return "pmpaddr7";
+ 12'd952: return "pmpaddr8";
+ 12'd953: return "pmpaddr9";
+ 12'd954: return "pmpaddr10";
+ 12'd955: return "pmpaddr11";
+ 12'd956: return "pmpaddr12";
+ 12'd957: return "pmpaddr13";
+ 12'd958: return "pmpaddr14";
+ 12'd959: return "pmpaddr15";
+ 12'd2816: return "mcycle";
+ 12'd2818: return "minstret";
+ 12'd2819: return "mhpmcounter3";
+ 12'd2820: return "mhpmcounter4";
+ 12'd2821: return "mhpmcounter5";
+ 12'd2822: return "mhpmcounter6";
+ 12'd2823: return "mhpmcounter7";
+ 12'd2824: return "mhpmcounter8";
+ 12'd2825: return "mhpmcounter9";
+ 12'd2826: return "mhpmcounter10";
+ 12'd2827: return "mhpmcounter11";
+ 12'd2828: return "mhpmcounter12";
+ 12'd2829: return "mhpmcounter13";
+ 12'd2830: return "mhpmcounter14";
+ 12'd2831: return "mhpmcounter15";
+ 12'd2832: return "mhpmcounter16";
+ 12'd2833: return "mhpmcounter17";
+ 12'd2834: return "mhpmcounter18";
+ 12'd2835: return "mhpmcounter19";
+ 12'd2836: return "mhpmcounter20";
+ 12'd2837: return "mhpmcounter21";
+ 12'd2838: return "mhpmcounter22";
+ 12'd2839: return "mhpmcounter23";
+ 12'd2840: return "mhpmcounter24";
+ 12'd2841: return "mhpmcounter25";
+ 12'd2842: return "mhpmcounter26";
+ 12'd2843: return "mhpmcounter27";
+ 12'd2844: return "mhpmcounter28";
+ 12'd2845: return "mhpmcounter29";
+ 12'd2846: return "mhpmcounter30";
+ 12'd2847: return "mhpmcounter31";
+ 12'd2944: return "mcycleh";
+ 12'd2946: return "minstreth";
+ 12'd2947: return "mhpmcounter3h";
+ 12'd2948: return "mhpmcounter4h";
+ 12'd2949: return "mhpmcounter5h";
+ 12'd2950: return "mhpmcounter6h";
+ 12'd2951: return "mhpmcounter7h";
+ 12'd2952: return "mhpmcounter8h";
+ 12'd2953: return "mhpmcounter9h";
+ 12'd2954: return "mhpmcounter10h";
+ 12'd2955: return "mhpmcounter11h";
+ 12'd2956: return "mhpmcounter12h";
+ 12'd2957: return "mhpmcounter13h";
+ 12'd2958: return "mhpmcounter14h";
+ 12'd2959: return "mhpmcounter15h";
+ 12'd2960: return "mhpmcounter16h";
+ 12'd2961: return "mhpmcounter17h";
+ 12'd2962: return "mhpmcounter18h";
+ 12'd2963: return "mhpmcounter19h";
+ 12'd2964: return "mhpmcounter20h";
+ 12'd2965: return "mhpmcounter21h";
+ 12'd2966: return "mhpmcounter22h";
+ 12'd2967: return "mhpmcounter23h";
+ 12'd2968: return "mhpmcounter24h";
+ 12'd2969: return "mhpmcounter25h";
+ 12'd2970: return "mhpmcounter26h";
+ 12'd2971: return "mhpmcounter27h";
+ 12'd2972: return "mhpmcounter28h";
+ 12'd2973: return "mhpmcounter29h";
+ 12'd2974: return "mhpmcounter30h";
+ 12'd2975: return "mhpmcounter31h";
+ 12'd803: return "mhpmevent3";
+ 12'd804: return "mhpmevent4";
+ 12'd805: return "mhpmevent5";
+ 12'd806: return "mhpmevent6";
+ 12'd807: return "mhpmevent7";
+ 12'd808: return "mhpmevent8";
+ 12'd809: return "mhpmevent9";
+ 12'd810: return "mhpmevent10";
+ 12'd811: return "mhpmevent11";
+ 12'd812: return "mhpmevent12";
+ 12'd813: return "mhpmevent13";
+ 12'd814: return "mhpmevent14";
+ 12'd815: return "mhpmevent15";
+ 12'd816: return "mhpmevent16";
+ 12'd817: return "mhpmevent17";
+ 12'd818: return "mhpmevent18";
+ 12'd819: return "mhpmevent19";
+ 12'd820: return "mhpmevent20";
+ 12'd821: return "mhpmevent21";
+ 12'd822: return "mhpmevent22";
+ 12'd823: return "mhpmevent23";
+ 12'd824: return "mhpmevent24";
+ 12'd825: return "mhpmevent25";
+ 12'd826: return "mhpmevent26";
+ 12'd827: return "mhpmevent27";
+ 12'd828: return "mhpmevent28";
+ 12'd829: return "mhpmevent29";
+ 12'd830: return "mhpmevent30";
+ 12'd831: return "mhpmevent31";
+ 12'd1952: return "tselect";
+ 12'd1953: return "tdata1";
+ 12'd1954: return "tdata2";
+ 12'd1955: return "tdata3";
+ 12'd1968: return "dcsr";
+ 12'd1969: return "dpc";
+ 12'd1970: return "dscratch";
+ 12'd512: return "hstatus";
+ 12'd514: return "hedeleg";
+ 12'd515: return "hideleg";
+ 12'd516: return "hie";
+ 12'd517: return "htvec";
+ 12'd576: return "hscratch";
+ 12'd577: return "hepc";
+ 12'd578: return "hcause";
+ 12'd579: return "hbadaddr";
+ 12'd580: return "hip";
+ 12'd896: return "mbase";
+ 12'd897: return "mbound";
+ 12'd898: return "mibase";
+ 12'd899: return "mibound";
+ 12'd900: return "mdbase";
+ 12'd901: return "mdbound";
+ 12'd800: return "mucounteren";
+ 12'd801: return "mscounteren";
+ 12'd802: return "mhcounteren";
+ default: return $sformatf("0x%x", csr_addr);
+ endcase
+ endfunction
+
+ function void decode_mnemonic(input string mnemonic);
+ decoded_str = mnemonic;
+ endfunction
+
+ function void decode_r_insn(input string mnemonic);
+ data_accessed = RS1 | RS2 | RD;
+ decoded_str = $sformatf("%s\tx%0d,x%0d,x%0d", mnemonic, rvfi_rd_addr, rvfi_rs1_addr, rvfi_rs2_addr);
+ endfunction
+
+ function void decode_i_insn(input string mnemonic);
+ data_accessed = RS1 | RD;
+ decoded_str = $sformatf("%s\tx%0d,x%0d,%0d", mnemonic, rvfi_rd_addr, rvfi_rs1_addr,
+ $signed({{20 {rvfi_insn[31]}}, rvfi_insn[31:20]}));
+ endfunction
+
+ function void decode_i_shift_insn(input string mnemonic);
+ // SLLI, SRLI, SRAI
+ logic [4:0] shamt;
+ shamt = {rvfi_insn[24:20]};
+ data_accessed = RS1 | RD;
+ decoded_str = $sformatf("%s\tx%0d,x%0d,0x%0x", mnemonic, rvfi_rd_addr, rvfi_rs1_addr, shamt);
+ endfunction
+
+ function void decode_i_jalr_insn(input string mnemonic);
+ // JALR
+ data_accessed = RS1 | RD;
+ decoded_str = $sformatf("%s\tx%0d,%0d(x%0d)", mnemonic, rvfi_rd_addr,
+ $signed({{20 {rvfi_insn[31]}}, rvfi_insn[31:20]}), rvfi_rs1_addr);
+ endfunction
+
+ function void decode_u_insn(input string mnemonic);
+ data_accessed = RD;
+ decoded_str = $sformatf("%s\tx%0d,0x%0x", mnemonic, rvfi_rd_addr, {rvfi_insn[31:12]});
+ endfunction
+
+ function void decode_j_insn(input string mnemonic);
+ // JAL
+ data_accessed = RD;
+ decoded_str = $sformatf("%s\tx%0d,%0x", mnemonic, rvfi_rd_addr, rvfi_pc_wdata);
+ endfunction
+
+ function void decode_b_insn(input string mnemonic);
+ logic [31:0] branch_target;
+ logic [31:0] imm;
+
+ // We cannot use rvfi_pc_wdata for conditional jumps.
+ imm = $signed({ {19 {rvfi_insn[31]}}, rvfi_insn[31], rvfi_insn[7],
+ rvfi_insn[30:25], rvfi_insn[11:8], 1'b0 });
+ branch_target = rvfi_pc_rdata + imm;
+
+ data_accessed = RS1 | RS2 | RD;
+ decoded_str = $sformatf("%s\tx%0d,x%0d,%0x", mnemonic, rvfi_rs1_addr, rvfi_rs2_addr, branch_target);
+ endfunction
+
+ function void decode_csr_insn(input string mnemonic);
+ logic [11:0] csr;
+ string csr_name;
+ csr = rvfi_insn[31:20];
+ csr_name = get_csr_name(csr);
+
+ data_accessed = RD;
+
+ if (!rvfi_insn[14]) begin
+ data_accessed |= RS1;
+ decoded_str = $sformatf("%s\tx%0d,%s,x%0d", mnemonic, rvfi_rd_addr, csr_name, rvfi_rs1_addr);
+ end else begin
+ decoded_str = $sformatf("%s\tx%0d,%s,%0d", mnemonic, rvfi_rd_addr, csr_name, { 27'b0, rvfi_insn[19:15]});
+ end
+ endfunction
+
+ function void decode_cr_insn(input string mnemonic);
+ if (rvfi_rs2_addr == 5'b0) begin
+ data_accessed = RS1;
+ decoded_str = $sformatf("%s\tx%0d", mnemonic, rvfi_rs1_addr);
+ end else begin
+ data_accessed = RS1 | RS2 | RD; // RS1 == RD
+ decoded_str = $sformatf("%s\tx%0d,x%0d", mnemonic, rvfi_rd_addr, rvfi_rs2_addr);
+ end
+ endfunction
+
+ function void decode_ci_cli_insn(input string mnemonic);
+ logic [5:0] imm;
+ imm = {rvfi_insn[12], rvfi_insn[6:2]};
+ data_accessed = RD;
+ decoded_str = $sformatf("%s\tx%0d,%0d", mnemonic, rvfi_rd_addr, $signed(imm));
+ endfunction
+
+ function void decode_ci_caddi_insn(input string mnemonic);
+ logic [5:0] nzimm;
+ nzimm = {rvfi_insn[12], rvfi_insn[6:2]};
+ data_accessed = RS1 | RD;
+ decoded_str = $sformatf("%s\tx%0d,%0d", mnemonic, rvfi_rd_addr, $signed(nzimm));
+ endfunction
+
+ function void decode_ci_caddi16sp_insn(input string mnemonic);
+ logic [9:0] nzimm;
+ nzimm = {rvfi_insn[12], rvfi_insn[4:3], rvfi_insn[5], rvfi_insn[2], rvfi_insn[6], 4'b0};
+ data_accessed = RS1 | RD;
+ decoded_str = $sformatf("%s\tx%0d,%0d", mnemonic, rvfi_rd_addr, $signed(nzimm));
+ endfunction
+
+ function void decode_ci_clui_insn(input string mnemonic);
+ logic [5:0] nzimm;
+ nzimm = {rvfi_insn[12], rvfi_insn[6:2]};
+ data_accessed = RD;
+ decoded_str = $sformatf("%s\tx%0d,0x%0x", mnemonic, rvfi_rd_addr, 20'($signed(nzimm)));
+ endfunction
+
+ function void decode_ci_cslli_insn(input string mnemonic);
+ logic [5:0] shamt;
+ shamt = {rvfi_insn[12], rvfi_insn[6:2]};
+ data_accessed = RS1 | RD;
+ decoded_str = $sformatf("%s\tx%0d,0x%0x", mnemonic, rvfi_rd_addr, shamt);
+ endfunction
+
+ function void decode_ciw_insn(input string mnemonic);
+ // C.ADDI4SPN
+ logic [9:0] nzuimm;
+ nzuimm = {rvfi_insn[10:7], rvfi_insn[12:11], rvfi_insn[5], rvfi_insn[6], 2'b00};
+ data_accessed = RD;
+ decoded_str = $sformatf("%s\tx%0d,x2,%0d", mnemonic, rvfi_rd_addr, nzuimm);
+ endfunction
+
+ function void decode_cb_sr_insn(input string mnemonic);
+ logic [5:0] shamt;
+ shamt = {rvfi_insn[12], rvfi_insn[6:2]};
+ data_accessed = RS1 | RD;
+ decoded_str = $sformatf("%s\tx%0d,0x%0x", mnemonic, rvfi_rs1_addr, shamt);
+ endfunction
+
+ function void decode_cb_insn(input string mnemonic);
+ logic [7:0] imm;
+ logic [31:0] jump_target;
+ if (rvfi_insn[15:13] == 3'b110 || rvfi_insn[15:13] == 3'b111) begin
+ // C.BNEZ and C.BEQZ
+ // We cannot use rvfi_pc_wdata for conditional jumps.
+ imm = {rvfi_insn[12], rvfi_insn[6:5], rvfi_insn[2], rvfi_insn[11:10], rvfi_insn[4:3]};
+ jump_target = rvfi_pc_rdata + 32'($signed({imm, 1'b0}));
+ data_accessed = RS1;
+ decoded_str = $sformatf("%s\tx%0d,%0x", mnemonic, rvfi_rs1_addr, jump_target);
+ end else if (rvfi_insn[15:13] == 3'b100) begin
+ // C.ANDI
+ imm = {{2{rvfi_insn[12]}}, rvfi_insn[12], rvfi_insn[6:2]};
+ data_accessed = RS1 | RD; // RS1 == RD
+ decoded_str = $sformatf("%s\tx%0d,%0d", mnemonic, rvfi_rd_addr, $signed(imm));
+ end else begin
+ imm = {rvfi_insn[12], rvfi_insn[6:2], 2'b00};
+ data_accessed = RS1;
+ decoded_str = $sformatf("%s\tx%0d,0x%0x", mnemonic, rvfi_rs1_addr, imm);
+ end
+ endfunction
+
+ function void decode_cs_insn(input string mnemonic);
+ data_accessed = RS1 | RS2 | RD; // RS1 == RD
+ decoded_str = $sformatf("%s\tx%0d,x%0d", mnemonic, rvfi_rd_addr, rvfi_rs2_addr);
+ endfunction
+
+ function void decode_cj_insn(input string mnemonic);
+ decoded_str = $sformatf("%s\t%0x", mnemonic, rvfi_pc_wdata);
+ endfunction
+
+ function void decode_compressed_load_insn(input string mnemonic);
+ logic [7:0] imm;
+
+ if (rvfi_insn[1:0] == OPCODE_C0) begin
+ // C.LW
+ imm = {1'b0, rvfi_insn[5], rvfi_insn[12:10], rvfi_insn[6], 2'b00};
+ end else begin
+ // C.LWSP
+ imm = {rvfi_insn[3:2], rvfi_insn[12], rvfi_insn[6:4], 2'b00};
+ end
+ data_accessed = RS1 | RD | MEM;
+ decoded_str = $sformatf("%s\tx%0d,%0d(x%0d)", mnemonic, rvfi_rd_addr, imm, rvfi_rs1_addr);
+ endfunction
+
+ function void decode_compressed_store_insn(input string mnemonic);
+ logic [7:0] imm;
+ if (rvfi_insn[1:0] == OPCODE_C0) begin
+ // C.SW
+ imm = {1'b0, rvfi_insn[5], rvfi_insn[12:10], rvfi_insn[6], 2'b00};
+ end else begin
+ // C.SWSP
+ imm = {rvfi_insn[8:7], rvfi_insn[12:9], 2'b00};
+ end
+ data_accessed = RS1 | RS2 | MEM;
+ decoded_str = $sformatf("%s\tx%0d,%0d(x%0d)", mnemonic, rvfi_rs2_addr, imm, rvfi_rs1_addr);
+ endfunction
+
+ function void decode_load_insn();
+ string mnemonic;
+
+ /*
+ Gives wrong results in Verilator < 4.020.
+ See https://github.com/lowRISC/ibex/issues/372 and
+ https://www.veripool.org/issues/1536-Verilator-Misoptimization-in-if-and-case-with-default-statement-inside-a-function
+
+ unique case (rvfi_insn[14:12])
+ 3'b000: mnemonic = "lb";
+ 3'b001: mnemonic = "lh";
+ 3'b010: mnemonic = "lw";
+ 3'b100: mnemonic = "lbu";
+ 3'b101: mnemonic = "lhu";
+ default: begin
+ decode_mnemonic("INVALID");
+ return;
end
- endfunction // printMnemonic
+ endcase
+ */
+ logic [2:0] size;
+ size = rvfi_insn[14:12];
+ if (size == 3'b000) begin
+ mnemonic = "lb";
+ end else if (size == 3'b001) begin
+ mnemonic = "lh";
+ end else if (size == 3'b010) begin
+ mnemonic = "lw";
+ end else if (size == 3'b100) begin
+ mnemonic = "lbu";
+ end else if (size == 3'b101) begin
+ mnemonic = "lhu";
+ end else begin
+ decode_mnemonic("INVALID");
+ return;
+ end
- function void printRInstr(input string mnemonic);
- begin
- regs_read.push_back('{rs1, rs1_value_i});
- regs_read.push_back('{rs2, rs2_value_i});
- regs_write.push_back('{rd, 'x});
- str = $sformatf("%-16s x%0d, x%0d, x%0d", mnemonic, rd, rs1, rs2);
+
+ data_accessed = RD | RS1 | MEM;
+ decoded_str = $sformatf("%s\tx%0d,%0d(x%0d)", mnemonic, rvfi_rd_addr,
+ $signed({{20 {rvfi_insn[31]}}, rvfi_insn[31:20]}), rvfi_rs1_addr);
+ endfunction
+
+ function void decode_store_insn();
+ string mnemonic;
+
+ unique case (rvfi_insn[13:12])
+ 2'b00: mnemonic = "sb";
+ 2'b01: mnemonic = "sh";
+ 2'b10: mnemonic = "sw";
+ default: begin
+ decode_mnemonic("INVALID");
+ return;
end
- endfunction // printRInstr
+ endcase
- function void printIInstr(input string mnemonic);
- begin
- regs_read.push_back('{rs1, rs1_value_i});
- regs_write.push_back('{rd, 'x});
- str = $sformatf("%-16s x%0d, x%0d, %0d", mnemonic, rd, rs1, $signed({{20 {instr[31]}}, instr[31:20]}));
- end
- endfunction // printIInstr
+ if (!rvfi_insn[14]) begin
+ // regular store
+ data_accessed = RS1 | RS2 | MEM;
+ decoded_str = $sformatf("%s\tx%0d,%0d(x%0d)", mnemonic, rvfi_rs2_addr,
+ $signed({ {20 {rvfi_insn[31]}}, rvfi_insn[31:25], rvfi_insn[11:7] }), rvfi_rs1_addr);
+ end else begin
+ decode_mnemonic("INVALID");
+ end
+ endfunction
- function void printIuInstr(input string mnemonic);
- begin
- regs_read.push_back('{rs1, rs1_value_i});
- regs_write.push_back('{rd, 'x});
- str = $sformatf("%-16s x%0d, x%0d, 0x%0x", mnemonic, rd, rs1, {{20 {instr[31]}}, instr[31:20]});
- end
- endfunction // printIuInstr
+ function string get_fence_description(logic [3:0] bits);
+ string desc = "";
+ if (bits[3]) begin
+ desc = {desc, "i"};
+ end
+ if (bits[2]) begin
+ desc = {desc, "o"};
+ end
+ if (bits[1]) begin
+ desc = {desc, "r"};
+ end
+ if (bits[0]) begin
+ desc = {desc, "w"};
+ end
+ return desc;
+ endfunction
- function void printUInstr(input string mnemonic);
- begin
- regs_write.push_back('{rd, 'x});
- str = $sformatf("%-16s x%0d, 0x%0h", mnemonic, rd, {instr[31:12], 12'h000});
- end
- endfunction // printUInstr
-
- function void printUJInstr(input string mnemonic);
- begin
- regs_write.push_back('{rd, 'x});
- str = $sformatf("%-16s x%0d, %0d", mnemonic, rd, $signed({ {12 {instr[31]}}, instr[19:12], instr[20], instr[30:21], 1'b0 }));
- end
- endfunction // printUJInstr
-
- function void printSBInstr(input string mnemonic);
- begin
- regs_read.push_back('{rs1, rs1_value_i});
- regs_read.push_back('{rs2, rs2_value_i});
- str = $sformatf("%-16s x%0d, x%0d, %0d", mnemonic, rs1, rs2, $signed({ {19 {instr[31]}}, instr[31], instr[7], instr[30:25], instr[11:8], 1'b0 }));
- end
- endfunction // printSBInstr
-
- function void printCSRInstr(input string mnemonic);
- logic [11:0] csr;
- begin
- csr = instr_i[31:20];
-
- regs_write.push_back('{rd, 'x});
-
- if (!instr_i[14]) begin
- regs_read.push_back('{rs1, rs1_value_i});
- str = $sformatf("%-16s x%0d, x%0d, 0x%h", mnemonic, rd, rs1, csr);
- end else begin
- str = $sformatf("%-16s x%0d, 0x%h, 0x%h", mnemonic, rd, { 27'b0, instr[`REG_S1] }, csr);
- end
- end
- endfunction // printCSRInstr
-
- function void printCRInstr(input string mnemonic);
- logic [4:0] rs1;
- logic [4:0] rs2;
- begin
- rs1 = instr_i[11:7];
- rs2 = instr_i[6:2];
-
- if (rs2 == 5'b0) begin
- regs_read.push_back('{rs1, rs1_value_i});
- str = $sformatf("%-16s x%0d", mnemonic, rs1);
- end else begin
- regs_write.push_back('{rs1, 'x});
- regs_read.push_back('{rs2, rs2_value_i});
- str = $sformatf("%-16s x%0d, x%0d", mnemonic, rs1, rs2);
- end
- end
- endfunction // printCRInstr
-
- function void printCIInstr(input string mnemonic);
- begin
- regs_write.push_back('{rd, 'x});
- str = $sformatf("%-16s x%0d, 0x%h", mnemonic, rd, {instr_i[12], instr_i[4:0]});
- end
- endfunction // printCIInstr
-
- function void printCIWInstr(input string mnemonic);
- logic [4:0] rd;
- begin
- rd = {2'b01, instr_i[4:2]};
- regs_write.push_back('{rd, 'x});
- str = $sformatf("%-16s x%0d, 0x%h", mnemonic, rd, {instr_i[10:7], instr_i[12:11], instr_i[5], instr_i[6]});
- end
- endfunction // printCIWInstr
-
- function void printCBInstr(input string mnemonic);
- logic [4:0] rs1;
- logic [8:1] imm;
- begin
- rs1 = {2'b01, instr_i[9:7]};
- if ((instr_i[15:13] == 3'b110) || (instr_i[15:13] == 3'b111)) begin
- imm = {instr_i[12], instr_i[6:5], instr_i[2], instr_i[11:10], instr_i[4:3]};
- regs_read.push_back('{rs1, rs1_value_i});
- end else begin
- imm = {instr_i[12], instr_i[6:2], 2'b00};
- regs_write.push_back('{rs1, 'x});
- end
- str = $sformatf("%-16s x%0d, 0x%h", mnemonic, rs1, imm);
- end
- endfunction // printCBInstr
-
- function void printCSInstr(input string mnemonic);
- logic [4:0] rd;
- logic [4:0] rs2;
- begin
- rd = {2'b01, instr_i[9:7]};
- rs2 = {2'b01, instr_i[4:2]};
-
- regs_write.push_back('{rd, 'x});
- regs_read.push_back('{rs2, rs2_value_i});
- str = $sformatf("%-16s x%0d, x%0d", mnemonic, rd, rs2);
- end
- endfunction // printCSInstr
-
- function void printCJInstr(input string mnemonic);
- logic [11:1] imm;
- imm = {instr_i[12], instr_i[8], instr_i[10:9], instr_i[6],
- instr_i[7], instr[2], instr[11], instr_i[5:3]};
- begin
- str = $sformatf("%-16s 0x%h", mnemonic, imm);
- end
- endfunction // printCJInstr
-
- function void printCompressedLoadInstr(input string mnemonic);
- logic [4:0] rd;
- logic [4:0] rs1;
- logic [7:0] imm;
- mem_acc_t mem_acc;
- begin
- // Detect C.LW intruction
- if (instr_i[1:0] == OPCODE_C0) begin
- rd = {2'b01, instr_i[4:2]};
- rs1 = {2'b01, instr_i[9:7]};
- imm = {1'b0, instr[5], instr[12:10], instr[6], 2'b00};
- end else begin
- // LWSP instruction
- rd = instr_i[11:7];
- rs1 = 5'h2;
- imm = {instr[3:2], instr[12], instr[6:4], 2'b00};
- end
- regs_write.push_back('{rd, 'x});
- regs_read.push_back('{rs1, rs1_value_i});
- str = $sformatf("%-16s x%0d, %0d(x%0d)", mnemonic, rd, rs1, imm);
- mem_acc.addr = ex_data_addr_i;
- mem_acc.rdata = ex_data_rdata_i;
- mem_access.push_back(mem_acc);
- end
- endfunction // printCompressedLoadInstr()
-
- function void printCompressedStoreInstr(input string mnemonic);
- logic [4:0] rs1;
- logic [4:0] rs2;
- logic [7:0] imm;
- mem_acc_t mem_acc;
- begin
- // Detect C.SW instruction
- if (instr_i[1:0] == OPCODE_C0) begin
- rs1 = {2'b01, instr_i[9:7]};
- rs2 = {2'b01, instr_i[4:2]};
- imm = {1'b0, instr[5], instr[12:10], instr[6], 2'b0};
- end else begin
- // SWSP instruction
- rs1 = 5'h2;
- rs2 = instr_i[11:7];
- imm = {instr[8:7], instr[12:9], 2'b00};
- end
- str = $sformatf("%-16s x%0d, %0d(x%0d)", mnemonic, rs2, rs1, imm);
- regs_read.push_back('{rs1, rs1_value_i});
- regs_read.push_back('{rs2, rs2_value_i});
- mem_acc.addr = ex_data_addr_i;
- mem_acc.we = 1'b1;
- mem_acc.wdata = ex_data_wdata_i;
- mem_access.push_back(mem_acc);
- end
- endfunction // printCompressedStoreInstr
-
- function void printLoadInstr();
- string mnemonic;
- logic [2:0] size;
- mem_acc_t mem_acc;
- begin
- // detect reg-reg load and find size
- size = instr_i[14:12];
- if (instr_i[14:12] == 3'b111) begin
- size = instr_i[30:28];
- end
-
- unique case (size)
- 3'b000: mnemonic = "lb";
- 3'b001: mnemonic = "lh";
- 3'b010: mnemonic = "lw";
- 3'b100: mnemonic = "lbu";
- 3'b101: mnemonic = "lhu";
- 3'b110: mnemonic = "p.elw";
- 3'b011,
- 3'b111: begin
- printMnemonic("INVALID");
- return;
- end
- default: begin
- printMnemonic("INVALID");
- return;
- end
- endcase
-
- regs_write.push_back('{rd, 'x});
-
- if (instr_i[14:12] != 3'b111) begin
- // regular load
- regs_read.push_back('{rs1, rs1_value_i});
- str = $sformatf("%-16s x%0d, %0d(x%0d)", mnemonic, rd, $signed({{20 {instr[31]}}, instr[31:20]}), rs1);
- end else begin
- printMnemonic("INVALID");
- end
-
- mem_acc.addr = ex_data_addr_i;
- mem_acc.rdata = ex_data_rdata_i;
- mem_access.push_back(mem_acc);
- end
- endfunction
-
- function void printStoreInstr();
- string mnemonic;
- mem_acc_t mem_acc;
- begin
-
- unique case (instr_i[13:12])
- 2'b00: mnemonic = "sb";
- 2'b01: mnemonic = "sh";
- 2'b10: mnemonic = "sw";
- 2'b11: begin
- printMnemonic("INVALID");
- return;
- end
- default: begin
- printMnemonic("INVALID");
- return;
- end
- endcase
-
- if (!instr_i[14]) begin
- // regular store
- regs_read.push_back('{rs2, rs2_value_i});
- regs_read.push_back('{rs1, rs1_value_i});
- str = $sformatf("%-16s x%0d, %0d(x%0d)", mnemonic, rs2, $signed({ {20 {instr[31]}}, instr[31:25], instr[11:7] }), rs1);
- end else begin
- printMnemonic("INVALID");
- end
-
- mem_acc.addr = ex_data_addr_i;
- mem_acc.we = 1'b1;
- mem_acc.wdata = ex_data_wdata_i;
- mem_access.push_back(mem_acc);
- end
- endfunction // printSInstr
-
- endclass
-
- mailbox #(instr_trace_t) instr_ex = new ();
- mailbox #(instr_trace_t) instr_wb = new ();
+ function void decode_fence();
+ string predecessor;
+ string successor;
+ predecessor = get_fence_description(rvfi_insn[27:24]);
+ successor = get_fence_description(rvfi_insn[23:20]);
+ decoded_str = $sformatf("fence\t%s,%s", predecessor, successor);
+ endfunction
// cycle counter
always_ff @(posedge clk_i or negedge rst_ni) begin
if (!rst_ni) begin
- cycles = 0;
+ cycle <= 0;
end else begin
- cycles = cycles + 1;
+ cycle <= cycle + 1;
end
end
- // open/close output file for writing
- initial begin
- wait(rst_ni == 1'b1);
- wait(fetch_enable_i == 1'b1);
- $sformat(fn, "trace_core_%h.log", hart_id_i);
- $display("[TRACER] Output filename is: %s", fn);
- f = $fopen(fn, "w");
- $fwrite(f, " Time Cycles PC Instr Mnemonic\n");
- end
-
+ // close output file for writing
final begin
- $fclose(f);
+ if (file_handle != 32'h0) begin
+ $fclose(file_handle);
+ end
end
- assign rd = instr_i[`REG_D];
- assign rs1 = instr_i[`REG_S1];
- assign rs2 = instr_i[`REG_S2];
- assign rs3 = instr_i[`REG_S3];
-
// log execution
- always @(posedge clk_i) begin
- instr_trace_t trace;
- mem_acc_t mem_acc;
- // special case for WFI because we don't wait for unstalling there
- if (valid_i) begin
- trace = new ();
+ always_ff @(posedge clk_i) begin
+ if (rvfi_valid) begin
+ printbuffer_dumpline();
+ end
+ end
- trace.simtime = $time;
- trace.cycles = cycles;
- trace.pc = pc_i;
- trace.instr = instr_i;
+ always_comb begin
+ decoded_str = "";
+ data_accessed = 4'h0;
+ insn_is_compressed = 0;
- // Check for compressed instructions
- if (instr_i[1:0] != 2'b11) begin
- // Separate case to avoid overlapping decoding
- if ((instr_i[15:13] == 3'b100) && (instr_i[1:0] == 2'b10)) begin
- if (instr_i[12]) begin
- if (instr_i[11:2] == 10'h0) begin
- trace.printMnemonic("c.ebreak");
- end else if (instr_i[6:2] == 5'b0) begin
- trace.printCRInstr("c.jalr");
- end else begin
- trace.printCRInstr("c.add");
- end
+ // Check for compressed instructions
+ if (rvfi_insn[1:0] != 2'b11) begin
+ insn_is_compressed = 1;
+ // Separate case to avoid overlapping decoding
+ if (rvfi_insn[15:13] == 3'b100 && rvfi_insn[1:0] == 2'b10) begin
+ if (rvfi_insn[12]) begin
+ if (rvfi_insn[11:2] == 10'h0) begin
+ decode_mnemonic("c.ebreak");
+ end else if (rvfi_insn[6:2] == 5'b0) begin
+ decode_cr_insn("c.jalr");
end else begin
- if (instr_i[6:2] == 5'h0) begin
- trace.printCRInstr("c.jr");
- end else begin
- trace.printCRInstr("c.mv");
- end
+ decode_cr_insn("c.add");
end
end else begin
- // use casex instead of case inside due to ModelSim bug
- unique casex (instr_i)
- // C0 Opcodes
- INSTR_CADDI4SPN: trace.printCIWInstr("c.addi4spn");
- INSTR_CLW: trace.printCompressedLoadInstr("c.lw");
- INSTR_CSW: trace.printCompressedStoreInstr("c.sw");
- // C1 Opcodes
- INSTR_CADDI: trace.printCIInstr("c.addi");
- INSTR_CJAL: trace.printCJInstr("c.jal");
- INSTR_CJ: trace.printCJInstr("c.j");
- INSTR_CLI: trace.printCIInstr("c.li");
- INSTR_CLUI: trace.printCIInstr("c.lui");
- INSTR_CSRLI: trace.printCBInstr("c.srli");
- INSTR_CSRAI: trace.printCBInstr("c.srai");
- INSTR_CANDI: trace.printCBInstr("c.andi");
- INSTR_CSUB: trace.printCSInstr("c.sub");
- INSTR_CXOR: trace.printCSInstr("c.xor");
- INSTR_COR: trace.printCSInstr("c.or");
- INSTR_CAND: trace.printCSInstr("c.and");
- INSTR_CBEQZ: trace.printCBInstr("c.beqz");
- INSTR_CBNEZ: trace.printCBInstr("c.bnez");
- // C2 Opcodes
- INSTR_CSLLI: trace.printCIInstr("c.slli");
- INSTR_CLWSP: trace.printCompressedLoadInstr("c.lwsp");
- INSTR_SWSP: trace.printCompressedStoreInstr("c.swsp");
- default: trace.printMnemonic("INVALID");
- endcase // unique casex (instr_i)
+ if (rvfi_insn[6:2] == 5'h0) begin
+ decode_cr_insn("c.jr");
+ end else begin
+ decode_cr_insn("c.mv");
+ end
end
- end else if (instr_i == 32'h00_00_00_13) begin
- // separate case for 'nop' instruction to avoid overlapping with 'addi'
- trace.printMnemonic("nop");
end else begin
- // use casex instead of case inside due to ModelSim bug
- unique casex (instr_i)
- // Regular opcodes
- INSTR_LUI: trace.printUInstr("lui");
- INSTR_AUIPC: trace.printUInstr("auipc");
- INSTR_JAL: trace.printUJInstr("jal");
- INSTR_JALR: trace.printIInstr("jalr");
- // BRANCH
- INSTR_BEQ: trace.printSBInstr("beq");
- INSTR_BNE: trace.printSBInstr("bne");
- INSTR_BLT: trace.printSBInstr("blt");
- INSTR_BGE: trace.printSBInstr("bge");
- INSTR_BLTU: trace.printSBInstr("bltu");
- INSTR_BGEU: trace.printSBInstr("bgeu");
- // OPIMM
- INSTR_ADDI: trace.printIInstr("addi");
- INSTR_SLTI: trace.printIInstr("slti");
- INSTR_SLTIU: trace.printIInstr("sltiu");
- INSTR_XORI: trace.printIInstr("xori");
- INSTR_ORI: trace.printIInstr("ori");
- INSTR_ANDI: trace.printIInstr("andi");
- INSTR_SLLI: trace.printIuInstr("slli");
- INSTR_SRLI: trace.printIuInstr("srli");
- INSTR_SRAI: trace.printIuInstr("srai");
- // OP
- INSTR_ADD: trace.printRInstr("add");
- INSTR_SUB: trace.printRInstr("sub");
- INSTR_SLL: trace.printRInstr("sll");
- INSTR_SLT: trace.printRInstr("slt");
- INSTR_SLTU: trace.printRInstr("sltu");
- INSTR_XOR: trace.printRInstr("xor");
- INSTR_SRL: trace.printRInstr("srl");
- INSTR_SRA: trace.printRInstr("sra");
- INSTR_OR: trace.printRInstr("or");
- INSTR_AND: trace.printRInstr("and");
- // SYSTEM (CSR manipulation)
- INSTR_CSRRW: trace.printCSRInstr("csrrw");
- INSTR_CSRRS: trace.printCSRInstr("csrrs");
- INSTR_CSRRC: trace.printCSRInstr("csrrc");
- INSTR_CSRRWI: trace.printCSRInstr("csrrwi");
- INSTR_CSRRSI: trace.printCSRInstr("csrrsi");
- INSTR_CSRRCI: trace.printCSRInstr("csrrci");
- // SYSTEM (others)
- INSTR_ECALL: trace.printMnemonic("ecall");
- INSTR_EBREAK: trace.printMnemonic("ebreak");
- INSTR_MRET: trace.printMnemonic("mret");
- INSTR_DRET: trace.printMnemonic("dret");
- INSTR_WFI: trace.printMnemonic("wfi");
- // RV32M
- INSTR_PMUL: trace.printRInstr("mul");
- INSTR_PMUH: trace.printRInstr("mulh");
- INSTR_PMULHSU: trace.printRInstr("mulhsu");
- INSTR_PMULHU: trace.printRInstr("mulhu");
- INSTR_DIV: trace.printRInstr("div");
- INSTR_DIVU: trace.printRInstr("divu");
- INSTR_REM: trace.printRInstr("rem");
- INSTR_REMU: trace.printRInstr("remu");
- // LOAD & STORE
- INSTR_LOAD: trace.printLoadInstr();
- INSTR_STORE: trace.printStoreInstr();
- // MISC-MEM
- INSTR_FENCE: trace.printMnemonic("fence");
- default: trace.printMnemonic("INVALID");
- endcase // unique case (instr_i)
+ unique casez (rvfi_insn[15:0])
+ // C0 Opcodes
+ INSN_CADDI4SPN: decode_ciw_insn("c.addi4spn");
+ INSN_CLW: decode_compressed_load_insn("c.lw");
+ INSN_CSW: decode_compressed_store_insn("c.sw");
+ // C1 Opcodes
+ INSN_CADDI: decode_ci_caddi_insn("c.addi");
+ INSN_CJAL: decode_cj_insn("c.jal");
+ INSN_CJ: decode_cj_insn("c.j");
+ INSN_CLI: decode_ci_cli_insn("c.li");
+ INSN_CLUI: begin
+ // These two instructions share opcode
+ if (rvfi_insn[11:7] == 5'd2) begin
+ decode_ci_caddi16sp_insn("c.addi16sp");
+ end else begin
+ decode_ci_clui_insn("c.lui");
+ end
+ end
+ INSN_CSRLI: decode_cb_sr_insn("c.srli");
+ INSN_CSRAI: decode_cb_sr_insn("c.srai");
+ INSN_CANDI: decode_cb_insn("c.andi");
+ INSN_CSUB: decode_cs_insn("c.sub");
+ INSN_CXOR: decode_cs_insn("c.xor");
+ INSN_COR: decode_cs_insn("c.or");
+ INSN_CAND: decode_cs_insn("c.and");
+ INSN_CBEQZ: decode_cb_insn("c.beqz");
+ INSN_CBNEZ: decode_cb_insn("c.bnez");
+ // C2 Opcodes
+ INSN_CSLLI: decode_ci_cslli_insn("c.slli");
+ INSN_CLWSP: decode_compressed_load_insn("c.lwsp");
+ INSN_SWSP: decode_compressed_store_insn("c.swsp");
+ default: decode_mnemonic("INVALID");
+ endcase
end
-
- // replace register written back
- foreach(trace.regs_write[i]) begin
- if ((trace.regs_write[i].addr == ex_reg_addr_i)) begin
- trace.regs_write[i].value = ex_reg_wdata_i;
+ end else begin
+ unique casez (rvfi_insn)
+ // Regular opcodes
+ INSN_LUI: decode_u_insn("lui");
+ INSN_AUIPC: decode_u_insn("auipc");
+ INSN_JAL: decode_j_insn("jal");
+ INSN_JALR: decode_i_jalr_insn("jalr");
+ // BRANCH
+ INSN_BEQ: decode_b_insn("beq");
+ INSN_BNE: decode_b_insn("bne");
+ INSN_BLT: decode_b_insn("blt");
+ INSN_BGE: decode_b_insn("bge");
+ INSN_BLTU: decode_b_insn("bltu");
+ INSN_BGEU: decode_b_insn("bgeu");
+ // OPIMM
+ INSN_ADDI: begin
+ if (rvfi_insn == 32'h00_00_00_13) begin
+ // TODO: objdump doesn't decode this as nop currently, even though it would be helpful
+ // Decide what to do here: diverge from objdump, or make the trace less readable to
+ // users.
+ //decode_mnemonic("nop");
+ decode_i_insn("addi");
+ end else begin
+ decode_i_insn("addi");
+ end
end
- end
-
- trace.printInstrTrace();
+ INSN_SLTI: decode_i_insn("slti");
+ INSN_SLTIU: decode_i_insn("sltiu");
+ INSN_XORI: decode_i_insn("xori");
+ INSN_ORI: decode_i_insn("ori");
+ INSN_ANDI: decode_i_insn("andi");
+ INSN_SLLI: decode_i_shift_insn("slli");
+ INSN_SRLI: decode_i_shift_insn("srli");
+ INSN_SRAI: decode_i_shift_insn("srai");
+ // OP
+ INSN_ADD: decode_r_insn("add");
+ INSN_SUB: decode_r_insn("sub");
+ INSN_SLL: decode_r_insn("sll");
+ INSN_SLT: decode_r_insn("slt");
+ INSN_SLTU: decode_r_insn("sltu");
+ INSN_XOR: decode_r_insn("xor");
+ INSN_SRL: decode_r_insn("srl");
+ INSN_SRA: decode_r_insn("sra");
+ INSN_OR: decode_r_insn("or");
+ INSN_AND: decode_r_insn("and");
+ // SYSTEM (CSR manipulation)
+ INSN_CSRRW: decode_csr_insn("csrrw");
+ INSN_CSRRS: decode_csr_insn("csrrs");
+ INSN_CSRRC: decode_csr_insn("csrrc");
+ INSN_CSRRWI: decode_csr_insn("csrrwi");
+ INSN_CSRRSI: decode_csr_insn("csrrsi");
+ INSN_CSRRCI: decode_csr_insn("csrrci");
+ // SYSTEM (others)
+ INSN_ECALL: decode_mnemonic("ecall");
+ INSN_EBREAK: decode_mnemonic("ebreak");
+ INSN_MRET: decode_mnemonic("mret");
+ INSN_DRET: decode_mnemonic("dret");
+ INSN_WFI: decode_mnemonic("wfi");
+ // RV32M
+ INSN_PMUL: decode_r_insn("mul");
+ INSN_PMUH: decode_r_insn("mulh");
+ INSN_PMULHSU: decode_r_insn("mulhsu");
+ INSN_PMULHU: decode_r_insn("mulhu");
+ INSN_DIV: decode_r_insn("div");
+ INSN_DIVU: decode_r_insn("divu");
+ INSN_REM: decode_r_insn("rem");
+ INSN_REMU: decode_r_insn("remu");
+ // LOAD & STORE
+ INSN_LOAD: decode_load_insn();
+ INSN_STORE: decode_store_insn();
+ // MISC-MEM
+ INSN_FENCE: decode_fence();
+ INSN_FENCEI: decode_mnemonic("fence.i");
+ default: decode_mnemonic("INVALID");
+ endcase
end
- end // always @ (posedge clk_i)
+ end
endmodule
-
-`undef REG_S1
-`undef REG_S2
-`undef REG_S3
-`undef REG_D
diff --git a/hw/vendor/lowrisc_ibex/rtl/ibex_tracer_pkg.sv b/hw/vendor/lowrisc_ibex/rtl/ibex_tracer_pkg.sv
index d834d2f..9527091 100644
--- a/hw/vendor/lowrisc_ibex/rtl/ibex_tracer_pkg.sv
+++ b/hw/vendor/lowrisc_ibex/rtl/ibex_tracer_pkg.sv
@@ -11,100 +11,104 @@
parameter logic [1:0] OPCODE_C2 = 2'b10;
// instruction masks (for tracer)
-parameter logic [31:0] INSTR_LUI = { 25'b?, {OPCODE_LUI } };
-parameter logic [31:0] INSTR_AUIPC = { 25'b?, {OPCODE_AUIPC} };
-parameter logic [31:0] INSTR_JAL = { 25'b?, {OPCODE_JAL } };
-parameter logic [31:0] INSTR_JALR = { 17'b?, 3'b000, 5'b?, {OPCODE_JALR } };
+parameter logic [31:0] INSN_LUI = { 25'b?, {OPCODE_LUI } };
+parameter logic [31:0] INSN_AUIPC = { 25'b?, {OPCODE_AUIPC} };
+parameter logic [31:0] INSN_JAL = { 25'b?, {OPCODE_JAL } };
+parameter logic [31:0] INSN_JALR = { 17'b?, 3'b000, 5'b?, {OPCODE_JALR } };
+
// BRANCH
-parameter logic [31:0] INSTR_BEQ = { 17'b?, 3'b000, 5'b?, {OPCODE_BRANCH} };
-parameter logic [31:0] INSTR_BNE = { 17'b?, 3'b001, 5'b?, {OPCODE_BRANCH} };
-parameter logic [31:0] INSTR_BLT = { 17'b?, 3'b100, 5'b?, {OPCODE_BRANCH} };
-parameter logic [31:0] INSTR_BGE = { 17'b?, 3'b101, 5'b?, {OPCODE_BRANCH} };
-parameter logic [31:0] INSTR_BLTU = { 17'b?, 3'b110, 5'b?, {OPCODE_BRANCH} };
-parameter logic [31:0] INSTR_BGEU = { 17'b?, 3'b111, 5'b?, {OPCODE_BRANCH} };
-parameter logic [31:0] INSTR_BALL = { 17'b?, 3'b010, 5'b?, {OPCODE_BRANCH} };
+parameter logic [31:0] INSN_BEQ = { 17'b?, 3'b000, 5'b?, {OPCODE_BRANCH} };
+parameter logic [31:0] INSN_BNE = { 17'b?, 3'b001, 5'b?, {OPCODE_BRANCH} };
+parameter logic [31:0] INSN_BLT = { 17'b?, 3'b100, 5'b?, {OPCODE_BRANCH} };
+parameter logic [31:0] INSN_BGE = { 17'b?, 3'b101, 5'b?, {OPCODE_BRANCH} };
+parameter logic [31:0] INSN_BLTU = { 17'b?, 3'b110, 5'b?, {OPCODE_BRANCH} };
+parameter logic [31:0] INSN_BGEU = { 17'b?, 3'b111, 5'b?, {OPCODE_BRANCH} };
+parameter logic [31:0] INSN_BALL = { 17'b?, 3'b010, 5'b?, {OPCODE_BRANCH} };
+
// OPIMM
-parameter logic [31:0] INSTR_ADDI = { 17'b?, 3'b000, 5'b?, {OPCODE_OP_IMM} };
-parameter logic [31:0] INSTR_SLTI = { 17'b?, 3'b010, 5'b?, {OPCODE_OP_IMM} };
-parameter logic [31:0] INSTR_SLTIU = { 17'b?, 3'b011, 5'b?, {OPCODE_OP_IMM} };
-parameter logic [31:0] INSTR_XORI = { 17'b?, 3'b100, 5'b?, {OPCODE_OP_IMM} };
-parameter logic [31:0] INSTR_ORI = { 17'b?, 3'b110, 5'b?, {OPCODE_OP_IMM} };
-parameter logic [31:0] INSTR_ANDI = { 17'b?, 3'b111, 5'b?, {OPCODE_OP_IMM} };
-parameter logic [31:0] INSTR_SLLI = { 7'b0000000, 10'b?, 3'b001, 5'b?, {OPCODE_OP_IMM} };
-parameter logic [31:0] INSTR_SRLI = { 7'b0000000, 10'b?, 3'b101, 5'b?, {OPCODE_OP_IMM} };
-parameter logic [31:0] INSTR_SRAI = { 7'b0100000, 10'b?, 3'b101, 5'b?, {OPCODE_OP_IMM} };
+parameter logic [31:0] INSN_ADDI = { 17'b?, 3'b000, 5'b?, {OPCODE_OP_IMM} };
+parameter logic [31:0] INSN_SLTI = { 17'b?, 3'b010, 5'b?, {OPCODE_OP_IMM} };
+parameter logic [31:0] INSN_SLTIU = { 17'b?, 3'b011, 5'b?, {OPCODE_OP_IMM} };
+parameter logic [31:0] INSN_XORI = { 17'b?, 3'b100, 5'b?, {OPCODE_OP_IMM} };
+parameter logic [31:0] INSN_ORI = { 17'b?, 3'b110, 5'b?, {OPCODE_OP_IMM} };
+parameter logic [31:0] INSN_ANDI = { 17'b?, 3'b111, 5'b?, {OPCODE_OP_IMM} };
+parameter logic [31:0] INSN_SLLI = { 7'b0000000, 10'b?, 3'b001, 5'b?, {OPCODE_OP_IMM} };
+parameter logic [31:0] INSN_SRLI = { 7'b0000000, 10'b?, 3'b101, 5'b?, {OPCODE_OP_IMM} };
+parameter logic [31:0] INSN_SRAI = { 7'b0100000, 10'b?, 3'b101, 5'b?, {OPCODE_OP_IMM} };
+
// OP
-parameter logic [31:0] INSTR_ADD = { 7'b0000000, 10'b?, 3'b000, 5'b?, {OPCODE_OP} };
-parameter logic [31:0] INSTR_SUB = { 7'b0100000, 10'b?, 3'b000, 5'b?, {OPCODE_OP} };
-parameter logic [31:0] INSTR_SLL = { 7'b0000000, 10'b?, 3'b001, 5'b?, {OPCODE_OP} };
-parameter logic [31:0] INSTR_SLT = { 7'b0000000, 10'b?, 3'b010, 5'b?, {OPCODE_OP} };
-parameter logic [31:0] INSTR_SLTU = { 7'b0000000, 10'b?, 3'b011, 5'b?, {OPCODE_OP} };
-parameter logic [31:0] INSTR_XOR = { 7'b0000000, 10'b?, 3'b100, 5'b?, {OPCODE_OP} };
-parameter logic [31:0] INSTR_SRL = { 7'b0000000, 10'b?, 3'b101, 5'b?, {OPCODE_OP} };
-parameter logic [31:0] INSTR_SRA = { 7'b0100000, 10'b?, 3'b101, 5'b?, {OPCODE_OP} };
-parameter logic [31:0] INSTR_OR = { 7'b0000000, 10'b?, 3'b110, 5'b?, {OPCODE_OP} };
-parameter logic [31:0] INSTR_AND = { 7'b0000000, 10'b?, 3'b111, 5'b?, {OPCODE_OP} };
+parameter logic [31:0] INSN_ADD = { 7'b0000000, 10'b?, 3'b000, 5'b?, {OPCODE_OP} };
+parameter logic [31:0] INSN_SUB = { 7'b0100000, 10'b?, 3'b000, 5'b?, {OPCODE_OP} };
+parameter logic [31:0] INSN_SLL = { 7'b0000000, 10'b?, 3'b001, 5'b?, {OPCODE_OP} };
+parameter logic [31:0] INSN_SLT = { 7'b0000000, 10'b?, 3'b010, 5'b?, {OPCODE_OP} };
+parameter logic [31:0] INSN_SLTU = { 7'b0000000, 10'b?, 3'b011, 5'b?, {OPCODE_OP} };
+parameter logic [31:0] INSN_XOR = { 7'b0000000, 10'b?, 3'b100, 5'b?, {OPCODE_OP} };
+parameter logic [31:0] INSN_SRL = { 7'b0000000, 10'b?, 3'b101, 5'b?, {OPCODE_OP} };
+parameter logic [31:0] INSN_SRA = { 7'b0100000, 10'b?, 3'b101, 5'b?, {OPCODE_OP} };
+parameter logic [31:0] INSN_OR = { 7'b0000000, 10'b?, 3'b110, 5'b?, {OPCODE_OP} };
+parameter logic [31:0] INSN_AND = { 7'b0000000, 10'b?, 3'b111, 5'b?, {OPCODE_OP} };
// SYSTEM
-parameter logic [31:0] INSTR_CSRRW = { 17'b?, 3'b001, 5'b?, {OPCODE_SYSTEM} };
-parameter logic [31:0] INSTR_CSRRS = { 17'b?, 3'b010, 5'b?, {OPCODE_SYSTEM} };
-parameter logic [31:0] INSTR_CSRRC = { 17'b?, 3'b011, 5'b?, {OPCODE_SYSTEM} };
-parameter logic [31:0] INSTR_CSRRWI = { 17'b?, 3'b101, 5'b?, {OPCODE_SYSTEM} };
-parameter logic [31:0] INSTR_CSRRSI = { 17'b?, 3'b110, 5'b?, {OPCODE_SYSTEM} };
-parameter logic [31:0] INSTR_CSRRCI = { 17'b?, 3'b111, 5'b?, {OPCODE_SYSTEM} };
-parameter logic [31:0] INSTR_ECALL = { 12'b000000000000, 13'b0, {OPCODE_SYSTEM} };
-parameter logic [31:0] INSTR_EBREAK = { 12'b000000000001, 13'b0, {OPCODE_SYSTEM} };
-parameter logic [31:0] INSTR_MRET = { 12'b001100000010, 13'b0, {OPCODE_SYSTEM} };
-parameter logic [31:0] INSTR_DRET = { 12'b011110110010, 13'b0, {OPCODE_SYSTEM} };
-parameter logic [31:0] INSTR_WFI = { 12'b000100000101, 13'b0, {OPCODE_SYSTEM} };
+parameter logic [31:0] INSN_CSRRW = { 17'b?, 3'b001, 5'b?, {OPCODE_SYSTEM} };
+parameter logic [31:0] INSN_CSRRS = { 17'b?, 3'b010, 5'b?, {OPCODE_SYSTEM} };
+parameter logic [31:0] INSN_CSRRC = { 17'b?, 3'b011, 5'b?, {OPCODE_SYSTEM} };
+parameter logic [31:0] INSN_CSRRWI = { 17'b?, 3'b101, 5'b?, {OPCODE_SYSTEM} };
+parameter logic [31:0] INSN_CSRRSI = { 17'b?, 3'b110, 5'b?, {OPCODE_SYSTEM} };
+parameter logic [31:0] INSN_CSRRCI = { 17'b?, 3'b111, 5'b?, {OPCODE_SYSTEM} };
+parameter logic [31:0] INSN_ECALL = { 12'b000000000000, 13'b0, {OPCODE_SYSTEM} };
+parameter logic [31:0] INSN_EBREAK = { 12'b000000000001, 13'b0, {OPCODE_SYSTEM} };
+parameter logic [31:0] INSN_MRET = { 12'b001100000010, 13'b0, {OPCODE_SYSTEM} };
+parameter logic [31:0] INSN_DRET = { 12'b011110110010, 13'b0, {OPCODE_SYSTEM} };
+parameter logic [31:0] INSN_WFI = { 12'b000100000101, 13'b0, {OPCODE_SYSTEM} };
// RV32M
-parameter logic [31:0] INSTR_DIV = { 7'b0000001, 10'b?, 3'b100, 5'b?, {OPCODE_OP} };
-parameter logic [31:0] INSTR_DIVU = { 7'b0000001, 10'b?, 3'b101, 5'b?, {OPCODE_OP} };
-parameter logic [31:0] INSTR_REM = { 7'b0000001, 10'b?, 3'b110, 5'b?, {OPCODE_OP} };
-parameter logic [31:0] INSTR_REMU = { 7'b0000001, 10'b?, 3'b111, 5'b?, {OPCODE_OP} };
-parameter logic [31:0] INSTR_PMUL = { 7'b0000001, 10'b?, 3'b000, 5'b?, {OPCODE_OP} };
-parameter logic [31:0] INSTR_PMUH = { 7'b0000001, 10'b?, 3'b001, 5'b?, {OPCODE_OP} };
-parameter logic [31:0] INSTR_PMULHSU = { 7'b0000001, 10'b?, 3'b010, 5'b?, {OPCODE_OP} };
-parameter logic [31:0] INSTR_PMULHU = { 7'b0000001, 10'b?, 3'b011, 5'b?, {OPCODE_OP} };
+parameter logic [31:0] INSN_DIV = { 7'b0000001, 10'b?, 3'b100, 5'b?, {OPCODE_OP} };
+parameter logic [31:0] INSN_DIVU = { 7'b0000001, 10'b?, 3'b101, 5'b?, {OPCODE_OP} };
+parameter logic [31:0] INSN_REM = { 7'b0000001, 10'b?, 3'b110, 5'b?, {OPCODE_OP} };
+parameter logic [31:0] INSN_REMU = { 7'b0000001, 10'b?, 3'b111, 5'b?, {OPCODE_OP} };
+parameter logic [31:0] INSN_PMUL = { 7'b0000001, 10'b?, 3'b000, 5'b?, {OPCODE_OP} };
+parameter logic [31:0] INSN_PMUH = { 7'b0000001, 10'b?, 3'b001, 5'b?, {OPCODE_OP} };
+parameter logic [31:0] INSN_PMULHSU = { 7'b0000001, 10'b?, 3'b010, 5'b?, {OPCODE_OP} };
+parameter logic [31:0] INSN_PMULHU = { 7'b0000001, 10'b?, 3'b011, 5'b?, {OPCODE_OP} };
// LOAD & STORE
-parameter logic [31:0] INSTR_LOAD = {25'b?, {OPCODE_LOAD } };
-parameter logic [31:0] INSTR_STORE = {25'b?, {OPCODE_STORE} };
+parameter logic [31:0] INSN_LOAD = {25'b?, {OPCODE_LOAD } };
+parameter logic [31:0] INSN_STORE = {25'b?, {OPCODE_STORE} };
// MISC-MEM
-parameter logic [31:0] INSTR_FENCE = { 17'b?, 3'b000, 5'b?, {OPCODE_MISC_MEM} };
+parameter logic [31:0] INSN_FENCE = { 17'b?, 3'b000, 5'b?, {OPCODE_MISC_MEM} };
+parameter logic [31:0] INSN_FENCEI = { 17'b0, 3'b001, 5'b0, {OPCODE_MISC_MEM} };
// Compressed Instructions
// C0
-parameter logic [15:0] INSTR_CADDI4SPN = { 3'b000, 11'b?, {OPCODE_C0} };
-parameter logic [15:0] INSTR_CLW = { 3'b010, 11'b?, {OPCODE_C0} };
-parameter logic [15:0] INSTR_CSW = { 3'b110, 11'b?, {OPCODE_C0} };
+parameter logic [15:0] INSN_CADDI4SPN = { 3'b000, 11'b?, {OPCODE_C0} };
+parameter logic [15:0] INSN_CLW = { 3'b010, 11'b?, {OPCODE_C0} };
+parameter logic [15:0] INSN_CSW = { 3'b110, 11'b?, {OPCODE_C0} };
// C1
-parameter logic [15:0] INSTR_CADDI = { 3'b000, 11'b?, {OPCODE_C1} };
-parameter logic [15:0] INSTR_CJAL = { 3'b001, 11'b?, {OPCODE_C1} };
-parameter logic [15:0] INSTR_CJ = { 3'b101, 11'b?, {OPCODE_C1} };
-parameter logic [15:0] INSTR_CLI = { 3'b010, 11'b?, {OPCODE_C1} };
-parameter logic [15:0] INSTR_CLUI = { 3'b011, 11'b?, {OPCODE_C1} };
-parameter logic [15:0] INSTR_CBEQZ = { 3'b110, 11'b?, {OPCODE_C1} };
-parameter logic [15:0] INSTR_CBNEZ = { 3'b111, 11'b?, {OPCODE_C1} };
-parameter logic [15:0] INSTR_CSRLI = { 3'b100, 1'b?, 2'b00, 8'b?, {OPCODE_C1} };
-parameter logic [15:0] INSTR_CSRAI = { 3'b100, 1'b?, 2'b01, 8'b?, {OPCODE_C1} };
-parameter logic [15:0] INSTR_CANDI = { 3'b100, 1'b?, 2'b10, 8'b?, {OPCODE_C1} };
-parameter logic [15:0] INSTR_CSUB = { 3'b100, 1'b0, 2'b11, 3'b?, 2'b00, 3'b?, {OPCODE_C1} };
-parameter logic [15:0] INSTR_CXOR = { 3'b100, 1'b0, 2'b11, 3'b?, 2'b01, 3'b?, {OPCODE_C1} };
-parameter logic [15:0] INSTR_COR = { 3'b100, 1'b0, 2'b11, 3'b?, 2'b10, 3'b?, {OPCODE_C1} };
-parameter logic [15:0] INSTR_CAND = { 3'b100, 1'b0, 2'b11, 3'b?, 2'b11, 3'b?, {OPCODE_C1} };
+parameter logic [15:0] INSN_CADDI = { 3'b000, 11'b?, {OPCODE_C1} };
+parameter logic [15:0] INSN_CJAL = { 3'b001, 11'b?, {OPCODE_C1} };
+parameter logic [15:0] INSN_CJ = { 3'b101, 11'b?, {OPCODE_C1} };
+parameter logic [15:0] INSN_CLI = { 3'b010, 11'b?, {OPCODE_C1} };
+parameter logic [15:0] INSN_CLUI = { 3'b011, 11'b?, {OPCODE_C1} };
+parameter logic [15:0] INSN_CBEQZ = { 3'b110, 11'b?, {OPCODE_C1} };
+parameter logic [15:0] INSN_CBNEZ = { 3'b111, 11'b?, {OPCODE_C1} };
+parameter logic [15:0] INSN_CSRLI = { 3'b100, 1'b?, 2'b00, 8'b?, {OPCODE_C1} };
+parameter logic [15:0] INSN_CSRAI = { 3'b100, 1'b?, 2'b01, 8'b?, {OPCODE_C1} };
+parameter logic [15:0] INSN_CANDI = { 3'b100, 1'b?, 2'b10, 8'b?, {OPCODE_C1} };
+parameter logic [15:0] INSN_CSUB = { 3'b100, 1'b0, 2'b11, 3'b?, 2'b00, 3'b?, {OPCODE_C1} };
+parameter logic [15:0] INSN_CXOR = { 3'b100, 1'b0, 2'b11, 3'b?, 2'b01, 3'b?, {OPCODE_C1} };
+parameter logic [15:0] INSN_COR = { 3'b100, 1'b0, 2'b11, 3'b?, 2'b10, 3'b?, {OPCODE_C1} };
+parameter logic [15:0] INSN_CAND = { 3'b100, 1'b0, 2'b11, 3'b?, 2'b11, 3'b?, {OPCODE_C1} };
// C2
-parameter logic [15:0] INSTR_CSLLI = { 3'b000, 11'b?, {OPCODE_C2} };
-parameter logic [15:0] INSTR_CLWSP = { 3'b010, 11'b?, {OPCODE_C2} };
-parameter logic [15:0] INSTR_SWSP = { 3'b110, 11'b?, {OPCODE_C2} };
-parameter logic [15:0] INSTR_CMV = { 3'b100, 1'b0, 10'b?, {OPCODE_C2} };
-parameter logic [15:0] INSTR_CADD = { 3'b100, 1'b1, 10'b?, {OPCODE_C2} };
-parameter logic [15:0] INSTR_CEBREAK = { 3'b100, 1'b1, 5'b0, 5'b0, {OPCODE_C2} };
-parameter logic [15:0] INSTR_CJR = { 3'b100, 1'b0, 5'b?, 5'b0, {OPCODE_C2} };
-parameter logic [15:0] INSTR_CJALR = { 3'b100, 1'b1, 5'b?, 5'b0, {OPCODE_C2} };
+parameter logic [15:0] INSN_CSLLI = { 3'b000, 11'b?, {OPCODE_C2} };
+parameter logic [15:0] INSN_CLWSP = { 3'b010, 11'b?, {OPCODE_C2} };
+parameter logic [15:0] INSN_SWSP = { 3'b110, 11'b?, {OPCODE_C2} };
+parameter logic [15:0] INSN_CMV = { 3'b100, 1'b0, 10'b?, {OPCODE_C2} };
+parameter logic [15:0] INSN_CADD = { 3'b100, 1'b1, 10'b?, {OPCODE_C2} };
+parameter logic [15:0] INSN_CEBREAK = { 3'b100, 1'b1, 5'b0, 5'b0, {OPCODE_C2} };
+parameter logic [15:0] INSN_CJR = { 3'b100, 1'b0, 5'b?, 5'b0, {OPCODE_C2} };
+parameter logic [15:0] INSN_CJALR = { 3'b100, 1'b1, 5'b?, 5'b0, {OPCODE_C2} };
endpackage
diff --git a/hw/vendor/lowrisc_ibex/vendor/google_riscv-dv.lock.hjson b/hw/vendor/lowrisc_ibex/vendor/google_riscv-dv.lock.hjson
index b4e5d34..4852610 100644
--- a/hw/vendor/lowrisc_ibex/vendor/google_riscv-dv.lock.hjson
+++ b/hw/vendor/lowrisc_ibex/vendor/google_riscv-dv.lock.hjson
@@ -9,6 +9,6 @@
upstream:
{
url: https://github.com/google/riscv-dv
- rev: 102791dbb7eb992d3bc22336d2e4e5f0d688e761
+ rev: d3419444ca2fdb499a204587b2d36c6f5c1e0c44
}
}
diff --git a/hw/vendor/lowrisc_ibex/vendor/google_riscv-dv/README.md b/hw/vendor/lowrisc_ibex/vendor/google_riscv-dv/README.md
index 58d642f..3e72762 100644
--- a/hw/vendor/lowrisc_ibex/vendor/google_riscv-dv/README.md
+++ b/hw/vendor/lowrisc_ibex/vendor/google_riscv-dv/README.md
@@ -7,12 +7,16 @@
- Supported privileged mode: machine mode, supervisor mode, user mode
- Page table randomization and exception
- Privileged CSR setup randomization
+- Privileged CSR test suite
- Trap/interrupt handling
- Test suite to stress test MMU
- Support sub-programs and random program calls
- Support illegal instruction and HINT instruction
- Random forward/backward branch instructions
- Supports mixing directed instructions with random instruction stream
+- Debug mode support, with fully randomized debug ROM
+- Instruction generation coverage model
+- Communication of information to any integrated SV testbench
- Supports co-simulation with multiple ISS : spike, riscv-ovpsim
A CSR test generation script written in Python is also provided, to generate a
@@ -59,6 +63,7 @@
python3 run.py --test riscv_arithmetic_basic_test --simulator ius
python3 run.py --test riscv_arithmetic_basic_test --simulator vcs
python3 run.py --test riscv_arithmetic_basic_test --simulator questa
+python3 run.py --test riscv_arithmetic_basic_test --simulator dsim
```
The complete test list can be found in [yaml/testlist.yaml](https://github.com/google/riscv-dv/blob/master/yaml/testlist.yaml). To run a full
regression, simply use below command
@@ -77,22 +82,22 @@
```
// Run a single test 10 times
-python3 run.py --test riscv_page_table_exception_test --iterations 10
+python3 run.py --test riscv_arithmetic_basic_test --iterations 10
// Run a test with verbose logging
-python3 run.py --test riscv_page_table_exception_test --verbose
+python3 run.py --test riscv_arithmetic_basic_test --verbose
// Run a test with a specified seed
-python3 run.py --test riscv_page_table_exception_test --seed 123
+python3 run.py --test riscv_arithmetic_basic_test --seed 123
// Skip the generation, run ISS simulation with previously generated program
-python3 run.py --test riscv_page_table_exception_test --steps iss_sim
+python3 run.py --test riscv_arithmetic_basic_test --steps iss_sim
// Run the generator only, do not compile and simluation with ISS
-python3 run.py --test riscv_page_table_exception_test --steps gen
+python3 run.py --test riscv_arithmetic_basic_test --steps gen
// Compile the generator only, do not simulate
-python3 run.py --test riscv_page_table_exception_test --co
+python3 run.py --test riscv_arithmetic_basic_test --co
....
```
@@ -184,6 +189,37 @@
...
```
+### Setup the memory map
+
+Here's a few cases that you might want to allocate the instruction and data
+sections to match the actual memory map
+- The processor has internal memories, and you want to test load/store from
+ various internal/externel memory regions
+- The processor implments the PMP feature, and you want to configure the memory
+ map to match PMP setting.
+- Virtual address translation is implmented and you want to test load/store from
+ sparse memory locations to verify data TLB replacement logic.
+
+You can configure the memory map in [riscv_instr_gen_config.sv](https://github.com/google/riscv-dv/blob/master/src/riscv_instr_gen_config.sv)
+
+```
+ mem_region_t mem_region[$] = '{
+ '{name:"region_0", size_in_bytes: 4096, xwr: 3'b111},
+ '{name:"region_1", size_in_bytes: 4096 * 4, xwr: 3'b111},
+ '{name:"region_2", size_in_bytes: 4096 * 2, xwr: 3'b111},
+ '{name:"region_3", size_in_bytes: 512, xwr: 3'b111},
+ '{name:"region_4", size_in_bytes: 4096, xwr: 3'b111}
+ };
+```
+
+Each memory region belongs to a separate section in the generated assembly
+program. You can modify the link script to link each section to the target
+memory location. Please avoid setting a large memory range as it could takes a
+long time to randomly initializing the memory. You can break down a large memory
+region to a few representative small regions which covers all the boundary
+conditions for the load/store testing.
+
+
### Runtime options of the generator
| Option | Description | Default |
@@ -192,14 +228,16 @@
| num_of_sub_program | Number of sub-program in one test | 5 |
| instr_cnt | Instruction count per test | 200 |
| enable_page_table_exception | Enable page table exception | 0 |
+| enable_unaligned_load_store | Enable unaligned memory operations | 0 |
| no_ebreak | Disable ebreak instruction | 1 |
| no_wfi | Disable WFI instruction | 1 |
+| no_dret | Disable dret instruction | 1 |
| no_branch_jump | Disable branch/jump instruction | 0 |
| no_load_store | Disable load/store instruction | 0 |
| no_csr_instr | Disable CSR instruction | 0 |
| no_fence | Disable fence instruction | 0 |
-| enable_illegal_instruction | Enable illegal instructions | 0 |
-| enable_hint_instruction | Enable HINT instruction | 0 |
+| illegal_instr_ratio | Number of illegal instructions every 1000 instr | 0 |
+| hint_instr_ratio | Number of HINT instructions every 1000 instr | 0 |
| boot_mode | m:Machine mode, s:Supervisor mode, u:User mode | m |
| no_directed_instr | Disable directed instruction stream | 0 |
| require_signature_addr | Set to 1 if test needs to talk to testbench | 0 |
@@ -207,6 +245,9 @@
| enable_interrupt | Enable MStatus.MIE, used in interrupt test | 0 |
| gen_debug_section | Disables randomized debug_rom section | 0 |
| num_debug_sub_program | Number of debug sub-programs in test | 0 |
+| enable_ebreak_in_debug_rom | Generate ebreak instructions inside debug ROM | 0 |
+| set_dcsr_ebreak | Randomly enable dcsr.ebreak(m/s/u) | 0 |
+| randomize_csr | Fully randomize main CSRs (xSTATUS, xIE) | 0 |
### Setup Privileged CSR description
@@ -295,7 +336,7 @@
```
// Run ISS with spike
-python3 run.py --test riscv_page_table_exception_test --iss spike
+python3 run.py --test riscv_arithmetic_basic_test --iss spike
// Run ISS with riscv-ovpsim
python3 run.py --test riscv_rand_instr_test --iss ovpsim
@@ -336,16 +377,31 @@
Simulate with the new ISS
```
-python3 run.py --test riscv_page_table_exception_test --iss new_iss_name
+python3 run.py --test riscv_arithmetic_basic_test --iss new_iss_name
```
## End-to-end RTL and ISS co-simulation flow
We have collaborated with LowRISC to apply this flow for [IBEX RISC-V core
verification](https://github.com/lowRISC/ibex/blob/master/doc/verification.rst). You can use
-it as a reference to setup end-to-end co-simulation flow. It's also a good
-reference for [customizing the generator](https://github.com/lowRISC/ibex/tree/master/dv/uvm/riscv_dv_extension) without getting impacted by upstream
-changes.
+it as a reference to setup end-to-end co-simulation flow.
+This repo is still under active development, here's recommended approach to
+customize the instruction generator while keeping the minimum effort of merging
+upstream changes.
+- Do not modify the upstream classes directly. When possible, extending from
+ the upstream classses and implment your own functionalities.
+- Add your extensions under user_extension directory, and add the files to
+ user_extension/user_extension.svh. If you prefer to put your extensions in a
+ different directory, you can use "-ext <user_extension_path>" to override the
+ user extension path.
+- Create a new file for riscv_core_setting.sv, add the path with below option:
+ "-cs <new_core_setting_path>"
+- Use command line type override to use your extended classes.
+ --sim_opts="+uvm_set_type_override=<upstream_class>,<extended_class>"
+
+You can refer to [riscv-dv extension for ibex](https://github.com/lowRISC/ibex/blob/master/dv/uvm/Makefile#L68) for a working example.
+
+
We have plan to open-source the end-to-end environment of other advanced RISC-V
processors. Stay tuned!
@@ -362,14 +418,6 @@
verification platform. Free feel to submit your pull request for review.
Please refer to CONTRIBUTING.md for license related questions.
-## Future release plan
-
-We have some work in progress which will be part of future releases:
-
-- Privileged CSR test suite.
-- Coverage model.
-- Debug mode support
-
## Disclaimer
This is not an officially supported Google product.
diff --git a/hw/vendor/lowrisc_ibex/vendor/google_riscv-dv/cov.py b/hw/vendor/lowrisc_ibex/vendor/google_riscv-dv/cov.py
new file mode 100644
index 0000000..c7eccc7
--- /dev/null
+++ b/hw/vendor/lowrisc_ibex/vendor/google_riscv-dv/cov.py
@@ -0,0 +1,160 @@
+"""
+Copyright 2019 Google LLC
+
+Licensed under the Apache License, Version 2.0 (the "License");
+you may not use this file except in compliance with the License.
+You may obtain a copy of the License at
+
+ http://www.apache.org/licenses/LICENSE-2.0
+
+Unless required by applicable law or agreed to in writing, software
+distributed under the License is distributed on an "AS IS" BASIS,
+WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+See the License for the specific language governing permissions and
+limitations under the License.
+
+Regression script for RISC-V random instruction generator
+"""
+
+import argparse
+import os
+import subprocess
+import re
+import sys
+import logging
+
+from datetime import date
+from scripts.lib import *
+from scripts.spike_log_to_trace_csv import *
+from scripts.ovpsim_log_to_trace_csv import *
+from scripts.sail_log_to_trace_csv import *
+
+LOGGER = logging.getLogger()
+
+def collect_cov(log_dir, out, iss, testlist, batch_size, lsf_cmd, steps, opts, timeout):
+ """Collect functional coverage from the instruction trace
+
+ Args:
+ log_dir : ISS log directory
+ out : Output directory
+ iss : Instruction set simulator
+ test_list : Testlist of the coverage test
+ batch_size : Number of trace CSV to process per test
+ lsf_cmd : LSF command used to run the instruction generator
+ steps : csv:log to CSV, cov:sample coverage
+ opts : Additional options to the instruction generator
+ timeout : Timeout limit in seconds
+ """
+ log_list = []
+ csv_list = []
+ trace_log = ("%s/%s_trace_log" % (out, iss))
+ logging.info("Processing trace log under %s" % log_dir)
+ run_cmd("find %s -name \"*.log\" | sort > %s" % (log_dir, trace_log))
+ with open(trace_log) as f:
+ for line in f:
+ line = line.rstrip()
+ log_list.append(line)
+ csv = line[0:-4] + ".csv"
+ csv_list.append(csv)
+ if steps == "all" or re.match("csv", steps):
+ for i in range(len(log_list)):
+ log = log_list[i]
+ csv = csv_list[i]
+ logging.info("Process %0s log[%0d/%0d] : %s" % (iss, i+1, len(log_list), log))
+ if iss == "spike":
+ process_spike_sim_log(log, csv, 1)
+ else:
+ logging.error("Full trace for %s is not supported yet" % iss)
+ sys.exit(1)
+ if steps == "all" or re.match("cov", steps):
+ build_cmd = ("%s python3 run.py --co -o %s --cov -tl %s %s" %
+ (lsf_cmd, out, testlist, opts))
+ base_sim_cmd = ("%s python3 run.py --so -o %s --cov -tl %s %s "
+ "-tn riscv_instr_cov_test --steps gen --sim_opts \"<trace_csv_opts>\"" %
+ (lsf_cmd, out, testlist, opts))
+ run_cmd(build_cmd)
+ file_idx = 0
+ trace_idx = 0
+ trace_csv_opts = ""
+ batch_cnt = 1
+ sim_cmd_list = []
+ logging.info("Collecting functional coverage from %0d trace CSV" % len(csv_list))
+ if batch_size > 0:
+ batch_cnt = (len(csv_list)+batch_size-1)/batch_size;
+ logging.info("Batch size: %0d, Batch cnt:%0d" % (batch_size, batch_cnt))
+ for i in range(len(csv_list)):
+ if batch_size > 0:
+ file_idx = i / batch_size;
+ trace_idx = i % batch_size;
+ else:
+ file_idx = 0
+ trace_idx = i
+ trace_csv_opts += (" +trace_csv_%0d=%s" % (trace_idx, csv_list[i]))
+ if ((i == len(csv_list)-1) or ((batch_size > 0) and (trace_idx == batch_size-1))):
+ sim_cmd = base_sim_cmd.replace("<trace_csv_opts>", trace_csv_opts)
+ sim_cmd += (" --log_suffix _%d" % file_idx)
+ if lsf_cmd == "":
+ logging.info("Processing batch %0d/%0d" % (file_idx+1, batch_cnt))
+ run_cmd(sim_cmd)
+ else:
+ sim_cmd_list.append(sim_cmd)
+ trace_csv_opts = ""
+ if lsf_cmd != "":
+ run_parallel_cmd(sim_cmd_list, timeout)
+ logging.info("Collecting functional coverage from %0d trace CSV...done" % len(csv_list))
+
+
+def setup_parser():
+ """Create a command line parser.
+
+ Returns: The created parser.
+ """
+ # Parse input arguments
+ parser = argparse.ArgumentParser()
+ parser.add_argument("-o", "--output", type=str,
+ help="Output directory name", dest="o")
+ parser.add_argument("-v", "--verbose", dest="verbose", action="store_true",
+ help="Verbose logging")
+ parser.add_argument("--dir", type=str,
+ help="Directory of ISS log")
+ parser.add_argument("-bz", "--batch_size", dest="batch_size", type=int, default=0,
+ help="Number of CSV to process per run")
+ parser.add_argument("-to", "--timeout", dest="timeout", type=int, default=1000,
+ help="Number of CSV to process per run")
+ parser.add_argument("-s", "--steps", type=str, default="all",
+ help="Run steps: csv,cov", dest="steps")
+ parser.add_argument("--iss", type=str, default="spike",
+ help="RISC-V instruction set simulator: spike,ovpsim,sail")
+ parser.add_argument("-tl", "--testlist", type=str, default="",
+ help="Regression testlist", dest="testlist")
+ parser.add_argument("--opts", type=str, default="",
+ help="Additional options for the instruction generator")
+ parser.add_argument("--lsf_cmd", type=str, default="",
+ help="LSF command. Run in local sequentially if lsf \
+ command is not specified")
+ parser.set_defaults(verbose=False)
+ return parser
+
+def main():
+ """This is the main entry point."""
+ parser = setup_parser()
+ args = parser.parse_args()
+ cwd = os.path.dirname(os.path.realpath(__file__))
+ setup_logging(args.verbose)
+
+ if not args.testlist:
+ args.testlist = cwd + "/yaml/cov_testlist.yaml"
+
+ # Create output directory
+ if args.o is None:
+ output_dir = "out_" + str(date.today())
+ else:
+ output_dir = args.o
+
+ subprocess.run(["mkdir", "-p", output_dir])
+
+ collect_cov(args.dir, output_dir, args.iss, args.testlist, args.batch_size,
+ args.lsf_cmd, args.steps, args.opts, args.timeout)
+
+if __name__ == "__main__":
+ main()
diff --git a/hw/vendor/lowrisc_ibex/vendor/google_riscv-dv/files.f b/hw/vendor/lowrisc_ibex/vendor/google_riscv-dv/files.f
index 8722407..9945943 100644
--- a/hw/vendor/lowrisc_ibex/vendor/google_riscv-dv/files.f
+++ b/hw/vendor/lowrisc_ibex/vendor/google_riscv-dv/files.f
@@ -13,11 +13,11 @@
// limitations under the License.
// HEADERS
-+incdir+./src
-+incdir+./test
++incdir+${RISCV_DV_ROOT}/src
++incdir+${RISCV_DV_ROOT}/test
// SOURCES
-./src/riscv_signature_pkg.sv
-./src/riscv_instr_pkg.sv
-./test/riscv_instr_test_pkg.sv
-./test/riscv_instr_gen_tb_top.sv
+${RISCV_DV_ROOT}/src/riscv_signature_pkg.sv
+${RISCV_DV_ROOT}/src/riscv_instr_pkg.sv
+${RISCV_DV_ROOT}/test/riscv_instr_test_pkg.sv
+${RISCV_DV_ROOT}/test/riscv_instr_gen_tb_top.sv
diff --git a/hw/vendor/lowrisc_ibex/vendor/google_riscv-dv/run.py b/hw/vendor/lowrisc_ibex/vendor/google_riscv-dv/run.py
index 0da97d8..b01eadc 100644
--- a/hw/vendor/lowrisc_ibex/vendor/google_riscv-dv/run.py
+++ b/hw/vendor/lowrisc_ibex/vendor/google_riscv-dv/run.py
@@ -32,12 +32,13 @@
LOGGER = logging.getLogger()
-def get_generator_cmd(simulator, simulator_yaml):
+def get_generator_cmd(simulator, simulator_yaml, cov):
""" Setup the compile and simulation command for the generator
Args:
simulator : RTL simulator used to run instruction generator
simulator_yaml : RTL simulator configuration file in YAML format
+ cov : Enable functional coverage
Returns:
compile_cmd : RTL simulator command to compile the instruction generator
@@ -49,8 +50,23 @@
for entry in yaml_data:
if entry['tool'] == simulator:
logging.info("Found matching simulator: %s" % entry['tool'])
- compile_cmd = entry['compile_cmd']
- sim_cmd = entry['sim_cmd']
+ compile_spec = entry['compile']
+ compile_cmd = compile_spec['cmd']
+ for i in range(len(compile_cmd)):
+ if ('cov_opts' in compile_spec) and cov:
+ compile_cmd[i] = re.sub('<cov_opts>', compile_spec['cov_opts'].rstrip(), compile_cmd[i])
+ else:
+ compile_cmd[i] = re.sub('<cov_opts>', '', compile_cmd[i])
+ sim_cmd = entry['sim']['cmd']
+ if ('cov_opts' in entry['sim']) and cov:
+ sim_cmd = re.sub('<cov_opts>', entry['sim']['cov_opts'].rstrip(), sim_cmd)
+ else:
+ sim_cmd = re.sub('<cov_opts>', '', sim_cmd)
+ if 'env_var' in entry:
+ for env_var in entry['env_var'].split(','):
+ for i in range(len(compile_cmd)):
+ compile_cmd[i] = re.sub("<"+env_var+">", get_env_var(env_var), compile_cmd[i])
+ sim_cmd = re.sub("<"+env_var+">", get_env_var(env_var), sim_cmd)
return compile_cmd, sim_cmd
logging.error("Cannot find RTL simulator %0s" % simulator)
sys.exit(1)
@@ -102,7 +118,8 @@
def gen(test_list, csr_file, end_signature_addr, isa, simulator,
simulator_yaml, output_dir, sim_only, compile_only, lsf_cmd, seed,
- cwd, cmp_opts, sim_opts, timeout_s):
+ cwd, cmp_opts, sim_opts, timeout_s, core_setting_dir, ext_dir, cov,
+ log_suffix, batch_size):
"""Run the instruction generator
Args:
@@ -120,6 +137,11 @@
cmp_opts : Compile options for the generator
sim_opts : Simulation options for the generator
timeout_s : Timeout limit in seconds
+ core_setting_dir : Path for riscv_core_setting.sv
+ ext_dir : User extension directory
+ cov : Enable functional coverage
+ log_suffix : Simulation log file name suffix
+ batch_size : Number of tests to generate per run
"""
# Mutually exclusive options between compile_only and sim_only
if compile_only and sim_only:
@@ -127,8 +149,8 @@
# Setup the compile and simulation command for the generator
compile_cmd = []
sim_cmd = ""
- compile_cmd, sim_cmd = get_generator_cmd(simulator, simulator_yaml);
- if len(test_list) == 0:
+ compile_cmd, sim_cmd = get_generator_cmd(simulator, simulator_yaml, cov);
+ if ((compile_only == 0) and (len(test_list) == 0)):
return
# Compile the instruction generator
if not sim_only:
@@ -136,8 +158,17 @@
logging.info("Building RISC-V instruction generator")
for cmd in compile_cmd:
cmd = re.sub("<out>", os.path.abspath(output_dir), cmd)
+ if core_setting_dir == "":
+ cmd = re.sub("<setting>", "<cwd>/setting", cmd)
+ else:
+ cmd = re.sub("<setting>", core_setting_dir, cmd)
+ if ext_dir == "":
+ cmd = re.sub("<user_extension>", "<cwd>/user_extension", cmd)
+ else:
+ cmd = re.sub("<user_extension>", ext_dir, cmd)
cmd = re.sub("<cwd>", cwd, cmd)
cmd = re.sub("<cmp_opts>", cmp_opts, cmd)
+
logging.debug("Compile command: %s" % cmd)
logging.debug(run_cmd(cmd))
# Run the instruction generator
@@ -149,6 +180,7 @@
logging.info("Running RISC-V instruction generator")
for test in test_list:
iterations = test['iterations']
+ logging.info("Generating %d %s" % (iterations, test['test']))
if iterations > 0:
"""
If we are running a CSR test, need to call a separate python script
@@ -161,23 +193,39 @@
(" --iterations %i" % iterations) + \
(" --out %s/asm_tests" % output_dir) + \
(" --end_signature_addr %s" % end_signature_addr)
+ if lsf_cmd:
+ cmd_list.append(cmd)
+ else:
+ run_cmd(cmd, timeout_s)
else:
- rand_seed = get_seed(seed)
- cmd = lsf_cmd + " " + sim_cmd.rstrip() + \
- (" +UVM_TESTNAME=%s " % test['gen_test']) + \
- (" +num_of_tests=%i " % iterations) + \
- (" +asm_file_name=%s/asm_tests/%s " % (output_dir, test['test'])) + \
- (" -l %s/sim_%s.log " % (output_dir, test['test']))
- cmd = re.sub("<seed>", str(rand_seed), cmd)
- if "gen_opts" in test:
- cmd += test['gen_opts']
- if not re.search("c", isa):
- cmd += "+disable_comparessed_instr=1";
- logging.info("Generating %d %s" % (iterations, test['test']))
- if lsf_cmd:
- cmd_list.append(cmd)
- else:
- run_cmd(cmd, timeout_s)
+ if batch_size > 0:
+ batch_cnt = int((iterations + batch_size - 1) / batch_size);
+ else:
+ batch_cnt = 1
+ logging.info("Running %s with %0d batches" % (test['test'], batch_cnt))
+ for i in range(0, batch_cnt):
+ rand_seed = get_seed(seed)
+ if i < batch_cnt - 1:
+ test_cnt = batch_size
+ else:
+ test_cnt = iterations - i * batch_size;
+ cmd = lsf_cmd + " " + sim_cmd.rstrip() + \
+ (" +UVM_TESTNAME=%s " % test['gen_test']) + \
+ (" +num_of_tests=%i " % test_cnt) + \
+ (" +start_idx=%d " % (i*batch_size)) + \
+ (" +asm_file_name=%s/asm_tests/%s " % (output_dir, test['test'])) + \
+ (" -l %s/sim_%s_%d%s.log " % (output_dir, test['test'], i, log_suffix))
+ cmd = re.sub("<seed>", str(rand_seed), cmd)
+ if "gen_opts" in test:
+ cmd += test['gen_opts']
+ if not re.search("c", isa):
+ cmd += "+disable_comparessed_instr=1";
+ if lsf_cmd:
+ cmd_list.append(cmd)
+ else:
+ logging.info("Running %s, batch %0d/%0d, test_cnt:%0d" %
+ (test['test'], i+1, batch_cnt, test_cnt))
+ run_cmd(cmd, timeout_s)
if lsf_cmd:
run_parallel_cmd(cmd_list, timeout_s)
@@ -193,7 +241,9 @@
"""
for test in test_list:
for i in range(0, test['iterations']):
- prefix = ("%s/asm_tests/%s.%d" % (output_dir, test['test'], i))
+ if 'no_gcc' in test and test['no_gcc'] == 1:
+ continue
+ prefix = ("%s/asm_tests/%s_%d" % (output_dir, test['test'], i))
asm = prefix + ".S"
elf = prefix + ".o"
binary = prefix + ".bin"
@@ -201,8 +251,10 @@
cmd = ("%s -static -mcmodel=medany \
-fvisibility=hidden -nostdlib \
-nostartfiles %s \
- -Tscripts/link.ld %s -o %s " % \
- (get_env_var("RISCV_GCC"), asm, opts, elf))
+ -I%s/user_extension \
+ -T%s/scripts/link.ld %s -o %s " % \
+ (get_env_var("RISCV_GCC"), asm, get_env_var("RISCV_DV_ROOT"),
+ get_env_var("RISCV_DV_ROOT"), opts, elf))
if 'gcc_opts' in test:
cmd += test['gcc_opts']
# If march/mabi is not defined in the test gcc_opts, use the default
@@ -222,6 +274,45 @@
logging.debug(output)
+def run_assembly(asm_test, iss_yaml, isa, mabi, iss):
+ """Run a directed assembly test with spike
+
+ Args:
+ asm_tset : Assembly test file
+ iss_yaml : ISS configuration file in YAML format
+ isa : ISA variant passed to the ISS
+ mabi : MABI variant passed to GCC
+ iss : Instruction set simulators
+ """
+ asm = asm_test
+ elf = asm_test + ".o"
+ binary = asm_test + ".bin"
+ log = asm_test + ".log"
+ logging.info("Compiling assembly test : %s" % asm)
+ # gcc comilation
+ cmd = ("%s -static -mcmodel=medany \
+ -fvisibility=hidden -nostdlib \
+ -nostartfiles %s \
+ -I%s/user_extension \
+ -T%s/scripts/link.ld -o %s " % \
+ (get_env_var("RISCV_GCC"), asm, get_env_var("RISCV_DV_ROOT"),
+ get_env_var("RISCV_DV_ROOT"), elf))
+ cmd += (" -march=%s" % isa)
+ cmd += (" -mabi=%s" % mabi)
+ logging.info("Compiling %s" % asm)
+ output = subprocess.check_output(cmd.split())
+ # Convert the ELF to plain binary, used in RTL sim
+ logging.info("Converting to %s" % binary)
+ cmd = ("%s -O binary %s %s" % (get_env_var("RISCV_OBJCOPY"), elf, binary))
+ output = subprocess.check_output(cmd.split())
+ logging.debug(output)
+ base_cmd = parse_iss_yaml(iss, iss_yaml, isa)
+ logging.info("[%0s] Running ISS simulation: %s" % (iss, elf))
+ cmd = get_iss_cmd(base_cmd, elf, log)
+ run_cmd(cmd, 20)
+ logging.info("[%0s] Running ISS simulation: %s ...done" % (iss, elf))
+
+
def iss_sim(test_list, output_dir, iss_list, iss_yaml, isa, timeout_s):
"""Run ISS simulation with the generated test program
@@ -243,11 +334,11 @@
continue
else:
for i in range(0, test['iterations']):
- prefix = ("%s/asm_tests/%s.%d" % (output_dir, test['test'], i))
+ prefix = ("%s/asm_tests/%s_%d" % (output_dir, test['test'], i))
elf = prefix + ".o"
log = ("%s/%s.%d.log" % (log_dir, test['test'], i))
cmd = get_iss_cmd(base_cmd, elf, log)
- logging.info("Running ISS simulation: %s" % elf)
+ logging.info("Running %s sim: %s" % (iss, elf))
run_cmd(cmd, timeout_s)
logging.debug(cmd)
@@ -268,7 +359,7 @@
run_cmd("rm -rf %s" % report)
for test in test_list:
for i in range(0, test['iterations']):
- elf = ("%s/asm_tests/%s.%d.o" % (output_dir, test['test'], i))
+ elf = ("%s/asm_tests/%s_%d.o" % (output_dir, test['test'], i))
logging.info("Comparing ISS sim result %s/%s : %s" %
(iss_list[0], iss_list[1], elf))
csv_list = []
@@ -321,6 +412,8 @@
help="Verbose logging")
parser.add_argument("--co", dest="co", action="store_true",
help="Compile the generator only")
+ parser.add_argument("--cov", dest="cov", action="store_true",
+ help="Enable functional coverage")
parser.add_argument("--so", dest="so", action="store_true",
help="Simulate the generator only")
parser.add_argument("--cmp_opts", type=str, default="",
@@ -342,7 +435,7 @@
help="Generator timeout limit in seconds")
parser.add_argument("--end_signature_addr", type=str, default="0",
help="Address that privileged CSR test writes to at EOT")
- parser.add_argument("--iss_timeout", type=int, default=50,
+ parser.add_argument("--iss_timeout", type=int, default=25,
help="ISS sim timeout limit in seconds")
parser.add_argument("--iss_yaml", type=str, default="",
help="ISS setting YAML")
@@ -350,33 +443,27 @@
help="RTL simulator setting YAML")
parser.add_argument("--csr_yaml", type=str, default="",
help="CSR description file")
-
+ parser.add_argument("-cs", "--core_setting_dir", type=str, default="",
+ help="Path for the riscv_core_setting.sv")
+ parser.add_argument("-ext", "--user_extension_dir", type=str, default="",
+ help="Path for the user extension directory")
+ parser.add_argument("--asm_test", type=str, default="",
+ help="Directed assembly test")
+ parser.add_argument("--log_suffix", type=str, default="",
+ help="Simulation log name suffix")
+ parser.add_argument("-bz", "--batch_size", type=int, default=0,
+ help="Number of tests to generate per run. You can split a big"
+ " job to small batches with this option")
parser.set_defaults(co=False)
parser.set_defaults(so=False)
parser.set_defaults(verbose=False)
-
+ parser.set_defaults(cov=False)
return parser
-def setup_logging(verbose):
- """Setup the root logger.
-
- Args:
- verbose: Verbose logging
- """
- if verbose:
- logging.basicConfig(format="%(asctime)s %(filename)s:%(lineno)-5s %(levelname)-8s %(message)s",
- datefmt='%a, %d %b %Y %H:%M:%S',
- level=logging.DEBUG)
- else:
- logging.basicConfig(format="%(asctime)s %(levelname)-8s %(message)s",
- datefmt='%a, %d %b %Y %H:%M:%S',
- level=logging.INFO)
-
-
def main():
"""This is the main entry point."""
-
+ check_riscv_dv_setting()
parser = setup_parser()
args = parser.parse_args()
cwd = os.path.dirname(os.path.realpath(__file__))
@@ -394,26 +481,34 @@
if not args.testlist:
args.testlist = cwd + "/yaml/testlist.yaml"
+ if args.asm_test != "":
+ run_assembly(args.asm_test, args.iss_yaml, args.isa, args.mabi, args.iss)
+ return
+
# Create output directory
if args.o is None:
output_dir = "out_" + str(date.today())
else:
output_dir = args.o
+
subprocess.run(["mkdir", "-p", output_dir])
subprocess.run(["mkdir", "-p", ("%s/asm_tests" % output_dir)])
# Process regression test list
matched_list = []
- process_regression_list(args.testlist, args.test, args.iterations, matched_list)
- if len(matched_list) == 0:
- sys.exit("Cannot find %s in %s" % (args.test, args.testlist))
+
+ if not args.co:
+ process_regression_list(args.testlist, args.test, args.iterations, matched_list)
+ if len(matched_list) == 0:
+ sys.exit("Cannot find %s in %s" % (args.test, args.testlist))
# Run instruction generator
if args.steps == "all" or re.match("gen", args.steps):
gen(matched_list, args.csr_yaml, args.end_signature_addr, args.isa,
args.simulator, args.simulator_yaml, output_dir, args.so,
args.co, args.lsf_cmd, args.seed, cwd, args.cmp_opts,
- args.sim_opts, args.gen_timeout)
+ args.sim_opts, args.gen_timeout, args.core_setting_dir,
+ args.user_extension_dir, args.cov, args.log_suffix, args.batch_size)
if not args.co:
# Compile the assembly program to ELF, convert to plain binary
diff --git a/hw/vendor/lowrisc_ibex/vendor/google_riscv-dv/sample/sample.S b/hw/vendor/lowrisc_ibex/vendor/google_riscv-dv/sample/sample.S
deleted file mode 100644
index d95bfac..0000000
--- a/hw/vendor/lowrisc_ibex/vendor/google_riscv-dv/sample/sample.S
+++ /dev/null
@@ -1,19195 +0,0 @@
-.macro init
-.endm
-.section .text.init
-.globl _start
-_start:
- li x0, 0x1
- li x1, 0x0
- li x2, 0x4e04f00
- li x3, 0x80000000
- li x4, 0x0
- li x5, 0x0
- li x6, 0x80000000
- li x7, 0x0
- li x8, 0x0
- li x9, 0x2486412d
- li x10, 0xf96da636
- li x11, 0x80000000
- li x12, 0x0
- li x13, 0x6a169e6f
- li x14, 0x0
- li x15, 0x0
- li x16, 0x9
- li x17, 0xecebb53e
- li x18, 0x80000000
- li x19, 0x6
- li x20, 0x0
- li x21, 0xfd7b9523
- li x22, 0xf6a1c7ac
- li x23, 0xf2d48ef9
- li x24, 0x80000000
- li x25, 0x3
- li x26, 0x80000000
- li x27, 0x80000000
- li x28, 0x22f2ef4
- li x29, 0xfdbae154
- li x30, 0x34168a6f
- li x31, 0xf1e45ffd
-kernel_sp:
- la tp, _kernel_stack_end
-
-trap_vec_init:
- la a0, mtvec_handler
- csrw 0x305, a0 # MTVEC
-
-mepc_setup:
- la x10, _init
- csrw mepc, x10
- j init_machine_mode
-
-_init:
- la sp, _user_stack_end
-_main: c.srai a2, 29
- lui zero, 238737
- lui s11, 235721
- auipc s7, 76889
- xor t3, ra, s6
- c.addi gp, 29
- c.addi a0, -27
- lui a2, 384033
- c.sub a0, a5
- c.slli t1, 28
- srai t1, a1, 2
- auipc a7, 827597
- c.slli t1, 5
- c.addi s9, 2
- c.srli s0, 26
- c.srai s0, 31
- c.slli a7, 28
- nop
- c.beqz s0, 23f
- divu s5, s3, zero
- la t6, data_page_10+2392 #start riscv_load_store_rand_instr_stream_28
- remu t4, a1, zero
- sw t1, 124(t6)
- sb zero, -1935(t6)
- c.addi s4, 17
- sltiu t5, a6, 801
- lb s5, 1505(t6)
- auipc a5, 279144
- lw a2, 1536(t6)
- lui a6, 614242
- c.srli s0, 25
- auipc t3, 220077
- c.lui t3, 28
- auipc s0, 305607
- c.slli t1, 6
- c.addi t1, 22
- auipc s7, 871831
- lb s4, -1011(t6)
- c.slli a2, 15
- div zero, s6, s2
- auipc s4, 324009
- c.slli t5, 29
- c.lui t1, 10
- sh s9, -952(t6)
- sb ra, -1602(t6)
- lui s1, 459072
- c.addi gp, -29
- c.lui s4, 17
- lb s1, -1291(t6)
- c.or a0, a3
- auipc s1, 674641
- lui s0, 792087
- sb a1, 1581(t6)
- sb s8, 378(t6)
- auipc s3, 870733
- lbu s1, 849(t6)
- sb t4, -1621(t6)
- c.addi s1, 28
- lb s3, 1245(t6)
- auipc a2, 410504
- auipc gp, 783318
- lh t4, -64(t6)
- lb gp, -1679(t6)
- lw s1, -928(t6)
- sub t3, t2, a6
- lb a6, 477(t6)
- c.addi a3, 12
- lb s8, -1681(t6) #end riscv_load_store_rand_instr_stream_28
- lui a5, 538415
- bgeu sp, s0, 31f
- mul s10, t6, s6
-23: auipc s10, 359030
- lui gp, 347341
- c.andi a4, -2
- lui t6, 399070
- c.addi t5, -26
- c.lui a0, 11
- c.slli a5, 11
- c.srai a1, 5
-31: c.srai s0, 3
- lui s1, 610938
- sltu t2, sp, t3
- c.addi t4, 29
- sra a5, t4, s9
- mulh a7, s3, s7
- c.srli s0, 25
- c.srli a1, 27
- lui gp, 188064
- c.or a5, a0
- c.srai a3, 19
- c.lui s4, 25
- blt s10, s0, 49f
- fence.i
- c.addi a3, 23
- c.addi s11, -27
- c.slli s2, 6
- c.lui t1, 22
-49: c.addi a0, 16
- c.andi a2, 30
- c.addi s8, -9
- slti a3, s10, 221
- lui t5, 395389
- c.lui a6, 5
- lui t1, 827400
- c.srai a2, 18
- c.addi s5, -11
- c.addi t6, 7
- c.addi t6, 18
- auipc t2, 473859
- c.addi t3, -17
- xori s11, s8, 669
- lui a1, 173394
- c.nop
- c.addi s10, -19
- c.addi s3, 11
- c.addi s9, -6
- c.srli a5, 20
- sra gp, a3, s1
- lui s7, 700176
- sra t5, t4, s6
- c.addi a1, -22
- c.addi s8, 11
- nop
- c.addi a4, 17
- lui t1, 790428
- c.slli s8, 8
- mulh s1, t3, tp
- bne ra, zero, 86f
- lui a6, 8130
- c.srli a3, 13
- c.mv s11, t3
- c.or a2, s1
- c.srai s1, 7
- c.mv a5, s9
-86: auipc s7, 819547
- remu gp, t5, s11
- div a7, s10, s10
- c.addi s3, -8
- c.addi s3, -12
- bne a1, sp, 101f
- rem a3, a3, t5
- c.addi a4, 16
- lui zero, 695379
- lui zero, 690954
- c.addi s8, -13
- lui t4, 388194
- lui t2, 218029
- auipc a0, 533303
- c.add a0, a4
-101: xori s7, t4, -314
- c.addi s8, -27
- auipc a3, 448156
- c.addi t4, 28
- c.addi s2, 25
- c.srai s1, 30
- xori s5, s2, -427
- c.and a2, s0
- auipc s2, 697995
- c.lui s3, 23
- auipc s11, 545666
- c.sub s0, s0
- div zero, s3, tp
- divu t3, gp, s6
- c.slli a0, 25
- remu t6, s1, s9
- c.srai a4, 17
- c.srli s0, 14
- c.srai a3, 11
- auipc a3, 567602
- mulhsu s4, a2, s9
- c.addi a5, 17
- auipc a3, 503184
- c.lui t6, 18
- blt a5, t1, 140f
- c.slli t1, 15
- c.addi s0, 26
- c.addi gp, 19
- c.lui t6, 30
- auipc s2, 31723
- c.lui s1, 31
- c.lui a0, 2
- c.addi s7, -30
- c.addi a2, -32
- c.srai a5, 28
- c.lui s3, 22
- lui a2, 609043
- c.addi a0, 14
- auipc t1, 230242
-140: lui a1, 158565
- blt ra, s11, 161f
- c.slli s4, 3
- lui s9, 379078
- c.sub a1, s1
- c.lui a2, 3
- c.addi t4, 28
- lui a2, 1047086
- c.addi a4, -28
- auipc s4, 228213
- c.or s1, a5
- c.lui t1, 14
- lui t3, 574314
- c.srai a0, 7
- mul a4, t5, sp
- c.lui s7, 27
- c.bnez a5, 159f
- c.lui a1, 21
- lui a2, 674232
-159: auipc a7, 761974
- addi s5, t1, -414
-161: c.mv s2, s0
- c.slli s9, 20
- c.addi a5, -18
- lui s3, 185509
- mulhu s10, t4, t0
- c.addi t2, 11
- c.addi s8, -20
- c.addi a5, 20
- lui s0, 374194
- addi s9, a4, -839
- c.srai s1, 28
- c.slli a5, 15
- slt t4, t5, t1
- c.addi a2, -4
- mulhu s11, tp, s3
- lui s8, 1008998
- beq s4, a4, 193f
- sra a2, s9, s10
- lui t5, 582185
- mul t3, tp, a2
- auipc t3, 920837
- mulhsu s6, t0, s6
- c.addi a7, 8
- auipc zero, 1038009
- c.addi a4, -28
- lui s6, 997119
- auipc a3, 779630
- auipc s5, 878993
- c.srli a2, 29
- c.addi t3, -10
- c.lui s3, 15
- auipc a0, 145555
-193: bgeu ra, ra, 201f
- andi gp, a2, -494
- c.srai a2, 15
- slli t6, a0, 17
- c.mv s10, t5
- c.addi s2, 9
- c.addi s8, -15
- c.addi t2, -10
-201: c.slli a0, 4
- c.slli t2, 1
- c.beqz a0, 217f
- c.addi s5, -2
- c.srli a3, 23
- c.addi s11, -6
- sltiu t3, t6, -45
- c.and s0, a1
- auipc s9, 1557
- c.addi a5, -28
- auipc t4, 5097
- auipc t5, 687856
- addi s6, s9, -678
- c.addi s10, 20
- c.srai a5, 8
- blt gp, s1, 219f
-217: c.srai a2, 8
- auipc t6, 157471
-219: c.addi a6, -24
- c.srai s1, 9
- c.addi s4, 23
- c.addi s2, 29
- auipc t2, 945652
- c.addi a2, 3
- lui s6, 212122
- c.srai a5, 7
- c.addi t2, 6
- bgeu a0, s11, 230f
- c.lui a4, 30
-230: c.addi s3, 8
- auipc s8, 776288
- c.addi t1, -17
- auipc s6, 551060
- bltu tp, s7, 247f
- c.addi a4, -20
- lui zero, 658128
- andi a4, t1, -764
- la a4, data_page_11+2224 #start riscv_load_store_rand_instr_stream_52
- lbu s8, 583(a4)
- lb t5, -2043(a4)
- c.addi t1, -4
- c.addi t5, 18
- lbu t2, -621(a4)
- c.addi s3, -20
- lh t4, 1428(a4)
- lh t5, 1786(a4)
- lhu s3, -2(a4)
- c.addi a2, 12
- lb t1, 1591(a4)
- c.or s1, s1
- lw t5, 328(a4)
- fence
- lb s8, 1753(a4)
- lui a7, 361756
- sub s4, t3, a6
- lbu s5, -1997(a4)
- slli t6, s2, 29
- lb s3, -807(a4)
- c.srli a5, 19
- lb s4, -1211(a4)
- lbu s5, 1593(a4)
- c.addi s4, -20
- auipc s4, 972420
- lbu s4, -898(a4)
- c.slli a6, 22
- c.lui s0, 11
- c.addi t2, 30
- lbu s0, 954(a4)
- lb s1, 1479(a4)
- lhu s8, -1530(a4)
- rem t2, a4, s1
- lbu a3, 868(a4)
- lb t6, -1699(a4)
- fence.i
- c.addi s11, 27
- mulh s2, t5, a1
- rem t1, t2, s6
- sh s3, -1278(a4)
- c.slli s2, 5
- auipc s10, 96484
- xori s5, s1, 54
- lui t3, 198499
- sb s1, 686(a4)
- lb s6, 1559(a4) #end riscv_load_store_rand_instr_stream_52
- c.addi a5, 13
- c.addi a5, 24
- auipc t1, 544505
- c.addi s3, -29
- sra s7, s9, t3
- c.srli s1, 18
- lui t6, 1021882
- c.addi a0, 21
- lui s9, 581582
-247: c.srai s1, 4
- lui s3, 790332
- c.slli t2, 21
- c.slli a2, 3
- c.addi t4, -10
- c.addi a7, 31
- c.srai a3, 17
- c.addi a7, -17
- auipc s0, 269048
- c.srli a4, 5
- lui t1, 602326
- lui a6, 371662
- c.addi t1, -31
- lui gp, 600642
- c.lui a0, 28
- c.addi a4, 31
- lui a5, 311416
- c.addi s9, 21
- sltiu s1, s0, -72
- c.lui t3, 9
- c.srai a5, 28
- lui a5, 853294
- c.addi s3, 3
- c.addi s2, 25
- auipc s5, 494201
- c.addi s5, 16
- ori s1, t2, 252
- c.addi t1, -12
- c.addi s5, -23
- c.addi s5, 4
- lui t3, 830400
- c.addi t4, -27
- xor s4, s5, t0
- srli a6, a6, 3
- auipc a7, 682700
- and s8, zero, s6
- andi a0, s5, 689
- c.addi s1, 9
- srai s11, a6, 4
- lui a5, 535401
- c.srai s0, 3
- and a6, t4, a7
- lui t1, 260102
- bgeu s6, a7, 300f
- c.addi s9, 31
- lui a1, 376678
- auipc s10, 343826
- c.lui gp, 5
- lui a3, 16797
- c.addi s10, 5
- auipc s1, 425800
- c.lui s10, 23
- srl s11, a7, t5
-300: lui a7, 985039
- lui a3, 264571
- c.addi s8, -14
- bltu zero, a1, 304f
-304: c.srli s0, 4
- lui a0, 694127
- lui t6, 416887
- c.addi gp, 16
- c.srai a3, 8
- c.addi t4, 15
- c.lui t2, 1
- c.addi t6, 5
- lui t3, 449411
- c.addi s0, -27
- c.srai a0, 29
- auipc a6, 638349
- c.slli t2, 3
- c.srli a5, 6
- blt s7, s3, 338f
- c.or s1, a4
- c.slli gp, 5
- c.addi s8, 20
- c.addi a6, -20
- c.addi s8, 4
- c.srai s0, 24
- fence
- lui a5, 1046512
- c.lui a3, 8
- c.slli a1, 16
- c.addi t5, 13
- c.srai a0, 7
- c.andi a5, 10
- xor t5, t2, a3
- auipc s0, 689803
- lui t2, 449359
- lui s1, 62087
- c.srli a2, 3
- srli t5, a3, 26
-338: c.addi a0, 11
- c.add a3, a5
- c.addi s2, 31
- c.addi s11, -16
- auipc a4, 671584
- c.srli a3, 25
- lui a4, 38256
- lui s9, 349156
- bgeu s7, t6, 366f
- c.srai a5, 4
- c.nop
- c.addi a3, -5
- c.lui s1, 16
- c.srai a5, 14
- lui s5, 447102
- c.lui s11, 15
- bgeu s7, ra, j__main_sub_2_2 #branch to jump instr
- lui s4, 109441
- c.slli a1, 11
- lui a4, 43748
- c.addi s3, 21
- slti t1, t4, -304
-j__main_sub_2_2: jal ra, sub_2
- lui s8, 775557
- beq gp, s1, 354f
- c.add a2, a0
- lui s0, 680257
-354: c.addi a6, 19
- c.srai a1, 13
- c.srai a3, 3
- c.srli a5, 29
- c.or a4, s0
- lui s10, 4729
- auipc s4, 494582
- c.addi s8, 26
- c.li s1, 4
- c.lui s8, 4
- c.lui a7, 13
- lui a0, 691732
-366: c.addi t4, -13
- c.slli t1, 4
- c.addi s1, -14
- c.srai a2, 12
- auipc t3, 1025792
- c.addi s0, 21
- auipc a5, 683643
- srli a7, t1, 17
- c.xor a1, a5
- and a3, a0, a7
- sra s6, a3, t3
- c.lui s11, 7
- auipc s9, 950518
- c.srai s0, 10
- bltu s4, s3, 399f
- la s1, data_page_0+1492 #start riscv_load_store_rand_instr_stream_64
- fence.i
- auipc t4, 460297
- auipc s5, 418203
- lbu t4, 225(s1)
- lbu s9, 1409(s1)
- lb a3, -791(s1)
- lb a1, 723(s1)
- auipc gp, 845379
- sh s6, -868(s1)
- c.addi a4, -2
- lbu a1, 1939(s1)
- lb t4, -1473(s1)
- c.srai a0, 2
- c.addi a3, 25
- c.srai a3, 17
- c.or a1, a1
- lh zero, 1266(s1)
- srl s9, s1, s4
- c.srli a2, 7
- c.srli a0, 27
- c.srli a0, 18
- lh t4, 1228(s1)
- c.srli a3, 1
- lh s2, -1094(s1)
- lhu s8, -1178(s1)
- c.slli a5, 21
- lw s2, -160(s1)
- div s4, gp, s5
- c.addi s2, -10
- lb s8, -671(s1)
- lb t5, 373(s1)
- lbu s8, 112(s1)
- c.srai a4, 29
- sb t6, 1781(s1)
- lhu a4, 870(s1)
- lbu a3, 863(s1)
- lb s7, -633(s1)
- lbu s2, -1435(s1)
- lh gp, -1020(s1)
- c.xor s0, s0
- sb s7, 1165(s1)
- lb a3, 160(s1)
- c.addi s9, 30
- lhu t2, -1202(s1)
- c.slli s7, 18
- remu t1, s4, a6
- sb t1, -1266(s1)
- lb a1, 547(s1)
- c.mv s3, s7
- lb a0, 1494(s1)
- lui a4, 901233
- addi a1, a3, 532
- lbu a7, -329(s1) #end riscv_load_store_rand_instr_stream_64
- bge s5, t4, 392f
- c.addi s0, -11
- c.addi a6, -22
- sltiu a1, s4, -693
- c.lui s0, 10
- auipc t2, 187959
- c.addi t2, 29
- auipc s9, 197709
- c.slli gp, 10
- c.srli a1, 27
- c.addi a0, -21
-392: slli s11, gp, 13
- c.addi t5, -11
- c.addi t5, 10
- slti t2, ra, 716
- c.srli a3, 23
- c.addi t1, -22
- lui t1, 127783
-399: c.andi s1, 0
- c.srli s0, 17
- c.addi a1, 12
- c.addi a3, 13
- c.srli a4, 19
- c.lui a0, 1
- c.addi s2, 10
- auipc zero, 1022497
- c.li a4, -14
- mulhu s4, s4, s7
- auipc t3, 563250
- c.slli s5, 16
- c.xor a1, a4
- c.addi s7, -1
- lui a1, 149662
- c.lui s7, 11
- slli s4, tp, 9
- c.srli a1, 1
- c.srai a3, 22
- lui s11, 1032940
- c.srai s0, 11
- c.slli a3, 3
- auipc t4, 1028306
- c.srai a5, 5
- lui a5, 375450
- lui a0, 692917
- auipc a7, 633069
- c.slli s5, 2
- auipc s4, 167821
- c.addi s4, -19
- auipc t5, 944054
- bgeu s7, a1, 444f
- andi t6, t4, -237
- c.srai a5, 10
- srai t4, sp, 21
- c.addi a7, -11
- c.srai a1, 14
- c.addi s10, 27
- c.lui s1, 18
- c.srli a3, 11
- auipc s11, 199200
- and s4, a6, s8
- auipc s2, 107016
- c.addi s0, -19
- auipc s9, 30280
-444: c.addi s7, -31
- bne t4, tp, 464f
- or s1, a4, a2
- c.lui s9, 7
- c.addi a7, 11
- remu s11, t4, a2
- c.srli a1, 3
- c.srli a2, 14
- c.addi a6, -1
- c.slli s7, 20
- srai a6, t5, 15
- c.srai a3, 26
- c.addi s11, 6
- c.addi s3, -32
- c.nop
- mulh a2, s11, t5
- c.addi t4, 24
- c.srai a4, 31
- c.addi a4, -2
- srai s7, ra, 16
-464: auipc t1, 435844
- auipc s10, 100898
- c.slli s0, 16
- auipc a3, 254598
- c.addi s11, 17
- c.srai s0, 4
- auipc t1, 563972
- c.addi a3, 18
- div s6, a7, s10
- c.addi s4, -4
- c.srli a2, 5
- c.addi s9, -22
- auipc s6, 778876
- c.addi a6, -15
- c.addi a5, 10
- lui zero, 263379
- c.addi a5, -29
- lui a3, 29651
- lui a2, 978869
- lui s8, 736912
- c.addi s1, -22
- c.addi gp, -20
- c.addi a1, -4
- c.lui a1, 23
- srli s11, a1, 23
- c.addi a7, 15
- lui a4, 828997
- c.slli t5, 23
- c.nop
- auipc a7, 61928
- c.srai a1, 3
- c.srai a0, 14
- c.addi s10, -31
- c.srai s1, 25
- c.slli a4, 15
- srai a4, s3, 10
- lui s6, 604940
- c.srli a5, 7
- lui s11, 490326
- lui t2, 236336
- auipc s7, 193630
- c.addi s8, 28
- c.addi a2, -32
- c.addi t2, -21
- c.addi a6, -17
- c.addi s11, -1
- c.lui s6, 9
- c.slli s5, 4
- fence
- c.addi gp, 17
- c.addi a5, 7
- c.srai a2, 12
- auipc a5, 95600
- auipc s7, 325515
- auipc s7, 395439
- lui s3, 17730
- c.addi s9, -9
- c.addi a1, -26
- c.addi a0, -7
- auipc t6, 166548
- c.addi t1, 29
- auipc s8, 557038
- c.srai s1, 5
- auipc a3, 151841
- c.addi t6, 11
- c.or a3, a2
- c.addi a4, 20
- c.addi gp, -14
- auipc gp, 685873
- c.addi a4, 14
- c.slli a5, 8
- sll s11, s6, a3
- sll s1, s7, a5
- c.addi s9, 10
- c.lui s2, 5
- c.slli a4, 31
- la a0, data_page_16+2651 #start riscv_load_store_rand_instr_stream_11
- lui s2, 677975
- lbu s6, 1266(a0)
- c.addi s7, -24
- auipc gp, 893098
- lb s11, 1291(a0)
- auipc a7, 123834
- sh s0, -727(a0)
- c.srai a4, 17
- c.addi t1, 16
- c.srai a5, 12
- auipc s4, 138483
- sh s2, -425(a0)
- lbu t3, -1950(a0)
- c.addi a7, 26
- nop
- lw s10, -407(a0)
- lhu t3, 1033(a0)
- lb a7, 604(a0)
- c.nop
- auipc s11, 463200
- srli s2, gp, 22
- lb a6, -556(a0)
- srl a6, s7, s8
- c.srai a3, 17
- sh s4, 851(a0)
- auipc t5, 869023
- c.addi a4, 5
- c.addi a5, 12
- c.addi t6, -32
- c.addi s2, 14
- lbu s10, -1862(a0)
- srl a4, zero, zero
- slli s9, t2, 30
- lui t1, 758692
- c.addi a2, -18
- lui a4, 633612
- sb a7, -984(a0) #end riscv_load_store_rand_instr_stream_11
- c.and s1, s0
- bltu a5, s4, 561f
- sra t3, t6, zero
- auipc s4, 73153
- c.addi a5, 21
- addi a3, a3, 69
- lui s3, 550687
- c.srai s1, 4
- c.srai a5, 29
- div t1, a1, s11
- c.addi s5, 30
- or a6, zero, ra
- lui s5, 182884
- c.addi t4, 17
- c.addi a7, -20
- c.addi t2, -1
- c.addi s1, 9
- xori s2, s9, 562
- xor s6, t0, t1
- auipc a0, 429914
- rem s10, zero, a6
-561: bltu s6, s7, 563f
- div t6, s11, s11
-563: c.addi s11, -25
- nop
- c.addi t6, 18
- c.addi s3, 13
- c.addi gp, 8
- c.srai a2, 10
- lui a3, 446328
- c.srai a1, 7
- c.addi t4, 2
- c.srli a4, 13
- c.addi s7, 15
- slt t1, a5, s4
- c.lui s2, 3
- c.srai a0, 12
- c.lui s1, 13
- c.addi s3, 4
- c.srai a0, 22
- c.addi s4, -20
- c.addi s2, 11
- c.slli a7, 27
- auipc a5, 212688
- c.addi s5, 4
- c.srai a4, 2
- c.srai a3, 27
- c.slli a7, 25
- beq sp, gp, 600f
- c.or a1, a4
- c.addi s0, 26
- auipc s10, 258803
- c.lui a2, 4
- c.srli s1, 10
- c.srli s0, 16
- c.slli a1, 18
- c.sub s0, a4
- c.addi s10, 15
- lui a3, 417118
- auipc a7, 914260
-600: auipc s0, 682039
- c.addi s7, 27
- lui s2, 889859
- c.slli a2, 19
- sltiu s6, t1, -21
- c.addi t1, 5
- c.addi s7, -29
- c.srli a2, 9
- c.addi s4, 12
- xori a6, s5, 146
- c.srai a3, 10
- auipc s6, 422956
- c.addi s4, 22
- c.addi s0, 12
- c.srli a3, 24
- auipc t5, 244872
- c.lui s8, 13
- c.lui s8, 30
- c.addi s5, -27
- fence.i
- lui a3, 994628
- c.addi t6, -2
- c.slli s2, 14
- c.beqz a3, 637f
- auipc gp, 128473
- auipc a1, 437860
- lui s5, 229811
- c.addi s9, -6
- c.addi s3, 3
- auipc s6, 243702
- auipc s6, 884541
- c.addi a3, -31
- auipc a6, 820980
- c.mv a3, t1
- c.srli s0, 8
- c.addi s10, -13
- auipc zero, 207844
-637: c.srai s0, 23
- auipc s0, 668958
- c.addi a2, -9
- c.srai s1, 28
- ori a2, a6, -807
- bltu a6, zero, 656f
- slti a2, t2, -769
- auipc a2, 891048
- c.addi s0, 4
- c.slli a7, 11
- srai s4, s0, 19
- c.andi a0, 14
- c.slli s8, 25
- c.andi s0, -15
- auipc t4, 219980
- c.addi t2, 21
- sra s2, s5, a6
- c.slli s2, 26
- auipc t4, 264867
-656: lui a1, 690306
- c.slli gp, 9
- c.srai a1, 18
- c.slli s4, 20
- mulh zero, a1, s3
- blt s6, s4, 679f
- auipc s4, 1046395
- lui s8, 880860
- c.lui a7, 7
- c.slli t1, 3
- c.addi a0, -28
- c.addi a0, 4
- c.slli t5, 25
- lui a2, 384207
- c.lui a7, 4
- fence
- add zero, s0, gp
- srli gp, a6, 24
- lui a4, 54286
- beq s4, a3, 678f
- divu s7, a7, a3
- c.addi a5, -26
-678: c.lui s1, 8
-679: blt s0, t0, 688f
- c.addi s0, -22
- c.slli t4, 7
- c.slli t1, 19
- srli s11, a0, 1
- lui a5, 236700
- sltu s1, a7, s8
- c.slli s1, 7
- auipc s8, 932021
-688: c.addi s5, 15
- c.srli a2, 26
- lui s8, 877764
- c.srli a0, 14
- c.lui s7, 9
- c.srai s0, 15
- bge sp, a6, 709f
- c.addi a0, -17
- rem s2, t3, s7
- c.addi s9, -24
- c.srli s1, 18
- lui s5, 678544
- c.addi a3, -6
- lui zero, 526443
- lui s5, 163422
- c.addi s0, 28
- add a7, s0, a0
- auipc zero, 298302
- lui s0, 922806
- div s0, ra, a7
- c.slli a1, 6
-709: c.and a0, a2
- auipc a7, 329824
- c.addi a4, 26
- c.srai s0, 1
- auipc a5, 956672
- auipc t5, 543404
- mulh a0, t6, t5
- auipc a4, 1037276
- lui a3, 682997
- c.addi s10, -17
- mul t1, a1, s6
- auipc zero, 465779
- c.addi a4, 6
- nop
- c.addi t1, 31
- c.addi s4, 9
- c.slli a7, 1
- auipc s4, 389515
- auipc zero, 831625
- auipc gp, 95212
- auipc zero, 860212
- mulhu a3, s8, s2
- auipc s0, 812022
- c.addi a6, -27
- lui a1, 63596
- c.srli a0, 3
- auipc t4, 99309
- lui a5, 38321
- c.addi s5, 7
- c.slli t6, 3
- lui s9, 278381
- c.srai s0, 14
- srl s7, t2, s3
- auipc a5, 780951
- c.lui t1, 21
- lui gp, 221602
- c.slli s6, 14
- c.nop
- auipc t5, 415099
- c.slli gp, 29
- bltu tp, t0, j__main_sub_1_1 #branch to jump instr
- c.srai s1, 24
- c.slli gp, 6
-j__main_sub_1_1: jal ra, sub_1
- c.addi s8, 7
- c.srai s0, 4
- c.srli a5, 15
- auipc t4, 634659
- sub s6, s3, sp
- lui a7, 762190
- xori s9, t2, 256
- srli a7, s2, 15
- lui s8, 237823
- c.beqz a4, 757f
- c.addi a7, -10
- sub s9, s9, s1
- blt a6, s0, 775f
- c.srai a5, 5
-757: lui a1, 944155
- c.addi a7, -12
- c.addi s7, -14
- c.addi t6, 21
- nop
- c.addi s8, 24
- c.addi t2, -25
- c.addi s7, -8
- c.lui gp, 8
- c.addi t2, -13
- mul s6, a4, s2
- c.lui a2, 8
- addi t3, a5, -87
- sll a2, a5, s5
- beq t0, s4, 785f
- c.addi gp, -21
- lui a2, 61344
- mulh s4, a5, s3
-775: c.addi s1, 26
- c.and a0, a0
- auipc a0, 687384
- c.addi t5, -32
- c.srai a1, 20
- c.beqz s0, 792f
- c.addi s4, -10
- c.addi s5, -23
- c.mv t4, s6
- c.addi a5, -11
-785: srli s1, a3, 8
- c.addi s7, -26
- c.addi t6, -17
- c.addi s0, 13
- lui t5, 974165
- c.add a4, a1
- slt t1, t0, ra
-792: c.addi s7, -6
- auipc s4, 235522
- lui s9, 920086
- lui a7, 225536
- c.srai a3, 15
- c.addi a6, -10
- auipc zero, 32660
- lui s9, 239905
- c.srai a5, 5
- c.addi a4, 14
- mulhu t2, t5, a2
- c.slli s11, 11
- mulh a7, a3, a3
- auipc s9, 682405
- auipc s1, 749015
- mulhu s2, a3, a4
- c.addi s11, 24
- c.slli t2, 9
- auipc s2, 103002
- c.mv a1, t2
- mulhsu s1, a0, sp
- lui zero, 330455
- c.addi a3, 22
- c.srai a2, 17
- or s5, s6, s2
- c.addi t5, -28
- lui t1, 186801
- xor t3, t6, s5
- c.srli a5, 23
- c.slli t2, 31
- c.srai a0, 7
- c.lui gp, 12
- bne t3, a0, 832f
- c.srai a4, 3
- c.srli a1, 23
- auipc s10, 268917
- auipc t5, 673960
- c.srai a0, 29
- c.srli a4, 17
- c.srli a4, 10
-832: c.srai s1, 11
- c.slli s5, 11
- slti s10, s8, 715
- c.addi s9, -28
- c.addi t5, -18
- c.addi a7, 24
- lui t4, 677639
- auipc gp, 486315
- c.bnez a2, 846f
- lui a2, 604350
- c.addi s7, -12
- c.lui s11, 21
- c.addi t1, -19
- sra s11, a5, t5
-846: c.srli a4, 17
- c.lui a3, 19
- c.addi t1, -18
- c.addi a2, 28
- c.slli s5, 11
- auipc s10, 66254
- auipc zero, 361722
- c.addi a4, 25
- c.addi a5, -25
- bne a1, a2, 865f
- auipc s8, 675017
- c.addi a2, 24
- fence
- c.addi a0, -29
- c.addi a4, -3
- slli zero, t1, 17
- lui zero, 638282
- c.or a1, a3
- lui a0, 967671
-865: lui s3, 141214
- c.lui t6, 3
- c.srli a3, 24
- c.addi s8, 17
- c.nop
- c.addi s11, -5
- lui a4, 263199
- c.srli a0, 9
- c.nop
- c.srai s0, 8
- c.srli a2, 18
- c.slli s9, 8
- srli t5, a0, 2
- c.slli s11, 8
- c.addi t6, -4
- auipc zero, 188225
- c.addi t5, -10
- div s10, ra, t4
- c.srai a0, 7
- c.addi s8, 17
- srai t3, sp, 14
- c.addi t4, 2
- c.addi a1, 30
- lui t3, 259752
- lui s1, 139287
- lui t4, 950285
- lui s6, 825854
- auipc s0, 702119
- c.addi s4, -12
- lui a1, 236741
- slti zero, t2, 363
- c.addi s11, -23
- c.srli a3, 28
- c.slli s8, 8
- c.srai a5, 5
- c.addi t3, 12
- c.lui s0, 6
- c.slli t1, 21
- sra s0, zero, s4
- c.addi t2, 18
- c.slli s5, 11
- lui a7, 719474
- c.lui t4, 25
- c.srai a2, 8
- auipc a0, 755032
- lui t3, 676474
- c.srai a4, 9
- c.srli a5, 7
- auipc s11, 447190
- lui t2, 1787
- c.srli a0, 25
- c.addi s2, -21
- auipc s10, 511423
- c.lui a2, 4
- c.xor a3, a0
- c.addi t1, 22
- slti s11, t0, -210
- blt t3, s7, 939f
- auipc s1, 794184
- lui zero, 741657
- c.srai a5, 10
- c.srli a0, 18
- c.srli a1, 7
- bne t1, a2, 933f
- c.addi gp, 22
- c.addi s9, 29
- lui t4, 466063
- c.srli a1, 29
-933: c.slli s8, 18
- c.lui a7, 31
- divu a5, a4, a5
- c.addi s1, 4
- c.slli s6, 2
- c.addi s11, 24
-939: c.addi gp, 4
- c.addi a4, -23
- c.addi t3, 14
- c.addi s6, 9
- c.and a3, a3
- and a3, a5, s3
- c.lui t5, 15
- c.addi s9, 31
- c.slli s6, 1
- c.srai a5, 21
- auipc s11, 896169
- c.addi s1, 24
- c.slli s4, 18
- lui t2, 492633
- mulhu a5, sp, s7
- c.srli a1, 26
- c.lui t3, 9
- lui t5, 694853
- auipc s0, 446961
- c.nop
- c.lui s4, 8
- c.srli a2, 16
- c.addi s7, -23
- c.addi s1, 22
- c.slli t4, 28
- slli s1, tp, 3
- c.slli s11, 12
- c.srli a0, 8
- c.addi t3, 6
- srai s7, s5, 12
- c.addi a7, -5
- c.lui s9, 1
- srl s10, t4, s4
- c.addi s5, -22
- lui s6, 165197
- lui s8, 808861
- lui s9, 447092
- sltu t5, zero, zero
- c.lui t5, 4
- c.or a0, s0
- c.xor a1, a0
- auipc s6, 1024152
- c.slli s4, 9
- auipc t2, 207620
- c.lui t5, 11
- c.beqz a5, 988f
- la s11, data_page_1+2630 #start riscv_load_store_rand_instr_stream_4
- sb t3, 269(s11)
- c.srai a1, 17
- sb t3, -1121(s11)
- lbu a7, 323(s11)
- lbu a0, -207(s11)
- lbu s7, -1223(s11)
- lui t4, 261232
- lb a3, -1241(s11)
- lb a1, -1546(s11)
- c.addi s2, -17
- sltu s10, s7, a5
- sh a1, -864(s11)
- sb s2, 672(s11)
- sb s3, 1241(s11)
- sb gp, -1245(s11)
- lbu t2, -1179(s11)
- lbu s7, 1107(s11)
- slt gp, t3, s0
- lbu a6, -1658(s11)
- lh s7, 1182(s11)
- c.add a3, s0
- c.addi s3, 1
- c.slli s3, 3
- c.srli a5, 31
- lbu t3, 33(s11)
- lui a5, 483618
- c.addi a6, 23
- c.andi a1, -3
- nop
- auipc a5, 507618
- c.srli a4, 24
- sw a7, 1026(s11)
- c.slli t2, 11
- lw a2, -206(s11)
- c.addi t4, -8
- lbu s7, 1025(s11)
- sb s8, 1309(s11)
- c.addi s2, 23
- lb a3, -793(s11)
- sb t1, -1806(s11)
- lb t3, -1075(s11)
- sb s5, -1091(s11)
- sb a6, 1417(s11)
- sb t6, -1125(s11)
- lbu a7, -488(s11) #end riscv_load_store_rand_instr_stream_4
- c.srli s0, 26
- c.addi s2, -6
- c.addi s10, -19
-988: c.beqz s0, 999f
- auipc s6, 413318
- c.lui t6, 15
- c.addi s5, -16
- c.lui s11, 1
- lui s9, 279039
- sltiu t4, a2, -410
- c.addi s10, 15
- lui a6, 6368
- auipc a1, 1006566
- fence
-999: slt t6, t5, a4
- c.addi a3, 5
- beq t4, t6, 1016f
- rem a7, t1, t2
- lui a2, 99607
- c.slli s0, 8
- c.slli s11, 12
- c.addi a6, -24
- la s11, data_page_5+1543 #start riscv_load_store_rand_instr_stream_7
- c.srli a2, 27
- lbu s1, 1577(s11)
- lhu s8, -811(s11)
- lbu t1, 530(s11)
- c.srli s1, 25
- lb a7, 1709(s11)
- c.lui s0, 4
- lbu s7, 1788(s11)
- c.lui s9, 27
- sb a0, 140(s11)
- lb t3, -1528(s11)
- lbu s9, 1722(s11)
- lhu s3, 1435(s11)
- sb sp, -428(s11)
- sb ra, 408(s11)
- sra s5, t5, t5
- sb s9, 118(s11)
- sb t1, -1417(s11)
- auipc s10, 207075
- c.srli a0, 19
- lui s10, 96014
- c.srli s1, 19
- c.addi s8, -30
- lh a7, -1063(s11)
- nop
- mulh t6, zero, t5
- sh t1, 2009(s11)
- sb s8, -740(s11)
- lbu s2, 596(s11)
- sb t3, 640(s11)
- lb s7, 675(s11)
- lh s4, 863(s11)
- lbu s2, 28(s11)
- lhu t2, -521(s11)
- sb s6, -558(s11)
- c.or s0, a3
- lhu s1, 1983(s11)
- lb a7, 1213(s11)
- sh a0, 1313(s11)
- lb a6, -778(s11) #end riscv_load_store_rand_instr_stream_7
- lui s8, 790887
- c.lui a5, 9
- c.addi s11, -9
- c.nop
- c.addi s9, 10
- c.addi s11, -30
- beq s7, t5, 1019f
- c.srli s0, 16
- c.slli t1, 24
-1016: c.srai a5, 7
- lui a0, 331489
- c.lui a1, 20
-1019: ori s8, s11, -589
- c.srli a1, 24
- c.addi a1, -6
- c.srli a2, 1
- fence.i
- c.slli t3, 30
- auipc a1, 683881
- auipc t4, 119934
- c.addi a6, -8
- c.srai a5, 10
- c.lui t2, 22
- or gp, t4, a1
- c.addi a2, 6
- c.slli s5, 9
- c.addi s8, -14
- slti s10, t2, -728
- auipc s5, 866547
- lui a6, 120865
- c.addi s3, -22
- c.srai s1, 11
- lui a5, 42815
- c.addi a5, -28
- auipc s9, 1011478
- auipc a7, 441599
- div s7, s3, t2
- la s2, data_page_1+1724 #start riscv_load_store_rand_instr_stream_20
- c.addi s1, 15
- sb t5, -645(s2)
- sh t5, 282(s2)
- c.addi t3, 30
- sb t5, -1653(s2)
- lbu a6, -469(s2)
- c.lui s0, 23
- sb t2, 1893(s2)
- lbu a1, 556(s2)
- c.addi s4, -16
- sh s10, -1342(s2)
- c.xor a4, s1
- sb s7, -1562(s2)
- auipc t6, 708188
- sw s6, -148(s2)
- c.addi t6, 22
- lui t2, 348584
- or s0, zero, s2
- lbu t5, 85(s2)
- c.srai a4, 29
- lb a1, 1610(s2)
- c.add a5, a5
- lui t6, 1041524
- slli zero, t2, 23
- sb t5, 73(s2)
- sh t6, -306(s2)
- c.srli a1, 4
- mul a4, ra, s5
- sb a2, 388(s2)
- auipc a6, 913922
- c.lui gp, 28
- lui s9, 962267
- auipc s1, 996200
- lbu s9, -59(s2) #end riscv_load_store_rand_instr_stream_20
- c.addi s0, -19
- auipc a4, 222235
- addi s6, t4, 1017
- lui s9, 702747
- c.slli t5, 27
- c.addi s8, 11
- c.addi a3, -11
- sra t4, t5, a3
- c.srai a5, 8
- c.addi s11, -4
- c.slli a3, 6
- c.addi s6, 5
- c.srai a2, 31
- lui s7, 671113
- auipc gp, 704043
- lui a2, 368874
- c.addi s3, 23
- auipc a6, 330102
- c.addi t5, -3
- c.srai a2, 19
- c.lui t5, 1
- c.addi s0, -28
- c.add s1, a2
- lui s11, 455321
- c.beqz a1, 1069f
-1069: c.addi t4, 29
- sltiu s8, s10, 1015
- c.addi s9, 12
- auipc t5, 804000
- bltu s0, s0, 1075f
- c.srli a1, 8
-1075: c.lui s0, 25
- c.addi s3, -3
- auipc s8, 652640
- c.beqz s1, 1087f
- c.srai a4, 5
- c.slli s7, 18
- lui s8, 795346
- lui a3, 693738
- lui s0, 166776
- c.srli a2, 19
- c.lui s3, 24
- c.srai s1, 3
-1087: andi zero, a5, -399
- lui s11, 367858
- bgeu t5, a6, 1108f
- c.slli t5, 15
- c.srai s0, 10
- lui s3, 784594
- c.slli s1, 11
- c.slli a0, 18
- c.bnez a3, 1112f
- auipc s10, 681744
- lui a6, 641348
- or s10, t4, tp
- sra a7, ra, s5
- sub s6, a2, s2
- c.addi s6, 17
- c.srai s0, 13
- auipc a5, 462929
- c.srai a2, 12
- lui s7, 1043471
- c.add a3, a0
- c.slli s4, 14
-1108: c.srli a3, 22
- c.srli a5, 31
- c.srai s1, 30
- lui s8, 520317
-1112: srli a7, s11, 6
- c.addi s7, -7
- c.addi s11, 23
- lui s6, 907921
- c.sub a4, s0
- lui a1, 1013181
- c.addi a0, -23
- c.addi t6, -8
- auipc t1, 937048
- c.addi s6, -31
- c.addi t5, -10
- lui a7, 64308
- sltu s4, a1, s1
- c.addi s2, 20
- auipc s7, 803028
- c.addi s2, 4
- c.slli a6, 25
- and gp, a5, a2
- lui s9, 101155
- c.addi s10, 20
- auipc a1, 871498
- c.slli a5, 26
- or a1, s11, gp
- c.srai s0, 19
- c.srai a0, 14
- c.li s5, 17
- c.addi s6, -20
- srai t5, s9, 3
- c.addi s2, 28
- auipc s9, 839827
- lui s9, 938338
- c.addi a7, -3
- c.lui t5, 13
- c.addi s1, -15
- fence.i
- c.srai s1, 26
- lui t5, 801837
- c.addi a6, 15
- c.slli t5, 19
- c.srai a4, 26
- fence
- c.addi s11, 11
- c.addi t6, 8
- lui gp, 614888
- c.addi s11, 9
- c.slli t1, 21
- lui a6, 458400
- c.addi t2, 5
- c.bnez a5, 1166f
- c.addi gp, 25
- c.sub a3, a4
- c.addi s7, 19
- c.addi a5, -8
- xori a5, t3, -60
-1166: c.srai a4, 15
- c.and a3, a4
- lui t1, 378074
- auipc s5, 759562
- auipc s1, 134935
- c.srli a3, 23
- c.xor a5, a5
- nop
- ori s4, s8, -172
- c.addi s2, 17
- lui t5, 836223
- auipc s11, 931116
- lui a4, 800192
- c.srai s1, 1
- lui s6, 464928
- c.addi a2, -4
- c.addi a6, 28
- c.srai a2, 19
- c.addi s2, -7
- c.addi s8, 28
- lui s5, 836100
- c.addi a5, -23
- beq a4, s1, 1205f
- lui t6, 728693
- c.addi s5, 16
- srli a3, t6, 5
- auipc a5, 332743
- c.lui s8, 23
- c.slli s6, 5
- c.addi gp, -13
- ori t1, a2, -508
- c.slli s7, 31
- lui t1, 8942
- la s8, data_page_13+2421 #start riscv_load_store_rand_instr_stream_14
- c.addi a4, 2
- lb s3, -799(s8)
- sb a2, -1278(s8)
- c.lui a2, 11
- c.srai a0, 29
- lui t6, 695772
- addi a1, a7, 928
- auipc t2, 91169
- c.addi gp, -9
- lbu t4, -1367(s8)
- mul a6, t0, a2
- c.addi a4, -16
- lui s6, 728944
- sb a2, 1643(s8)
- lui s10, 984077
- nop
- lb s0, 221(s8)
- lui gp, 622819
- slli a4, s0, 31
- lbu s6, 186(s8)
- lh zero, 301(s8)
- sra s11, zero, gp
- c.lui s9, 20
- sb s1, 79(s8)
- xor t5, s4, s3
- sra a2, t2, a0
- sb a5, 694(s8)
- lb s3, -57(s8)
- lui a5, 931897
- c.addi t6, -29
- divu s10, s2, a2
- c.addi a3, 10
- c.addi a4, 6
- lb s2, 607(s8) #end riscv_load_store_rand_instr_stream_14
- div s8, s11, zero
- mulh a1, zero, gp
- c.lui a0, 9
- c.slli t5, 20
- c.slli s3, 15
- c.slli s4, 7
-1205: and s9, t1, a4
- c.lui a1, 6
- auipc t2, 1034334
- c.sub s0, a2
- c.addi a7, -18
- sra s5, s7, a0
- c.addi s8, 6
- c.addi a3, -8
- c.srli a3, 28
- c.addi t1, 7
- c.addi s4, -29
- c.addi t6, 16
- auipc s10, 525781
- auipc t3, 1018180
- auipc s6, 895265
- auipc s1, 60492
- and s3, ra, a4
- c.slli s9, 20
- c.lui t2, 2
- c.srai a4, 23
- c.addi a2, -4
- slli t2, s0, 6
- c.addi t2, 9
- c.lui s3, 10
- auipc a5, 300851
- c.lui a4, 8
- c.addi s7, -1
- c.addi s11, -3
- c.srai a1, 30
- c.srli s0, 3
- c.srli s0, 7
- c.srai a5, 27
- c.addi t6, -22
- la s11, data_page_0+1771 #start riscv_load_store_rand_instr_stream_30
- lb s2, -461(s11)
- c.lui s7, 23
- lh s10, 523(s11)
- lbu s8, 288(s11)
- lw s3, -187(s11)
- lhu s1, 1063(s11)
- c.slli a2, 7
- lb s1, -270(s11)
- lh s7, -7(s11)
- lb t3, 1190(s11)
- lbu t1, 1782(s11)
- c.addi t1, 7
- lbu s4, 693(s11)
- c.slli a4, 26
- c.addi a0, 23
- c.xor s0, a0
- auipc a6, 317523
- lb s6, -1450(s11)
- andi gp, s6, -613
- sb s4, 1970(s11)
- c.srli a2, 24
- lbu a6, -734(s11)
- auipc s4, 276395
- sra s6, a1, a5
- sw tp, -1231(s11)
- lh a4, 1347(s11)
- lbu a3, -907(s11)
- sb t5, 1263(s11)
- lb t6, -1355(s11)
- sb t6, 1429(s11)
- sb t2, 1749(s11)
- c.addi a2, 21
- lhu a0, 1523(s11)
- c.addi s7, 22
- c.slli gp, 14
- lhu a7, -825(s11)
- lh t4, 1491(s11)
- sltu t1, a7, s7
- c.addi s0, -2
- c.li a2, -23
- sb s10, -1102(s11)
- c.srai a0, 8
- lbu s9, 1654(s11)
- sb s0, 272(s11)
- lbu s9, 1292(s11) #end riscv_load_store_rand_instr_stream_30
- auipc a6, 848854
- lui s3, 472616
- c.addi s8, 10
- c.lui a3, 3
- lui s1, 849718
- c.srai a4, 9
- c.addi t5, -31
- divu s7, s3, zero
- c.srli a3, 24
- c.slli t1, 25
- auipc s9, 72748
- or s9, ra, s2
- c.addi t5, 21
- lui a2, 987006
- c.addi a7, -5
- c.addi s9, -5
- div a1, zero, s4
- divu a6, s0, a3
- auipc a4, 68096
- bgeu s7, t5, 1276f
- sltiu s0, a2, -974
- c.srai a4, 9
- c.addi a2, -27
- lui a1, 86752
- c.addi s1, 25
- c.slli a2, 26
- lui gp, 548602
- c.srai a3, 10
- c.bnez a3, 1270f
- c.mv t2, a3
- c.lui t1, 8
- c.addi s5, -5
-1270: add a3, sp, a0
- lui s0, 842855
- c.srai s1, 22
- lui a0, 986239
- c.li s8, -7
- lui t4, 844279
-1276: mul s11, gp, s3
- c.addi t4, 4
- fence.i
- auipc a3, 680069
- c.lui s10, 8
- auipc t1, 486570
- c.addi t2, 22
- c.addi s7, 20
- lui a7, 399143
- lui s9, 115047
- auipc s8, 164519
- c.slli s11, 12
- c.addi s4, 18
- bgeu a5, s5, 1306f
- auipc s11, 939445
- c.lui a2, 20
- c.nop
- c.srli a3, 11
- c.slli s3, 7
- c.beqz a1, 1304f
- bltu s8, s5, 1298f
- c.srli s0, 13
-1298: c.and a2, s1
- c.lui a5, 12
- mul s1, t5, a5
- c.srli s0, 26
- c.addi a7, -6
- c.slli s0, 27
-1304: auipc s9, 44757
- c.srli a1, 6
-1306: c.sub a1, a1
- c.lui gp, 12
- and t3, gp, s11
- xori a5, s5, -955
- c.lui a1, 20
- c.xor a4, a5
- auipc a5, 935577
- c.addi s9, -10
- fence.i
- xor s3, tp, sp
- srl s4, t3, s2
- c.slli gp, 29
- c.srai s1, 31
- bge s0, t1, 1329f
- c.addi t4, -29
- c.nop
- c.addi s2, 17
- la a0, data_page_12+1825 #start riscv_load_store_rand_instr_stream_62
- sh t4, -723(a0)
- lbu s11, 1892(a0)
- lh s2, 443(a0)
- lbu t4, 357(a0)
- xori s8, s3, 339
- auipc s0, 434421
- lbu gp, -1063(a0)
- sh s9, -1611(a0)
- andi a1, s0, 244
- mul a5, sp, a5
- c.slli s8, 5
- lb t3, 402(a0)
- auipc s2, 779977
- lb a4, 189(a0)
- lui s0, 1007077
- c.addi s6, 3
- sb s3, -455(a0)
- c.addi t2, -7
- c.addi s0, -21
- lhu s3, -1435(a0)
- auipc t2, 1041398
- auipc gp, 757890
- lbu a1, -380(a0)
- lb s0, 1456(a0)
- lbu s1, -215(a0)
- c.slli a6, 27
- c.lui a3, 5
- sb t6, 1604(a0)
- lbu s8, -973(a0)
- sb t1, 717(a0)
- c.addi gp, 16
- mulhsu a6, a6, s4
- sb ra, 305(a0)
- lb s10, 156(a0)
- c.lui s3, 5
- c.srai a3, 8
- c.lui t1, 22
- lh s11, -821(a0) #end riscv_load_store_rand_instr_stream_62
- auipc a3, 1029053
- c.addi s7, -5
- auipc s4, 1005310
- c.addi t1, -26
- c.lui t5, 5
- lui a4, 21081
-1329: c.lui s7, 22
- c.addi a6, 13
- c.addi s6, 3
- c.addi s7, -11
- c.srli a0, 21
- c.addi t6, -32
- c.addi s2, -7
- c.addi t5, 6
- sub a5, a6, a5
- or t4, tp, s6
- c.slli s5, 28
- div s11, t6, a2
- la s4, data_page_14+1844 #start riscv_load_store_rand_instr_stream_53
- lb zero, 182(s4)
- c.srli s0, 10
- lb t1, -414(s4)
- lb t4, -771(s4)
- sb tp, -1155(s4)
- rem s3, t5, t5
- lui s1, 944122
- c.lui s2, 19
- sb t3, -182(s4)
- sb tp, 1819(s4)
- lw a0, 336(s4)
- lhu s8, 694(s4)
- lbu s2, -737(s4)
- c.slli a3, 31
- c.addi s2, -6
- sltiu a0, a7, 77
- c.addi s10, -24
- mulhsu s6, a6, t0
- lui s1, 1044687
- c.addi s10, -11
- lb t6, 979(s4)
- auipc a2, 781810
- c.lui s9, 15
- lb t3, 411(s4)
- and s10, a2, s2
- lbu t6, -227(s4)
- c.srai s0, 4
- c.addi s11, 27
- sb zero, 1588(s4)
- lui a5, 680568
- c.li gp, -13
- mul s11, a6, s11
- lui gp, 640587
- c.addi s3, 1
- c.lui a6, 23
- c.slli a7, 1
- c.srai a2, 15
- lui s0, 709472
- sb s9, 803(s4)
- c.addi a2, 27
- sb s1, -499(s4)
- lui a2, 249519
- c.srli a5, 25
- lb s2, 501(s4)
- auipc t3, 270073
- c.addi s11, -19
- lbu s9, -1801(s4)
- sh t3, 1206(s4)
- lbu a4, -739(s4)
- lb a6, -102(s4) #end riscv_load_store_rand_instr_stream_53
- auipc s9, 794964
- c.srli a2, 8
- or a0, a3, a2
- lui s1, 179380
- c.and s1, s1
- andi s5, a5, 816
- c.addi t1, 22
- ori t4, s11, 634
- c.slli t3, 4
- c.addi a1, 29
- sra s2, a3, s10
- c.addi s9, 6
- c.addi s3, 14
- c.addi t5, -5
- c.addi s2, 5
- lui a0, 417459
- c.slli s7, 9
- c.lui s10, 18
- lui s10, 830928
- c.addi a7, -28
- lui a5, 556747
- auipc s0, 678597
- beq a6, s10, 1364f
-1364: auipc t4, 61505
- fence
- c.srli s1, 4
- c.srai a1, 15
- c.addi t4, 9
- lui a6, 521290
- c.xor a2, a4
- fence
- c.addi s0, -24
- lui a5, 875803
- blt ra, zero, 1377f
- c.addi s3, -16
- c.addi s7, 11
-1377: xor a6, a0, s6
- c.addi a3, -26
- c.slli a1, 27
- c.srli s0, 9
- remu t5, s7, gp
- c.addi s6, 4
- c.addi s4, 15
- c.addi t3, -28
- slli s0, ra, 15
- div a1, s4, ra
- auipc s10, 946116
- slli s6, s5, 19
- auipc a3, 863730
- c.addi t4, 2
- c.addi s11, -31
- auipc a6, 680798
- c.srai a4, 21
- slti s10, tp, 719
- lui t5, 627780
- bge s7, a1, 1413f
- c.sub a4, a2
- fence.i
- c.slli a5, 4
- c.lui s1, 31
- c.addi a4, -4
- srai s3, a3, 1
- lui t6, 982699
- bge s11, t2, 1419f
- c.addi s0, -5
- divu a0, a3, s9
- c.li a2, 0
- auipc t5, 506679
- lui a0, 772363
- and s5, a7, gp
- auipc a0, 777985
- auipc a4, 876749
-1413: c.srai a2, 25
- c.addi s3, 22
- c.addi t1, -10
- sltiu s4, s9, 941
- slli a1, s1, 7
- lui a0, 734643
-1419: c.lui t2, 25
- c.addi a2, -18
- lui s1, 82773
- sltiu a5, t2, -329
- c.addi t1, -8
- auipc t1, 188875
- c.lui t2, 17
- c.srli a1, 9
- c.slli s10, 8
- c.addi s5, 14
- c.addi s10, -26
- c.slli s0, 6
- c.addi a5, 29
- c.srli a0, 14
- c.srai a3, 8
- lui s8, 973427
- c.addi t3, 14
- c.lui s10, 6
- c.srli a1, 29
- c.slli gp, 21
- c.addi t5, -5
- c.slli a6, 20
- c.srai s1, 9
- c.addi s7, 30
- c.slli t3, 7
- c.addi s1, -15
- lui s11, 599643
- lui s7, 104762
- mulh s6, a4, gp
- c.addi a4, 3
- c.addi a3, 23
- lui s1, 151454
- c.lui s4, 9
- bge tp, t2, 1458f
- bge s5, a7, 1473f
- c.slli a0, 8
- c.addi s4, 24
- c.addi a1, -31
- sltiu a5, s10, -1001
-1458: c.slli a3, 26
- add t3, t5, t2
- c.addi s2, 15
- lui t4, 593590
- c.srli s0, 4
- c.addi s7, 28
- c.srli a2, 3
- c.addi t4, 13
- lui s6, 345561
- and a6, a3, s8
- c.lui a0, 3
- c.addi t3, 28
- lui a2, 744887
- c.addi a7, -1
- mulhsu gp, gp, a5
-1473: or zero, a7, ra
- auipc s4, 823919
- bgeu s1, t4, 1488f
- c.slli a2, 13
- c.addi a4, -26
- c.slli a5, 18
- lui s10, 782514
- c.srli a1, 24
- c.lui a2, 8
- sll zero, s8, a3
- c.srli a1, 24
- auipc a4, 32662
- auipc s6, 131750
- lui s9, 541476
- andi gp, a4, -127
-1488: slti zero, a3, -106
- c.srai a1, 27
- c.srli a3, 8
- c.addi s8, -26
- and a1, a5, t5
- c.slli s1, 17
- c.slli a3, 6
- mulhu t5, sp, a6
- mulh s8, gp, s8
- lui a2, 944657
- lui s6, 95264
- bltu a3, s8, 1516f
- and s3, s0, a4
- sub t1, s8, a4
- c.lui gp, 10
- auipc s8, 102267
- div t3, t5, a7
- or a4, s7, tp
- c.slli s3, 10
- c.addi t3, 22
- lui s9, 197262
- lui s6, 254709
- auipc s10, 43869
- c.li s3, 4
- c.beqz a2, 1532f
- c.addi a0, 17
- c.addi t5, -16
- c.lui t5, 10
-1516: c.addi t2, 7
- lui a0, 878359
- fence.i
- lui a1, 966684
- c.addi s4, 1
- bne t2, a4, 1524f
- auipc a3, 102439
- andi zero, a6, 62
-1524: auipc s11, 530572
- auipc a2, 289985
- c.addi s0, -29
- c.lui gp, 21
- lui s6, 144134
- c.addi s0, 18
- c.addi t1, 29
- lui s0, 195374
-1532: c.addi t3, -13
- c.srli a1, 30
- mul a0, a2, tp
- c.srai s1, 30
- auipc a3, 996938
- bltu tp, s9, 1542f
- c.addi a2, 22
- c.lui s3, 22
- c.addi s3, 7
- rem a1, s9, t4
-1542: lui a4, 924453
- c.addi s11, -25
- auipc a2, 521986
- beq t5, s10, 1564f
- c.addi s11, -26
- auipc t2, 412993
- c.addi t6, 19
- c.addi s6, -4
- auipc a0, 98830
- c.lui s7, 24
- c.slli s3, 21
- xori s10, ra, 881
- c.addi t3, -15
- c.mv s11, s10
- c.srli s0, 29
- c.addi s1, -7
- c.srli a2, 26
- lui s6, 192187
- c.lui t2, 26
- c.lui t3, 11
- c.lui t1, 15
- c.lui a1, 28
-1564: andi gp, s2, -7
- c.srli s0, 25
- c.addi s11, 8
- andi s11, a6, 765
- auipc gp, 558666
- auipc s0, 213918
- c.srai s0, 16
- c.addi t1, 21
- divu t2, tp, s7
- c.addi s8, 4
- andi s3, a1, -115
- auipc t3, 763510
- lui s7, 710011
- c.addi a3, 18
- c.slli t4, 10
- c.srli a4, 15
- lui s3, 562833
- lui a1, 862259
- c.srai a4, 24
- lui s8, 526701
- and s10, a7, t0
- c.addi s0, -18
- lui s7, 655846
- c.addi s6, -1
- auipc a4, 56341
- c.addi s9, 14
- lui a7, 789822
- auipc t6, 523409
- c.addi t4, 22
- div s2, s0, sp
- c.lui s6, 11
- c.addi t5, 28
- c.srai a5, 16
- mul gp, s8, s5
- c.addi t1, -19
- c.addi a5, 12
- c.addi t4, -8
- c.srai a1, 7
- sra s8, a0, ra
- c.addi t4, -25
- c.srai a3, 18
- c.addi s6, 31
- c.addi gp, 4
- c.addi s10, -2
- c.or a0, a4
- c.lui a3, 25
- c.slli t3, 11
- auipc s3, 203246
- c.addi s0, -12
- c.addi t3, -7
- c.lui t1, 26
- rem s8, s9, s5
- or a6, a3, s9
- addi s4, s0, 558
- nop
- c.addi a0, 13
- c.bnez a5, 1637f
- c.srai a4, 21
- lui a0, 955744
- mul s10, s9, s1
- c.addi a4, -11
- c.slli a4, 13
- c.srai s0, 16
- c.addi s10, -22
- c.addi s3, 20
- c.srli a0, 27
- c.srai a1, 29
- c.srai a3, 27
- c.srli a1, 7
- mulhu t5, s1, gp
- auipc t2, 53382
- lui s11, 258391
- mulhsu t4, t0, s3
-1637: auipc a2, 75374
- nop
- c.slli t2, 22
- mulhsu t6, a5, s2
- c.lui s7, 18
- c.slli a6, 28
- c.lui a5, 2
- c.srli a4, 16
- bltu a2, a5, 1646f
-1646: c.slli t6, 6
- c.slli s0, 20
- c.srli s1, 9
- c.addi s5, -4
- c.addi t6, 7
- c.addi s3, -5
- auipc t6, 897499
- auipc s3, 994142
- nop
- auipc t1, 395617
- sltu t2, a4, t2
- srai s8, s10, 14
- c.srli a1, 21
- c.slli t1, 30
- auipc s3, 500989
- c.addi s4, -32
- auipc a1, 531841
- lui s0, 792199
- c.srai a4, 29
- c.srli s1, 5
- c.addi s11, 26
- bgeu t5, ra, 1676f
- c.addi a0, 9
- c.addi s1, 8
- lui a1, 562929
- c.addi a0, -21
- c.slli s8, 5
- c.addi a4, -20
- slti s0, a6, -252
- sra s10, t5, s10
-1676: c.addi a1, -4
- c.lui s3, 12
- c.addi a3, -21
- lui t1, 436648
- c.addi a4, -22
- c.lui s8, 19
- c.srai a3, 31
- c.lui a5, 7
- sub s11, t6, a3
- mul gp, s4, s0
- c.srli a2, 28
- c.addi s1, 31
- c.addi s10, 28
- rem a4, s7, a6
- srai s7, t5, 28
- c.srli s0, 3
- c.slli s1, 20
- c.addi s2, -19
- srl zero, s5, a0
- lui s8, 721061
- c.slli t6, 14
- c.addi a5, -15
- auipc s7, 67148
- divu zero, a0, s6
- c.addi a5, -28
- lui s3, 109861
- lui s3, 210410
- ori s1, s1, 404
- c.addi s0, 23
- lui t5, 171570
- c.lui a2, 21
- xor s1, t6, t1
- c.srli a2, 5
- la s11, data_page_12+2133 #start riscv_load_store_rand_instr_stream_35
- c.srai a0, 1
- srli s2, a1, 25
- lui a3, 705079
- lb t1, -265(s11)
- lbu a5, -864(s11)
- lb a7, 504(s11)
- lhu s5, -1811(s11)
- xori a7, s8, 484
- sh t6, -193(s11)
- c.addi s9, -17
- c.add s1, a4
- lb t5, 1142(s11)
- lw t1, 135(s11)
- c.and a3, s1
- lhu t4, -1813(s11)
- c.lui t5, 19
- c.lui t1, 8
- lb s1, 1706(s11)
- lb s9, -1456(s11)
- lb t1, -1982(s11)
- lh a3, 1393(s11)
- c.srai a1, 1
- xor s4, s11, t2
- lh a0, -489(s11)
- auipc gp, 149162
- c.srli s0, 23
- sh s0, -437(s11)
- lb a0, -1343(s11)
- lui s2, 102727
- c.or a2, s1
- c.addi s2, -13
- sh s3, 1327(s11)
- sh s7, 71(s11)
- sb t0, 1632(s11)
- auipc a2, 463577
- lb a2, 1631(s11)
- lb t1, -1806(s11)
- lb s8, -1242(s11)
- lb s6, -1240(s11)
- c.srli a3, 25
- lb t2, 433(s11)
- sb zero, 1731(s11)
- slti a0, t0, -703
- sb s1, -1432(s11)
- lw t1, 791(s11)
- auipc gp, 210937
- lbu t2, -341(s11)
- sw ra, -997(s11)
- sb s11, 770(s11) #end riscv_load_store_rand_instr_stream_35
- c.srli s0, 20
- c.addi s5, 2
- lui s4, 167681
- sll t6, s4, a4
- c.srli a4, 5
- c.lui s3, 23
- lui a2, 96765
- c.addi t4, -20
- c.srli a1, 12
- c.sub s1, a0
- xori a0, a6, 601
- c.addi a4, -24
- c.addi s10, -23
- c.srai a1, 4
- c.addi t1, -10
- c.addi t2, -19
- lui a3, 301600
- c.srai a5, 18
- c.slli t5, 25
- auipc t5, 927593
- remu t2, t5, a2
- lui t2, 232550
- c.srai s0, 15
- c.addi s7, -26
- c.addi s6, -3
- c.addi a6, 28
- lui s1, 454149
- auipc a0, 989152
- ori s9, s3, -385
- auipc a3, 985948
- lui gp, 674405
- remu s1, t1, a2
- c.bnez s1, 1749f
- lui s4, 137730
- c.addi a4, -25
- auipc a7, 297504
- c.addi a2, 5
- c.addi t2, 15
- slli s8, s8, 11
- c.addi s3, -13
-1749: c.lui s8, 6
- c.addi s1, 31
- c.nop
- c.slli t5, 4
- c.addi t6, -1
- auipc zero, 544295
- c.srai s0, 23
- c.addi s10, -2
- c.addi s2, -8
- c.addi a7, 10
- c.addi t1, -5
- c.lui t5, 13
- auipc s10, 546697
- c.addi s1, -21
- auipc s0, 852686
- c.slli s1, 20
- srai s8, t5, 19
- c.addi a7, 26
- c.srli s0, 7
- c.addi a3, 3
- c.addi a0, 7
- c.addi t3, -25
- auipc t6, 865215
- auipc s9, 131751
- bgeu s10, gp, 1779f
- c.addi a6, 1
- c.srai a0, 22
- lui a3, 368459
- c.addi a4, 21
- lui t6, 888345
-1779: c.addi a6, 9
- c.bnez a0, 1795f
- addi s3, s10, -359
- c.addi s8, -7
- c.addi s8, -24
- xor s11, t6, a7
- slti s0, a0, -843
- c.addi s11, 22
- c.srli s1, 15
- c.andi a1, 19
- srai s8, s2, 22
- lui a2, 979935
- auipc a0, 984523
- c.addi s6, 6
- c.addi a6, -8
- c.addi a5, 31
-1795: c.srai a0, 20
- auipc s7, 861975
- c.srli a0, 20
- la t6, data_page_2+2503 #start riscv_load_store_rand_instr_stream_48
- sh a3, -677(t6)
- sb s7, 987(t6)
- divu s1, t5, a0
- c.addi s4, -27
- sw s0, -435(t6)
- auipc a7, 886710
- lb a1, 313(t6)
- c.addi a0, -13
- sb t0, -104(t6)
- auipc a1, 936706
- c.addi t2, 20
- auipc a0, 940896
- c.addi s4, 2
- lui s9, 90422
- sw s9, 1529(t6)
- c.lui a3, 22
- lb t2, -600(t6)
- auipc s6, 751602
- lb a4, 88(t6)
- sb t1, 83(t6)
- lb a1, -974(t6)
- sb a3, -1722(t6) #end riscv_load_store_rand_instr_stream_48
- c.andi s1, 14
- c.beqz s0, 1804f
- c.addi s6, 26
- srl s9, a6, t2
- auipc a5, 537901
- lui t2, 953172
-1804: lui a3, 548393
- auipc gp, 16528
- c.addi t3, 24
- la s11, data_page_7+1543 #start riscv_load_store_rand_instr_stream_63
- lbu s3, 608(s11)
- c.srai a1, 14
- lw a0, 93(s11)
- remu a4, s10, a4
- sb s4, -996(s11)
- lui gp, 56584
- lw a4, 629(s11)
- lb s10, 380(s11)
- lb a2, 1203(s11)
- add s10, t3, s9
- sb s2, 428(s11)
- lb a0, 742(s11)
- fence.i
- c.slli s9, 25
- c.srai a1, 17
- lb s5, 1952(s11)
- c.srai a1, 3
- lui s6, 263629
- lbu s3, 587(s11)
- sb s9, 1678(s11)
- c.addi s9, -22
- c.srai a5, 11
- c.srai a2, 26
- c.slli s3, 15
- c.srai a0, 23
- c.addi a5, -14
- lb a2, -1222(s11)
- c.lui s10, 14
- c.andi a3, -16
- sll s9, t5, s3
- lb s2, 652(s11)
- lui s8, 198493
- sb gp, 1497(s11)
- c.addi a1, 16
- c.srli a3, 23
- slti s4, zero, 319
- auipc a7, 330031
- sw a5, 709(s11)
- c.mv gp, s10
- mulh s6, s9, gp
- lhu t3, 1521(s11)
- lbu s6, 156(s11)
- lui s9, 783578
- lb t2, 1934(s11) #end riscv_load_store_rand_instr_stream_63
- xor s11, s11, t1
- c.li s5, 31
- c.addi a6, -22
- c.addi gp, -27
- c.addi a4, -29
- div a5, a6, s5
- sub t4, a3, a5
- c.bnez a0, 1832f
- c.srli s1, 10
- c.srli a5, 16
- c.addi s0, -12
- auipc a6, 329090
- c.addi s2, 12
- lui s5, 370149
- remu t4, a2, a4
- c.slli a7, 29
- c.srli a2, 10
- auipc s8, 66952
- sra a1, s10, gp
- c.slli t2, 20
- auipc t5, 343436
- xor s1, a0, t3
- c.addi a4, -7
- lui s9, 671831
- auipc s9, 912751
- la s9, data_page_4+1740 #start riscv_load_store_rand_instr_stream_39
- c.lui a4, 5
- auipc s7, 527944
- sb ra, 36(s9)
- lbu s7, 389(s9)
- lbu s3, -1113(s9)
- c.slli t1, 22
- lh a2, 708(s9)
- lb a0, -1354(s9)
- lbu gp, 428(s9)
- c.addi a1, 12
- lbu gp, -1532(s9)
- sb s11, 2028(s9)
- lb t6, 1870(s9)
- lh a6, 1050(s9)
- lui t1, 467304
- c.addi a2, -6
- sb ra, -901(s9)
- sh t0, -250(s9)
- sb s0, 1571(s9)
- sb a6, 304(s9)
- div a4, s9, a1
- lui s8, 990582
- c.lui t1, 14
- sw s11, 1888(s9)
- srl a3, a7, t3
- sh s10, 734(s9)
- lb s5, -1441(s9)
- lb a0, -1543(s9)
- c.nop
- lui s2, 681189
- lui s5, 801952
- sb s2, 1303(s9)
- lb s7, -506(s9)
- lh s2, -816(s9)
- lw t4, 1200(s9)
- c.srai a5, 8
- c.srli a3, 23
- lbu s1, 1781(s9)
- lh s7, -1082(s9)
- andi zero, tp, 934
- sb s10, 1246(s9)
- lw s8, 1900(s9)
- srli a1, sp, 12
- lbu t3, 903(s9)
- lw s1, -328(s9)
- c.srli a1, 23
- lh t3, -176(s9) #end riscv_load_store_rand_instr_stream_39
-1832: c.srli a2, 5
- c.addi a4, 16
- auipc a3, 814522
- c.srli a5, 1
- c.addi s2, 3
- c.slli s0, 25
- auipc t3, 148703
- lui t1, 1043002
- c.xor s1, a0
- c.addi a3, -12
- auipc s8, 359430
- c.srli a5, 18
- c.addi s2, 24
- c.addi s1, -26
- c.addi t5, 26
- c.srai a2, 19
- xor t2, t1, a6
- c.srli s1, 6
- nop
- c.lui a2, 30
- c.addi a0, 3
- srli gp, a2, 21
- c.lui a6, 26
- c.addi s8, 1
- c.addi gp, 1
- c.lui s8, 21
- c.addi a0, 25
- c.addi a5, -25
- c.slli s8, 22
- lui t5, 595435
- c.addi s3, -26
- lui a4, 311158
- auipc a1, 965221
- auipc t5, 983850
- c.addi a3, 10
- c.addi t3, -18
- c.srai s0, 20
- mulhu gp, a5, s2
- auipc zero, 546827
- lui s1, 19635
- divu s0, s4, t1
- c.addi a0, 10
- auipc s1, 979090
- mulh a6, a0, a5
- c.nop
- c.sub a2, a3
- c.srai a5, 14
- sll t6, t6, a3
- lui s9, 1520
- c.addi t1, -6
- c.addi s1, 26
- c.slli s11, 17
- c.lui s5, 11
- c.addi a1, -30
- la a2, data_page_17+1992 #start riscv_load_store_rand_instr_stream_51
- sb t6, 169(a2)
- sb s6, 155(a2)
- lh s10, 1520(a2)
- auipc s9, 355175
- lhu s9, -1986(a2)
- sb s8, 1753(a2)
- sltiu t6, a2, -694
- c.addi s2, -9
- lbu s2, 949(a2)
- lbu s3, 1969(a2)
- lbu a7, 290(a2)
- lb a5, 1098(a2)
- c.srai a3, 29
- lb gp, 22(a2)
- lbu s0, 215(a2)
- lbu s0, -841(a2)
- lb s10, 749(a2)
- lui a7, 674250
- lb a0, -1267(a2)
- lb t6, -1881(a2)
- lh t3, -1170(a2)
- c.srli a1, 19
- lbu a1, -1630(a2)
- lb t6, -1510(a2)
- c.mv a3, s9
- lh s11, 1578(a2)
- lb t2, 994(a2)
- sb a7, -1565(a2)
- lui a4, 1041924
- lui s7, 364090
- sb a1, 612(a2)
- lb a3, 1537(a2)
- c.or a0, a3
- lbu a5, -1169(a2)
- auipc s10, 90273
- lbu t5, -606(a2)
- sb a7, -1224(a2)
- sb a3, -873(a2)
- auipc t1, 385914
- lbu s6, 1887(a2) #end riscv_load_store_rand_instr_stream_51
- auipc a7, 878710
- c.addi a2, 9
- c.addi a7, -30
- c.srli a3, 12
- c.srli a0, 3
- c.lui s8, 6
- auipc t5, 990314
- auipc a0, 656047
- c.lui a0, 2
- c.slli t1, 9
- c.lui a3, 23
- ori s4, s2, -322
- c.addi t3, 26
- c.addi a7, -19
- auipc a5, 463322
- bltu a2, sp, 1905f
- lui a0, 252213
- srli gp, s1, 12
- c.addi s0, -3
-1905: lui s7, 602832
- sltu a1, t2, a7
- auipc s6, 565548
- la a4, data_page_9+2030 #start riscv_load_store_rand_instr_stream_60
- divu s8, tp, a6
- lh s11, -1256(a4)
- c.addi a5, -15
- sb a2, 133(a4)
- lb a6, 419(a4)
- c.lui s6, 2
- lbu t6, -2016(a4)
- sh a3, 1740(a4)
- lui a6, 890201
- lhu s2, 848(a4)
- sb t5, -872(a4)
- c.addi s8, -6
- sb t6, 373(a4)
- c.addi s2, 31
- lbu a0, -1237(a4)
- lbu gp, 621(a4)
- sb sp, 237(a4)
- lui s0, 787273
- c.addi t1, 20
- lbu t4, 1585(a4)
- sb s0, 1759(a4)
- lb a5, 733(a4)
- lb a2, -1003(a4)
- lb t1, 577(a4)
- rem s5, a5, s2
- lh zero, -470(a4)
- sb t6, 961(a4)
- lb s10, 1657(a4)
- lh s6, -1300(a4)
- auipc s6, 790716
- sw zero, 674(a4)
- c.lui t2, 17
- sb tp, 1858(a4)
- sh t1, 556(a4)
- c.sub s0, a0
- sb sp, -1254(a4)
- lh t4, -610(a4)
- c.srli a1, 13
- auipc t3, 278045
- c.addi a7, 4
- lb s11, 778(a4)
- lbu t1, -257(a4)
- lui a6, 319628
- lh s9, 1080(a4)
- c.slli a2, 28
- auipc s8, 928654
- srl t4, s0, s1
- sb sp, -1239(a4) #end riscv_load_store_rand_instr_stream_60
- lui gp, 922246
- c.srli s0, 18
- c.addi t5, 30
- lui t6, 525744
- c.lui a0, 25
- lui s7, 60147
- lui t6, 384917
- auipc s0, 81512
- lui t6, 799931
- c.srai a4, 9
- c.addi a5, -31
- or s4, zero, t3
- c.addi t4, 27
- c.xor s0, a3
- c.addi s9, -30
- c.srai a1, 15
- lui a4, 142895
- c.lui s4, 26
- auipc s11, 402455
- c.sub a3, a3
- c.srli a2, 14
- c.addi t5, 23
- and t5, a3, t1
- c.addi s4, 26
- c.srli a5, 6
- lui s10, 484818
- auipc a3, 221149
- sra a4, a5, s4
- la s4, data_page_5+2139 #start riscv_load_store_rand_instr_stream_69
- lui a5, 462253
- auipc s6, 550898
- auipc t2, 182425
- lhu t2, -1479(s4)
- c.srai a4, 19
- lb s11, 1008(s4)
- sb tp, -1039(s4)
- sb s1, 1423(s4)
- c.addi a5, 24
- sb a4, 203(s4)
- sb zero, -445(s4)
- c.addi s0, 22
- lb a4, 238(s4)
- lbu s8, 1640(s4)
- sb s1, -1952(s4)
- div t5, a3, a3
- sb s11, 1732(s4)
- sb s2, -860(s4)
- sb s7, -548(s4)
- lb a4, 407(s4)
- mulh s11, s0, s8
- c.add a2, a3
- lbu a0, 870(s4)
- lb s8, 1696(s4)
- lb a2, 620(s4)
- auipc a3, 766907
- c.srai a1, 8
- sb s7, -1442(s4)
- c.srli s0, 3
- sb t4, -637(s4)
- lbu a2, -707(s4)
- c.or a4, a5
- c.addi t1, -4
- c.addi s2, 3
- c.srli a2, 23
- lhu t5, -1935(s4)
- sb s2, -646(s4)
- lbu a1, 831(s4)
- c.xor a2, a5
- sb s9, -536(s4)
- mul a6, a4, sp
- c.lui a3, 31
- sb t0, 1323(s4)
- lw s8, 1521(s4)
- c.addi a6, -30
- sb a4, 684(s4)
- lb s11, 816(s4)
- auipc s6, 729940
- lh t3, 1465(s4) #end riscv_load_store_rand_instr_stream_69
- c.addi s0, -26
- lui s1, 175503
- c.srli a1, 30
- lui s9, 270028
- auipc s4, 769434
- auipc a4, 434390
- auipc s3, 965256
- c.addi t1, 16
- auipc t1, 1003810
- c.lui s11, 23
- c.lui t5, 26
- bne t5, s6, 1952f
- auipc s5, 269713
- mul a7, zero, s4
- c.addi a0, 27
- sltu a3, a1, t5
-1952: srl t6, t6, a3
- c.srai s1, 14
- c.srai a1, 29
- lui a6, 45412
- c.addi s0, 14
- c.beqz s0, 1975f
- c.addi s3, 11
- srai t1, s10, 0
- c.addi t2, -20
- and a5, s1, a1
- c.addi a5, -3
- c.addi s9, -24
- c.srai a4, 3
- auipc t3, 18126
- c.srai s0, 22
- c.srli a2, 5
- c.addi gp, 19
- c.addi t5, 11
- c.addi s10, -6
- ori a6, s4, 981
- c.addi gp, -20
- c.lui a6, 28
- mulhsu s5, a7, a5
-1975: auipc s4, 303718
- auipc s4, 603139
- c.andi a5, -5
- sub s0, s1, s10
- auipc s2, 488125
- c.lui s8, 14
- c.srli a4, 6
- mulh s1, a1, a5
- c.slli t3, 31
- c.addi a5, 28
- c.srai s0, 22
- auipc zero, 406501
- lui t5, 221654
- lui s7, 418305
- c.srli a3, 24
- c.slli s0, 21
- bgeu s1, sp, 1995f
- auipc a5, 689031
- c.addi s10, -12
- c.addi s3, 2
-1995: c.srai s1, 28
- auipc s6, 16770
- sltu s10, a1, s0
- c.beqz s0, 1999f
-1999: c.addi t4, -6
- c.slli s3, 25
- auipc s9, 57187
- auipc a0, 808500
- sll a2, s0, s9
- c.addi a6, 31
- remu s11, tp, a7
- c.srai a5, 8
- c.addi s11, -6
- c.slli a4, 16
- bltu s9, a4, 2012f
- c.srli a1, 3
- addi s8, s0, -52
-2012: c.srai a3, 2
- c.srli s0, 28
- c.addi a4, 11
- auipc t6, 316424
- bge t5, a0, 2017f
-2017: c.addi s10, -31
- c.srai a3, 26
- sra a3, ra, t0
- c.srli s0, 17
- lui s1, 890452
- auipc a5, 977995
- c.srli a2, 29
- auipc a5, 780337
- c.srai a2, 16
- srl zero, tp, s3
- c.addi s11, 26
- c.addi s9, -13
- c.lui a2, 14
- c.li t2, 27
- c.or a5, a4
- la t3, data_page_16+2425 #start riscv_load_store_rand_instr_stream_23
- c.slli t6, 10
- lb t6, -1719(t3)
- sb a6, 1253(t3)
- sb s9, -1704(t3)
- lhu s4, -657(t3)
- c.srai a4, 19
- lh t1, -751(t3)
- auipc zero, 541040
- sw gp, -1233(t3)
- fence
- sb zero, 1151(t3)
- lbu a7, 538(t3)
- c.slli s8, 11
- lb a6, 47(t3)
- c.addi t6, -7
- lbu s8, 946(t3)
- lbu s3, -1470(t3)
- lh t5, 1233(t3)
- lbu t4, 1435(t3)
- c.lui s3, 3
- c.addi s7, 23
- lui s10, 779248
- c.nop
- lhu a2, -635(t3)
- lh t6, -179(t3)
- lb a1, -846(t3)
- lb zero, -1874(t3)
- sh s8, -1103(t3)
- sw a5, -1621(t3)
- lbu a1, 155(t3)
- sb s1, -622(t3)
- c.slli t1, 2
- sb s10, 104(t3)
- sh s8, 83(t3)
- lbu a5, 962(t3)
- lbu gp, 352(t3)
- lbu s11, 1214(t3)
- sb a0, 1027(t3)
- sb a6, 1604(t3)
- lb a5, -1363(t3) #end riscv_load_store_rand_instr_stream_23
- c.srai s1, 11
- lui t2, 573969
- c.addi t3, 15
- remu s11, s4, a6
- c.addi a1, -25
- c.lui t6, 20
- bne s3, s9, 2039f
-2039: c.lui s8, 7
- c.addi a3, -8
- auipc t1, 854768
- lui a1, 974885
- c.li s6, 4
- c.srai a1, 20
- c.addi s7, -31
- c.addi a2, -32
- c.addi a3, -11
- c.addi t2, 27
- c.srai a1, 2
- c.srai s1, 31
- slt s9, a3, a2
- lui a0, 341706
- c.beqz a5, 2060f
- c.addi s0, -19
- c.addi s6, -23
- c.srli a1, 22
- c.addi s6, -31
- sll s8, a4, t6
- auipc s11, 678016
-2060: c.addi gp, -8
- c.slli a6, 27
- c.lui a4, 10
- c.addi s2, 25
- c.lui a7, 27
- lui s6, 793446
- c.slli s3, 23
- c.lui s9, 6
- srl zero, s9, s3
- auipc a0, 917236
- lui s6, 695792
- c.lui s3, 14
- mulhu s9, a2, ra
- c.addi s7, 14
- c.addi s5, 25
- c.slli s5, 6
- c.srai a4, 18
- c.addi s11, -2
- sltu t4, t3, s5
- c.slli t1, 9
- c.srli a1, 24
- lui a0, 12369
- c.lui s6, 6
- lui s4, 366649
- c.srai a2, 5
- auipc t2, 73866
- auipc s6, 756711
- c.addi s1, -24
- c.addi s11, 18
- c.slli s11, 15
- c.addi a7, -3
- c.and s0, a3
- c.slli t5, 6
- c.bnez a5, 2098f
- auipc s8, 181874
- lui s11, 456591
- sub s3, s8, t3
- c.sub a1, a2
-2098: lui s3, 470971
- c.addi s3, -3
- srl t5, s11, s10
- c.addi s1, -26
- c.lui t2, 17
- c.lui a0, 9
- c.srli s0, 18
- la t5, data_page_15+1961 #start riscv_load_store_rand_instr_stream_0
- lbu s4, 1854(t5)
- lbu t3, 112(t5)
- lhu a7, 999(t5)
- lb s1, -64(t5)
- c.srai s0, 31
- sh a5, 601(t5)
- lui a6, 197077
- c.lui s5, 19
- ori zero, a6, -391
- sb tp, -447(t5)
- auipc s2, 496573
- sh a1, 497(t5)
- sh a0, -1221(t5)
- c.lui t2, 14
- sb s8, 529(t5)
- c.addi s8, -23
- ori a0, gp, 113
- lb t4, 1672(t5)
- c.srai a5, 22
- lhu a7, -1681(t5)
- lw a5, -729(t5)
- c.addi s7, 27
- c.slli s4, 11
- c.addi s1, -25
- lhu a4, 393(t5)
- lhu s1, 639(t5)
- sltu s7, t5, a6
- lh s4, 1899(t5)
- auipc s1, 962489
- sh t1, 1503(t5)
- lb t1, -1680(t5)
- lbu s11, -571(t5)
- c.srai a1, 27
- sb a5, -352(t5)
- lhu zero, 423(t5)
- lbu a4, -1866(t5)
- c.srai a0, 24
- c.slli s11, 15
- lui t2, 479247
- slt t4, s7, a0
- mul t2, a3, t0
- lh s7, -105(t5)
- lbu s6, -554(t5)
- sw zero, -993(t5)
- fence
- lw s11, 603(t5)
- lui gp, 985587
- lb t2, -118(t5)
- lbu t4, 1708(t5) #end riscv_load_store_rand_instr_stream_0
- auipc t3, 735589
- addi s2, a6, -1
- lui a3, 77439
- c.mv a1, t5
- lui s6, 146185
- c.addi s3, -6
- c.addi s1, 10
- andi t1, s5, -461
- c.addi a0, 6
- c.addi t6, -27
- slli s3, a1, 14
- lui s10, 667895
- auipc a3, 449642
- c.slli s4, 10
- lui t5, 674181
- c.srli a3, 26
- auipc a0, 156250
- slli a3, s4, 22
- c.addi a0, -14
- c.addi a6, -16
- c.slli a7, 31
- c.addi s1, 13
- c.xor a1, a1
- c.lui s8, 13
- nop
- lui a6, 923562
- c.slli s6, 22
- c.srli a1, 2
- auipc s2, 266498
- c.addi s4, 26
- c.lui s1, 5
- auipc s9, 242794
- sltu a2, t2, s6
- c.nop
- c.srai a4, 4
- c.bnez a3, 2142f
- lui s6, 477656
-2142: c.addi a0, -32
- lui s10, 834685
- c.nop
- c.lui a2, 27
- mulhsu s9, gp, gp
- c.addi s5, 22
- c.beqz a1, 2165f
- c.addi a0, 29
- remu a4, t5, t2
- c.addi s5, -20
- auipc a1, 631524
- fence.i
- add s8, zero, t1
- c.addi t2, 8
- mul s4, s8, a6
- auipc s3, 807605
- auipc a1, 569270
- c.srli a0, 6
- fence.i
- c.or a0, a4
- blt a7, a0, 2165f
- c.slli a6, 13
- c.addi s10, -13
-2165: c.srai a1, 11
- auipc a7, 597807
- c.slli t1, 7
- auipc s3, 820927
- c.slli a5, 5
- c.addi s6, -24
- lui a3, 501529
- rem s2, s10, sp
- lui a2, 444421
- bltu a5, s6, 2179f
- c.addi s9, -6
- c.slli s6, 24
- srai a7, t6, 24
- c.slli a0, 21
- la t4, data_page_11+2031 #start riscv_load_store_rand_instr_stream_46
- lhu a4, 571(t4)
- c.addi a2, 19
- sh s10, -231(t4)
- fence
- lbu s2, 1425(t4)
- c.addi t5, -20
- srai s4, a2, 2
- c.srai a2, 6
- or s5, s5, s4
- sw s8, -987(t4)
- lbu gp, 628(t4)
- c.srai a5, 8
- srli s1, ra, 1
- c.srli s1, 17
- lui t3, 64349
- c.srai s0, 31
- lb t6, -1773(t4)
- sw tp, 513(t4)
- lbu s0, 534(t4)
- sb s8, 1061(t4)
- sb a6, 653(t4)
- c.srai a0, 21
- c.addi t1, -5
- c.lui s9, 17
- lb s10, -1540(t4)
- c.addi a4, 31
- srl t2, s10, s11
- sh tp, 1199(t4)
- lui s7, 616483
- c.srai a5, 9
- c.addi t3, -17
- auipc a1, 693980
- lui a3, 918384
- c.srli a4, 31
- lui t1, 62385
- auipc s8, 110641
- c.srli a5, 8
- lui t3, 927764
- sll s0, a3, sp
- auipc a7, 1004050
- lh s0, -345(t4)
- c.addi t5, -13
- remu s8, s0, t4
- lb a1, 1922(t4) #end riscv_load_store_rand_instr_stream_46
-2179: c.addi a2, -27
- c.srli a4, 25
- c.srli a1, 23
- c.srai a4, 9
- lui a3, 344882
- c.beqz a5, 2191f
- c.mv s6, t6
- c.addi s11, -32
- c.addi s6, -26
- lui t1, 222053
- c.srai a3, 19
- c.addi s8, 16
-2191: auipc gp, 149523
- c.addi t5, 2
- c.srli a1, 23
- lui s3, 911036
- c.addi s9, -9
- c.lui s5, 15
- c.lui a0, 13
- lui a4, 716933
- c.addi s5, 1
- lui a3, 268337
- c.lui s1, 4
- auipc t2, 88047
- c.srli a1, 18
- bltu s0, t6, 2211f
- c.slli a0, 10
- auipc s9, 22627
- lui s8, 41080
- c.addi t3, 5
- c.addi s6, 21
- c.lui a3, 9
-2211: auipc s7, 442117
- auipc s1, 82412
- c.addi s7, -4
- c.srai a5, 30
- c.slli a0, 13
- fence
- c.srai a0, 2
- fence
- lui a2, 421872
- lui s10, 138635
- slli t6, s10, 1
- auipc t6, 317496
- c.addi t3, 18
- c.lui a2, 26
- c.addi s5, 10
- c.xor s1, a4
- c.addi s1, 14
- auipc a4, 869127
- lui t4, 186959
- bgeu zero, s10, 2247f
- c.lui a2, 10
- c.addi s11, 20
- c.addi s4, -30
- auipc a4, 786666
- c.lui a3, 5
- c.addi a3, 4
- lui a5, 809502
- auipc a5, 815870
- c.lui s1, 25
- c.addi gp, 11
- lui s11, 973828
- c.lui t2, 7
- c.addi a0, -6
- lui s4, 454012
- c.addi s3, -23
- c.addi t6, -1
-2247: remu a0, a4, ra
- lui t3, 407791
- c.addi gp, 23
- c.srai a4, 13
- c.addi s2, 18
- c.srai s1, 16
- c.srai a5, 21
- c.addi t5, -7
- c.lui a7, 21
- div s11, s7, s5
- auipc s8, 782012
- c.addi s0, 3
- c.addi s0, -22
- blt a7, zero, 2275f
- auipc s4, 10255
- c.addi t5, 20
- c.addi a7, -32
- c.addi t4, 22
- auipc t2, 269271
- c.lui a4, 8
- c.addi s0, -15
- lui s3, 273856
- lui s8, 325157
- c.slli t5, 18
- c.xor a1, a0
- c.mv t3, t6
- la t6, data_page_3+1939 #start riscv_load_store_rand_instr_stream_49
- lh t2, -1711(t6)
- lb t5, 1563(t6)
- lbu s0, -714(t6)
- lb a4, 766(t6)
- c.addi s1, -9
- c.slli s8, 15
- lbu s1, -1598(t6)
- slli s3, s11, 15
- lbu s9, 18(t6)
- sb a2, -462(t6)
- c.addi s0, 4
- c.addi s3, -25
- lui s3, 1043585
- lui s5, 1025475
- c.addi t5, 3
- lb t4, -1893(t6)
- sb s9, 947(t6)
- sb t0, 1976(t6)
- lb s3, 1124(t6)
- sb t3, -848(t6)
- c.srli a3, 22
- c.srai a3, 19
- lui a0, 720752
- c.slli a5, 23
- sh tp, 795(t6)
- lui s8, 837920
- lbu a5, 1278(t6)
- sb gp, 1158(t6)
- lui s1, 283922
- c.srli a1, 7
- lb t2, 1854(t6)
- srai s0, a0, 11
- sb s5, 986(t6)
- lui t5, 910330
- c.slli s8, 18
- srai t5, t6, 16
- c.slli s8, 22
- lbu s11, 348(t6)
- sltiu s9, a0, 892
- srai a3, a6, 8
- c.slli s3, 6
- c.addi a3, 21
- lui s3, 220726
- lui t1, 531360
- lh s3, -1851(t6)
- lui zero, 717317
- srli t1, s11, 28
- c.slli s1, 3
- auipc s2, 792136
- lh s3, 591(t6)
- sb a4, 920(t6) #end riscv_load_store_rand_instr_stream_49
- c.srai a3, 5
- lui a1, 315813
-2275: xori a5, s6, -479
- c.lui a3, 31
- auipc s3, 218523
- la t1, data_page_2+2040 #start riscv_load_store_rand_instr_stream_67
- lb a5, 235(t1)
- lb a5, -1151(t1)
- sb a7, -229(t1)
- c.addi a2, -21
- lbu zero, 184(t1)
- lbu a5, 1297(t1)
- sra a5, a2, a0
- lbu t2, -891(t1)
- lbu s6, -1601(t1)
- lb s7, 1981(t1)
- lb zero, -1323(t1)
- lb s4, 8(t1)
- sb ra, 1759(t1)
- c.mv s6, a7
- lbu s0, 1841(t1)
- lh s1, -1254(t1)
- lb a3, 1911(t1)
- sb a7, 1401(t1)
- lbu t4, 279(t1)
- lb s2, -1010(t1)
- lbu s3, -99(t1)
- c.addi s5, 1
- c.addi s10, -13
- sb s10, 1187(t1)
- lw s6, 732(t1)
- srli s9, s9, 11
- sltiu t4, a3, -459
- lb s4, -783(t1)
- auipc s11, 876006
- c.addi s8, -7
- lb a3, -1117(t1)
- lui a1, 582596
- lui a7, 849834
- auipc a4, 282879
- auipc a0, 504331
- lb a6, 1409(t1)
- lb t6, -299(t1)
- sw s3, -1128(t1)
- lhu t3, -1450(t1) #end riscv_load_store_rand_instr_stream_67
- c.lui t6, 4
- auipc s0, 727510
- c.beqz a2, 2300f
- auipc t4, 903513
- c.lui a2, 25
- mulhsu s6, s0, sp
- c.addi s4, 4
- c.srai a0, 3
- bge s2, a0, 2305f
- auipc a7, 91755
- c.addi s1, -32
- rem s11, s9, gp
- c.srli a5, 10
- auipc s7, 206659
- c.li a1, -18
- auipc s9, 62901
- c.addi a2, 19
- auipc a4, 18616
- fence
- c.slli a0, 17
- auipc t4, 823615
- c.srli a3, 25
-2300: bltu s2, s1, 2318f
- c.addi s8, 9
- lui t4, 792282
- lui s2, 1010477
- c.lui t1, 30
-2305: c.srli a4, 16
- c.srli a3, 8
- c.addi a5, 23
- srli s8, s8, 22
- c.addi a2, -4
- blt t6, t6, 2323f
- auipc s0, 302692
- c.srai s1, 25
- c.srai a2, 22
- auipc s6, 150518
- sltu s5, zero, t3
- auipc s4, 305021
- la a7, data_page_18+1804 #start riscv_load_store_rand_instr_stream_19
- auipc t5, 923834
- sb a5, 923(a7)
- sub s2, a5, s9
- c.addi a1, 29
- c.addi a6, 3
- lhu zero, 1898(a7)
- c.addi a6, -17
- c.srai a2, 8
- c.lui s6, 20
- lb s10, -1465(a7)
- c.slli t6, 19
- c.addi a2, -32
- c.add a5, a4
- c.addi s4, 3
- lh s2, 148(a7)
- lh t3, -822(a7)
- lbu s2, -1217(a7)
- c.lui s5, 2
- lui t2, 892518
- c.slli a4, 9
- auipc a1, 207232
- auipc t6, 658989
- c.srai a1, 22
- c.slli a5, 6
- sb s6, 521(a7)
- lui s6, 521869
- addi s8, s0, 750
- c.xor a4, a2
- c.lui s2, 28
- c.li s9, 29
- lhu s11, -1254(a7)
- addi s7, t6, -401
- c.addi a3, -27
- lhu s4, 1194(a7)
- lui a4, 851415
- xori s5, a5, 402
- divu s5, t4, s10
- lbu gp, 554(a7) #end riscv_load_store_rand_instr_stream_19
- c.addi t3, 18
-2318: c.addi t6, -13
- c.srli s0, 24
- c.addi s6, -24
- nop
- c.addi s11, 22
-2323: c.lui a3, 23
- c.addi s6, 31
- c.addi gp, 18
- c.nop
- c.nop
- sub a5, tp, s10
- andi t1, tp, -888
- sra s11, s2, zero
- slt t4, s1, t3
- c.andi s1, 4
- bgeu tp, s9, 2338f
- c.addi s5, 3
- lui s3, 483302
- c.addi t1, 1
- lui a4, 228489
-2338: c.addi t5, 23
- sra s3, s2, a5
- c.addi s6, 25
- beq tp, tp, 2359f
- lui a2, 18784
- xor a4, t2, s2
- c.srai a3, 13
- c.addi s1, -20
- bne ra, a2, 2358f
- srli s10, tp, 17
- c.srli s0, 12
- c.or a0, a1
- lui t1, 794980
- auipc a4, 74620
- c.addi s3, -7
- xor s8, a6, s4
- lui zero, 311662
- lui gp, 572792
- auipc s11, 676611
- bge a6, t6, 2359f
-2358: c.addi s6, -4
-2359: c.addi s7, -27
- auipc s4, 375168
- c.slli s0, 19
- lui s6, 911841
- c.srli a2, 7
- sltu a0, s8, s5
- c.lui t3, 11
- lui s0, 229591
- c.slli s2, 25
- slli a4, t2, 12
- c.addi a5, -9
- c.addi s11, 27
- c.srli a2, 9
- c.addi t3, 28
- sll s0, s4, a0
- lui s8, 785631
- c.nop
- lui t5, 610661
- c.srli a0, 27
- c.addi t5, 17
- c.addi s1, 23
- lui t4, 968445
- c.srli a0, 25
- c.addi a4, -18
- lui t1, 651413
- lui s3, 445396
- c.addi s10, -25
- auipc s8, 910745
- slt a7, t5, t4
- c.addi t5, 24
- c.addi s6, -6
- c.addi a1, -31
- sra a2, a6, gp
- c.addi a3, 1
- c.add a5, a4
- c.srai a0, 19
- auipc s1, 201010
- auipc a1, 356128
- auipc zero, 1002468
- auipc t1, 976446
- c.addi s7, 22
- srli a2, t2, 1
- c.nop
- la a4, data_page_19+2828 #start riscv_load_store_rand_instr_stream_31
- slli a6, t2, 18
- lh gp, -206(a4)
- lb t6, 170(a4)
- c.srai a1, 4
- lb a6, 250(a4)
- c.srai a0, 4
- lhu s5, -1950(a4)
- auipc t1, 649263
- c.addi a6, -7
- sw sp, -380(a4)
- mul s10, a5, s9
- c.addi t5, -16
- c.srai a3, 7
- sh s7, 514(a4)
- lh a0, -1552(a4)
- c.slli s1, 12
- sb s9, 617(a4)
- c.slli s10, 18
- remu t1, s4, s4
- sb s3, -1198(a4)
- lhu s9, -290(a4)
- lbu s2, 595(a4)
- c.addi a3, 6
- c.addi a3, -30
- sub s2, a5, t2
- lw s6, 1128(a4)
- lhu a0, 1136(a4)
- lb s11, 781(a4)
- sb t1, 372(a4)
- lb s2, 1092(a4)
- sb tp, -1276(a4)
- remu a7, t6, sp
- lb s5, -135(a4)
- c.addi s6, 16
- c.slli a0, 15
- lb s3, -717(a4)
- lh a5, -1332(a4)
- lh gp, -252(a4)
- nop
- c.addi s3, -17
- sb tp, -510(a4)
- sb s6, -1901(a4)
- lbu s7, 1150(a4)
- lui s4, 175053
- slti zero, sp, 270
- lb s6, 286(a4)
- lb s2, 437(a4)
- lbu s3, -533(a4)
- sb t0, -1229(a4)
- c.or a0, a3
- lbu a1, 1013(a4)
- lbu s4, 5(a4) #end riscv_load_store_rand_instr_stream_31
- divu a3, s8, a5
- auipc a7, 313251
- c.addi s4, 27
- c.addi s4, 28
- c.srli a4, 31
- sltiu s10, s9, 483
- c.srli s0, 12
- c.srli a2, 29
- remu s3, sp, s2
- c.slli s6, 28
- c.addi t1, 11
- sltiu t4, s4, 264
- c.addi s9, -15
- srl t4, a5, s3
- lui s11, 515051
- lui s11, 179595
- c.srli a4, 8
- auipc a1, 820305
- c.addi s11, -16
- auipc gp, 362245
- c.slli a3, 28
- sra a2, gp, t4
- c.srai a2, 3
- c.addi t5, 19
- c.lui a6, 14
- c.addi s11, -8
- c.sub a3, a0
- c.lui a4, 13
- c.srli a5, 16
- c.slli s4, 20
- add a2, a4, t3
- auipc a0, 785446
- c.addi s9, -28
- c.addi a2, -26
- c.addi s11, 4
- c.andi a5, 5
- lui zero, 737329
- mul s11, a5, s4
- c.addi s9, 12
- slti gp, s9, -354
- c.slli gp, 12
- c.addi a7, 12
- c.slli a3, 28
- lui s10, 87200
- c.srai a5, 26
- c.slli a7, 27
- c.srli s0, 11
- lui a3, 749113
- c.addi t2, 28
- c.xor s1, s1
- c.addi s10, 3
- srai s2, a1, 3
- c.lui a5, 24
- c.srai a0, 27
- c.slli t6, 16
- c.nop
- bge a5, t5, 2475f
- auipc s10, 4157
- la a1, data_page_0+2419 #start riscv_load_store_rand_instr_stream_41
- sb a3, -186(a1)
- auipc a7, 968141
- sh t1, 433(a1)
- lbu a5, -461(a1)
- lbu s3, 1406(a1)
- srl a2, s11, t0
- c.srai a2, 2
- lbu a3, 959(a1)
- lb a7, 1102(a1)
- mul s0, t2, s10
- lb a7, -1627(a1)
- lb s7, -740(a1)
- ori a4, s9, 549
- sb t1, -388(a1)
- lb s10, -536(a1)
- lh t1, -1991(a1)
- lbu a4, -1318(a1)
- lb t5, -781(a1)
- sb a4, -1693(a1)
- ori zero, s4, 775
- lbu a3, 1648(a1)
- c.addi s11, 19
- lb a6, -1501(a1)
- lb t2, -1676(a1)
- c.slli t6, 11
- sb s3, 538(a1)
- auipc s9, 983074
- lbu s1, 1386(a1)
- sb t6, 1107(a1)
- c.srli a3, 9
- sb s8, -1666(a1)
- c.addi a4, -30
- lb a4, 1546(a1)
- mulhu s8, a3, s2
- sh t3, 1125(a1)
- lb t3, -1705(a1) #end riscv_load_store_rand_instr_stream_41
- c.addi s11, -16
- mulh a6, t2, s6
- c.addi t1, -19
- lui zero, 700553
- div a1, s7, t0
- c.addi s9, -26
- c.addi a0, 20
- c.srai a1, 22
- c.srli s0, 20
- c.addi gp, -31
- divu s4, s5, a4
- c.slli s6, 17
- c.addi a6, 9
- c.slli s9, 12
- lui t2, 902839
-2475: c.add a4, a5
- fence
- c.lui a6, 7
- c.nop
- c.addi s2, 24
- srl a6, s9, t4
- mulhu s9, s0, s2
- auipc t2, 785640
- srli t1, a7, 10
- slli a1, ra, 13
- lui a2, 492005
- c.addi t6, -16
- c.addi t1, 19
- c.addi s2, 2
- c.srai s1, 20
- c.addi t2, -25
- auipc a4, 323929
- lui t4, 864476
- auipc gp, 311801
- c.addi t4, 30
- srl a7, t3, tp
- c.srai a2, 2
- c.addi a2, 16
- sub s10, s3, gp
- lui t6, 91381
- c.srli a4, 7
- c.slli t1, 30
- c.addi t2, -20
- or gp, s6, a2
- c.addi s10, -32
- c.addi s6, 1
- bgeu t3, t1, 2516f
- c.addi a5, 21
- lui a6, 539752
- c.srai s1, 29
- auipc a5, 258905
- lui a1, 856988
- mulh a7, a7, s8
- c.addi a7, -28
- c.lui s7, 14
- la s0, data_page_8+2125 #start riscv_load_store_rand_instr_stream_2
- lw a6, 1515(s0)
- lb t4, 1130(s0)
- srli a6, s2, 19
- sb a0, -1356(s0)
- c.sub a0, s0
- lhu t1, -1093(s0)
- sb t4, 164(s0)
- rem s4, t5, t5
- lb a3, -1726(s0)
- lbu s1, -1338(s0)
- add s7, a3, t3
- c.addi t3, -1
- auipc s11, 144141
- lb a2, 1006(s0)
- c.srli a0, 20
- auipc gp, 162967
- c.lui a6, 21
- auipc a4, 888620
- lb t6, 260(s0)
- sb s4, -740(s0)
- lb a1, 1146(s0)
- sb ra, -448(s0)
- lui a0, 111746
- lbu a1, 141(s0)
- auipc s10, 873882
- sltu a1, s5, tp
- sw s6, -473(s0)
- lhu t6, 1719(s0)
- lbu t1, 1607(s0)
- lui t2, 939958
- lb gp, -1147(s0)
- c.srli a2, 22
- lb s8, -1186(s0)
- lb s3, -1570(s0)
- lbu s2, 30(s0) #end riscv_load_store_rand_instr_stream_2
- c.slli s3, 29
-2516: c.addi s2, -20
- andi s4, s5, -666
- c.addi s1, 16
- c.xor a4, a5
- c.addi t1, 21
- c.lui t2, 1
- srli s10, a4, 27
- c.slli t5, 29
- c.or a4, a2
- c.lui s7, 14
- c.lui a3, 2
- c.slli t4, 3
- auipc t3, 45033
- c.addi a4, 27
- c.slli s11, 31
- lui s11, 666960
- c.lui a1, 22
- c.srai s1, 26
- c.addi a4, 5
- c.lui a6, 14
- c.addi a7, 12
- c.srai s0, 4
- auipc a3, 588044
- c.srai a0, 16
- or s0, t3, zero
- c.srli a0, 6
- c.addi s2, -29
- c.addi a5, -18
- auipc a6, 694129
- c.addi s2, -21
- c.lui t4, 30
- c.lui s10, 17
- c.bnez a5, 2552f
- c.addi s0, -20
- c.addi t4, 21
- fence.i
-2552: c.slli a2, 15
- blt s9, zero, 2569f
- c.addi s11, 24
- c.xor s1, s0
- c.lui s4, 8
- slli t4, s11, 15
- sll s7, s0, s5
- auipc a0, 841525
- c.addi t3, -17
- c.sub a2, s1
- andi s9, t1, 860
- auipc s6, 664865
- lui t3, 549283
- c.lui t3, 11
- c.addi s2, -10
- addi a7, a5, 337
- srl s1, t1, t0
-2569: c.addi s4, -10
- c.srai a5, 24
- sub s6, zero, s9
- auipc s9, 460186
- beq s10, a2, 2588f
- lui a7, 457644
- bge t1, t6, 2576f
-2576: lui s8, 85532
- c.slli a3, 30
- c.or a4, a4
- auipc s6, 11396
- c.xor a4, a0
- addi s0, s11, 404
- bltu a3, s7, 2588f
- c.lui t3, 7
- c.lui t1, 19
- c.addi s11, -13
- sub a2, ra, t6
- c.addi s7, -20
-2588: lui t3, 433658
- c.srai a4, 18
- nop
- andi zero, a0, -698
- lui s11, 491966
- auipc s2, 222743
- c.addi s4, -24
- sll t1, ra, t6
- auipc a3, 888777
- c.addi t3, 6
- slt s3, s1, s0
- lui a2, 649583
- bge t5, tp, 2608f
- auipc t1, 1047723
- sll t5, s0, s8
- c.addi s10, -27
- andi gp, a0, -1023
- fence
- fence
- c.addi s0, -13
-2608: auipc t2, 90273
- auipc t1, 623272
- mul a1, a0, s5
- c.srli a0, 2
- c.addi s6, 9
- srl s8, s10, a0
- c.addi s2, 16
- lui a5, 155746
- c.addi s7, 26
- c.slli s0, 10
- c.addi a7, 25
- c.slli t2, 15
- auipc s8, 274680
- c.addi a7, 8
- c.addi s6, -32
- and s1, s9, s4
- c.addi a3, -30
- c.add a5, a5
- beq s11, t2, 2644f
- c.lui a6, 3
- add t6, t1, t3
- c.srli a3, 2
- blt s11, ra, 2650f
- c.slli t2, 25
- addi a3, t6, -539
- div s4, a1, a3
- c.srai a0, 20
- c.addi a2, -8
- c.nop
- c.nop
- c.srli s1, 5
- c.addi s4, 8
- la s3, data_page_15+1831 #start riscv_load_store_rand_instr_stream_38
- c.lui s2, 28
- c.addi t6, 17
- c.slli s7, 28
- lh zero, 1681(s3)
- sh sp, 1667(s3)
- sb tp, -1457(s3)
- fence.i
- lhu s9, -289(s3)
- lb a1, 1728(s3)
- auipc a6, 41648
- srai t6, s0, 28
- c.srai a4, 29
- lui s4, 23064
- lbu a3, 1140(s3)
- sb s1, -107(s3)
- auipc s11, 805943
- c.andi a0, 17
- sb s7, 1279(s3)
- div s8, s8, t6
- c.lui a0, 16
- c.slli t1, 22
- fence.i
- lh t4, -1283(s3)
- sb t1, -503(s3)
- lhu a6, -417(s3)
- c.srai a4, 8
- lbu t5, 194(s3)
- c.add a2, a3
- lhu t4, -1295(s3)
- sb a5, 685(s3)
- c.addi t5, 14
- c.addi a4, 29
- sh ra, -209(s3)
- c.addi t4, 27
- sh s4, -1809(s3)
- xori s9, s11, -100
- c.add a1, s1
- c.srai a4, 10
- nop
- auipc t4, 315074
- lb s11, -1300(s3)
- lui t1, 285538
- sb s11, -1062(s3)
- xor t6, t2, s2
- sb s2, 1626(s3)
- c.li a4, -26
- c.xor a5, a5
- sw t6, 2009(s3)
- lbu t5, 1812(s3)
- c.addi s2, -16
- lh s2, 551(s3)
- sb a7, -1165(s3)
- c.addi s1, -6
- lhu a1, 1771(s3)
- sh t4, -727(s3) #end riscv_load_store_rand_instr_stream_38
- la s10, data_page_7+1936 #start riscv_load_store_rand_instr_stream_50
- c.addi s6, 20
- lbu s0, -319(s10)
- lb t6, 1624(s10)
- lhu a7, -1042(s10)
- lb s0, -1589(s10)
- c.addi s3, 15
- lb a1, 1836(s10)
- c.lui t2, 24
- c.addi a1, 4
- lb t3, 1205(s10)
- c.srli a3, 20
- sb t1, 879(s10)
- sra t6, s5, a1
- auipc a5, 853821
- auipc a3, 176264
- lui t4, 926852
- lb s6, 1347(s10)
- lb a2, 1065(s10)
- sb gp, -685(s10)
- c.xor s1, a1
- lbu s7, -557(s10)
- lb s5, -1215(s10)
- c.addi t1, -19
- lbu t3, 969(s10)
- lbu s8, 1140(s10)
- sb a4, -569(s10)
- lui a7, 132380
- lb s5, -240(s10)
- lui s0, 213497
- auipc a4, 209883
- lhu t6, 686(s10)
- sb s3, -1009(s10)
- c.slli t4, 30
- lbu s9, 987(s10)
- c.mv s6, a5
- sb s3, 585(s10)
- lbu t3, 633(s10) #end riscv_load_store_rand_instr_stream_50
- c.slli t3, 2
- c.addi s0, -5
- auipc a0, 634640
- lui s7, 731993
-2644: c.addi a3, -7
- c.addi t5, -11
- c.srai a4, 19
- c.srai a2, 5
- lui s3, 52963
- c.add a0, a2
-2650: lui s1, 388621
- c.addi a5, 31
- xor a6, s1, tp
- sll s1, zero, t6
- c.addi a6, 29
- xori s1, tp, 403
- c.addi a7, -15
- andi s0, a0, -1010
- la s2, data_page_14+2190 #start riscv_load_store_rand_instr_stream_61
- c.slli t1, 8
- c.lui s1, 22
- slt t6, t1, s2
- lb s8, 233(s2)
- c.xor a2, s0
- lb a7, 1813(s2)
- auipc a7, 555858
- lb s6, 1001(s2)
- c.addi s8, 22
- sb a4, -255(s2)
- lbu zero, 389(s2)
- sb s6, 1257(s2)
- sh t0, -1898(s2)
- auipc s7, 467484
- lbu s11, -753(s2)
- lh a1, 1280(s2)
- sh ra, -536(s2)
- andi gp, s9, 629
- auipc s9, 579468
- c.lui s0, 6
- sb sp, 259(s2)
- c.slli t6, 25
- sb s0, -685(s2)
- c.srai a2, 29
- sb a0, -1021(s2)
- and a3, a5, t1
- c.addi s6, 9
- sb s10, -597(s2)
- c.srli a2, 15
- nop
- auipc a0, 161872
- sub t3, t1, ra
- c.addi s7, -9
- auipc a4, 794185
- lbu s1, 1206(s2)
- c.srai a1, 11
- lb t3, -1893(s2)
- lb s6, 356(s2)
- c.addi a4, 22
- andi a0, a3, 907
- lbu s10, -2046(s2)
- lbu a6, -650(s2)
- lbu t3, -1600(s2)
- lb t4, 803(s2)
- auipc t2, 229542
- c.nop
- lh t2, 0(s2)
- xori s5, t1, -145
- lui a7, 6301
- c.srai a3, 2
- c.srli a1, 10
- sb s1, 869(s2)
- sb t1, 918(s2)
- lui s6, 189018
- lhu t4, 1816(s2)
- lb gp, 353(s2) #end riscv_load_store_rand_instr_stream_61
- c.slli s5, 26
- auipc s2, 551348
- andi t3, t5, -408
- auipc zero, 706677
- c.addi s5, 2
- auipc s1, 297993
- fence
- bge t2, s7, 2682f
- lui s9, 1028582
- and s7, a4, a2
- c.addi a4, 8
- c.srai a1, 7
- c.addi a5, 8
- c.or a5, a1
- c.addi a4, -16
- auipc t5, 322131
- beq t6, t5, 2694f
- c.addi t6, 13
- fence.i
- c.addi s11, -9
- c.addi a2, -4
- auipc s3, 738218
- auipc s6, 506319
- c.addi a1, -23
-2682: srli gp, s6, 14
- lui s10, 170574
- c.addi a4, -26
- c.srai a0, 13
- c.srai s0, 10
- c.srli a3, 7
- slli a2, a7, 4
- lui s9, 491907
- lui t3, 862907
- lui s7, 297531
- andi s10, a6, 781
- lui t3, 1041433
-2694: c.addi a3, 26
- c.srai s1, 13
- c.addi s11, 14
- lui t6, 909931
- auipc s9, 200616
- c.sub a1, a1
- c.lui a6, 17
- auipc a2, 162863
- lui s6, 641093
- auipc s0, 213529
- c.addi s1, 30
- c.addi s10, 27
- xor s4, a7, a5
- auipc t1, 163842
- c.andi a3, 26
- lui s9, 1008752
- c.addi t3, -18
- mulh s11, t3, a0
- c.addi s6, -4
- c.slli s5, 5
- c.lui t4, 5
- c.slli t3, 26
- div s2, a6, s8
- auipc t3, 211174
- c.addi t3, 28
- lui a7, 673468
- c.srai a2, 8
- lui a2, 589829
- lui s3, 988449
- lui s3, 135151
- sll s9, t6, a4
- lui t4, 575899
- c.srli a4, 11
- c.addi s7, -16
- c.addi a4, -20
- c.slli s9, 26
- c.addi t1, -5
- auipc t6, 549703
- c.addi s1, 11
- c.addi t5, 10
- lui a2, 655698
- nop
- auipc s10, 565116
- c.addi a1, 9
- c.lui s10, 8
- lui s8, 501949
- xori s8, a0, -705
- mul a4, a2, sp
- lui s2, 871933
- c.add a4, a4
- auipc s8, 63719
- c.addi s9, 19
- auipc s7, 812065
- auipc s7, 361570
- c.srli a0, 5
- c.srai a5, 21
- lui t6, 22804
- c.slli a2, 29
- c.addi a6, 3
- c.addi t4, -13
- beq tp, s4, 2772f
- c.srai a1, 14
- auipc s9, 112328
- c.xor a0, a1
- c.addi a1, 13
- c.addi a2, 15
- c.srai a4, 16
- c.addi t6, 27
- c.mv t4, t3
- lui s9, 843665
- c.mv a2, s8
- beq a2, s0, 2784f
- c.srai s1, 4
- c.srli s0, 18
- c.srli a4, 12
- c.and a1, a1
- bltu t3, a1, 2780f
- c.nop
-2772: c.srai a5, 22
- lui s3, 192841
- lui s4, 982267
- c.addi s4, 13
- c.li s4, -12
- bge t5, t2, 2791f
- c.addi s0, -12
- remu s1, s1, ra
-2780: c.addi a1, 23
- c.slli s10, 27
- lui s4, 793059
- lui s1, 856929
-2784: c.srli a0, 31
- c.slli s11, 31
- c.slli s5, 2
- c.slli a2, 22
- slti a4, t2, -595
- c.addi s2, 18
- c.andi a1, -7
-2791: c.srli s0, 10
- auipc t4, 579795
- mulh a0, t0, s5
- c.addi s11, 30
- c.add a1, s1
- c.addi s10, -4
- lui s2, 456639
- la gp, data_page_1+1826 #start riscv_load_store_rand_instr_stream_55
- lbu a5, 1910(gp)
- lbu t6, -1653(gp)
- c.xor a0, a2
- lui s9, 644750
- lbu a6, 299(gp)
- lbu s10, 968(gp)
- c.slli s7, 27
- sb s7, -515(gp)
- sb a1, 1045(gp)
- auipc t4, 636552
- sb sp, -981(gp)
- c.slli s10, 23
- lb s9, -1729(gp)
- lhu s2, 314(gp)
- fence
- lhu a2, 1252(gp)
- c.addi t1, -16
- c.lui s1, 15
- c.srli s0, 25
- c.srli a2, 16
- lb a0, -1273(gp)
- c.addi a1, 17
- srli s5, zero, 2
- sb zero, -1647(gp)
- c.srai a4, 10
- lbu t3, 1367(gp)
- sll t2, a1, s0
- c.addi a4, 15
- c.addi t5, -9
- auipc a5, 144588
- c.addi a5, 15
- sb s8, 772(gp)
- c.addi a2, -25
- lbu t1, -1802(gp)
- lbu s5, -73(gp)
- divu s7, s7, s9
- sb s2, 967(gp)
- sh t5, 146(gp)
- c.slli s3, 23
- lh s9, -40(gp) #end riscv_load_store_rand_instr_stream_55
- c.addi a3, -9
- remu s7, t2, s2
- c.addi a3, -25
- lui s11, 78300
- c.addi s9, 28
- c.srai s0, 9
- c.addi s11, 18
- lui t5, 1013736
- c.mv t3, ra
- lui a3, 346460
- c.srai s0, 10
- c.addi a7, 24
- c.slli t6, 18
- c.addi s4, 6
- auipc s6, 553960
- c.addi s5, 7
- c.srli a2, 19
- auipc t2, 466109
- c.or a0, a3
- c.srli s0, 7
- c.addi s8, -1
- lui t6, 200609
- slti s4, s11, -683
- c.lui s7, 8
- lui s2, 209606
- lui s3, 998287
- auipc a1, 217922
- c.slli t6, 18
- c.li gp, -16
- c.add a3, a4
- la s2, data_page_10+2220 #start riscv_load_store_rand_instr_stream_37
- add a1, t4, tp
- c.srli a4, 13
- ori t6, t2, -623
- lbu s8, -1789(s2)
- c.srli a2, 30
- auipc a6, 504941
- c.addi t1, -23
- lb t6, -551(s2)
- lb a0, 1172(s2)
- lui t1, 53052
- c.addi a7, -17
- sb t4, -1135(s2)
- lh s7, 1268(s2)
- sb sp, 547(s2)
- auipc a4, 501497
- c.srli a1, 23
- lbu t2, 1365(s2)
- srl gp, s8, s0
- c.slli t6, 27
- sb a5, -16(s2)
- sh t6, -1104(s2)
- lb t3, 1048(s2)
- lbu s1, -265(s2)
- fence
- c.addi t5, -23
- lb t1, -1214(s2)
- lbu a7, 959(s2)
- lhu gp, -608(s2)
- lbu a0, 1285(s2)
- lhu s8, 312(s2) #end riscv_load_store_rand_instr_stream_37
- divu s2, s8, tp
- mul s5, t4, s11
- c.addi s4, -5
- c.addi s11, -11
- auipc zero, 451361
- c.addi t3, 27
- c.addi a5, -20
- c.srai a0, 11
- auipc s5, 752879
- xor s4, s10, s5
- addi a5, sp, 518
- c.lui s0, 30
- lui s0, 579577
- srai s5, a0, 16
- c.addi s6, 20
- sub a4, t5, s8
- xor s4, t0, t5
- auipc t6, 758666
- auipc s5, 340144
- slli t3, a4, 11
- c.addi a4, -10
- lui a0, 706266
- lui t5, 212987
- c.srli a0, 25
- c.addi t1, 1
- auipc a7, 237374
- c.addi t1, -6
- c.addi t3, 12
- c.addi a6, -6
- c.addi s2, -20
- c.addi a7, 29
- c.srli a2, 10
- lui s6, 782631
- nop
- slt t2, a0, t1
- slti gp, s10, -655
- c.lui a3, 6
- c.addi a5, -10
- c.addi s4, -24
- c.lui t5, 17
- auipc gp, 258890
- c.add s1, a4
- auipc t1, 457915
- c.srai a1, 11
- c.srli a2, 20
- c.addi a0, 29
- xori a7, a5, 695
- rem a2, t2, s2
- c.add a0, a1
- c.srli a4, 31
- c.addi s1, -28
- auipc t6, 307432
- lui a2, 824088
- fence.i
- and s3, a5, a5
- c.addi s5, -8
- auipc s11, 88457
- c.srli a0, 28
- lui s11, 30545
- c.addi a0, 22
- auipc s4, 96594
- srl s2, tp, s9
- c.lui a5, 8
- c.lui a0, 15
- c.addi s4, 10
- c.srai a2, 25
- c.srli a0, 18
- c.addi s5, -22
- c.addi a7, 10
- lui s9, 5235
- lui t6, 700972
- c.li s6, 4
- c.mv gp, t4
- c.addi t6, 31
- c.srai a0, 23
- auipc s2, 488494
- c.addi a2, -6
- lui s5, 662233
- c.andi a4, 11
- lui a7, 248149
- c.srai a5, 28
- c.addi a7, 2
- srli a2, ra, 0
- c.sub a0, a0
- sltu t4, gp, t0
- c.srai a5, 1
- c.addi s7, 27
- lui s7, 653010
- bge s3, a4, 2920f
- c.addi s9, -18
- c.slli a1, 20
- c.srai a0, 15
-2920: c.xor s1, s1
- c.addi s11, -14
- divu s5, a2, s10
- lui t5, 385855
- lui s6, 572925
- c.slli s1, 11
- c.srai a1, 2
- c.addi s6, 22
- c.add a2, a1
- c.addi a7, 20
- c.lui a2, 10
- c.addi s8, -14
- c.addi a0, 24
- c.addi t6, -31
- c.lui t5, 6
- bge s7, t0, 2953f
- auipc t5, 310764
- c.addi s7, 14
- srli t2, s7, 31
- slt a7, t3, s8
- c.addi a0, 25
- c.addi s2, -24
- srli s2, t6, 10
- auipc s3, 1012994
- c.slli s2, 4
- c.srli a5, 14
- c.slli s2, 31
- lui t6, 179583
- c.addi a5, 19
- c.addi a1, -4
- c.addi s9, 29
- c.srai a1, 25
- c.addi t6, 20
-2953: c.addi s2, 5
- auipc a4, 925480
- c.srai a2, 15
- c.addi t5, -24
- auipc s10, 147051
- lui s1, 364357
- remu s7, s9, s0
- auipc s8, 657167
- lui a5, 804981
- c.lui s5, 28
- c.srli a3, 1
- c.srai s1, 25
- auipc a3, 467140
- c.or a4, a3
- c.addi a6, -7
- c.addi t4, -17
- c.addi s6, -4
- c.addi t5, -24
- c.lui s10, 20
- auipc t2, 399589
- auipc s11, 856240
- c.addi t6, 26
- c.addi s9, 29
- c.slli a5, 28
- c.addi s3, -24
- c.srli a4, 10
- c.or a2, s1
- c.li s11, -19
- c.addi s1, -16
- add s1, s3, s10
- c.srli a1, 21
- c.srai s1, 21
- auipc gp, 645966
- auipc s11, 533920
- c.addi gp, 3
- auipc t3, 965730
- lui t3, 205092
- c.nop
- c.srli a4, 26
- c.addi t3, -25
- c.addi s3, -20
- lui s11, 1024783
- c.srai a0, 11
- c.addi s4, -30
- nop
- c.srli a4, 10
- auipc t3, 655833
- auipc s3, 788937
- auipc t3, 632490
- c.xor a2, a5
- c.addi s7, -19
- c.srai a0, 24
- c.lui t6, 8
- c.slli a2, 17
- remu t3, t4, s11
- c.and a4, a0
- c.addi s0, 27
- c.srai a3, 27
- c.addi a6, -11
- auipc s10, 1018261
- c.addi a0, 29
- lui a4, 908091
- c.lui t5, 6
- auipc a2, 900968
- srai s1, s5, 25
- srl s10, zero, s9
- lui gp, 588766
- auipc a4, 793097
- c.addi s2, -11
- auipc a6, 674430
- xor zero, a3, s8
- c.srai a3, 9
- auipc a6, 493605
- c.srai a0, 3
- and s7, t5, s1
- c.addi s2, -29
- c.srai a5, 5
- c.nop
- c.addi a3, 23
- lui s6, 1033511
- c.li a0, 5
- add t2, s10, a2
- c.addi t4, -8
- c.lui s5, 8
- c.slli t5, 28
- c.or a2, s1
- c.addi s8, -23
- lui zero, 771279
- c.addi t5, -8
- c.addi s8, -26
- c.addi s6, -2
- c.addi gp, 12
- c.addi t4, 17
- c.addi gp, 12
- c.li t4, 11
- auipc a2, 553150
- c.addi a7, -18
- fence
- c.addi t6, 16
- c.addi s1, -11
- rem s3, s2, s0
- c.srai a2, 3
- lui s3, 391379
- c.add a5, s1
- addi a7, t2, -407
- c.slli s2, 10
- xori a1, t3, 227
- c.srli a1, 15
- c.addi gp, -7
- slti a7, zero, -593
- lui s2, 647404
- c.lui s10, 26
- c.li s0, 17
- auipc s10, 154735
- c.srai a3, 5
- c.srli a2, 18
- c.slli a5, 27
- auipc s7, 662206
- c.slli s5, 23
- blt t2, gp, 3079f
- c.addi s8, -11
- lui s10, 714651
- c.slli a5, 29
- c.srai a3, 7
- and s6, a2, gp
- c.addi a6, -25
-3079: c.srai a2, 29
- c.addi a3, 12
- c.srai a0, 22
- c.slli a2, 29
- c.addi s4, 16
- c.addi s9, 11
- c.addi t5, 30
- c.lui t3, 11
- c.lui t6, 5
- remu gp, a5, tp
- beq gp, s6, 3105f
- c.srai a4, 17
- c.slli a6, 6
- c.srai a4, 6
- c.addi s2, 20
- c.addi s7, -22
- bgeu s1, s9, 3099f
- c.lui s5, 12
- c.slli s1, 22
- and s3, a0, ra
-3099: auipc s10, 730837
- auipc t1, 443011
- mulhu t1, sp, zero
- c.addi s2, -3
- bltu t2, s3, 3116f
- auipc a2, 400899
-3105: auipc s6, 57656
- c.mv a1, s6
- c.nop
- auipc t5, 577912
- auipc s2, 874064
- divu s10, s11, t5
- c.andi a2, 12
- c.lui t4, 18
- c.addi a0, 11
- and s4, gp, t3
- c.slli a1, 24
-3116: c.addi t4, 2
- c.addi t4, 19
- c.srai a4, 10
- auipc gp, 675734
- div a2, s8, t6
- c.lui s1, 28
- c.addi s1, 9
- lui a7, 350061
- c.slli gp, 20
- lui s5, 581130
- auipc s2, 400731
- c.addi s9, 22
- auipc s11, 114308
- c.srli a4, 4
- c.srai a3, 27
- c.lui s0, 7
- srl s3, s0, s10
- xor t2, zero, t3
- c.lui t3, 4
- or gp, tp, s7
- c.nop
- c.addi s1, 31
- auipc zero, 244823
- fence.i
- auipc t5, 661491
- c.addi t1, -4
- c.addi s11, -9
- c.addi a7, -26
- lui s9, 552388
- c.lui t5, 26
- auipc t3, 472849
- lui a3, 668289
- c.sub a5, s1
- c.bnez a2, 3152f
- c.lui t3, 29
- nop
-3152: slt s9, s11, s0
- c.addi s9, 12
- c.xor a5, s0
- c.slli a2, 21
- c.srli a1, 9
- c.addi a1, -14
- c.addi t3, -5
- addi s4, a7, -896
- c.srli a2, 4
- c.addi s3, -18
- c.srli a3, 29
- c.srai a3, 3
- auipc a6, 827472
- c.srai a4, 24
- c.srai a2, 30
- c.srai a4, 3
- c.and a0, a0
- auipc s11, 922524
- c.and a4, s1
- bge sp, s9, 3176f
- div s2, a5, s2
- xori s3, t5, -609
- c.lui s7, 8
- c.slli t5, 14
-3176: bgeu s9, ra, 3177f
-3177: lui s0, 141203
- lui t1, 483318
- c.addi gp, 15
- c.srli a1, 21
- slli s4, a6, 13
- c.lui t6, 26
- fence.i
- auipc s9, 173359
- lui a5, 462664
- div a7, a5, s0
- auipc a4, 936864
- lui s5, 564169
- c.nop
- c.addi s6, -14
- auipc t2, 792707
- mulh a7, s5, s2
- c.addi a7, 1
- c.addi s10, 5
- beq t0, a5, 3200f
- c.addi s5, 23
- c.addi s2, -2
- c.srai a2, 7
- c.srai a5, 6
-3200: c.srli a5, 3
- c.lui s6, 25
- lui s0, 308669
- auipc s5, 710984
- c.addi t3, 23
- c.lui s9, 10
- lui t1, 814267
- lui s9, 628894
- auipc a7, 616342
- c.addi s6, -1
- c.addi s8, -3
- lui a4, 868650
- srai t3, a0, 18
- lui s0, 25645
- c.addi s5, 19
- c.addi a1, -19
- c.srli a4, 25
- c.srli a3, 24
- fence
- c.addi gp, 29
- c.srli s1, 16
- c.addi a3, -9
- auipc s11, 141877
- sltu a6, zero, a2
- c.srai s0, 15
- c.addi s5, 5
- c.addi s8, -5
- c.addi a5, 26
- auipc s0, 352431
- c.lui t1, 30
- c.lui a5, 15
- c.addi a7, 17
- sltu s9, zero, s4
- lui t1, 590252
- c.nop
- lui t3, 293502
- nop
- auipc s8, 23186
- auipc a3, 593943
- c.slli a1, 2
- c.addi s10, 29
- bne s7, gp, 3243f
- c.addi s8, -4
-3243: c.lui s11, 22
- lui s11, 321348
- auipc s7, 835611
- mulhsu s0, s6, s7
- slt t6, t1, t4
- lui s8, 368192
- c.addi t2, 7
- auipc t5, 293503
- c.lui s4, 16
- c.slli a7, 27
- c.addi t6, -28
- c.addi s10, 30
- auipc a6, 1013614
- auipc t2, 1030471
- c.slli s6, 16
- c.bnez a3, 3262f
- lui s9, 544288
- lui zero, 737895
- lui s8, 904557
-3262: c.addi a4, -6
- c.srli a3, 27
- c.srai s0, 15
- auipc s1, 434105
- c.srai a5, 3
- c.lui t5, 2
- bltu t5, a3, 3286f
- xor a6, t6, s6
- c.srai a5, 7
- c.add s0, a3
- lui t4, 451829
- c.lui t6, 16
- c.bnez a4, 3285f
- slti s6, zero, 751
- auipc a2, 173241
- c.slli s1, 8
- c.addi a6, 6
- c.addi a3, -24
- auipc a7, 902921
- c.srai s0, 13
- c.addi gp, -23
- c.slli a2, 14
- lui s6, 1004191
-3285: slli a3, s0, 27
-3286: auipc a7, 57439
- xori s9, s0, -941
- divu s2, a2, t0
- auipc a5, 439408
- auipc t4, 165754
- c.addi t2, -23
- bne s3, s2, 3304f
- lui a7, 944417
- c.addi a1, -29
- slt t6, s7, s8
- c.mv a1, a5
- c.lui a4, 31
- c.addi t2, -26
- auipc t3, 866865
- auipc t3, 432444
- c.li s9, -28
- auipc t5, 590473
- sltiu s7, a7, 689
-3304: slli a7, sp, 14
- mulh t2, s0, s11
- c.srai a1, 29
- c.addi a1, -31
- lui t1, 261295
- c.lui a0, 19
- blt s3, gp, 3324f
- mul s11, a7, t3
- auipc s9, 1018338
- c.srli a2, 24
- slt s6, sp, s4
- c.addi a0, -3
- srl s11, a0, a4
- srai s11, s3, 0
- auipc a3, 819524
- c.addi t5, -17
- c.lui a2, 19
- c.srai s0, 10
- c.addi t6, -14
- c.addi s1, 4
-3324: lui s11, 398898
- lui a6, 605900
- la a4, data_page_6+2291 #start riscv_load_store_rand_instr_stream_45
- lbu t4, -728(a4)
- lui t4, 320362
- auipc t1, 29453
- lhu t5, -1095(a4)
- lhu t5, -725(a4)
- c.addi s4, 1
- andi a0, a7, -778
- c.or s1, a0
- lui t3, 495236
- sltu t3, gp, a0
- sh a2, -923(a4)
- c.li t5, 21
- sh gp, -827(a4)
- c.addi t2, -3
- sh t2, -831(a4)
- c.addi s9, 14
- lui t6, 1022649
- lui a3, 670228
- sb ra, 890(a4)
- lui t3, 70039
- nop
- sb s3, 711(a4)
- sh s2, -517(a4)
- lui a6, 485885
- c.lui s4, 10
- lbu s8, 1574(a4)
- lbu gp, 325(a4)
- sb s3, -1790(a4)
- lb s1, 455(a4) #end riscv_load_store_rand_instr_stream_45
- c.addi s3, 29
- auipc s2, 367580
- c.addi t4, 8
- c.addi a2, -4
- lui t3, 208163
- c.addi a3, -29
- bge t1, t4, 3350f
- mul s8, s3, t0
- fence
- c.mv s5, s3
- bltu a5, a7, 3354f
- mulhsu t6, s11, t1
- lui t2, 281901
- slti a3, t5, 434
- auipc a6, 286446
- c.srai a2, 14
- c.or s1, a4
- auipc s0, 237954
- div s7, a0, a0
- c.addi a1, 24
- c.srai a0, 9
- c.addi a5, 6
- auipc a1, 744686
- c.addi s5, 24
-3350: auipc s7, 196293
- c.addi t3, -4
- fence.i
- lui s1, 611411
-3354: c.lui s1, 27
- sll a1, sp, t1
- c.lui s2, 1
- c.addi a5, -15
- c.addi a5, -22
- slti a2, s3, -310
- c.slli s8, 4
- c.srli a3, 12
- srai t2, s2, 18
- slli s9, a5, 24
- c.srli s0, 23
- c.lui s10, 19
- c.mv a3, s7
- c.srai s1, 27
- c.lui a4, 31
- lui s8, 207839
- c.addi s11, 2
- c.addi t1, -6
- c.addi t4, -32
- c.slli t6, 27
- la a7, data_page_19+2443 #start riscv_load_store_rand_instr_stream_56
- lbu a1, -1169(a7)
- lb a4, -868(a7)
- auipc a4, 642532
- lh t4, -1507(a7)
- c.addi s2, -8
- lb a5, 1245(a7)
- c.srli a1, 25
- c.addi s10, -5
- auipc s2, 572825
- lb a2, 137(a7)
- c.addi s9, -20
- c.srai a4, 27
- fence
- lui a2, 306910
- lbu s4, 226(a7)
- nop
- c.addi s11, -10
- sb t5, -1130(a7)
- lb a6, 252(a7)
- lb s4, -1014(a7)
- c.addi t3, -26
- div a4, a4, t5
- lb a0, 211(a7)
- or t1, t3, a5
- lb a1, -902(a7)
- sb a0, 239(a7)
- lbu s2, -204(a7)
- divu t4, a3, a0
- sh s10, -1589(a7)
- auipc s4, 862613
- lb a5, 872(a7)
- lb s1, 1400(a7)
- lbu t5, -2020(a7)
- c.lui t4, 23
- lui t2, 687709
- sh s6, -537(a7)
- lb a0, 1222(a7)
- sb s1, -646(a7)
- lhu a4, 395(a7)
- lbu s10, 464(a7)
- sb s2, -673(a7) #end riscv_load_store_rand_instr_stream_56
- lui s5, 67006
- auipc s0, 192366
- c.srli a3, 5
- bgeu t4, a2, 3396f
- c.lui s0, 19
- c.addi a6, 8
- c.nop
- c.nop
- c.slli s0, 10
- auipc s1, 613961
- c.srai a3, 16
- c.srai s1, 17
- c.li a0, 7
- c.add s1, a1
- bge a2, s0, 3395f
- c.bnez a2, 3397f
- auipc s2, 1040322
- c.slli a2, 10
- slti s11, s10, 352
- addi s0, a0, -17
- auipc s2, 278276
-3395: c.addi t1, 9
-3396: lui s10, 209127
-3397: c.addi a7, -22
- auipc t5, 829126
- c.lui t6, 25
- c.addi a5, -21
- c.addi t4, 25
- c.li a1, -15
- c.lui s4, 17
- c.addi t3, -1
- c.addi s8, -15
- c.addi s8, 16
- c.srai a2, 31
- auipc s3, 915780
- c.slli s7, 27
- auipc a4, 248796
- c.or a0, a0
- lui a5, 510120
- c.addi a1, -20
- c.addi s4, 29
- lui t1, 485799
- c.addi s3, 20
- c.slli s3, 16
- c.addi s11, 25
- auipc a6, 537207
- remu a7, t4, s10
- c.lui a1, 21
- lui a5, 406226
- auipc t6, 653086
- c.addi a1, 13
- c.srli a4, 5
- rem zero, s11, t5
- c.addi t4, -11
- c.lui a6, 6
- c.srai a2, 1
- srai a6, tp, 21
- fence
- c.slli t1, 6
- c.addi t4, 12
- c.addi a6, -9
- c.addi s11, -18
- sra s8, s9, s11
- c.srai a4, 27
- c.addi a4, 24
- c.li t2, -19
- mulh s4, a6, t3
- auipc gp, 494690
- c.addi a6, -12
- auipc a4, 443763
- blt a2, a3, 3456f
- sltiu a4, s8, -993
- srli t6, s7, 31
- c.lui a6, 16
- auipc a1, 474995
- c.srai a1, 26
- mulhu t4, t1, a4
- fence.i
- c.srai a0, 15
- c.addi t6, -30
- c.addi a0, -16
- c.addi s11, -30
-3456: c.addi a2, 23
- c.slli s3, 29
- remu s3, s3, a5
- auipc a3, 686741
- bltu t2, t1, 3471f
- c.addi a2, 5
- auipc t5, 901749
- mulh a5, s8, a0
- c.addi t4, -20
- auipc t1, 337420
- c.or a1, a3
- auipc s7, 223075
- sltiu a7, s0, -689
- auipc a7, 847757
- c.andi a2, -32
-3471: sra a1, t4, a7
- auipc s8, 774408
- c.bnez s0, 3491f
- fence
- c.lui s9, 24
- add s3, s2, t1
- auipc a3, 317995
- sltu a1, t1, s3
- c.slli a0, 11
- c.slli s4, 23
- c.lui s10, 5
- srai a5, s0, 4
- c.srai s1, 18
- srli s8, s3, 17
- c.addi s4, -18
- lui t5, 683201
- srl s4, s7, tp
- c.srli a5, 21
- c.addi s4, 6
- auipc a7, 163888
-3491: auipc s2, 297232
- c.addi s6, -28
- c.addi s0, -15
- c.addi a4, 18
- c.srli a1, 14
- c.addi s10, 5
- lui s5, 550125
- c.addi s2, -4
- bgeu ra, s2, 3517f
- c.srli a2, 6
- c.srli a0, 16
- la a1, data_page_3+2902 #start riscv_load_store_rand_instr_stream_3
- c.slli a3, 6
- c.lui s5, 18
- lui t6, 531252
- sb a4, 1007(a1)
- c.addi gp, -32
- rem t1, a2, a6
- lb t6, -1177(a1)
- andi s1, s7, -764
- lui s7, 823823
- lhu a4, -2048(a1)
- lui s8, 155598
- lh t2, -1714(a1)
- lui a4, 798761
- lb t6, -1645(a1)
- sh s6, -528(a1)
- c.lui s6, 14
- c.addi a2, -28
- c.lui a4, 11
- c.addi s4, 17
- lbu s6, -785(a1)
- lui s5, 529740
- sh t0, -40(a1)
- c.addi s1, 20
- fence
- c.lui s10, 3
- sb a5, 123(a1)
- lw a7, 1162(a1)
- and s5, s10, t0
- sb s2, -573(a1)
- lui a4, 945065
- c.sub a0, a1
- lbu s0, 815(a1)
- c.lui s4, 16
- sb sp, -182(a1)
- auipc a5, 29527
- sb s2, 561(a1)
- sb a6, 407(a1)
- c.addi s2, 15
- lui a7, 872619
- lw s6, -1878(a1)
- lw s5, -110(a1) #end riscv_load_store_rand_instr_stream_3
- c.srli s1, 5
- c.addi a3, 14
- c.addi a0, -27
- lui a0, 600950
- c.nop
- andi s5, s6, -627
- auipc a4, 719241
- lui s11, 103618
- sltu t5, a7, a4
- c.srai a0, 18
- lui a6, 796882
- c.addi s7, -30
- c.addi s11, -2
- lui a1, 216874
- c.lui s4, 2
-3517: auipc s6, 1019032
- c.lui a3, 29
- c.addi s4, -32
- lui a7, 128394
- c.slli s4, 28
- slli s7, t1, 23
- mulh s8, s8, s11
- c.lui s0, 25
- c.addi a0, -14
- c.addi a1, -24
- c.slli s7, 20
- bne s2, a3, 3538f
- srai a0, t0, 7
- auipc s10, 989126
- c.lui t5, 24
- c.and a5, s1
- c.addi s10, 24
- lui a3, 193139
- srl a4, t0, t0
- c.andi a2, -12
- la s0, data_page_3+1990 #start riscv_load_store_rand_instr_stream_1
- lbu t3, -281(s0)
- lui s10, 499132
- c.srai a2, 11
- lbu t1, -1731(s0)
- lui a2, 336553
- lbu gp, 43(s0)
- auipc a0, 642756
- c.add a0, a0
- sb a5, 1043(s0)
- c.srli a3, 26
- lbu a0, 1556(s0)
- lbu t1, -97(s0)
- auipc s2, 899751
- lui a5, 624357
- lb gp, -622(s0)
- c.srai a1, 25
- c.addi a5, -1
- lbu a5, -1437(s0)
- lui s11, 667604
- sb s3, 1295(s0)
- c.addi a0, 31
- c.addi s1, 13
- c.srai a2, 5
- lbu t5, 2007(s0)
- lbu t5, -437(s0)
- c.addi a2, -11
- lh s3, -644(s0)
- sb a1, 58(s0)
- c.lui s1, 9
- sh a0, 1164(s0)
- lbu s3, 1735(s0)
- c.srli s1, 4
- sb s8, 1933(s0)
- lb a5, -1367(s0)
- lbu s4, 425(s0)
- lbu zero, -53(s0)
- c.addi a0, -4
- lbu s10, 191(s0)
- c.srai a3, 6
- c.srai a0, 20
- c.lui a3, 26
- c.add a3, s0
- mul s3, a5, a7
- lbu t5, -273(s0)
- c.addi s10, 5
- nop
- c.slli a0, 17
- auipc gp, 476391
- sll t3, s1, s5
- c.addi s5, -22
- sh t0, -1970(s0)
- lbu a4, -564(s0)
- sh a4, 46(s0)
- sb a1, -1168(s0) #end riscv_load_store_rand_instr_stream_1
- c.srai s1, 15
-3538: c.addi t4, -9
- c.slli s1, 17
- c.addi s5, 25
- c.addi s8, -16
- fence.i
- lui s2, 80746
- srai s3, t1, 0
- c.slli s2, 15
- c.addi t5, 31
- la s3, data_page_4+1876 #start riscv_load_store_rand_instr_stream_25
- c.slli a5, 8
- sra s4, a0, gp
- lh a1, 868(s3)
- mul a1, t2, s5
- lui a5, 247481
- sh tp, 1590(s3)
- sra a0, t0, t6
- c.addi t4, 8
- lhu t2, 1918(s3)
- c.srai a5, 9
- c.srai a5, 18
- slti a1, t1, -196
- c.addi s5, -4
- sb a0, 1973(s3)
- lui t1, 876092
- nop
- lui s10, 145238
- c.srli a1, 18
- or s9, s6, t2
- lb a1, -597(s3)
- auipc a5, 309178
- lbu t5, 649(s3)
- sub a4, s8, gp
- c.lui t4, 16
- lui s10, 897986
- c.slli s10, 16
- lui s7, 937843
- lbu t2, -1576(s3)
- c.slli a7, 26
- c.slli a5, 28
- c.and s1, a1
- sb s3, -1085(s3)
- c.srli a5, 1
- lbu a2, -487(s3)
- c.addi a1, 23
- lb s10, -1234(s3) #end riscv_load_store_rand_instr_stream_25
- auipc a0, 951703
- bne s11, t5, 3556f
- c.lui a7, 25
- lui a5, 1003822
- andi zero, a0, 924
- c.slli a3, 16
- lui gp, 847564
- c.sub s1, a2
- auipc t3, 1003090
-3556: c.addi t6, 3
- bne s6, s8, 3559f
- c.addi a1, 25
-3559: c.addi s0, -11
- c.addi s4, 20
- c.srai s0, 26
- auipc a4, 685925
- c.addi s4, -20
- c.addi s6, 6
- lui a7, 53506
- c.srai a0, 18
- c.srai a2, 12
- c.addi s4, -2
- c.addi t4, 24
- bne a1, s11, 3589f
- c.addi a5, -20
- auipc a3, 537891
- c.addi s8, 1
- c.addi a4, -4
- c.andi a2, 1
- c.addi a2, 19
- lui t3, 370318
- bgeu a4, a0, 3591f
- c.addi t4, 22
- c.addi s11, -8
- lui s1, 796015
- beq a6, s4, 3587f
- auipc a2, 68349
- xori t6, t6, 881
- c.addi gp, 30
- c.addi a4, 30
-3587: auipc t1, 597889
- c.addi t2, 23
-3589: c.xor a0, a3
- lui a0, 615082
-3591: c.srai a2, 9
- add s3, a6, s7
- c.srai a2, 2
- c.lui gp, 2
- c.lui s3, 2
- c.nop
- auipc s1, 551305
- c.addi a6, -15
- lui s1, 336881
- c.slli gp, 22
- lui s3, 396344
- div s0, a2, a2
- c.addi s6, 11
- lui t4, 662972
- c.slli t2, 6
- c.addi s7, -25
- auipc t4, 1007889
- addi s9, s8, 394
- lui t5, 696636
- lui s5, 554878
- c.addi a3, 21
- c.addi s1, -2
- bne t2, a7, 3614f
-3614: sll a2, a3, t2
- c.srai a1, 6
- c.addi a5, -17
- auipc t2, 979639
- c.addi t5, -31
- andi t3, tp, -986
- bltu t5, s0, 3625f
- lui gp, 504220
- c.srli a4, 10
- auipc s8, 722919
- c.addi s3, 5
-3625: c.lui s2, 13
- c.lui s8, 17
- c.lui s9, 19
- c.addi a1, -21
- lui a5, 358571
- c.lui s6, 28
- lui t1, 994817
- c.addi s9, 22
- c.andi s1, -16
- c.slli a0, 14
- c.slli a0, 26
- c.srli a2, 16
- bltu s7, tp, 3641f
- c.andi a5, -12
- c.slli s9, 26
- c.addi a3, 26
-3641: c.slli s6, 16
- c.srai a0, 10
- auipc t4, 182205
- auipc t6, 358395
- auipc a7, 471618
- c.lui a7, 28
- xori s8, s5, -850
- c.srai s1, 11
- c.lui t3, 31
- c.slli s1, 4
- c.sub a1, a4
- c.addi s2, 5
- bne s3, s8, 3665f
- and t3, s10, t5
- auipc t3, 228872
- c.andi a2, -1
- c.srli a2, 24
- auipc t5, 233042
- lui s2, 972319
- c.addi s11, 8
- c.addi s0, 17
- lui s5, 688710
- c.addi s6, -15
- c.srai a5, 5
-3665: slli a5, s11, 24
- auipc s11, 827994
- c.addi s10, 24
- c.addi s7, -29
- c.srai s0, 4
- c.addi t1, 27
- c.srli s0, 6
- c.addi gp, 20
- sll a0, tp, a5
- auipc s10, 300657
- lui a5, 687268
- c.addi t2, -14
- c.li t5, 20
- c.srai a1, 5
- c.addi gp, 24
- lui t4, 5106
- c.addi a6, -5
- c.andi a4, -17
- fence
- c.addi s0, 18
- c.addi a3, 1
- c.addi s1, 3
- c.addi s5, 31
- c.addi s2, -19
- c.addi a3, 18
- c.bnez a0, 3696f
- c.lui t2, 23
- c.addi t5, 8
- rem s8, a5, t5
- c.slli s1, 12
- c.addi s11, 23
-3696: c.addi s10, 10
- c.srai s0, 31
- auipc s5, 369716
- auipc s3, 816149
- c.slli a4, 31
- c.addi a7, -29
- or s6, s9, a4
- c.srai s0, 7
- lui a1, 79702
- slti t1, a7, -836
- c.srai a1, 15
- c.lui a2, 5
- c.addi s1, 22
- auipc s8, 945048
- lui t5, 440604
- c.slli s3, 30
- lui t2, 821838
- c.addi s6, 6
- c.addi a1, -5
- c.srli a2, 7
- lui zero, 741382
- c.addi s7, 7
- c.addi t1, -23
- blt s5, gp, 3735f
- lui a2, 497623
- remu t2, t1, s1
- srl t6, gp, s8
- c.lui a3, 29
- c.srli a1, 9
- andi zero, a3, 988
- c.srli a4, 14
- c.srli a3, 22
- c.addi s1, -1
- ori t2, t3, -827
- and s4, s5, a4
- c.addi s11, -15
- xori s8, a6, 375
- sltiu a6, t5, 705
- c.addi t4, -10
-3735: andi s5, sp, 408
- auipc a6, 146421
- c.lui s10, 30
- c.slli a6, 31
- c.srli a1, 14
- c.addi a5, -4
- div a4, s10, a4
- c.addi t3, -31
- c.srli a2, 28
- ori a6, t4, -839
- lui a1, 935323
- c.addi s11, -31
- c.srai s1, 3
- c.addi s11, 24
- auipc t5, 277513
- c.slli t2, 30
- c.addi a2, 6
- c.srai a2, 24
- auipc gp, 1040024
- c.srli s1, 23
- c.xor a5, a0
- rem a4, s3, s4
- c.addi t1, 26
- c.addi s5, 23
- slli t3, s6, 20
- lui s10, 676902
- auipc a7, 876556
- auipc a1, 185585
- slli s10, s0, 30
- c.lui s7, 16
- lui a7, 900376
- c.srai a0, 3
- lui a6, 118797
- auipc a1, 130563
- c.slli s3, 15
- blt s7, tp, 3788f
- auipc s4, 159145
- auipc s5, 758862
- c.srli a0, 28
- lui s5, 208991
- auipc t4, 392977
- c.slli gp, 22
- c.addi s2, -16
- c.addi s9, 13
- add t1, s0, a0
- auipc a4, 169695
- c.addi s9, 9
- c.addi a7, 11
- auipc a3, 279196
- c.lui s8, 3
- c.lui t4, 26
- lui s4, 732573
- sll s3, a6, t3
-3788: c.slli a4, 4
- c.srai a5, 8
- c.addi s1, -5
- c.bnez a3, 3807f
- c.addi s3, -17
- c.sub a0, s0
- c.slli a2, 7
- addi a2, a1, -522
- c.addi s4, -17
- c.lui a3, 4
- c.srli s0, 29
- c.addi a1, -5
- c.addi s9, 26
- c.slli t4, 17
- and a2, t6, s11
- c.addi s1, 16
- c.slli t1, 18
- lui a5, 448054
- c.sub s0, a2
-3807: lui s3, 999302
- c.slli t4, 10
- c.li a7, -30
- lui s2, 331869
- c.addi s11, -15
- c.addi s6, -2
- la a7, data_page_13+2783 #start riscv_load_store_rand_instr_stream_13
- sb t4, -1058(a7)
- sb s8, -1569(a7)
- sb a2, -1853(a7)
- lbu a2, -1426(a7)
- sb s7, 363(a7)
- lui s9, 402083
- sh a4, 1269(a7)
- lb s3, 44(a7)
- lbu gp, -1082(a7)
- auipc t2, 845972
- c.addi a6, -13
- sb t1, -1274(a7)
- sub t3, a3, s10
- lbu s5, 943(a7)
- sb t0, -52(a7)
- c.addi a4, 17
- lb s10, 550(a7)
- mulhsu t2, s10, s11
- c.addi s6, -1
- lb s9, 187(a7)
- lb s9, 810(a7)
- sh t4, 1011(a7)
- sw sp, 361(a7)
- lui s8, 327374
- lh a6, -1403(a7)
- lhu a1, 991(a7)
- and s3, a6, s8
- sb t0, -59(a7)
- c.lui s8, 27
- sh a5, 915(a7)
- lb s7, -1809(a7)
- lui a3, 1036710
- c.sub a4, a1
- lw a4, -1767(a7)
- mulhsu a0, ra, t2
- c.addi a4, 22
- lh t6, -841(a7) #end riscv_load_store_rand_instr_stream_13
- c.mv s3, gp
- c.srai s1, 25
- auipc s10, 992949
- lui t5, 667471
- remu gp, a0, a6
- c.addi t1, 14
- auipc s6, 1009036
- c.addi a5, 31
- fence
- slti t2, t1, 426
- c.slli a4, 17
- c.lui a3, 19
- c.slli s9, 13
- lui s5, 482503
- auipc s1, 634132
- c.nop
- auipc t2, 150059
- remu gp, s1, zero
- fence.i
- c.and a5, a2
- c.xor a5, a0
- c.slli t2, 17
- c.addi s2, 13
- auipc a3, 155700
- c.addi s10, -31
- bltu s3, a0, 3854f
- bne s8, s11, 3854f
- c.lui a5, 6
- c.addi t4, 23
- lui t2, 70018
- auipc t6, 597844
- c.srai s0, 28
- c.srli a1, 29
- c.addi s9, -29
- c.lui s2, 2
- c.sub s1, a5
- sll s5, s2, s1
- c.lui s9, 26
- c.lui t5, 12
- c.lui t2, 1
- c.addi s3, 4
-3854: c.srli a4, 1
- bne a5, a3, 3872f
- c.addi s0, 23
- bge a0, t1, 3858f
-3858: c.srli a3, 9
- addi s7, t0, -924
- c.lui a3, 2
- slti zero, a1, 633
- lui s9, 1045847
- la a3, data_page_7+2048 #start riscv_load_store_rand_instr_stream_12
- add t5, a3, a1
- lbu t1, -229(a3)
- c.srli a4, 20
- slt a0, s7, t2
- lb a5, 889(a3)
- c.add s1, s0
- c.srli a5, 20
- c.andi a5, -32
- lui a2, 915920
- lh t6, 798(a3)
- c.srai a0, 1
- or s0, a0, t5
- lbu a4, 937(a3)
- lui s6, 652475
- xor t5, s7, t3
- c.xor a0, a1
- add t6, s10, a5
- c.addi s1, -28
- sb s2, -512(a3)
- lhu a1, -1474(a3)
- auipc s3, 136561
- lbu a4, 1786(a3)
- sb s11, 1751(a3)
- lh zero, 160(a3)
- lui s2, 712232
- lhu t4, 1564(a3)
- c.lui s3, 31
- sw a7, 1192(a3)
- lb gp, -1313(a3)
- c.addi s3, 27
- lb s6, -1911(a3)
- c.srli a0, 20
- auipc s3, 235304
- c.srai a1, 12
- lui zero, 1008468
- c.srai a5, 13
- sb t5, 507(a3)
- c.addi s0, -2
- lb a7, -345(a3)
- lb s6, 770(a3)
- c.srai a5, 10
- lb s3, -1438(a3)
- lbu s2, 1301(a3)
- sb a2, 189(a3) #end riscv_load_store_rand_instr_stream_12
- c.addi a4, -13
- c.addi a2, 20
- c.addi s1, 20
- c.srli s1, 26
- lui s9, 152670
- c.addi s5, -16
- c.addi s3, -24
- c.addi t1, -30
- c.addi t1, 9
-3872: c.lui t3, 6
- lui a0, 116938
- c.lui t6, 18
- lui s11, 413009
- beq t2, s3, 3883f
- lui a3, 698169
- c.addi a5, 20
- sra s9, a6, a3
- c.lui s6, 22
- auipc a7, 670722
- add s1, ra, gp
-3883: lui s2, 204354
- c.addi a0, -7
- auipc a2, 669010
- c.slli t2, 1
- add t5, a7, s6
- auipc a2, 2393
- c.lui a4, 18
- auipc s8, 691507
- auipc a2, 793358
- la s5, data_page_19+2322 #start riscv_load_store_rand_instr_stream_47
- lbu s9, 1477(s5)
- lbu s4, -1725(s5)
- c.addi a3, 6
- c.srli a3, 11
- add zero, gp, a1
- lw s4, 162(s5)
- lb t4, -765(s5)
- divu s3, s3, s7
- c.addi t4, -12
- c.sub s0, s1
- sb tp, 1521(s5)
- c.srli a0, 28
- lb s10, 769(s5)
- c.slli s6, 17
- lw a3, -1510(s5)
- sh t3, -760(s5)
- c.addi s4, -6
- c.lui t5, 5
- sltiu s1, zero, 444
- auipc zero, 742034
- lh s4, 724(s5)
- lbu a6, 1465(s5)
- c.sub a4, a0
- c.li t6, 31
- c.addi a1, 31
- c.srli a2, 20
- lhu s2, -1270(s5) #end riscv_load_store_rand_instr_stream_47
- blt t4, s10, 3906f
- lui a4, 517722
- c.slli s0, 3
- c.srai s1, 23
- addi a2, t5, 303
- c.addi s9, 31
- c.addi s11, -17
- c.lui a0, 13
- bge s8, a6, 3905f
- c.slli s8, 7
- c.srai a5, 4
- c.lui s2, 23
- ori s3, a2, -329
-3905: c.srai a1, 22
-3906: c.slli s3, 7
- auipc t1, 149573
- lui a1, 612166
- c.addi t1, -22
- c.slli a5, 2
- c.addi t4, -20
- c.li a0, 31
- lui s6, 349520
- lui s6, 217973
- c.addi s10, -3
- auipc a7, 429384
- c.addi a3, 27
- fence.i
- auipc s11, 872464
- c.addi s5, -21
- lui a4, 693597
- lui a5, 422462
- c.addi a2, -21
- c.addi a1, 21
- c.addi t5, 1
- c.lui s10, 11
- c.addi a2, 30
- c.srli a0, 28
- c.srai s0, 5
- bge t1, gp, 3935f
- c.lui a2, 20
- auipc a2, 565936
- c.andi s0, 11
- c.srli s1, 24
-3935: rem s3, s5, s10
- c.slli a7, 20
- c.srli a2, 11
- c.srai s1, 8
- auipc s5, 282827
- auipc t6, 168697
- c.xor s1, a1
- c.srai s0, 10
- la t4, data_page_5+1947 #start riscv_load_store_rand_instr_stream_22
- c.slli a1, 2
- c.addi s5, -24
- sb zero, -540(t4)
- srai a1, gp, 4
- c.srli a1, 18
- mulh a7, s9, gp
- c.srai a4, 3
- lb a4, -224(t4)
- auipc s10, 873506
- c.li a6, 1
- c.addi s3, 5
- sb s7, -688(t4)
- lui zero, 954228
- lb zero, 244(t4)
- lbu t2, 1230(t4)
- sltiu s9, t3, -980
- lb a2, -1809(t4)
- c.srli a5, 27
- lbu s10, 1787(t4)
- lhu s6, 1041(t4)
- lui s10, 645143
- or s1, a3, a7
- lw s11, -899(t4)
- c.addi s1, -25
- lbu a1, 1238(t4)
- lui a4, 962793
- c.srli a3, 16
- c.slli s9, 30
- sll s8, a5, s8
- sb t1, 838(t4)
- c.lui t2, 13
- add a3, a5, s3
- lb t6, -406(t4)
- c.srli a3, 20
- lbu a6, -1292(t4)
- lui t1, 359839
- auipc s8, 366870
- c.addi s8, 21
- sll t2, t5, zero
- c.lui a5, 20
- sb a2, 172(t4)
- sb s11, 1074(t4)
- sh ra, -1843(t4) #end riscv_load_store_rand_instr_stream_22
- c.addi a5, -31
- auipc t6, 137011
- c.addi t5, -6
- fence.i
- lui a2, 672688
- c.addi a1, -9
- ori s1, a5, 1020
- lui a6, 108752
- c.lui a3, 22
- slti s2, s4, -674
- c.srai a4, 17
- bltu s10, a2, 3960f
- divu a6, a6, t0
- auipc s10, 1035725
- c.srai s1, 27
- auipc s5, 304512
- c.addi a5, 3
-3960: c.srai a2, 3
- andi a4, s7, -483
- c.addi t2, 16
- auipc s1, 372288
- c.srli a2, 13
- lui s3, 802264
- c.addi s8, 11
- lui a4, 177377
- c.addi gp, -15
- c.slli s2, 30
- c.srli s0, 5
- lui t2, 687115
- c.addi s1, 7
- c.addi s6, -31
- c.slli a5, 26
- c.slli s2, 17
- c.addi a2, 11
- auipc a4, 957133
- c.addi a6, -1
- lui a1, 649422
- c.addi t1, 12
- sll s10, s2, gp
- c.srli a4, 27
- bgeu a5, s11, 3994f
- c.addi s3, 13
- div t3, s2, s7
- c.srai a0, 27
- lui s0, 575662
- c.srai a0, 3
- c.srai a0, 28
- c.add a5, a4
- c.beqz a5, 4005f
- c.slli a6, 10
- c.lui s10, 27
-3994: auipc a5, 318165
- c.addi a5, -9
- c.addi a7, 7
- lui t2, 477766
- c.lui t1, 12
- bge s9, ra, 4018f
- fence.i
- c.addi s0, 31
- beq s2, tp, 4022f
- auipc t4, 442896
- c.addi s7, -25
-4005: fence
- beq t3, t0, 4015f
- c.addi s7, 29
- auipc t4, 532961
- c.slli s5, 15
- ori t4, t1, 67
- lui a1, 508326
- lui a1, 993176
- addi zero, t3, -679
- auipc zero, 380829
-4015: c.addi t3, -14
- c.srai s0, 21
- c.srli a3, 6
-4018: c.srai s0, 31
- c.addi s1, 1
- slli s0, a0, 3
- c.addi s3, 22
-4022: auipc t3, 115687
- c.lui s11, 29
- xor s4, tp, a3
- c.addi t3, 2
- c.slli t5, 18
- c.addi t2, -30
- sra t4, t3, s6
- c.addi s5, -16
- c.addi s11, -7
- mul s10, s11, gp
- mul s8, s0, a7
- c.beqz a2, 4051f
- c.addi s7, -29
- lui s7, 259104
- lui t1, 128850
- c.lui s6, 10
- c.addi a6, 5
- auipc s10, 357426
- c.slli a2, 13
- lui gp, 1044911
- c.lui a4, 17
- c.addi a0, 25
- c.slli t4, 2
- c.addi a6, -21
- lui zero, 129082
- lui a4, 147695
- c.srai a1, 16
- auipc a1, 458918
- lui s6, 498931
-4051: c.addi a0, 11
- lui s6, 444350
- lui a7, 809854
- c.addi s1, 7
- mulhu a4, s1, t2
- auipc t3, 939273
- auipc s11, 287593
- lui t5, 88290
- c.srli a3, 12
- slti s0, s0, 96
- c.addi a7, 12
- c.addi s8, -31
- auipc a0, 386670
- auipc a4, 511492
- c.addi t4, -28
- c.addi s11, -16
- c.addi a2, 17
- auipc t2, 721980
- c.slli a2, 25
- c.slli t4, 1
- fence.i
- c.srai a1, 18
- c.addi s7, 6
- c.li s1, -14
- auipc zero, 996921
- c.addi s3, 1
- c.srai a4, 19
- auipc t1, 700006
- c.lui a0, 7
- auipc s3, 576321
- c.slli a0, 31
- c.mv s10, a4
- srai s9, a4, 17
- xor t3, t5, s10
- lui s3, 695038
- mulh s3, a0, s9
- c.lui s8, 17
- auipc a0, 964724
- c.srli a4, 15
- c.addi t1, -12
- c.addi a7, -3
- c.srli a5, 28
- c.slli s0, 2
- c.addi s7, 17
- c.srai s1, 31
- lui s8, 888452
- lui s6, 398545
- auipc t4, 845050
- auipc a6, 4204
- lui s10, 682032
- auipc s6, 273031
- c.lui t4, 10
- c.srai a1, 5
- c.addi s7, 17
- c.addi a2, 3
- c.addi s7, -32
- auipc s4, 612170
- c.lui a0, 17
- c.addi s11, 29
- lui s7, 55491
- and s4, s6, a2
- or a5, s11, gp
- c.lui s5, 11
- c.srli a5, 20
- c.addi a4, -8
- auipc s0, 1003004
- c.slli s2, 5
- c.addi t2, -10
- c.addi t6, -7
- auipc s3, 762068
- auipc a6, 729246
- c.slli a0, 7
- c.addi s8, -10
- la s5, data_page_15+2573 #start riscv_load_store_rand_instr_stream_34
- lui t5, 815093
- c.srli a3, 29
- divu t6, tp, s2
- c.srli a3, 31
- c.addi s9, 11
- sb s0, 624(s5)
- lb s8, -1668(s5)
- c.addi a5, 12
- lhu a5, -1579(s5)
- auipc gp, 433835
- lui gp, 57534
- c.slli s4, 5
- lb a4, -19(s5)
- lui a0, 1011884
- auipc s2, 859902
- lh s4, -891(s5)
- lb s2, -821(s5)
- c.slli s2, 16
- lbu s8, -1696(s5)
- srl a1, a7, t0
- c.slli a6, 27
- auipc s7, 626500
- remu zero, t4, s10
- lbu t3, 1460(s5)
- lh a5, -1039(s5)
- c.addi s8, -30
- c.srai a1, 26
- slli a5, t4, 0
- sb a1, 1185(s5)
- c.addi t6, 15
- c.addi s1, -6
- c.addi s1, -28
- sh tp, -1383(s5) #end riscv_load_store_rand_instr_stream_34
- srli a0, tp, 3
- c.addi s5, 26
- c.addi a6, 27
- c.srai s0, 6
- lui t3, 571052
- auipc a7, 529551
- slt t5, s6, s6
- nop
- mul a6, a3, s3
- c.slli a7, 11
- auipc t5, 551142
- slli a5, gp, 15
- c.srai a1, 20
- nop
- lui s2, 533832
- c.slli a1, 7
- c.lui t6, 28
- la t5, data_page_1+2088 #start riscv_load_store_rand_instr_stream_16
- c.addi s1, -31
- c.lui a5, 22
- sb zero, -1469(t5)
- lbu s9, 473(t5)
- c.srai a3, 15
- lui s3, 464789
- c.sub s0, a4
- c.slli s1, 30
- auipc a5, 711984
- auipc s8, 703828
- sb s0, 1439(t5)
- sltiu s7, t2, -83
- c.addi a0, 8
- sltiu s8, s6, 643
- c.addi t3, 25
- auipc s8, 850458
- slli a7, t1, 3
- auipc a1, 2924
- sh tp, 698(t5)
- c.li t3, -25
- sb s9, -818(t5)
- c.lui s1, 26
- c.slli a7, 10
- c.addi a7, 20
- lb s8, -57(t5)
- lbu a6, -786(t5)
- srl s0, t0, s0
- c.lui t4, 6
- lb a4, -517(t5)
- c.lui t6, 13
- sb a6, 523(t5)
- add a4, gp, a4
- auipc a0, 483835
- c.or a5, a2
- lui s0, 1020498
- sb t1, 235(t5)
- mul t4, s9, a5
- sh a2, 884(t5) #end riscv_load_store_rand_instr_stream_16
- c.bnez a1, 4158f
- c.addi s4, 18
- auipc s1, 771464
- c.lui s2, 9
- auipc s1, 1014007
- c.srai a5, 29
- c.slli a7, 15
- mul a0, s0, s6
- lui s2, 846729
- c.beqz a1, 4167f
- lui s5, 988694
- c.srli a1, 15
- lui a3, 770481
- c.lui s10, 25
- slti a3, s11, -336
- c.slli a0, 9
- lui t6, 189898
-4158: auipc s0, 80966
- auipc s3, 748568
- slli a7, zero, 25
- ori s10, t5, -733
- c.srli a5, 4
- ori s8, s9, 107
- c.srai a3, 16
- c.addi s8, -1
- c.beqz s1, 4170f
-4167: c.addi s5, -24
- c.lui a5, 4
- slli a2, t1, 3
-4170: c.lui t2, 28
- c.addi gp, 26
- c.slli t2, 29
- c.lui t1, 22
- lui a7, 1019963
- c.mv s11, s1
- c.addi s0, 27
- c.addi a1, 29
- addi t6, s7, -789
- c.addi t2, -4
- c.lui s3, 28
- remu a1, a1, a6
- lui s2, 729837
- slt a2, ra, a5
- c.slli gp, 2
- c.nop
- lui a4, 1011889
- c.addi t1, 6
- c.srai a3, 19
- bge tp, a2, 4192f
- c.addi s11, -31
- c.addi s2, 4
-4192: slt t1, s1, s1
- c.beqz s1, 4200f
- auipc t3, 324097
- auipc t4, 474314
- c.lui a3, 20
- c.srli a0, 16
- lui s5, 923963
- c.addi s7, 26
-4200: remu s9, sp, s3
- auipc a5, 479149
- addi a6, s11, -285
- c.srli a3, 18
- rem t3, s7, s11
- auipc s4, 121112
- c.srai a5, 11
- c.slli a2, 21
- rem a1, a4, a4
- c.slli s10, 23
- c.srli a1, 18
- lui t3, 364975
- c.lui t2, 18
- c.lui a7, 31
- c.addi t5, -31
- la t6, data_page_6+2125 #start riscv_load_store_rand_instr_stream_44
- lw t3, -265(t6)
- lb s4, -1303(t6)
- c.addi a6, 24
- lb s10, -914(t6)
- c.addi t5, -29
- auipc t1, 120627
- lbu t5, 1324(t6)
- sh sp, -473(t6)
- lb t4, -86(t6)
- sb s5, -2026(t6)
- c.addi s10, 24
- lbu t5, -561(t6)
- lh a2, 1695(t6)
- lb a4, 971(t6)
- c.addi s10, 30
- sb gp, 1602(t6)
- lui t4, 923299
- lhu a7, 1465(t6)
- lw s0, 1439(t6)
- c.srai s1, 28
- sb a1, -2036(t6)
- c.addi s4, 17
- c.addi t3, 26
- lbu t5, -1913(t6)
- sll s9, s1, s0
- lb s7, 423(t6)
- c.srli a1, 4
- lb s1, -1310(t6)
- c.addi t1, -8
- c.srli a0, 11
- c.addi s11, 21
- c.lui t1, 4
- lhu s7, 819(t6)
- lw s10, -2037(t6)
- sh t0, -1169(t6)
- lw a4, 1171(t6)
- c.slli gp, 20
- sb t1, 1516(t6)
- lhu a7, -839(t6)
- c.addi s1, 30
- lui a6, 69946
- lhu s0, 1049(t6)
- lb a3, -1236(t6)
- sb t3, 1582(t6)
- sb s1, -938(t6)
- c.srai a5, 26
- c.addi s1, -20
- lhu s3, 1415(t6)
- sb s11, -1622(t6)
- lb s7, -1139(t6) #end riscv_load_store_rand_instr_stream_44
- c.srai a2, 23
- c.addi a6, -29
- c.addi t6, -16
- slli s7, t0, 1
- c.addi s2, -16
- auipc gp, 291790
- c.addi s9, 6
- auipc a2, 387614
- auipc t3, 779622
- lui zero, 822729
- c.addi s8, -4
- c.slli s5, 29
- srai s1, t5, 8
- remu a7, tp, gp
- auipc t4, 384941
- andi a0, s3, 805
- c.addi a5, 9
- c.sub s1, a0
- c.lui s7, 22
- nop
- add t1, t6, a6
- lui a3, 29435
- c.add a5, a0
- c.andi a0, -9
- remu zero, s8, gp
- c.srli a0, 7
- c.slli s1, 12
- mulhsu a1, s8, a5
- c.addi a7, -8
- c.slli t5, 5
- c.srai s0, 13
- c.srai s1, 20
- c.slli s10, 27
- lui s7, 593334
- c.addi gp, -21
- slti a7, t4, -513
- auipc a5, 59022
- c.addi a5, -11
- auipc s9, 658138
- lui a4, 874361
- auipc s11, 985381
- c.addi s6, 12
- auipc s11, 147140
- c.addi t5, -1
- fence.i
- c.slli a6, 1
- auipc a1, 248720
- xori t2, s9, -254
- add a7, s10, zero
- c.srli s0, 6
- and s3, s11, a3
- addi s1, a1, 418
- c.srli a2, 10
- mul a6, s9, s9
- auipc s4, 83414
- c.addi t3, 29
- xor s8, a3, s11
- c.srli a4, 29
- c.lui a2, 4
- c.srai a2, 5
- c.slli a0, 19
- nop
- c.addi t3, 22
- c.srli a2, 1
- sra s2, ra, a0
- auipc t1, 723947
- c.lui a2, 28
- mulh s11, s6, a1
- auipc a3, 231331
- c.addi s10, 27
- c.lui s9, 29
- c.addi a0, -5
- xori t3, tp, -443
- sra s2, ra, a5
- rem t3, t3, a2
- auipc s3, 141987
- lui s11, 993312
- mulhsu t5, s5, s1
- auipc s10, 873125
- lui s1, 55914
- c.addi s8, -8
- c.addi t1, 1
- auipc a6, 890897
- c.srli a3, 21
- c.addi a4, 14
- slli a0, s0, 3
- c.beqz a4, 4309f
- c.srli a5, 14
- c.addi s5, -27
- auipc s1, 72964
- lui s0, 976843
- auipc a3, 341822
- c.addi t4, -6
- auipc a7, 762922
-4309: c.addi s8, 28
- c.srai a5, 4
- mulhsu s5, s4, s0
- and a0, s5, a7
- c.srai s1, 4
- c.addi gp, -25
- c.nop
- lui a1, 225917
- auipc t4, 631163
- c.addi s7, -31
- c.addi a4, 24
- auipc t4, 676961
- bne t5, s5, 4324f
- auipc t3, 388077
- auipc s10, 31265
-4324: c.addi s3, -6
- and a1, gp, s9
- lui t4, 816288
- c.addi t1, -16
- c.slli t5, 17
- c.slli s5, 21
- add t6, ra, t6
- c.addi a7, -25
- div t4, a3, a3
- c.lui a6, 9
- c.addi s5, 22
- c.srai a0, 12
- c.addi t3, -12
- c.lui t4, 8
- c.addi t2, -5
- c.addi s1, 16
- c.srai a0, 31
- lui t5, 796312
- c.srai a2, 14
- c.addi s0, 26
- c.srli a4, 23
- and s10, t1, s9
- c.srli s0, 15
- slti s0, t3, 389
- c.addi a0, -21
- lui a3, 1014673
- c.addi s10, -1
- fence
- c.slli a5, 26
- slti a6, t2, 716
- auipc a3, 861151
- c.addi a1, 8
- sltu s7, a7, s8
- c.srli a4, 10
- c.srai a5, 6
- mulhu s0, s11, s10
- c.lui s9, 17
- c.addi a5, 24
- c.srli a3, 5
- lui s3, 606985
- auipc zero, 1011110
- mulhsu t1, t3, a3
- c.addi s0, -31
- lui a1, 6400
- lui a0, 443953
- c.srai a3, 24
- c.addi s0, 13
- c.addi t1, 27
- c.srli a5, 4
- xor gp, a1, zero
- mulhu s10, t5, s1
- c.srai a4, 9
- c.slli s2, 10
- auipc t3, 145106
- lui a2, 230282
- sra a0, s10, s8
- auipc a2, 283426
- lui a5, 207359
- c.addi a5, 30
- c.add a5, s1
- c.addi s7, 21
- c.addi s0, -29
- rem s3, a3, s4
- nop
- c.add a5, a5
- c.srai a4, 25
- sra s2, zero, a7
- lui t3, 582730
- c.lui t4, 11
- ori a3, t1, -32
- c.srli a4, 4
- c.lui s2, 25
- beq a1, s3, 4414f
- c.addi a2, 10
- c.addi s6, 7
- c.addi a4, 2
- auipc a2, 840778
- bge t3, a7, 4405f
- c.srli a0, 22
- srai t6, a4, 10
- auipc s8, 699310
-4405: or s10, s1, t5
- c.addi s9, 5
- c.addi s9, -24
- c.addi t4, -8
- c.mv gp, s0
- c.lui a5, 5
- c.nop
- auipc s11, 30214
- auipc s5, 280226
-4414: auipc t4, 851418
- auipc t2, 744163
- lui s5, 902376
- remu a1, s7, t1
- fence
- c.slli s4, 4
- auipc s2, 734632
- slt s6, t5, t5
- bltu t4, zero, 4432f
- xor zero, s7, zero
- slli s2, s8, 5
- srl s3, s9, zero
- c.addi s5, 16
- lui a0, 472024
- c.addi t1, 8
- c.addi t6, -31
- lui s2, 724004
- slti a5, s3, 272
-4432: c.addi s7, -26
- c.addi t1, 7
- slt a4, s1, t0
- slt gp, t4, s9
- sll gp, a7, s4
- divu s10, a0, ra
- addi s5, s11, 138
- lui s2, 420567
- c.slli a0, 24
- c.addi a2, 18
- auipc t3, 47286
- c.addi s1, -7
- c.srli a5, 28
- c.addi s0, -13
- c.addi t2, -32
- auipc a0, 199552
- c.addi gp, -12
- c.srai a5, 11
- c.addi t3, -7
- c.addi s4, -32
- c.lui t6, 11
- c.addi a4, -14
- mul a2, s11, s5
- auipc a5, 636745
- c.addi s6, 26
- lui a1, 533414
- c.slli a6, 20
- mulh t3, sp, t5
- c.lui s7, 2
- xori s4, t5, 271
- mul t6, s10, t1
- mulhu gp, s10, a7
- c.addi s9, -21
- c.addi s0, 29
- c.srai s0, 22
- c.addi a7, -7
- c.slli t3, 29
- c.lui t4, 29
- c.srli a5, 12
- c.srai a2, 5
- lui s6, 835969
- c.srli a4, 23
- c.srli a0, 7
- sll s6, gp, s11
- c.srai a5, 11
- auipc a3, 652411
- auipc t4, 930274
- srl s0, s3, a2
- c.srai a0, 3
- c.addi s2, 4
- c.lui a3, 9
- c.addi gp, -15
- bge a0, s5, 4494f
- c.srai a0, 11
- bge s8, t6, 4491f
- auipc s8, 563934
- c.slli t3, 5
- c.addi s7, -22
- c.addi s4, 1
-4491: blt t6, a2, 4507f
- c.addi a2, 16
- c.addi s10, -22
-4494: c.slli gp, 16
- c.addi t4, 27
- lui s6, 408265
- c.addi s9, -25
- c.srli a3, 21
- c.addi a0, 24
- slti a7, a0, -861
- c.addi t6, 9
- c.and a4, s0
- nop
- auipc t1, 913741
- lui a1, 648746
- lui s11, 904945
-4507: c.srai a1, 22
- c.srai a2, 25
- c.addi s8, 6
- c.slli a5, 28
- lui a1, 756121
- auipc s4, 136290
- slt s5, a4, s7
- c.addi a7, 14
- c.addi t5, 21
- c.lui t3, 7
- c.xor s0, a4
- c.lui s9, 4
- bne s2, t5, 4530f
- xori s9, t2, 595
- la s11, data_page_6+2335 #start riscv_load_store_rand_instr_stream_66
- lb s4, 628(s11)
- sh s6, -365(s11)
- lb a0, 1498(s11)
- sb a7, 831(s11)
- c.nop
- sb gp, 1284(s11)
- sb t1, 998(s11)
- lhu s9, 1747(s11)
- lbu t3, 1299(s11)
- auipc a5, 644480
- c.srai s0, 20
- lb s3, -1841(s11)
- lbu t2, -274(s11)
- srl s7, a0, sp
- c.addi a5, 31
- sw a1, 309(s11)
- remu s2, a3, s7
- lbu a3, 140(s11)
- sb a3, -1328(s11)
- mul s9, tp, s8
- lb s1, -1846(s11)
- lhu s7, -1657(s11)
- lh s4, -1829(s11)
- addi a5, s9, 166
- lui s9, 82216
- sb s10, -1246(s11)
- c.srai a0, 23
- c.lui a1, 26
- auipc a2, 560078
- sh a6, 941(s11)
- sb s11, -341(s11)
- c.lui s4, 5
- sb t3, 1406(s11)
- sb t2, 1749(s11)
- lb s5, 1400(s11)
- lbu a1, 1118(s11)
- c.slli t3, 20
- lh a3, 297(s11)
- lbu a6, -1484(s11)
- lui a4, 978621
- fence
- c.addi t6, 28
- lb a3, 1735(s11)
- auipc a5, 277471
- sb gp, -1166(s11) #end riscv_load_store_rand_instr_stream_66
- c.lui a3, 21
- c.slli t2, 12
- la s7, data_page_18+1982 #start riscv_load_store_rand_instr_stream_68
- c.addi a1, -13
- sb s1, 1889(s7)
- c.addi s11, -5
- lb a4, -963(s7)
- auipc a5, 599389
- c.or a2, a2
- mul t5, s5, t5
- fence
- lb s1, -525(s7)
- c.and a5, a2
- lbu s6, -667(s7)
- c.srli s1, 2
- c.addi a3, 23
- auipc t1, 168119
- lui t1, 1043390
- c.slli t1, 22
- lhu s5, -364(s7)
- lb s0, -1665(s7)
- div a2, sp, a3
- sb a6, -828(s7)
- c.lui a6, 7
- c.addi s5, -7
- c.addi t5, -31
- add a6, a6, sp
- c.add a1, a5
- lhu t6, -792(s7)
- c.slli t2, 22
- lui t5, 126243
- lbu a6, -760(s7)
- lui a0, 1043503
- c.slli s3, 22
- auipc t2, 571002
- lw t2, 1586(s7)
- slt t3, s9, zero
- auipc s5, 96094
- auipc s6, 255165
- lbu s10, -403(s7)
- lui s9, 970464
- c.lui t3, 20
- c.addi s1, 16
- sb a5, 1220(s7)
- c.addi t6, 17
- lbu s2, 77(s7)
- sw a1, 1950(s7) #end riscv_load_store_rand_instr_stream_68
- srli s7, tp, 4
- c.addi s9, 12
- sltu t1, tp, s9
- c.addi s1, -23
- c.srai a1, 16
- sltiu a0, s8, 610
- c.srli a3, 2
-4530: c.addi s2, -23
- c.srli a0, 21
- auipc s8, 651943
- c.lui a3, 14
- c.srli a3, 20
- auipc s7, 465333
- c.addi a3, -11
- c.srai a2, 12
- lui t3, 982559
- c.addi s4, 29
- xori s8, zero, -493
- nop
- auipc s8, 956215
- la s11, data_page_15+1831 #start riscv_load_store_rand_instr_stream_58
- or t4, a6, s10
- c.and a2, a5
- c.addi s1, -8
- sb a6, 737(s11)
- lui gp, 575660
- divu t4, ra, a4
- lb s9, 1414(s11)
- sb t2, -1428(s11)
- lb t3, 274(s11)
- mulhu a0, t1, a7
- lb s8, 90(s11)
- c.li s9, 2
- sb a2, 618(s11)
- sh s7, 931(s11)
- lb t2, 138(s11)
- lh a4, 1011(s11)
- auipc a2, 335282
- c.add s1, a3
- c.addi gp, -31
- c.addi a6, 21
- auipc zero, 923122
- lbu a5, 231(s11)
- lhu t2, 879(s11)
- sw t6, -707(s11)
- c.slli s0, 20
- mulhu s4, t0, sp
- lui s5, 511311
- lb t6, 442(s11)
- lh s0, -815(s11)
- c.li t5, -9
- lbu a6, -1313(s11)
- lhu s10, 1963(s11)
- c.srai a2, 30
- auipc a7, 566302
- auipc a5, 646040
- lw a7, -1279(s11)
- fence.i
- c.li s2, 30
- auipc a0, 317318
- lh s7, -1459(s11)
- lb s0, 446(s11) #end riscv_load_store_rand_instr_stream_58
- auipc s0, 325999
- c.addi a5, 31
- lui a3, 132916
- c.srai s1, 9
- c.lui s5, 5
- c.srli a2, 31
- c.srli a3, 29
- c.srai a1, 8
- c.addi a5, -12
- bne ra, s3, 4554f
- c.addi a5, -13
-4554: c.addi s3, -2
- lui t2, 236932
- c.addi a6, -31
- c.slli a3, 28
- la s10, data_page_11+1971 #start riscv_load_store_rand_instr_stream_6
- nop
- sb t6, -629(s10)
- c.addi s9, -32
- auipc s3, 925628
- lbu zero, -1817(s10)
- c.slli s6, 3
- or a7, t2, sp
- c.addi s0, 28
- xor a0, a4, s4
- lbu a0, -1536(s10)
- lb t1, -1182(s10)
- xori a4, s11, 127
- lbu s7, -338(s10)
- c.addi s3, -22
- lbu a5, -807(s10)
- c.mv s2, a5
- c.srai s0, 25
- lb a3, 1420(s10)
- c.xor a3, a1
- sb a4, -638(s10)
- lui a3, 360054
- c.addi a6, -24
- lui s1, 1025620
- c.sub a1, a3
- lb s2, -208(s10)
- sb s2, -457(s10)
- lbu s7, -816(s10)
- sb s11, 1123(s10)
- lb a2, 695(s10)
- c.addi t3, 25
- lui s2, 874784
- lhu a5, 883(s10)
- sb s4, 708(s10)
- lb s6, -53(s10)
- lui t6, 891818
- lh s3, 1157(s10)
- c.addi a5, 9
- c.addi t6, 17
- c.lui t6, 3
- lhu t4, 571(s10)
- sb zero, 814(s10)
- lui s3, 557897
- lb s6, 444(s10)
- c.addi s6, -6
- lb t6, -1412(s10)
- c.slli s9, 14
- lb a3, 1252(s10)
- c.srli a3, 2
- lb t5, -1753(s10) #end riscv_load_store_rand_instr_stream_6
- auipc s5, 399855
- c.addi s2, 11
- c.slli s3, 8
- beq s7, t0, 4575f
- c.lui s11, 4
- c.addi gp, -7
- c.addi s0, 31
- c.addi s3, -22
- c.slli a1, 6
- auipc a7, 660917
- auipc a1, 28151
- auipc s0, 110551
- c.andi a2, 3
- c.addi s7, -15
- lui gp, 794557
- auipc a3, 832147
- lui s7, 348548
-4575: c.addi a0, -5
- c.srli a2, 3
- bne s3, a3, 4591f
- lui a3, 313988
- lui a4, 40263
- mul t1, tp, zero
- nop
- c.addi s11, 9
- c.andi a4, -28
- c.addi a2, -2
- c.addi t5, -8
- mulhsu zero, s8, t6
- auipc a7, 140559
- c.lui a5, 24
- slt a7, s10, s6
- c.addi s2, -12
-4591: c.srli a3, 1
- c.srli a5, 7
- c.slli t4, 29
- fence
- auipc t3, 996736
- lui t1, 890615
- c.or a3, a5
- lui s10, 188815
- fence.i
- c.slli t4, 21
- c.addi a6, -5
- c.xor a1, s0
- lui a7, 430332
- auipc a7, 109331
- c.srli a0, 4
- c.srai s1, 28
- sll a3, t2, sp
- c.lui t1, 2
- c.addi s5, 7
- lui s0, 567848
- lui s2, 329753
- div a1, zero, sp
- c.srai a1, 20
- c.slli s4, 1
- lui s2, 640068
- slt a7, zero, ra
- auipc s10, 371638
- lui s10, 45665
- c.addi s0, -2
- c.srai a3, 25
- auipc t3, 255572
- c.addi t3, -23
- mulh s9, s4, a2
- add s7, t5, a6
- c.addi t5, -13
- c.slli a4, 16
- c.addi t4, 22
- c.srli a3, 13
- c.addi s11, 12
- c.or a2, a1
- c.sub a0, a3
- addi s9, t3, -249
- lui a1, 238451
- lui t6, 365134
- lui a6, 887286
- c.lui a0, 17
- c.mv s8, a1
- lui zero, 712323
- addi s8, s0, -18
- c.lui s5, 23
- srl t5, a6, s1
- c.srli s1, 20
- c.srai a4, 24
- lui a4, 165270
- lui s5, 282653
- c.addi s1, -18
- c.addi s4, -8
- c.addi t1, 28
- c.addi a5, -30
- c.addi s7, -20
- c.slli s9, 17
- c.srai s0, 4
- beq ra, a3, 4661f
- add t3, a1, s1
- c.srli a1, 1
- c.addi s9, -19
- c.lui s11, 16
- c.addi gp, -11
- c.srli a3, 24
- bne a5, t1, 4677f
-4661: auipc zero, 90440
- c.srai s1, 27
- c.addi a1, 9
- c.addi a0, 11
- c.lui s2, 13
- divu a2, s2, t2
- c.addi s6, -9
- c.srai s0, 21
- c.srai a5, 20
- c.addi a5, -4
- c.addi t1, -14
- c.addi s10, 23
- c.addi s1, 5
- c.srli a2, 16
- nop
- c.srai a3, 6
-4677: c.addi t2, 31
- auipc s8, 504364
- c.srli a2, 27
- c.addi s4, 27
- c.or a2, a4
- mulhsu a1, s11, t5
- c.lui a7, 23
- c.srai a4, 14
- c.addi a5, -27
- lui s7, 937973
- c.slli a2, 13
- c.xor s1, a5
- rem a1, t1, s0
- c.xor a4, a0
- auipc a7, 180322
- c.addi s11, 20
- c.lui s6, 31
- c.addi t1, -13
- slt a2, s4, t2
- lui a4, 332318
- sltiu a1, s2, 883
- auipc t1, 860042
- c.and a5, a3
- c.srai a2, 7
- c.addi t1, 3
- c.addi s7, -12
- auipc t6, 833854
- lui a1, 5711
- auipc gp, 1014400
- lui s3, 999928
- c.addi a7, -13
- mulh a6, t6, s2
- fence.i
- auipc s3, 465351
- c.addi a7, 29
- c.addi t6, -17
- lui a5, 315945
- c.or a5, a0
- lui s1, 169703
- c.addi s3, -7
- or a7, gp, s10
- c.addi a4, 26
- c.slli s3, 23
- c.srli a0, 24
- c.addi a4, 16
- c.srai a2, 26
- c.addi t1, 29
- c.srai a5, 5
- c.addi gp, 20
- c.lui s4, 23
- auipc s11, 311221
- fence.i
- c.addi a2, -28
- sll t4, zero, t5
- sll a0, gp, a4
- c.addi t4, 25
- c.and a2, a2
- c.srai a2, 2
- c.addi a4, -21
- c.addi t4, -22
- c.addi t6, -8
- c.addi s0, 26
- c.addi a7, -15
- c.srai a1, 28
- c.srai a3, 13
- slt s6, tp, gp
- or a3, s5, s8
- c.addi a1, -17
- c.addi a4, -10
- c.addi s5, -29
- auipc a1, 502577
- c.addi a3, -17
- c.lui t2, 21
- lui a4, 304520
- c.addi t3, 14
- lui s7, 889348
- div a0, ra, s9
- c.srai a0, 8
- c.addi s9, -9
- c.or s0, s0
- c.srli a4, 28
- lui a5, 219914
- lui a0, 316260
- c.lui a0, 31
- auipc t3, 859197
- c.mv s1, s3
- c.addi s9, 25
- c.addi s10, -24
- fence.i
- c.addi a0, -32
- nop
- lui a7, 463008
- c.srai a5, 22
- c.addi s3, 7
- c.srai a5, 19
- xori t2, gp, -1009
- c.addi s10, -8
- mulhu s11, s0, ra
- c.addi s9, -20
- c.slli s7, 9
- c.srli a0, 7
- c.slli a3, 16
- and a0, a5, t5
- c.srai a4, 19
- lui t2, 466581
- c.lui s11, 15
- bge a6, s6, 4792f
- c.slli s3, 19
- c.slli s11, 4
- c.addi a6, -1
- srli a4, a3, 22
- c.slli t3, 11
- c.and s0, a2
- c.lui t2, 1
- c.addi t1, -14
-4792: c.addi t2, -5
- sll s6, t4, a4
- c.addi s4, 24
- auipc s6, 563201
- lui a3, 292051
- c.slli s10, 3
- bne sp, s9, 4799f
-4799: c.addi s8, -14
- c.li a1, 5
- or s2, sp, s6
- lui a1, 250240
- c.addi s6, -14
- c.addi t6, 26
- c.slli s9, 19
- c.addi s5, 13
- and gp, t2, t1
- c.lui t1, 7
- c.addi s10, -15
- srli t2, t4, 12
- c.lui a3, 26
- c.addi a2, 1
- lui gp, 996606
- c.slli t6, 20
- c.lui a3, 14
- c.srli a0, 30
- c.addi t2, -21
- nop
- c.addi t2, 29
- slli t5, a6, 26
- c.addi s6, 30
- lui s4, 659953
- c.addi gp, 29
- c.srli a5, 18
- c.srai a5, 7
- auipc t5, 1033850
- lui s5, 81019
- addi s7, t0, -849
- c.slli s5, 2
- c.or a3, a3
- c.srai a0, 3
- c.lui t4, 19
- c.addi a6, 17
- c.addi s5, 16
- c.srli a2, 10
- lui s8, 766742
- c.addi a6, 28
- c.nop
- lui a4, 225744
- lui t2, 190057
- c.srli a4, 24
- mulh s11, a6, t1
- c.srai s1, 17
- auipc a4, 816702
- c.addi s3, 10
- auipc a0, 68611
- c.mv s2, ra
- fence
- beq ra, sp, 4867f
- mul s1, t3, a5
- auipc s4, 869470
- c.slli t5, 3
- c.addi t3, 3
- lui a4, 793230
- c.lui s1, 12
- c.addi a3, -2
- sra a3, a5, a0
- c.addi a0, 21
- beq a6, a3, 4866f
- auipc a2, 319873
- lui a2, 304187
- c.lui a4, 19
- c.addi a3, -13
- c.addi t3, 20
- c.addi s5, 22
-4866: c.addi a6, -14
-4867: c.srli a1, 10
- auipc zero, 551031
- fence
- c.addi s1, -17
- lui a2, 71385
- c.andi a5, 3
- c.srai s1, 18
- slti s11, s6, 283
- c.addi s2, 13
- lui t6, 791507
- la s3, data_page_9+1954 #start riscv_load_store_rand_instr_stream_9
- ori s2, a2, -189
- lb a6, 1579(s3)
- auipc a7, 898302
- lb a1, -681(s3)
- auipc t3, 412787
- lhu s4, 1612(s3)
- sb t6, 29(s3)
- c.srai a0, 26
- auipc s1, 339851
- c.addi t4, 13
- xori a4, gp, -633
- divu t4, a0, a5
- lbu t5, 859(s3)
- c.slli s5, 25
- c.mv s1, s10
- lh gp, -1560(s3)
- c.addi a4, -7
- lb s10, -1723(s3)
- srli s1, s11, 10
- xor s1, s8, s1
- sltiu s4, s3, 491
- lw t3, -470(s3)
- lbu t2, 1121(s3)
- slli a5, gp, 12
- c.slli t4, 24
- c.addi s9, 6
- sltiu t4, s9, 646
- sb s5, 579(s3)
- lbu s11, 1208(s3)
- sb s7, -296(s3)
- sb a5, 921(s3)
- lbu a2, -127(s3)
- sb zero, 543(s3)
- c.addi a2, -7
- lui a6, 289915
- sb s1, 977(s3)
- lw t1, 598(s3)
- lb s7, -968(s3)
- lb s1, 1407(s3)
- mul a7, t6, s11
- sh tp, 440(s3)
- lbu s11, -1945(s3)
- auipc a1, 99547
- lb s5, 241(s3)
- c.addi s1, 10
- lui a6, 1008720
- c.addi a6, 23
- c.nop
- slt s4, gp, t0
- lbu s11, -107(s3)
- lui s9, 665050
- sb t1, 1053(s3)
- sb s7, 243(s3)
- lh a1, 128(s3) #end riscv_load_store_rand_instr_stream_9
- auipc a3, 275463
- sub s11, sp, t6
- srai gp, a6, 22
- c.addi a6, 15
- c.lui t1, 20
- c.lui s4, 26
- c.addi t1, 30
- c.andi a4, 17
- c.lui a1, 22
- auipc a0, 349323
- auipc s3, 754968
- c.sub a1, s1
- lui s3, 1585
- lui t2, 811924
- c.lui a7, 5
- c.addi s8, 8
- c.addi t2, -17
- c.srai a4, 29
- c.xor s0, s0
- c.addi s6, 22
- c.srli a0, 2
- sltiu a7, s2, -917
- c.lui a7, 26
- c.addi s8, 12
- c.mv a4, ra
- lui t2, 467925
- c.addi s9, -23
- c.srai a4, 16
- auipc zero, 553705
- c.srli a0, 9
- sll s2, s1, a7
- c.addi t1, 28
- c.addi s6, 2
- lui a7, 820104
- slti s7, ra, -212
- c.andi a1, -17
- auipc a7, 99103
- auipc s9, 567717
- lui a1, 760470
- c.addi a1, 9
- auipc s8, 603303
- lui t6, 781280
- c.srai s0, 22
- lui a7, 519407
- auipc t1, 100859
- c.addi a0, -2
- lui s6, 172029
- c.addi a2, -23
- c.addi s6, 22
- c.addi t2, 6
- c.addi a1, 14
- auipc t5, 706283
- auipc s5, 343012
- c.slli t5, 12
- c.lui s0, 24
- auipc s9, 950928
- c.and a4, a3
- c.srli s1, 19
- lui a2, 447292
- auipc t6, 28004
- auipc zero, 37888
- auipc t1, 566584
- c.srai a3, 15
- c.addi s4, 4
- auipc s10, 920842
- xor s6, t2, s0
- c.srai s0, 18
- auipc a4, 720670
- c.srai a0, 15
- c.addi s1, 13
- c.nop
- lui s11, 65000
- lui s8, 446185
- c.addi a2, 15
- c.or a2, a1
- mul t4, s7, s4
- auipc s5, 988581
- div s0, a6, ra
- srl t1, zero, s8
- lui t4, 923755
- c.addi s11, -5
- auipc a3, 731520
- fence.i
- addi gp, t5, 424
- c.addi s8, -15
- c.slli t5, 31
- lui a7, 679813
- c.addi s4, 15
- c.srai a2, 29
- c.addi t5, -15
- c.slli a5, 24
- div s9, s9, a7
- c.addi a2, 24
- c.srai a1, 22
- auipc s6, 783877
- c.addi t6, -12
- c.srli s1, 2
- auipc t1, 178850
- bne t2, s0, 4980f
- c.addi s11, 19
- c.lui gp, 7
- lui zero, 318426
- c.addi s6, 23
-4980: c.srli a2, 3
- auipc zero, 122050
- c.lui t6, 5
- c.bnez s1, 4998f
- c.srli a5, 28
- c.addi t3, 14
- or a6, s5, t3
- addi a7, a2, -645
- lui t3, 624335
- c.srli a3, 20
- lui a7, 105917
- bge s10, tp, 4997f
- fence
- c.srai s1, 6
- c.lui t2, 2
- c.addi t6, 26
- lui s1, 755816
-4997: lui a3, 395594
-4998: lui a3, 526044
- srai s8, s4, 4
- c.sub a3, a2
- c.lui s4, 24
- sltiu gp, s10, 442
- la s11, data_page_2+2354 #start riscv_load_store_rand_instr_stream_18
- sb t5, 1523(s11)
- lui s0, 542801
- lbu s6, -1360(s11)
- c.addi a0, -28
- lui a7, 453107
- lb a5, -1858(s11)
- lb s2, -1863(s11)
- c.slli a1, 2
- sw s3, 1410(s11)
- sh zero, -1290(s11)
- c.addi t2, 27
- sb a2, -1927(s11)
- c.slli s0, 1
- lb s5, 1691(s11)
- sb s4, 967(s11)
- lui s10, 251240
- c.or a4, s0
- lbu s1, 1045(s11)
- c.addi gp, 18
- sh a5, -152(s11)
- c.li t4, 6
- c.lui t6, 3
- lb a3, -489(s11)
- lhu s8, -568(s11)
- sh t0, -1480(s11)
- lhu s7, 220(s11)
- sb t4, 1553(s11)
- lhu s10, -1004(s11)
- c.lui a3, 19
- lbu t4, -1159(s11)
- lb a5, -745(s11)
- sb a7, -1277(s11)
- c.slli a7, 23
- lh s8, -782(s11)
- lbu s3, 263(s11)
- lb s1, 739(s11)
- lbu t4, -1347(s11)
- sw gp, 574(s11)
- sw zero, -242(s11)
- lbu s5, -1339(s11) #end riscv_load_store_rand_instr_stream_18
- c.srai a1, 12
- mul a2, a0, t2
- nop
- c.srli a4, 19
- mulhsu a6, s11, s11
- c.srai a2, 15
- c.addi s7, -5
- lui s4, 598921
- c.addi s3, 1
- c.lui s6, 21
- c.srli a5, 17
- c.addi s5, -14
- c.srli s0, 15
- c.addi a7, -5
- mulhsu a4, s10, ra
- lui s9, 907628
- lui gp, 1042829
- c.addi a5, -9
- lui s5, 577314
- lui s5, 524637
- lui a6, 538829
- c.lui t6, 15
- c.srli a2, 3
- c.slli a2, 24
- c.addi a3, 12
- auipc t5, 269684
- c.addi t6, -27
- c.addi s3, -13
- c.addi a0, -26
- mulhu s3, a6, s7
- c.slli t3, 1
- lui s7, 702027
- c.addi t2, -7
- c.srai s0, 18
- addi s0, t3, -915
- andi a3, s0, 587
- c.slli a6, 15
- srli t1, s3, 17
- auipc a2, 227992
- c.srai a5, 19
- c.addi s10, -11
- auipc gp, 333151
- sll a4, s2, a4
- c.addi a3, -9
- c.addi a0, 19
- lui a7, 720979
- auipc s2, 529174
- c.addi s11, 11
- c.addi a4, 27
- c.srli s0, 25
- c.lui s9, 15
- auipc s4, 401120
- c.srai a1, 4
- c.beqz a3, 5071f
- c.slli t2, 11
- la gp, data_page_4+1814 #start riscv_load_store_rand_instr_stream_27
- c.addi s10, -12
- sh t4, -272(gp)
- lb a6, 1653(gp)
- c.addi s10, -24
- c.addi s0, 22
- c.addi s5, 11
- ori t6, s1, 1011
- auipc t6, 563090
- lui s1, 429013
- sb t4, -1163(gp)
- c.addi a1, 16
- lui s2, 668978
- lbu s10, -709(gp)
- lb s8, -522(gp)
- c.srli s1, 29
- c.addi s11, -8
- lui zero, 3671
- c.srli s0, 17
- c.mv s3, t0
- sb a2, -56(gp)
- srai t6, a0, 14
- fence
- sb tp, -1531(gp)
- mulhu t1, a0, sp
- remu a7, s1, s1
- lbu t2, 798(gp)
- auipc t6, 229513
- c.lui t5, 11
- lbu s0, -1172(gp)
- lb a2, 1032(gp) #end riscv_load_store_rand_instr_stream_27
- fence.i
- c.srli a5, 13
- remu gp, s9, s8
- c.addi gp, -23
- lui s10, 713972
- c.addi s1, -7
- c.addi s1, 2
- c.srli a3, 24
- c.srli a1, 1
- c.srli a1, 9
- c.addi s6, 22
- or s9, s10, gp
- lui t5, 754140
-5071: c.srli a2, 20
- sra a2, t0, t0
- lui s11, 122626
- c.addi a4, 7
- mul t6, a0, t0
- lui t5, 798975
- fence.i
- c.addi t5, -11
- c.add a3, s1
- c.add s0, a4
- bltu tp, t5, 5091f
- lui a1, 103973
- srli a6, s6, 5
- auipc t5, 813332
- lui a4, 155722
- fence
- auipc t4, 326660
- c.slli s4, 18
- addi s7, s5, -973
- auipc s1, 1020772
-5091: slti s0, s2, -326
- bne s2, a3, 5097f
- c.slli s3, 8
- lui s0, 1048015
- c.addi s0, -5
- auipc a6, 459818
-5097: mulh s0, a1, a4
- c.srai s1, 25
- auipc gp, 306262
- c.addi s1, 10
- auipc s5, 478931
- c.addi t2, 25
- c.addi s4, -24
- c.addi s1, -20
- c.addi gp, 30
- lui s4, 365009
- andi a1, t2, -33
- lui a3, 318987
- lui t5, 620716
- c.srli a1, 27
- c.addi a1, 9
- c.addi a3, -32
- lui a0, 303348
- c.slli a7, 20
- c.addi a0, 10
- auipc s3, 137555
- c.addi s2, 19
- auipc a2, 709727
- remu a2, a3, t1
- lui s7, 484661
- lui a5, 883040
- c.and s0, a4
- c.addi a2, -1
- fence.i
- lui s9, 920008
- addi s9, s2, 920
- divu s4, a6, a6
- c.addi s1, 16
- lui a0, 922162
- c.addi s0, -22
- bltu a6, a6, 5133f
- c.srai a5, 16
-5133: c.addi a7, 4
- srli a0, a6, 11
- c.addi a2, -2
- auipc s7, 32546
- c.lui a7, 9
- auipc zero, 54333
- c.beqz s1, 5146f
- c.addi s11, -3
- auipc s5, 862873
- c.lui s3, 26
- c.beqz a4, 5158f
- addi s4, s3, -400
- auipc a3, 922009
-5146: bgeu ra, a0, 5163f
- lui t3, 508266
- c.addi a7, -4
- bltu a1, s8, 5159f
- c.srli a5, 12
- c.or s1, a1
- sub a7, t1, t3
- auipc gp, 246838
- mulhsu t6, s6, s0
- c.andi a5, 24
- c.addi a2, -24
- slli a1, a3, 21
-5158: lui a4, 851980
-5159: lui t6, 728960
- auipc a2, 719883
- rem t1, ra, sp
- sub s10, t2, sp
-5163: srai a4, s8, 26
- lui t1, 690351
- c.addi s9, -12
- auipc a3, 443749
- c.addi s2, -28
- add t4, a4, tp
- c.addi s2, 22
- c.lui s8, 12
- c.addi a5, -5
- divu zero, s1, gp
- c.addi a1, 3
- c.addi t4, 24
- c.addi a0, -28
- auipc a5, 730203
- auipc s9, 107987
- c.addi t2, 24
- c.lui a0, 15
- beq s3, s6, 5194f
- c.lui a1, 12
- beq t0, s9, 5202f
- c.srli a2, 4
- lui a1, 227759
- c.lui a5, 18
- c.addi a7, -23
- c.lui s2, 11
- sltu zero, t0, gp
- c.lui t6, 22
- c.addi a2, 10
- c.slli a6, 19
- c.lui s2, 23
- slli s7, t5, 10
-5194: addi t4, s4, -143
- c.addi t1, -14
- auipc gp, 687633
- lui s6, 631959
- srai a6, s5, 26
- c.addi t2, -21
- xor t6, a1, a3
- lui a7, 968854
-5202: mulhu s3, t0, a0
- auipc a7, 286318
- srli gp, s7, 30
- srl t6, s7, t1
- xori s4, a3, 332
- sub t1, s2, t0
- c.addi s10, -4
- c.slli s4, 24
- divu t5, a7, a2
- auipc t1, 90801
- c.li a5, 20
- c.xor a4, a3
- auipc s10, 358164
- c.lui s1, 1
- c.xor a5, a2
- c.addi t4, 7
- c.srli s1, 6
- auipc t1, 467726
- c.mv a5, t4
- lui a6, 403960
- auipc s11, 1021220
- c.addi gp, -17
- c.srai a1, 15
- bltu s0, a7, 5232f
- bne s4, s1, 5237f
- c.slli s6, 18
- c.addi s1, -17
- c.addi s3, 3
- auipc zero, 455709
- lui a1, 354633
-5232: c.addi s6, 29
- auipc s11, 570461
- lui a7, 664342
- c.addi s7, 29
- mul s5, gp, a0
-5237: c.addi s1, -23
- xor a0, s7, tp
- c.srai s1, 27
- c.lui a3, 1
- lui t5, 132062
- c.addi a3, 27
- c.addi t6, -28
- c.srai a3, 4
- c.slli s11, 25
- c.addi t1, 28
- rem a4, zero, gp
- c.slli s2, 2
- c.andi a3, 28
- c.addi s10, -25
- c.addi s7, 11
- c.lui t3, 10
- div s2, s0, a3
- lui s3, 591615
- c.srli a4, 17
- lui a0, 712408
- c.addi s10, -8
- lui s9, 234500
- c.addi s0, 29
- c.slli t3, 22
- c.addi a4, -16
- c.and a3, a3
- c.addi t5, -14
- auipc t3, 231942
- c.lui a6, 3
- slti a7, s1, 865
- c.addi s6, -20
- rem a1, a3, a2
- la a7, data_page_9+2263 #start riscv_load_store_rand_instr_stream_65
- sb s7, -1524(a7)
- lw zero, -567(a7)
- auipc s5, 713840
- c.addi t5, -16
- sb a4, -8(a7)
- c.srai s1, 12
- c.srli a5, 2
- lbu s11, -466(a7)
- c.addi s10, 24
- lb a2, -2002(a7)
- auipc a0, 320817
- sw t4, -1935(a7)
- c.slli a4, 13
- sb t0, 1800(a7)
- lbu s0, 3(a7)
- lb s3, 320(a7)
- lb t3, -766(a7)
- lh t1, 1765(a7)
- auipc t4, 117758
- lbu t6, -1730(a7)
- lb s4, -1284(a7)
- lbu t5, 927(a7)
- lui t2, 834018
- lhu s9, -467(a7)
- lbu s11, 738(a7)
- lw s10, -247(a7)
- lb t3, -593(a7)
- sb zero, 1437(a7)
- c.addi s9, 28
- lbu t1, -178(a7)
- auipc s3, 38290
- sb a5, 1176(a7)
- lbu gp, 1472(a7)
- sh ra, -897(a7)
- addi s1, t1, 853
- sb t6, 170(a7)
- c.addi s10, 16
- lb t2, 1542(a7)
- lhu gp, 1779(a7)
- sh s4, 561(a7)
- lh t3, 781(a7)
- lb t3, 1679(a7) #end riscv_load_store_rand_instr_stream_65
- auipc a2, 497299
- srai t1, s0, 26
- c.slli s7, 18
- sub a0, t0, t5
- c.srli s0, 2
- sra a1, zero, s8
- slti a1, s3, 196
- auipc a5, 270955
- mulh a0, t3, a4
- auipc a0, 376150
- c.addi s7, -24
- c.srli a3, 18
- c.lui t1, 14
- auipc s5, 876885
- c.srli a5, 23
- c.srli a1, 17
- auipc s7, 412135
- c.slli a1, 9
- auipc s6, 5210
- c.addi s5, -18
- auipc a0, 257487
- auipc t5, 653900
- c.addi s5, -30
- c.lui s2, 25
- c.srai s0, 12
- c.srai s1, 2
- lui s3, 736367
- c.addi s8, 2
- c.srli a0, 27
- c.srai a4, 8
- and s7, ra, gp
- add a1, s5, s9
- c.srai a4, 1
- c.addi s10, 7
- or t2, s5, t0
- c.slli s6, 29
- c.addi t5, -18
- fence.i
- c.srai a1, 4
- c.srli a3, 19
- c.srli a5, 26
- c.and a0, s0
- auipc t3, 152265
- c.addi t2, -31
- c.addi a1, 25
- auipc t2, 624278
- c.slli s5, 28
- c.slli a6, 28
- beq sp, s0, 5333f
- auipc s0, 819747
- slt a4, sp, a6
- sub s2, s7, a7
- c.sub s0, s0
- lui s10, 104624
- la s11, data_page_8+1167 #start riscv_load_store_rand_instr_stream_29
- sb s5, 46(s11)
- lb s10, 428(s11)
- c.lui s1, 9
- lb s9, 999(s11)
- lb s7, 683(s11)
- lbu t5, 992(s11)
- lbu zero, 260(s11)
- sh a7, -1089(s11)
- srai a3, t3, 0
- sb ra, 27(s11)
- auipc a3, 703150
- sb s9, 367(s11)
- lh a4, 1849(s11)
- sb s10, 1700(s11)
- lb s9, 362(s11)
- c.srai a0, 26
- sb a7, 1796(s11)
- c.andi a0, -19
- c.srli s0, 31
- rem s4, t5, a7
- lui gp, 786240
- lhu t2, 1369(s11)
- lw s0, 385(s11)
- lui s4, 945939
- sb s11, 913(s11)
- lui s8, 853793
- lbu a7, 1358(s11)
- lbu a5, -406(s11) #end riscv_load_store_rand_instr_stream_29
- lui gp, 112295
- c.mv s6, t3
- c.srli a0, 30
- c.slli a3, 15
- c.addi t3, 26
- c.slli s2, 27
- c.addi s3, -21
- c.addi s5, 6
- c.addi s0, -16
- c.bnez a0, 5339f
-5333: auipc a1, 131317
- c.slli a3, 12
- c.xor a4, a0
- auipc s11, 17861
- sub s0, a1, a2
- c.slli gp, 14
-5339: lui zero, 307184
- c.add a1, a3
- c.srai s1, 9
- auipc t6, 754568
- and a3, t3, s0
- c.lui a2, 19
- c.or a2, a2
- c.addi s11, 5
- lui s5, 454852
- auipc zero, 1007352
- c.srai a5, 26
- auipc a3, 439487
- auipc s8, 469339
- andi zero, s2, -902
- c.lui a2, 29
- c.lui t5, 27
- auipc s9, 145447
- c.sub s0, s1
- c.xor a2, a4
- c.addi t1, -9
- sltu t6, tp, s3
- c.addi a0, -19
- lui t1, 1037414
- c.mv s4, t6
- c.lui gp, 28
- lui t3, 968328
- nop
- c.sub a3, a1
- addi t1, s2, 517
- c.addi gp, -18
- c.srli a5, 11
- auipc s4, 254654
- c.lui s0, 28
- auipc t4, 777825
- c.slli a0, 25
- c.addi s9, -4
- mulhsu a4, s6, s9
- auipc a4, 1025193
- c.addi t5, -1
- c.slli a2, 29
- sltiu t6, a2, -304
- slli zero, t0, 27
- c.addi s2, 16
- lui t1, 1032707
- c.lui s10, 25
- c.xor s1, s0
- c.addi t3, -28
- c.addi a7, -20
- c.beqz a4, 5390f
- auipc a7, 567191
- lui t1, 990121
-5390: or s6, tp, t5
- c.addi s0, 10
- c.addi a0, -20
- c.mv gp, tp
- auipc s3, 219421
- c.or a5, a2
- c.addi s1, 4
- bgeu t3, s4, 5408f
- c.lui t4, 9
- c.addi a4, 20
- c.addi a4, -30
- lui t2, 194675
- c.srai a2, 13
- auipc a2, 1036905
- c.li s4, 9
- c.lui a4, 14
- sub a2, s8, s2
- lui s8, 876613
-5408: mulhsu s5, s3, tp
- c.srai a5, 7
- c.addi s6, -2
- slli t1, gp, 27
- srai s0, a4, 1
- lui s6, 715539
- la a3, data_page_19+1288 #start riscv_load_store_rand_instr_stream_32
- mul a4, a4, t5
- c.addi a0, -29
- lbu a0, -519(a3)
- sb s2, -530(a3)
- c.srai a1, 30
- c.srai a0, 25
- c.addi s10, 30
- lui a7, 955161
- sb a1, 799(a3)
- c.addi s9, 13
- auipc t3, 174229
- sw tp, 1712(a3)
- lhu a0, 726(a3)
- slli a2, t3, 15
- auipc s4, 55303
- sh t1, 1330(a3)
- add t6, s8, sp
- c.addi s1, -8
- auipc a4, 786770
- ori a2, sp, -961
- lui zero, 806788
- c.addi a5, -26
- lb t4, 441(a3)
- c.addi t6, -20
- auipc t3, 26776
- c.slli s0, 31
- sb s1, -104(a3)
- lui a6, 1011858
- sb sp, -1043(a3)
- c.addi s7, 18
- lui t1, 600904
- lui s10, 506360
- sltu s0, a2, a6
- sb a1, 347(a3)
- c.li s1, 5
- divu zero, t6, t4
- lui s10, 944380
- c.slli a1, 15
- slli s11, zero, 30
- lbu s4, -1125(a3) #end riscv_load_store_rand_instr_stream_32
- lui a6, 506859
- c.srai a4, 31
- lui s0, 867586
- c.addi a3, -28
- c.and a3, a1
- c.or a4, a3
- c.srai a2, 21
- c.addi gp, -25
- auipc s0, 1007907
- c.slli t1, 1
- c.lui a6, 16
- lui s6, 418377
- c.srli s0, 19
- c.bnez s1, 5439f
- c.addi a2, 27
- c.addi t2, -3
- auipc s5, 152600
- c.lui s4, 23
- sll a3, a0, s10
- mulh s11, s8, a6
- c.addi s2, -16
- lui s3, 634438
- c.srai a2, 25
- slt t5, t1, gp
- rem s10, s4, zero
-5439: c.lui a4, 26
- xor t4, t6, a0
- c.srai a1, 31
- lui t1, 1041849
- div t2, s6, a0
- c.addi t4, -25
- auipc t3, 489540
- c.lui t4, 3
- c.srai s1, 4
- c.lui s9, 3
- c.lui s8, 13
- auipc a6, 498061
- c.and a0, a0
- mulh s0, t0, a4
- slli a2, s1, 3
- c.addi s0, 29
- c.addi s0, -11
- c.and a1, a1
- mul s6, s9, a0
- c.addi a2, 25
- c.addi s3, 7
- auipc s3, 1002815
- c.bnez s1, 5476f
- auipc s4, 318027
- c.srli a3, 5
- c.slli t2, 23
- auipc s10, 563174
- sra t1, a3, s11
- sub a2, t1, a0
- c.srli a0, 2
- auipc s9, 798693
- c.lui s10, 13
- c.slli a3, 4
- auipc s11, 408224
- la t6, data_page_18+1282 #start riscv_load_store_rand_instr_stream_17
- lb gp, -362(t6)
- sra s7, t2, s9
- c.addi t3, -31
- auipc s10, 62509
- c.addi a2, -20
- sb a6, -671(t6)
- slli t3, t6, 5
- lw s2, 2018(t6)
- lbu s8, 554(t6)
- c.slli s7, 27
- mulh s6, tp, gp
- lhu t3, 460(t6)
- c.addi a4, -7
- c.addi s4, 19
- lui s4, 1041916
- lbu a4, -1081(t6)
- sb t5, -777(t6)
- sb t5, 1928(t6)
- c.lui s7, 28
- c.lui s1, 19
- c.or a4, a1
- lb s8, -1121(t6)
- lbu s10, -147(t6)
- lhu s9, 630(t6)
- c.lui s2, 10
- lb a5, 1901(t6)
- lbu a4, 557(t6)
- lhu s3, -776(t6)
- auipc a2, 390098
- sb sp, -789(t6) #end riscv_load_store_rand_instr_stream_17
- c.srai a3, 6
- c.addi gp, -2
- c.addi s10, 21
-5476: auipc a7, 777473
- auipc t6, 956047
- ori s9, a1, 1004
- c.addi s8, 20
- c.srli s1, 2
- c.addi t5, -15
- c.lui t4, 24
- mul s11, sp, a7
- srl a4, zero, t2
- c.addi s8, 5
- sub s3, s4, t3
- nop
- auipc s4, 314242
- c.addi s2, 19
- andi t5, s5, -934
- sltiu s9, t1, 251
- divu s10, s8, t1
- c.or a0, s0
- c.lui s10, 7
- c.addi s9, -14
- c.srli s0, 1
- c.srai a3, 15
- auipc s5, 243733
- auipc s8, 258131
- c.addi s11, 26
- c.slli t1, 28
- lui t5, 802054
- auipc zero, 29498
- c.srli a4, 21
- c.addi gp, -7
- lui t3, 389699
- sltu t2, a1, t0
- c.or a5, a0
- c.slli s10, 15
- bgeu s1, t2, 5515f
- c.addi a0, 26
- c.or a3, a2
- c.addi t4, 10
- c.addi t6, 20
-5515: c.slli s9, 17
- auipc a1, 573006
- lui s0, 949563
- lui s0, 59504
- c.srli s0, 21
- c.slli s4, 1
- c.srli a5, 10
- xori s7, a6, 887
- sub s3, a5, sp
- c.addi a1, -22
- c.lui a6, 25
- c.addi s10, -18
- c.lui a2, 2
- c.srai s1, 14
- slti t2, t0, 693
- auipc t5, 107648
- c.srli a4, 3
- c.addi s4, -2
- remu s4, t1, a7
- c.srai s0, 10
- c.lui s1, 3
- c.addi gp, 6
- c.slli t6, 13
- and a6, a0, t0
- c.addi s10, 31
- c.srli s1, 12
- c.addi gp, -17
- c.addi s7, -30
- lui a4, 120062
- c.addi t6, -3
- lui s4, 959950
- c.slli a5, 15
- c.addi t1, 19
- and s6, t4, a4
- la a6, data_page_12+2330 #start riscv_load_store_rand_instr_stream_15
- lbu a2, 1247(a6)
- c.addi a5, -31
- lhu s5, -288(a6)
- lbu s3, 771(a6)
- sb s3, 1407(a6)
- sh s9, -1304(a6)
- fence.i
- lbu t6, 245(a6)
- lh t6, -204(a6)
- lbu s4, -78(a6)
- c.or a0, a3
- c.srli a5, 17
- auipc s5, 568869
- lbu t1, -171(a6)
- lui a5, 822434
- auipc a0, 674677
- auipc s0, 959320
- c.lui t3, 15
- mul gp, s2, a4
- sb a6, 1560(a6)
- lhu t4, -1178(a6)
- sb s11, 351(a6)
- c.addi a2, 3
- auipc t4, 822590
- c.addi t2, -16
- slli s10, a2, 12
- lbu t5, 744(a6)
- or a3, s6, a5
- lb a3, -599(a6)
- lb s5, 1313(a6)
- divu s8, s11, s0
- lbu t5, -1582(a6)
- lui s6, 337557
- div s5, sp, t4
- sb s3, 1721(a6)
- auipc a5, 871182
- lb a4, 7(a6)
- lbu t5, 1056(a6)
- lb s0, 715(a6)
- divu s0, s2, ra
- lui a4, 848897
- lui a3, 45377
- sb t2, -1659(a6)
- c.lui t6, 16
- c.srai a3, 5
- c.lui s3, 28
- c.addi a0, 8
- lb a0, 1572(a6)
- sb s9, 344(a6)
- remu a1, t6, s11
- auipc s2, 730598
- nop
- lhu t3, -316(a6)
- sb s5, -225(a6)
- sb s7, -1336(a6)
- sb t1, 1289(a6) #end riscv_load_store_rand_instr_stream_15
- c.addi s4, 10
- c.addi a1, -19
- c.addi s9, -1
- c.lui t1, 18
- la s0, sub_2
- c.addi a5, 15
- c.addi a4, 8
- addi s0, s0, -526
- c.addi t1, -23
- c.srli a2, 6
- blt s7, t5, j__main_sub_2_3 #branch to jump instr
- c.addi a3, -31
- c.slli s7, 4
- c.slli a1, 8
- c.addi s11, -11
-j__main_sub_2_3: jalr ra, s0, 526
- xor t4, a0, s6
- c.addi s8, 26
- c.srli a1, 15
- auipc a3, 258425
- c.addi s6, 14
- c.xor a3, a4
- c.srli a0, 1
- c.addi a6, -6
- c.addi t4, -9
- c.addi s1, 16
- xor s11, t5, s11
- c.lui s6, 18
- auipc a5, 66964
- c.sub a2, a0
- slti s2, sp, -653
- auipc s7, 931678
- mulh a2, s5, sp
- beq gp, t0, 5585f
- c.addi s10, -16
- c.addi s10, 24
- auipc t5, 942350
- c.lui s7, 4
- lui t4, 787529
- c.slli s11, 27
- lui s11, 707275
- c.addi a5, -17
- c.lui s1, 28
- c.addi a0, -19
- c.srli a0, 5
- c.addi a3, -29
- c.addi a5, -29
- c.addi a3, -22
-5585: c.slli s10, 17
- c.addi a1, 19
- c.srli s0, 16
- remu s9, tp, s6
- bge a2, zero, 5603f
- auipc s4, 211037
- c.addi a2, 23
- c.addi s9, 14
- mul s6, s7, t3
- c.slli a3, 29
- beq s9, s5, 5598f
- c.srai a3, 20
- auipc a6, 919133
-5598: c.addi s7, 6
- auipc t5, 963808
- c.addi s0, 19
- nop
- slti s3, a0, 181
-5603: remu s3, t5, t0
- c.srai s1, 15
- sltu t1, t3, t0
- sltu t5, ra, s2
- or t1, s4, a6
- c.addi t4, 2
- auipc t5, 445082
- c.srai a2, 11
- lui s2, 426795
- srl s11, a5, t3
- c.addi a2, -11
- c.xor a3, s1
- c.addi a4, 8
- c.addi s0, 16
- slti s8, t2, -903
- c.srli s0, 16
- la s8, data_page_17+1572 #start riscv_load_store_rand_instr_stream_24
- sb s9, 362(s8)
- c.li s10, -27
- lbu s9, 1793(s8)
- or a1, s8, s7
- sb t4, -43(s8)
- c.li t2, 4
- c.addi s5, 31
- xor s7, s11, sp
- auipc t4, 669301
- auipc s4, 679465
- slli a5, a6, 23
- c.addi a2, 24
- ori a5, zero, -511
- remu t5, a3, a1
- sh a6, -960(s8)
- auipc s9, 10545
- sb s10, 1231(s8)
- auipc s4, 211043
- lbu a5, 829(s8)
- sb a0, -1478(s8)
- auipc a2, 786337
- sb a0, -67(s8)
- lb a2, -1505(s8)
- c.srai s0, 2
- mulh t1, s2, s5
- c.lui a7, 3
- c.srli a3, 19
- lh s1, 1214(s8)
- auipc a3, 358009
- nop
- divu t4, s3, s7
- sb a4, 961(s8)
- auipc s3, 344860
- c.addi t5, 20
- lbu a6, 347(s8) #end riscv_load_store_rand_instr_stream_24
- sra a1, t1, s0
- c.lui s11, 30
- c.lui s0, 28
- lui t1, 730833
- c.lui s8, 8
- lui s11, 66787
- auipc gp, 170666
- auipc t1, 840659
- c.srai a5, 7
- c.li s3, 13
- lui t4, 671924
- c.lui t6, 19
- lui a3, 614894
- auipc t6, 928607
- lui t2, 545579
- c.addi t3, 20
- c.srli a2, 29
- c.slli t5, 22
- c.srai a2, 23
- c.addi s1, 1
- c.and s0, a2
- c.addi t1, 30
- auipc s10, 350885
- add s9, a0, a4
- c.lui a1, 19
- auipc s1, 371749
- auipc a4, 674376
- c.slli t4, 31
- c.slli gp, 2
- ori a5, t6, 359
- c.slli t1, 1
- c.addi s7, 1
- and s0, sp, s0
- c.addi gp, 12
- c.srai a3, 17
- auipc t4, 588827
- c.addi a7, -8
- c.addi s8, -25
- auipc a4, 332898
- auipc a0, 145691
- fence
- auipc s10, 434817
- c.addi a6, -32
- c.addi s1, 30
- auipc t6, 649745
- c.xor a3, s1
- c.addi t3, -30
- c.srai a5, 15
- c.addi s3, -5
- c.lui s2, 23
- c.addi t3, -13
- c.lui s6, 10
- lui a6, 337913
- c.slli s5, 8
- auipc s3, 120491
- c.srli s1, 20
- auipc a0, 246660
- c.addi t5, 11
- auipc s5, 279602
- c.lui a1, 20
- c.slli a1, 31
- auipc t3, 729718
- c.addi gp, 6
- c.addi t1, -15
- c.sub a4, a1
- c.srli a0, 10
- c.addi s7, -25
- c.addi t1, -18
- c.srai a1, 7
- c.slli s4, 28
- andi t5, a5, 106
- lui t6, 762178
- bgeu t3, s6, 5710f
- c.srli a5, 16
- c.srli a0, 4
- c.lui s9, 22
- lui s5, 311876
- lui s1, 84674
- c.srli s1, 10
- andi zero, a0, -427
- auipc s7, 269466
- c.addi t4, 31
- nop
- andi t5, a5, 999
- c.andi a5, -18
- c.addi t1, -4
- c.srli a5, 3
- c.addi t4, -29
- la a1, data_page_11+2074 #start riscv_load_store_rand_instr_stream_59
- lb s10, -1322(a1)
- lui s9, 767422
- c.srai a3, 27
- and s1, s11, a1
- c.srli a5, 6
- lb t6, -1227(a1)
- lhu t2, -1480(a1)
- sb a5, 877(a1)
- fence
- lui s5, 80513
- lbu t2, -41(a1)
- rem t2, t1, s3
- auipc a7, 239104
- c.addi a5, -3
- auipc s8, 167409
- sb s9, 1892(a1)
- auipc s4, 114386
- auipc s8, 764381
- lh a7, 400(a1)
- c.lui a2, 4
- lb s0, 1501(a1)
- sb s4, 1458(a1)
- auipc s5, 724406
- lhu t5, -1526(a1)
- c.srli a3, 11
- lhu a5, -1064(a1)
- c.addi t4, 15
- sub a3, a1, s3
- auipc t5, 779984
- xor s5, a4, s9
- lb a5, 945(a1)
- lbu zero, 1607(a1)
- c.addi s0, 17
- sltu t3, t0, s5
- lb a7, -1097(a1)
- lbu s0, 1493(a1)
- c.addi a6, 3
- auipc a6, 650770
- lui s0, 227171
- c.addi s4, -1
- sb a0, -1085(a1) #end riscv_load_store_rand_instr_stream_59
- c.lui a1, 29
- c.srai a0, 25
- c.and a0, a4
-5710: c.addi a1, 16
- auipc s3, 1013246
- auipc s10, 952274
- auipc t1, 840655
- c.srai s0, 6
- auipc a2, 43269
- auipc s4, 990482
- c.addi a7, -14
- c.slli s8, 7
- c.addi a4, -2
- divu t1, s5, s8
- lui a4, 167303
- mul t6, s10, t2
- c.srai a2, 18
- c.addi t4, -7
- lui t3, 671375
- fence
- auipc s11, 809159
- lui s3, 31936
- c.srai a0, 23
- c.addi a6, -8
- c.addi s1, -21
- mulhsu t5, s0, ra
- c.srli s1, 23
- c.addi s5, 24
- c.addi gp, -21
- c.srli s0, 30
- c.slli s3, 23
- c.slli a1, 18
- c.addi s10, 25
- slli t4, s2, 9
- c.srai a4, 25
- slt s8, t5, a6
- nop
- or s9, s8, t3
- lui s1, 661577
- c.addi t3, 17
- beq a1, zero, 5756f
- auipc s5, 217787
- lui a0, 367270
- sub s10, s7, s10
- lui s4, 1000211
- c.addi s0, 30
- lui s0, 183158
- la s3, data_page_9+2026 #start riscv_load_store_rand_instr_stream_40
- lbu s8, 1346(s3)
- c.addi s5, -28
- sb a1, -1620(s3)
- c.srai s1, 10
- c.addi s7, -29
- fence
- fence
- lbu t2, -264(s3)
- lhu a7, -1098(s3)
- lb a1, 1547(s3)
- lb t3, 449(s3)
- auipc t5, 662946
- sb s1, 1195(s3)
- sb a3, 289(s3)
- c.srli a3, 18
- lbu s4, -1757(s3)
- auipc t1, 840751
- auipc t4, 389335
- lbu t1, -1439(s3)
- auipc t4, 187582
- auipc t1, 553096
- div gp, a3, s11
- c.mv t4, s10
- sb a2, -783(s3)
- c.slli s11, 23
- c.lui s4, 29
- c.sub s0, a1
- lhu a1, 758(s3)
- xori gp, s5, -191
- lh s11, -1756(s3)
- sb s9, -611(s3)
- sh a1, -742(s3) #end riscv_load_store_rand_instr_stream_40
- lui a1, 362042
- c.addi t3, 19
-5756: c.and s1, a0
- c.addi a4, 30
- c.srai s1, 18
- auipc s9, 965541
- c.srai a0, 28
- fence.i
- c.addi t5, -11
- andi t2, t2, 579
- add s11, a3, s4
- lui s4, 330188
- c.bnez s0, 5779f
- auipc s1, 800655
- or gp, a3, a5
- c.addi gp, 7
- slti a6, s1, 302
- c.addi a4, -20
- c.srli a0, 16
- c.addi a4, -3
- bltu gp, a2, 5794f
- div s7, s2, t4
- bge t6, s10, 5783f
- c.slli a5, 12
- c.addi a3, -30
-5779: sra s9, s6, a3
- c.addi s11, 2
- sltu t2, s4, s3
- auipc s3, 477866
-5783: c.slli t4, 22
- c.addi a6, 21
- c.beqz a2, 5791f
- c.addi s9, 8
- xori a0, t5, 101
- c.addi a5, -2
- auipc s9, 425454
- lui s8, 643372
-5791: c.srli s0, 28
- c.addi t6, -26
- c.addi s5, -10
-5794: c.lui s11, 5
- or a5, s7, s11
- c.srli a3, 7
- lui s4, 25390
- c.addi a3, -22
- la t1, data_page_2+1854 #start riscv_load_store_rand_instr_stream_26
- c.slli t2, 31
- sb a1, 946(t1)
- c.slli s0, 24
- c.addi t3, -12
- c.addi s2, 4
- c.srli a5, 12
- lbu s8, 750(t1)
- c.addi s6, 5
- sb a3, -1297(t1)
- add t6, t3, s5
- lbu s2, -263(t1)
- lh zero, 812(t1)
- sub t3, zero, gp
- lui a1, 409392
- lb a7, -517(t1)
- sb s10, 1323(t1)
- c.addi t3, 5
- lbu s2, 529(t1)
- sb s2, -243(t1)
- lb a1, 1665(t1)
- add a7, a2, zero
- lui a5, 167586
- fence
- lb s9, 1329(t1)
- lbu a0, -1059(t1)
- sb t0, 233(t1)
- lhu a7, -1230(t1)
- c.lui a6, 23
- sb t5, 132(t1)
- c.addi s7, 19
- c.addi s5, -16
- lbu t4, 533(t1)
- c.addi s8, 13
- lui zero, 561182
- mulhsu s1, a3, tp
- lbu a7, -1107(t1)
- lbu s4, 1908(t1)
- lb s4, -5(t1)
- lbu s0, 2029(t1)
- c.srli s0, 31
- sb a3, 645(t1)
- c.li a2, -22
- c.lui gp, 7
- lb s5, -87(t1)
- lbu t3, -1568(t1)
- sh s1, -552(t1)
- sb s8, -1473(t1)
- lh s9, -360(t1)
- ori t5, a3, -293
- lb t4, 1336(t1) #end riscv_load_store_rand_instr_stream_26
- c.addi s10, -5
- auipc a0, 810265
- c.slli a5, 16
- c.li s7, 1
- c.bnez a4, 5805f
- c.addi s7, 26
-5805: lui a0, 939771
- c.addi t6, 31
- auipc t3, 406221
- lui a5, 177812
- lui s8, 981863
- c.addi gp, -13
- auipc t4, 452180
- c.andi a2, -28
- c.add a5, a0
- c.addi s2, 3
- c.lui t2, 25
- c.addi s0, -18
- c.srai a5, 14
- lui s2, 812202
- lui s8, 483486
- auipc a1, 419804
- c.addi s5, 9
- la a0, data_page_18+1989 #start riscv_load_store_rand_instr_stream_21
- c.slli s10, 14
- mul a4, t6, t0
- lui gp, 76207
- lbu a6, -1715(a0)
- srl a3, t0, t3
- c.addi s0, 20
- lb a6, -850(a0)
- lb a1, -1760(a0)
- lb s3, -309(a0)
- sb t3, -1946(a0)
- lhu a5, 1557(a0)
- c.slli a4, 14
- auipc s8, 920092
- lh a7, 311(a0)
- c.addi t5, 8
- lbu t6, 1200(a0)
- lh a4, 869(a0)
- auipc s10, 122501
- lb s8, 196(a0)
- lui s9, 721785
- c.addi t1, 13
- mulhu s0, t6, a4
- sb t1, -1071(a0)
- c.addi s9, 28
- lui s1, 982955
- fence
- lh a3, 697(a0)
- xori s4, s4, -340
- lb s9, 1850(a0)
- auipc s6, 709197
- c.addi s10, -17
- c.srai s1, 27
- sb a7, -302(a0)
- c.addi gp, 4
- lb s3, 826(a0)
- c.srli a3, 20
- c.lui a2, 4
- lh a5, 597(a0)
- c.addi t6, 16
- sb a0, 1911(a0)
- lbu s9, -1987(a0)
- c.addi t5, -7
- lh s11, 25(a0)
- srli gp, a4, 29
- lui a1, 870066
- sb a6, -420(a0)
- auipc a7, 756681
- lb s10, 244(a0)
- sb a0, 457(a0)
- lbu s3, -1612(a0)
- lbu a3, 961(a0) #end riscv_load_store_rand_instr_stream_21
- beq ra, tp, 5841f
- auipc t4, 471453
- c.srli s0, 11
- sra s11, a7, gp
- c.lui s2, 26
- lui s8, 497376
- c.addi t4, -20
- c.slli a7, 2
- c.slli a3, 12
- c.slli t1, 8
- lui a0, 814999
- c.srai a0, 10
- slt zero, s5, a4
- c.addi t4, -9
- lui s9, 212593
- c.srai a2, 31
- slt gp, t0, s8
- blt a3, t2, 5841f
- lui t1, 261873
-5841: c.srli a4, 4
- c.lui s8, 11
- c.addi s11, -4
- lui a4, 702999
- lui s3, 191860
- lui a2, 826480
- auipc s4, 915644
- auipc s3, 549994
- auipc s5, 458374
- c.addi s4, -30
- c.slli t3, 23
- lui s9, 647471
- auipc a5, 650168
- c.srli s1, 13
- c.addi t5, 21
- auipc a3, 561378
- c.addi s6, -7
- c.sub a5, s1
- mulh a3, a2, ra
- lui s3, 309145
- auipc s9, 480706
- sub s9, a2, s6
- c.addi a5, -17
- c.addi s2, 24
- auipc s10, 612945
- slti a0, a4, -872
- c.addi a6, 7
- c.srai a1, 23
- c.addi a1, -5
- c.addi s6, 17
- auipc a4, 330597
- auipc t4, 74354
- lui s7, 584591
- c.srai s1, 23
- c.srai a5, 26
- c.lui a7, 16
- auipc s1, 1022375
- auipc t1, 391773
- lui t4, 342087
- lui zero, 57046
- c.srli a2, 26
- c.addi s7, 10
- la s8, data_page_3+1834 #start riscv_load_store_rand_instr_stream_5
- lh t5, -412(s8)
- sb t1, 1052(s8)
- c.addi s1, 10
- sh s11, 1594(s8)
- lb a3, 1682(s8)
- remu s11, t3, s0
- c.lui s0, 25
- lhu s6, -1712(s8)
- lbu s11, 896(s8)
- lh a2, -676(s8)
- c.slli a7, 4
- c.srai a4, 24
- sb a6, 1697(s8)
- auipc a3, 620417
- lhu s6, -742(s8)
- lbu a1, 1607(s8)
- c.addi a6, 31
- c.nop
- sb a0, 869(s8)
- c.addi s10, -10
- auipc t5, 495807
- c.addi a4, -27
- lbu t3, 428(s8)
- sw gp, 1006(s8)
- lb s7, 1326(s8)
- c.addi t3, 28
- lbu s7, -1523(s8)
- sb s4, 1130(s8)
- srl a2, tp, s1
- auipc t2, 509289
- lb t6, 1899(s8)
- c.lui gp, 16
- auipc s1, 627362
- sh a3, -506(s8)
- sb tp, -385(s8)
- lh t6, 486(s8)
- lb t5, 501(s8) #end riscv_load_store_rand_instr_stream_5
- lui s7, 151835
- c.addi s7, -10
- c.addi a4, 5
- c.mv s2, t3
- c.addi a3, -3
-5888: fence
- slti t6, t6, -887
- mulhsu t1, tp, t6
- c.lui a4, 11
- auipc a6, 213263
- c.addi a4, 25
- c.sub a3, a0
- lui s8, 381917
- c.lui s8, 14
- mulhsu t1, s9, s2
- c.slli t1, 26
- bge a2, sp, 5901f
- c.srai a0, 28
-5901: c.lui s8, 17
- auipc a6, 468042
- sll a7, s10, a2
- srai t6, a4, 9
- c.addi s5, -19
- c.addi t4, 6
- c.addi gp, 15
- lui a3, 757358
- c.and a1, s1
- c.addi t2, -26
- lui s11, 987299
- c.lui t5, 14
- c.srli a5, 29
- c.slli s4, 17
- c.and a5, a2
- c.lui s1, 2
- lui gp, 210423
- auipc t1, 9379
- remu s10, t4, s11
- auipc s10, 855532
- lui s11, 72716
- auipc t3, 698568
- c.addi s5, -30
- c.srli a4, 29
- auipc s4, 612073
- nop
- auipc t1, 592327
- c.srli a4, 19
- c.addi a7, -12
- c.addi a5, 20
- c.addi t4, -11
- lui s6, 102983
- sll s11, a2, s0
- c.lui t3, 10
- c.addi s7, -30
- lui a1, 78852
- c.addi s9, -28
- sub s1, t3, s2
- c.srli a5, 9
- divu t1, s6, gp
- div a4, sp, sp
- c.addi gp, 27
- c.addi t6, -31
- c.mv t5, t6
- c.beqz a1, 5947f
- lui t4, 747707
-5947: c.xor a0, a5
- auipc a7, 219579
- srl a0, s9, s8
- c.addi t6, 31
- c.addi s5, -14
- mulh s1, s0, s0
- lui s2, 563521
- c.addi s7, -7
- c.slli t4, 11
- c.addi s0, 27
- c.addi s9, -3
- c.srai a4, 11
- c.addi gp, 31
- xor a5, s5, a2
- c.bnez a0, 5965f
- c.addi t2, 6
- c.mv s1, s5
- c.slli s7, 7
-5965: lui s4, 555740
- c.andi a4, -7
- c.lui t1, 7
- c.sub s0, a3
- c.srli a4, 10
- c.add a3, a2
- lui s3, 405666
- c.srai s1, 4
- c.srli a4, 4
- c.addi a1, -30
- lui s0, 918418
- c.addi a4, -28
- sra s10, a7, s6
- add a5, s11, a6
- c.sub a4, a2
- div s9, t3, a0
- lui s4, 1017366
- add t3, a1, s2
- c.srli a3, 5
- c.addi s7, 28
- c.addi t2, -17
- c.addi a7, 5
- auipc t6, 923611
- c.beqz a3, 6004f
- lui a7, 814659
- c.addi t5, 1
- div a7, a5, zero
- add zero, s11, s2
- la t4, data_page_8+2089 #start riscv_load_store_rand_instr_stream_43
- mulh a7, s5, s9
- lh t5, 29(t4)
- lhu a6, 1047(t4)
- sb s10, -1659(t4)
- lh s2, 589(t4)
- sb t2, -1075(t4)
- lui s2, 968660
- lui t2, 874617
- c.addi s4, -22
- mulhu s1, s2, s3
- nop
- lui s7, 636578
- sb s9, -762(t4)
- c.sub a3, a4
- c.addi s0, 8
- lb s7, 979(t4)
- c.slli t5, 30
- lb t1, 1042(t4)
- lh a7, 567(t4)
- lui zero, 132591
- auipc s3, 643553
- lui s2, 354559
- lb a0, 172(t4)
- divu s4, t2, a1
- auipc s7, 4127
- lb a1, 1667(t4)
- lui s9, 286921
- xori t6, a2, -654
- c.slli a3, 4
- lbu a7, 154(t4)
- mulhsu s9, zero, s8
- lb s3, -314(t4)
- sh tp, -1887(t4)
- c.srai a3, 12
- c.addi s10, 24
- sb a7, -357(t4)
- c.lui s5, 16
- c.slli s11, 3
- c.addi a1, -32
- sb a2, -1407(t4)
- lb s7, 1256(t4)
- lbu t1, -512(t4)
- lui a1, 430464
- lbu a2, -1105(t4)
- auipc s3, 942294
- c.addi gp, -14
- sh a6, -2043(t4)
- lb a1, -1955(t4)
- lb s7, 589(t4)
- lbu a2, -1076(t4)
- lui t1, 880230
- c.addi gp, -23
- sb t3, -277(t4)
- lbu a7, -1739(t4)
- lh a3, -1687(t4)
- lb s10, -1948(t4)
- sb s5, 84(t4)
- lh s2, -423(t4)
- auipc a1, 674691
- lb zero, -834(t4) #end riscv_load_store_rand_instr_stream_43
- c.srli a0, 15
- sltiu a0, s0, -95
- lui s0, 774614
- srli s2, t4, 7
- addi t1, s7, 325
- add s10, a5, ra
- c.slli t4, 24
- xor a4, s11, a2
- lui t4, 56405
- c.lui gp, 25
- c.addi s4, -32
-6004: c.slli a7, 13
- c.srai a3, 22
- c.slli a0, 4
- auipc s3, 897699
- lui a0, 85458
- divu t3, t3, tp
- lui a3, 460354
- bne t5, a6, 6020f
- c.addi a5, -4
- c.srai a3, 18
- lui s7, 575426
- c.slli s6, 10
- c.sub a4, a4
- c.srli a3, 24
- lui a2, 713058
- div zero, a1, s3
-6020: c.addi s2, -22
- lui s1, 336786
- sra t1, t6, s0
- c.addi t3, -9
- c.xor a5, s1
- lui s1, 384743
- c.addi a6, 6
- c.slli s0, 16
- c.addi t3, 24
- ori s5, s3, -241
- auipc a4, 897622
- c.addi a1, -30
- c.addi a3, 5
- c.addi t5, 12
- lui zero, 648550
- srli t4, t5, 19
- la s2, data_page_4+1758 #start riscv_load_store_rand_instr_stream_33
- lb zero, -81(s2)
- c.lui a0, 13
- lbu a7, -281(s2)
- lb s9, -1221(s2)
- lhu zero, 618(s2)
- c.srai a0, 15
- sw t4, 134(s2)
- lb s9, 582(s2)
- sh s5, 362(s2)
- lh t5, 442(s2)
- c.lui s9, 13
- c.addi s5, 18
- sb s6, -113(s2)
- sb tp, -182(s2)
- lbu s11, 1539(s2)
- sb t6, 1872(s2)
- lb t5, 1591(s2)
- lh a1, 926(s2)
- sb a1, 252(s2)
- auipc s8, 677348
- lui a4, 148047
- c.sub a2, a0
- xor t6, t6, s8
- c.srai a1, 23
- lb a1, 1538(s2)
- lbu a6, 211(s2)
- c.li s9, 9
- c.lui gp, 22
- c.srli a5, 9
- lbu t3, 1666(s2)
- c.slli s3, 24
- sb a4, 952(s2)
- lbu t4, -175(s2)
- c.addi a7, -27
- sb tp, -1279(s2)
- c.lui t1, 2
- lhu s8, -256(s2)
- sw ra, 630(s2)
- c.lui t5, 18
- sh a5, 826(s2)
- lb a4, 567(s2) #end riscv_load_store_rand_instr_stream_33
- c.addi s9, 12
- auipc s8, 890975
- srai s11, t4, 8
- c.addi a7, 21
- lui a2, 974554
- c.addi t5, -6
- slli a4, s9, 13
- c.srli a3, 20
- and s4, t5, t3
- lui t3, 903160
- c.srai a5, 19
- c.addi a7, -28
- slli a1, s5, 18
- auipc s8, 645900
- c.xor s0, s1
- c.srai a4, 9
- lui s8, 768480
- mul s0, tp, s11
- lui s9, 598218
- mul a4, a5, s5
- c.addi t6, -19
- c.addi s6, 2
- c.slli s11, 27
- c.nop
- c.srli a5, 27
- c.addi s5, 8
- c.addi t4, 27
- auipc zero, 508603
- c.xor s0, a5
- c.lui s3, 13
- c.addi s5, -6
- c.lui a7, 25
- ori a2, gp, -443
- c.slli a6, 19
- srli t6, a3, 6
- c.srai a0, 2
- c.addi t6, 29
- c.addi a0, -26
- xori a4, zero, 264
- c.addi a2, 26
- c.addi s1, -5
- lui t5, 808417
- c.addi a1, -16
- auipc a2, 852965
- ori gp, zero, -304
- c.srli a0, 21
- auipc t6, 685089
- c.lui a2, 30
- lui s10, 744503
- lui s6, 898879
- c.addi gp, 11
- auipc s3, 73157
- mulhsu t2, s5, a0
- c.addi s5, -18
- nop
- c.slli a1, 12
- c.lui gp, 13
- mulhu s5, a0, s1
- c.srli a1, 20
- c.lui t3, 29
- c.srai a0, 18
- c.srli s1, 1
- andi gp, s9, 198
- c.lui t5, 13
- c.addi s4, -9
- c.srli a0, 24
- c.addi s9, 15
- c.lui t3, 12
- c.srli a1, 24
- auipc s5, 726446
- c.and a1, a3
- remu a2, s11, s4
- c.andi a0, -2
- c.srli a4, 1
- c.addi t5, -2
- auipc s7, 570581
- c.addi a7, 15
- auipc t1, 903463
- c.slli s7, 31
- lui t4, 237561
- c.lui t5, 4
- c.li s1, 23
- mul s10, s8, tp
- c.addi a5, -11
- c.addi s9, -18
- c.andi s0, -20
- c.srai a0, 22
- auipc s9, 549229
- lui s3, 775720
- lui s1, 211642
- c.addi t6, -10
- c.xor a1, s0
- c.li s11, -30
- c.srli a5, 15
- addi t1, tp, -81
- c.srai a4, 27
- auipc a1, 150357
- sra gp, s9, a2
- divu s10, a3, s10
- c.addi t2, 23
- c.srli s1, 4
- c.slli t2, 8
- c.lui s7, 17
- la s1, data_page_14+2749 #start riscv_load_store_rand_instr_stream_54
- lui a5, 560312
- c.addi s6, 6
- c.addi t3, -12
- auipc a2, 630373
- rem a7, t2, a1
- c.addi t4, -9
- c.slli t3, 10
- lbu zero, -868(s1)
- lbu s3, -270(s1)
- lhu t1, 505(s1)
- lb gp, -1395(s1)
- c.srli s0, 20
- c.srli a2, 13
- sb s6, -1964(s1)
- lb t2, -881(s1)
- lbu s5, 856(s1)
- c.srai s0, 1
- and s6, s8, a4
- lbu a4, 1132(s1)
- c.lui gp, 10
- lbu a1, 1044(s1)
- c.addi t3, 22
- lb s9, 614(s1)
- sb a0, 237(s1)
- sb t3, -561(s1)
- sb t6, -1188(s1)
- lbu t3, 230(s1)
- c.mv s11, s1
- lbu gp, 665(s1)
- lbu a3, -1332(s1)
- lui s5, 194324
- sra s10, t1, s0
- c.addi a1, 11
- sb tp, -1128(s1)
- c.addi s11, 14
- lb a2, 245(s1)
- lb a1, -80(s1)
- sh s4, 1189(s1)
- lb t4, 778(s1)
- nop
- lbu a2, -1976(s1)
- sw a3, -717(s1)
- lb s11, 1220(s1)
- auipc zero, 960622
- sh a3, 1003(s1)
- auipc a3, 996092
- auipc a2, 740825
- c.addi a2, 2
- sb s7, -782(s1)
- c.and a3, s0
- c.addi s3, -5
- lui t1, 741759
- lb a7, -8(s1)
- lbu a0, -1739(s1)
- c.addi s7, -13
- c.srli a1, 31
- lui s11, 1027909
- rem a1, tp, t5
- lbu s7, 1052(s1) #end riscv_load_store_rand_instr_stream_54
- lui t2, 346099
- c.or a4, s1
- c.addi t3, 25
- nop
- lui gp, 215211
- c.addi s10, -3
- lui a3, 288166
- c.beqz s0, 6158f
- c.srli s0, 29
- lui a2, 697203
- lui s3, 449582
- c.addi a0, 3
- xori s6, a0, -647
- lui a4, 812365
- c.srli a5, 16
- c.srai s1, 27
- c.bnez a5, 6170f
- c.addi a2, -12
- c.srli a2, 18
-6158: lui t4, 587724
- c.addi s11, -30
- auipc s8, 830759
- c.addi s2, -2
- mulhsu s10, gp, a6
- auipc t3, 611486
- c.srai s0, 23
- c.addi s9, 16
- auipc s11, 648359
- c.srai a4, 31
- c.srai a2, 26
- slli s10, sp, 10
-6170: auipc s4, 352247
- ori a1, s0, -565
- c.slli s2, 16
- lui s0, 91260
- sll s2, a4, s3
- c.addi a2, -3
- auipc t4, 930413
- c.slli s6, 24
- auipc t3, 918857
- c.andi a4, -2
- auipc a5, 521883
- c.addi s1, 31
- auipc a4, 929475
- add s5, s11, t0
- c.addi a1, 28
- c.addi s2, 27
- c.slli a7, 22
- c.srli s0, 17
- c.addi a7, -14
- c.addi s8, 11
- auipc s4, 374343
- c.srai a2, 4
- mulhsu s7, s7, t5
- c.addi s2, -23
- c.addi t3, 23
- c.bnez a4, 6206f
- c.lui s11, 8
- c.addi a3, 23
- slt s9, a6, a1
- auipc s3, 223168
- srl t2, ra, s0
- lui t1, 189886
- c.addi s11, 24
- c.addi s10, 8
- c.addi gp, -20
- auipc s0, 719847
-6206: c.beqz a2, 6207f
-6207: c.addi s8, -15
- ori s11, ra, 631
- lui t2, 915472
- c.addi s2, 29
- c.addi a5, 13
- lui t5, 392494
- c.addi t4, 12
- c.addi t5, 19
- c.addi s10, -32
- auipc a2, 390536
- lui s0, 64511
- lui a4, 665591
- bne gp, s3, 6233f
- c.addi s3, -28
- c.srli a4, 28
- c.addi t2, 9
- c.addi t3, -27
- c.addi t6, -22
- fence
- auipc s4, 914059
- slli a6, a3, 0
- c.addi t4, -1
- c.addi a7, -10
- c.addi s6, 28
- srl s3, a6, s1
- lui t2, 756220
-6233: remu s2, t6, ra
- c.srli a3, 12
- auipc a3, 25933
- la s1, data_page_15+1360 #start riscv_load_store_rand_instr_stream_8
- lh t6, -102(s1)
- slli gp, a3, 16
- c.addi a2, -5
- c.slli s4, 21
- c.srai a2, 26
- c.srli a4, 20
- c.srli a0, 31
- sb s10, 2030(s1)
- lui s5, 480856
- lui t4, 786976
- c.srli a0, 17
- auipc s8, 957605
- c.and s0, a2
- sh s11, -436(s1)
- lb a5, -1213(s1)
- sb s2, 1559(s1)
- lh s10, 444(s1)
- sb a3, 12(s1)
- lui a5, 464908
- lbu t6, 949(s1)
- c.srli a5, 7
- sh s10, 252(s1)
- c.addi t5, 26
- auipc s10, 36453
- c.srli s0, 29
- c.addi s4, -31
- srl s0, a5, t6
- lui t4, 658143
- lui a4, 780050
- lbu t1, -143(s1)
- c.addi a2, -31
- sll a6, a5, s4
- lb a7, -94(s1)
- lb a2, 1854(s1)
- lh s3, 156(s1)
- c.addi s6, -30
- lbu t6, -145(s1)
- lbu s8, -93(s1)
- lhu a2, -10(s1) #end riscv_load_store_rand_instr_stream_8
- auipc s0, 117747
- lui s3, 759405
- c.addi s10, -29
- c.lui t2, 31
- c.srli a4, 13
- c.addi s7, 3
- c.addi t4, -1
- lui s9, 499270
- lui t1, 207199
- c.addi gp, -25
- c.srli a2, 10
- divu a1, t4, s11
- c.nop
- auipc s4, 357441
- c.addi s7, -26
- c.slli a7, 26
- c.addi t6, -20
- c.li t1, 5
- c.addi s9, 13
- auipc a6, 699841
- auipc t4, 10917
- c.add a5, a2
- auipc t2, 443800
- c.sub a5, a2
- bltu t0, s1, 6277f
- c.addi t1, 27
- c.srli a5, 7
- lui a3, 461561
- c.addi s11, -24
- sltu t4, s1, s3
- c.srli a4, 31
- lui a3, 829387
- c.srai s0, 10
- c.srai a2, 11
- c.addi s8, 26
- c.lui a3, 12
- c.addi s6, 2
- auipc s3, 1013522
- c.srli a0, 3
- auipc s1, 960682
- auipc s0, 755759
-6277: lui zero, 902527
- c.srli a1, 17
- rem s7, s5, ra
- c.addi s9, -25
- c.slli s9, 24
- c.addi t4, -31
- xori a4, s3, 541
- blt s3, s6, 6288f
- c.addi t2, -28
- bge a5, zero, 6298f
- c.addi t5, -20
-6288: c.addi s0, -10
- auipc s3, 782574
- sll a7, t3, s0
- c.addi s1, -14
- c.addi a7, 1
- c.addi a3, -9
- c.addi t5, -10
- c.addi s11, -1
- divu a6, s11, s4
- div a4, a0, zero
-6298: c.addi s9, 7
- c.addi a2, 18
- c.addi s10, 28
- auipc a4, 789256
- srli s2, s4, 14
- c.srli s0, 5
- auipc s3, 270620
- lui s10, 52244
- c.addi a6, 31
- c.slli a4, 5
- c.addi s9, -19
- rem t4, s2, a2
- lui a4, 77149
- c.slli a7, 17
- c.and a5, a2
- c.addi s3, -26
- c.slli a5, 9
- lui s11, 826012
- c.addi a4, 6
- lui s9, 706772
- c.slli s7, 19
- c.slli s1, 13
- sll s9, s7, s4
- c.srai s1, 27
- c.srli a0, 2
- auipc s3, 855020
- c.addi s5, -32
- lui zero, 265981
- c.slli t4, 27
- srli t5, ra, 12
- c.addi s11, 9
- c.srai a5, 10
- srli s3, s8, 19
- and t3, s7, s10
- auipc s8, 795375
- c.lui s7, 3
- c.and a4, a0
- blt t0, s10, 6338f
- c.addi s4, 20
- c.slli t3, 26
-6338: auipc t1, 918674
- c.srli s1, 4
- c.srli a3, 23
- lui zero, 777047
- c.addi s10, -1
- c.beqz a3, 6351f
- lui s0, 75992
- c.srli a1, 29
- c.srli a0, 2
- auipc t5, 776612
- srli s9, t4, 27
- c.lui a4, 13
- c.slli s4, 21
-6351: auipc s5, 237098
- c.lui s3, 23
- c.addi s4, 17
- la a7, data_page_4+2287 #start riscv_load_store_rand_instr_stream_36
- lui s4, 410336
- lui a5, 563446
- lh s7, -917(a7)
- c.li s10, -23
- c.addi a2, 13
- lui s6, 460563
- c.addi s6, -16
- c.slli s6, 15
- c.addi t2, 18
- fence.i
- auipc s5, 389991
- c.add a4, s1
- auipc s5, 354794
- sb a0, -1840(a7)
- lh a4, -969(a7)
- c.addi s8, 18
- fence
- c.and s1, s1
- c.slli s5, 26
- lbu t3, -1362(a7)
- lb a5, -2015(a7)
- sb a6, 432(a7)
- c.or a4, a4
- lbu s11, 430(a7)
- lb s7, 1567(a7)
- lb a5, 78(a7)
- c.addi s10, -16
- c.lui a5, 30
- c.lui s11, 17
- lbu a6, -1214(a7)
- lbu s9, -1954(a7)
- lb s9, -822(a7)
- lui s7, 948747
- c.srli a4, 14
- c.addi t5, 17
- lui t1, 177905
- c.addi gp, 19
- lbu t1, 1135(a7)
- lbu s10, -1401(a7)
- c.mv s3, gp
- lbu s10, 1794(a7)
- lb t1, -1125(a7)
- auipc t4, 605809
- lb s8, 795(a7)
- sh t4, 1047(a7) #end riscv_load_store_rand_instr_stream_36
- c.addi a5, 21
- lui gp, 278634
- c.lui t1, 27
- c.lui t5, 23
- lui gp, 126356
- c.srli a4, 11
- c.lui s4, 17
- slt s1, s0, t5
- c.addi a4, -30
- sra a6, zero, a5
- c.srli a2, 7
- c.addi t4, 19
- sltu a7, s0, ra
- lui s4, 243425
- bltu gp, t2, 6385f
- lui s11, 188299
- c.addi t4, -25
- auipc s9, 539523
- c.addi a4, 14
- lui a4, 918573
- slli a1, s2, 12
- c.srai a1, 23
- c.addi t3, 2
- c.addi t6, -30
- auipc a0, 963886
- c.addi s7, 12
- srli a6, t3, 4
- lui a2, 143805
- c.addi t5, 29
- lui a0, 612640
- auipc s9, 656308
-6385: ori s4, gp, -59
- lui s11, 671180
- c.addi s3, -3
- sra a6, a4, s6
- c.addi a5, 10
- c.slli s0, 11
- c.slli t3, 5
- c.addi a3, 20
- c.addi s7, 20
- c.addi a0, -1
- auipc s4, 504249
- c.addi s7, -32
- c.srli a4, 28
- c.addi t2, -22
- c.lui t6, 10
- c.addi a2, -23
- sll s0, s8, ra
- c.addi a4, 9
- c.srai a1, 8
- c.addi a2, 25
- c.srai s0, 13
- srl a5, s1, a1
- addi a7, s8, 340
- lui s0, 916839
- lui s1, 387801
- fence.i
- c.srli a0, 12
- c.slli t5, 9
- auipc a2, 221369
- c.srai a1, 13
- lui s9, 206789
- c.and a3, a2
- auipc a4, 112845
- auipc a7, 401433
- auipc a5, 413878
- c.slli a3, 11
- sltiu t1, s11, 219
- auipc gp, 553781
- c.lui a6, 10
- lui t3, 65924
- c.srli a1, 11
- c.addi gp, 25
- c.addi s6, -8
- c.addi s10, -27
- srli zero, s3, 13
- c.addi a7, -24
- c.addi a2, 10
- c.slli s4, 23
- c.lui s9, 14
- add s3, s9, tp
- lui s2, 347828
- c.lui t4, 24
- c.lui t1, 10
- c.addi a3, -26
- divu a5, s3, s2
- c.slli s10, 1
- nop
- c.srai a2, 20
- c.srai a0, 18
- mulhu a5, ra, t4
- lui s3, 490290
- c.addi a3, 22
- c.addi s2, -15
- c.and a4, a2
- c.srli a2, 28
- c.addi s0, -3
- lui t6, 989791
- c.srli a2, 21
- c.lui t6, 6
- c.srai a4, 15
- c.addi s4, 11
- auipc a5, 948832
- xori s1, s1, 358
- div a0, s5, a7
- c.addi a7, -12
- blt s7, t5, 6470f
- lui a4, 125563
- fence
- lui s9, 562727
- lui t5, 965326
- bge a3, a7, 6470f
- c.srai a1, 30
- c.addi s5, -21
- auipc s10, 443833
- c.sub a4, a1
-6470: c.addi s7, -7
- c.srai a5, 25
- c.srai a5, 10
- c.slli s4, 2
- auipc s8, 878981
- c.srai s0, 30
- bltu a1, t4, 6487f
- auipc gp, 751552
- lui t5, 509728
- c.srai s0, 13
- lui s9, 476439
- c.andi a4, -1
- lui a5, 727366
- c.lui s2, 23
- c.addi s11, 7
- c.xor a2, a1
- c.srli s0, 6
-6487: or s7, s6, gp
- c.lui a1, 26
- divu t3, t5, sp
- c.addi s0, -13
- c.srli a2, 10
- auipc a2, 694835
- c.srai a4, 5
- auipc s1, 347525
- auipc s10, 61218
- c.lui s8, 4
- divu t6, s2, t6
- c.addi t3, 4
- auipc a3, 594521
- c.slli a2, 3
- auipc s6, 219875
- auipc s6, 1034821
- auipc a3, 645720
- auipc t1, 314746
- c.slli s1, 16
- auipc s11, 752181
- auipc s6, 828692
- c.addi t4, 20
- c.addi s2, 14
- lui zero, 808619
- c.addi a5, 12
- c.addi s6, 27
- slli zero, t6, 8
- auipc s2, 787267
- c.and a1, a2
- c.addi s7, 17
- c.slli a2, 19
- auipc t2, 422411
- c.slli s1, 9
- lui s7, 893668
- c.addi s0, 31
- c.lui s6, 6
- c.lui s8, 1
- c.srli a5, 14
- auipc a4, 399760
- srl a0, t1, t0
- auipc s11, 381110
- c.addi t5, -20
- sltu t2, t6, s10
- ori s3, s0, -904
- div s0, s7, a6
- xori a7, s11, 994
- mulhu a0, s11, a7
- c.addi t6, -19
- c.addi s0, -16
- c.srai a1, 27
- c.srli a4, 30
- bgeu s9, s11, 6554f
- auipc t4, 519384
- auipc zero, 259606
- xori s8, tp, 707
- auipc gp, 615253
- auipc a5, 754678
- c.addi s3, -3
- c.addi t5, 27
- lui a1, 193002
- c.srai a4, 18
- c.addi s0, 2
- sra zero, s7, s4
- auipc a4, 556123
- c.slli s0, 21
- c.slli s10, 22
- c.addi t5, 30
-6554: c.addi a6, 3
- bltu t3, tp, 6558f
- auipc a7, 619025
- auipc s3, 930885
-6558: c.slli s9, 27
- auipc s5, 515770
- c.srai a1, 30
- c.addi a3, 6
- c.addi a4, -12
- c.addi t5, 21
- c.addi gp, -22
- lui a3, 393990
- c.lui t5, 22
- auipc s6, 749999
- c.slli s5, 22
- c.addi s10, -4
- c.nop
- c.addi s0, 5
- c.addi a0, -26
- c.addi gp, 3
- auipc a1, 814881
- srl s0, t6, t3
- auipc a3, 837850
- lui a1, 463851
- c.addi s4, -29
- lui a1, 71125
- c.addi s11, -1
- c.addi s2, 15
- auipc s4, 727713
- c.add s0, s1
- lui s0, 927011
- c.slli s0, 11
- c.addi a2, -9
- lui s10, 651736
- c.slli a7, 2
- auipc a0, 68537
- auipc s9, 883371
- c.addi s9, 3
- c.srli a2, 15
- auipc s3, 104888
- lui s9, 9050
- c.mv t6, a2
- lui zero, 595255
- div t6, s11, zero
- c.srli a5, 19
- c.addi a2, -27
- c.slli a7, 18
- c.lui s3, 30
- div a6, a5, a7
- c.andi s1, 26
- fence
- sltu s6, s1, a2
- sub s5, s6, a3
- bgeu t6, t4, 6609f
- c.addi t5, 13
-6609: auipc a6, 765252
- c.srli a4, 30
- divu a0, t6, s4
- c.addi s10, -12
- mulh a5, s4, t3
- c.addi s8, -5
- c.and a5, s1
- bne a1, t2, 6633f
- c.lui s1, 1
- c.srai a0, 23
- c.srli a3, 17
- c.addi a5, 23
- sltu zero, t6, t1
- c.addi s1, 22
- lui s8, 780771
- c.srai a3, 9
- c.addi s2, 4
- srai gp, a1, 11
- remu a5, a2, s5
- c.srli s0, 12
- fence
- lui t3, 325857
- c.slli s8, 17
- c.srai a4, 15
-6633: c.addi a2, 6
- c.srli a5, 17
- c.srai a5, 24
- auipc s9, 162595
- c.addi t2, 23
- lui s0, 526464
- c.slli t1, 28
- c.srli a3, 12
- c.addi t4, 20
- mul t1, a2, s4
- auipc a3, 345515
- sll t4, s1, a3
- lui s10, 271386
- remu a3, s0, s10
- c.andi a5, 24
- c.slli s9, 14
- auipc zero, 169251
- c.li t1, 0
- lui s6, 409164
- c.addi s9, -16
- lui a7, 68534
- c.addi a2, 11
- c.li s9, 22
- c.beqz s0, 6670f
- c.xor a1, a2
- c.srli a1, 26
- c.srai a4, 11
- c.and a2, s1
- c.srli a2, 7
- auipc s0, 354797
- c.srai a3, 16
- lui t1, 495745
- c.addi a1, 25
- lui a5, 545164
- bgeu t5, s8, 6675f
- bge gp, s8, 6678f
- mulh t5, t5, t4
-6670: c.addi s4, 2
- c.srli a3, 28
- c.slli t2, 28
- c.nop
- c.addi a5, 2
-6675: auipc a5, 664441
- c.srli a3, 8
- c.addi s2, -27
-6678: c.addi a6, -13
- c.slli t3, 23
- auipc s11, 511041
- auipc s2, 705944
- mulhsu t4, s10, s0
- auipc s11, 207047
- fence
- c.addi s4, 24
- c.addi s7, -11
- lui t5, 401823
- c.addi a4, -1
- c.srli a5, 8
- div s10, ra, a1
- c.lui s8, 17
- lui s7, 728956
- lui t3, 116194
- sub s3, t3, sp
- c.lui s2, 29
- mul s9, s5, t1
- c.slli s5, 9
- c.addi t1, 13
- la s4, data_page_19+1981 #start riscv_load_store_rand_instr_stream_57
- lb a2, 1853(s4)
- c.lui s6, 13
- lui s11, 616694
- c.lui s10, 21
- lui s1, 697315
- auipc zero, 855873
- c.addi a7, 21
- c.addi s5, -28
- c.lui s9, 19
- lui s6, 267524
- lb t2, -1946(s4)
- andi t4, s2, 820
- c.addi s11, 13
- lui s8, 255685
- sub t1, t0, zero
- sb a7, 222(s4)
- lui s8, 571896
- auipc zero, 391782
- c.srai s1, 26
- auipc s6, 582603
- c.addi a4, -24
- lb a6, -1105(s4)
- nop
- c.lui a7, 22
- lb gp, 1374(s4)
- auipc t5, 656594
- addi s7, sp, 687
- lw a1, -673(s4)
- lui s2, 734286
- c.addi s0, -2
- lbu s11, 1241(s4)
- addi s7, tp, -960
- c.srli a5, 25
- lb s8, -1880(s4)
- lbu a7, 1461(s4)
- sb t1, 1728(s4)
- c.slli s11, 3
- c.addi s8, -9
- auipc a4, 281091
- c.srai a2, 1
- lb a5, 1050(s4) #end riscv_load_store_rand_instr_stream_57
- c.slli a1, 22
- lui s5, 750051
- lui t3, 667394
- c.srai s1, 27
- nop
- auipc s9, 145590
- c.srli s1, 13
- c.addi a6, 10
- bne s5, s0, 6718f
- c.addi s5, -12
- auipc s0, 981512
- c.lui a7, 8
- andi s7, t1, -820
- bgeu t2, s5, 6725f
- c.addi s10, -8
- c.srli a3, 20
- c.srli a1, 24
- c.addi t4, -17
- c.lui s7, 20
-6718: c.srli a3, 2
- lui s0, 43313
- c.srai a5, 22
- auipc s2, 698113
- lui s1, 328023
- auipc s2, 90995
- c.andi s0, 8
-6725: c.addi a4, -4
- c.slli t2, 1
- c.srai a0, 6
- sltiu s10, s10, 227
- c.slli s3, 11
- add s6, a3, s4
- c.srai a0, 5
- auipc s0, 992855
- lui s10, 945794
- auipc s3, 429783
- c.addi s0, -16
- c.addi s8, -16
- c.addi a1, -23
- c.srai a2, 11
- c.srli a3, 27
- c.addi s0, -11
- c.addi s5, 11
- c.mv t4, t0
- sltu s11, s2, s4
- c.addi t1, -31
- c.addi s0, -19
- auipc s1, 277246
- slti t1, s9, -180
- auipc t6, 510911
- auipc t1, 384561
- c.beqz s1, 6751f
-6751: auipc gp, 496610
- auipc a2, 1006210
- lui zero, 46450
- slt t4, s0, gp
- lui a0, 934581
- c.addi t2, 3
- mul s7, s5, gp
- sll s1, gp, gp
- and s3, s5, a3
- lui s7, 795203
- auipc a4, 886156
- auipc t1, 921354
- c.slli s1, 3
- c.addi s5, -11
- c.addi a5, 6
- lui t1, 619901
- bltu t5, a2, 6774f
- sltiu t4, a2, 838
- c.srli a0, 3
- c.lui a1, 9
- auipc a2, 109991
- slt s9, gp, s2
- c.srai s0, 26
-6774: c.srai s1, 16
- sub zero, a4, a0
- sltu a3, t6, t1
- lui a2, 413123
- lui s0, 407415
- c.addi t1, 8
- mulh s1, s6, s8
- c.srai a0, 24
- c.addi s11, -30
- lui a1, 963883
- lui s3, 708306
- c.addi a7, -20
- c.addi t6, 23
- c.srli a2, 24
- fence
- c.addi a7, 1
- c.srli a0, 8
- lui t2, 51333
- auipc s5, 780314
- c.srai s0, 9
- c.addi a4, 9
- auipc s9, 232642
- c.lui s11, 21
- auipc s8, 654592
- lui s1, 631525
- sltiu zero, s8, -613
- c.addi s0, 8
- c.lui a5, 27
- c.slli a7, 23
- auipc gp, 568692
- c.srli s0, 6
- auipc t5, 769667
- c.addi a7, -5
- c.slli t2, 29
- c.mv a0, s3
- blt s11, t0, 6812f
- c.addi s5, 11
- lui a2, 88060
-6812: c.lui a7, 30
- c.slli s7, 15
- sltu t4, s9, s10
- c.nop
- c.srai s0, 13
- auipc s9, 848226
- andi s9, s5, 43
- c.lui s1, 2
- slli s3, zero, 9
- lui s8, 476540
- auipc a0, 370801
- c.or a5, s0
- and a7, ra, s8
- c.addi s11, 21
- auipc s1, 250742
- auipc s2, 56165
- c.srli a5, 7
- c.addi a0, 6
- auipc t4, 708790
- fence.i
- c.add a1, a5
- c.srli s1, 17
- c.lui s9, 13
- lui a5, 786705
- lui t6, 386647
- bgeu a4, a0, 6841f
- c.addi a2, 24
- c.addi s0, 13
- c.and a4, a4
-6841: c.slli s8, 20
- c.lui a3, 30
- c.or s1, a2
- c.lui t2, 9
- c.srli a1, 19
- lui t1, 350127
- c.lui s10, 4
- c.lui gp, 15
- c.addi a1, -32
- c.addi s11, 3
- c.lui s11, 26
- addi t2, s0, -566
- auipc s9, 719525
- slli s1, t5, 19
- c.or a5, a2
- lui s2, 953895
- auipc t2, 496041
- c.srli s1, 26
- auipc a4, 999116
- c.srli a3, 26
- c.li s10, -12
- remu gp, s4, t1
- divu s11, s9, s10
- add a6, s7, a6
- fence.i
- c.slli s4, 16
- auipc t5, 916819
- c.slli s8, 4
- c.addi t2, -23
- lui zero, 733504
- c.srli s1, 26
- c.srai a0, 21
- c.srai a0, 2
- c.addi s10, 17
- auipc a6, 70677
- blt t5, t5, 6893f
- c.addi s8, 21
- c.addi s8, -23
- la t2, data_page_5+2156 #start riscv_load_store_rand_instr_stream_42
- c.addi s6, -14
- c.addi a4, -4
- lh s10, -1828(t2)
- lui t1, 490007
- lb a2, -1811(t2)
- sb ra, 1129(t2)
- lb s8, -1883(t2)
- sh s9, 1508(t2)
- c.addi t5, 25
- lb s2, 1693(t2)
- c.addi s3, -18
- lb t3, 1211(t2)
- lui a3, 1044530
- lb s3, -625(t2)
- lw s3, 688(t2)
- lui a5, 220733
- slt a6, a4, a4
- lh a3, -616(t2)
- c.addi s8, -9
- c.slli a6, 12
- lb s9, -1607(t2)
- sb t4, -146(t2)
- auipc t5, 676926
- lh s11, 290(t2)
- sb s1, 190(t2)
- lw a1, 728(t2)
- lb a6, 391(t2)
- c.lui t1, 23
- c.srai a1, 24
- sh t5, 282(t2)
- sb a2, 560(t2)
- sb s2, -909(t2)
- lb t1, 357(t2)
- c.slli a3, 27
- lhu s4, -1124(t2)
- c.addi t4, 19
- lbu t5, -1459(t2)
- c.mv s0, a3
- sw t2, 1196(t2)
- sb a0, 682(t2)
- mulhsu s3, t6, s3
- sh s9, 114(t2)
- lui s3, 8626
- sb a7, -1738(t2)
- lb s5, -950(t2) #end riscv_load_store_rand_instr_stream_42
- auipc a6, 239478
- c.addi s6, 5
- c.or s0, a0
- srli t2, a0, 14
- srai zero, s3, 22
- c.addi a3, -2
- lui a3, 361689
- div t4, s3, a7
- c.srai a2, 29
- lui t4, 673941
- mulhsu a3, a7, s1
- sltiu a5, s6, -374
- c.addi s4, -14
- lui s4, 855682
-6893: c.beqz s0, 6909f
- slti t6, a6, -497
- c.addi t2, 2
- c.srli a4, 19
- and a5, s8, s10
- mulhu s3, s7, s6
- c.addi a0, -10
- c.lui t3, 17
- lui a3, 556874
- mulhu a6, a4, a7
- c.and a4, a4
- c.srli s1, 30
- c.slli s11, 10
- c.slli s6, 13
- c.addi t5, -14
- xori gp, a3, -827
-6909: c.addi s8, -31
- lui t1, 140682
- c.addi s2, 9
- c.lui s10, 6
- and s0, s10, t2
- bltu s11, s7, 6927f
- c.srai s0, 27
- c.srli a1, 21
- auipc t1, 314973
- c.lui gp, 4
- c.addi a3, 7
- auipc s11, 204743
- c.addi s11, 1
- slli s3, t3, 20
- or a5, s0, sp
- lui a4, 14004
- remu s4, s0, s5
- c.addi t2, 10
-6927: c.addi t6, 22
- auipc a2, 156291
- lui zero, 2766
- c.srai a3, 19
- fence
- c.addi gp, -26
- c.addi gp, -4
- c.addi s3, 18
- lui zero, 712721
- c.addi a4, 24
- lui t2, 539046
- auipc s11, 758209
- auipc a6, 61953
- c.mv a5, ra
- c.srli a2, 7
- auipc a1, 350503
- c.addi a7, 4
- c.or a3, a3
- c.sub a5, a1
- c.srai a1, 14
- c.mv s2, t1
- c.addi a1, -31
- auipc s0, 785830
- auipc t6, 511908
- c.srli a1, 30
- c.lui s1, 23
- sltiu t6, zero, -876
- lui a3, 485980
- c.addi a2, -15
- c.srli s1, 26
- bne gp, a1, 6960f
- c.slli s4, 22
- c.slli s9, 15
-6960: auipc s8, 569155
- sll s3, t2, s0
- auipc t6, 290377
- c.addi s0, 18
- auipc a3, 1027553
- sll t4, a4, sp
- c.srli s0, 24
- c.addi s2, 4
- auipc t3, 568089
- c.lui s6, 22
- lui s9, 182889
- remu t2, t4, s11
- c.addi s6, 28
- c.addi t4, -26
- nop
- lui s3, 648922
- c.addi a3, 15
- lui a1, 641513
- lui t6, 648216
- c.srli a4, 25
- c.srai a5, 17
- c.addi t2, -16
- mulhu s9, a2, s0
- c.addi a5, -9
- auipc t2, 859625
- c.srli a5, 2
- ori a5, t6, -471
- c.srai s0, 8
- c.srai a0, 21
- bne a6, s4, 6997f
- sub a7, s11, s2
- slti s9, s5, 616
- c.add s1, a0
- c.addi t1, 22
- and t1, a2, sp
- lui a2, 727256
- auipc s0, 660299
-6997: c.srai a0, 3
- remu a2, sp, t1
- c.addi s2, 18
- c.slli t4, 12
- c.srai a1, 18
- mulh t4, s2, s10
- lui s9, 248523
- c.addi s9, -10
- c.addi a4, 26
- c.srai a4, 28
- c.addi s7, 28
- c.addi t3, 26
- la s11, data_page_11+2699 #start riscv_load_store_rand_instr_stream_10
- sb a6, -1753(s11)
- auipc a2, 329432
- c.addi a4, 21
- sh a7, -183(s11)
- andi t4, s8, 643
- c.addi t6, 14
- sb ra, 1351(s11)
- c.srai s1, 1
- auipc s0, 349524
- c.lui s10, 4
- srai s10, ra, 1
- c.addi t1, 19
- sb t5, -157(s11)
- divu s6, a3, a2
- lhu s1, 1267(s11)
- fence.i
- lb a3, -784(s11)
- lui zero, 729020
- sh ra, 1137(s11)
- sw a0, -1499(s11)
- sb s2, -733(s11)
- c.addi t3, -5
- lui s10, 78802
- c.slli s2, 15
- sb s10, -265(s11)
- auipc s2, 189427
- sra t5, s7, ra
- c.li t4, 24
- auipc t3, 591440
- sw t0, 617(s11)
- sb s10, -688(s11)
- sltu s9, a6, s4
- lbu t4, -805(s11)
- sb a4, -1123(s11)
- sh a7, 275(s11)
- c.addi s1, -29
- lbu a4, -1272(s11)
- lb a0, -1784(s11)
- lbu s1, 75(s11)
- sb t4, -830(s11)
- c.li s8, 11
- c.addi a5, -6
- c.addi s3, 29
- c.lui t5, 23
- c.srai a5, 13
- sh ra, -1561(s11) #end riscv_load_store_rand_instr_stream_10
- c.addi t3, -2
- auipc a7, 758696
- c.slli s7, 3
- c.lui s10, 9
- c.addi a3, -24
- c.slli gp, 24
- c.addi a5, 4
- sltiu s4, s10, 849
- c.srli a0, 8
- xori s10, zero, -532
- c.slli a4, 3
- c.slli s4, 13
- c.addi s0, -32
- c.addi s11, -30
- remu a3, a1, sp
- c.beqz s1, 7031f
- c.srai a2, 3
- lui gp, 100307
- auipc t6, 42229
- c.srai s0, 22
- c.slli t3, 22
- c.slli a2, 8
-7031: auipc t4, 1037428
- lui s3, 570292
- c.addi s0, 31
- c.lui s0, 20
- c.add a3, a0
- lui a0, 851689
- c.srai a5, 2
- c.addi t1, -6
- c.addi s6, 10
- auipc s0, 161487
- lui t1, 998134
- c.srai s1, 19
- auipc a5, 1029193
- c.lui a2, 7
- lui s0, 292016
- lui s7, 280008
- auipc gp, 494215
- c.addi t4, -16
- xor a6, a6, a3
- c.addi s4, 9
- c.lui s4, 24
- auipc t5, 267098
- c.srli a1, 2
- c.srli s1, 24
- c.srli a5, 25
- c.addi t3, 28
- c.addi s10, -17
- auipc t6, 800865
- lui s0, 532183
- c.addi a3, 27
- c.srli s1, 18
-test_done:
- li gp, 1
- ecall
-sub_1: bge s4, t1, sub_1_stack_p
-sub_1_stack_p: addi sp, sp, -32
- sw ra, 4(sp)
- c.addi t1, 4
- srai t6, a3, 9
- sw t0, 8(sp)
- auipc s8, 599512
- c.addi a4, 21
- c.lui t6, 23
- c.and a5, s0
- mulh a2, t4, t4
- c.srli a0, 26
- c.addi t5, 11
- c.addi s5, -15
- c.lui t6, 28
- c.addi s7, -11
- c.li a6, 8
- fence
- c.addi a0, -30
- c.addi t1, -14
- c.addi s4, 21
- nop
- c.addi t4, 29
- srli s8, a1, 1
- c.addi a6, 24
- c.srli s1, 30
- c.slli a6, 11
- auipc s10, 392995
- c.slli a1, 16
- c.srai s1, 8
- c.lui s7, 8
- c.addi a1, 8
- c.srli a1, 27
- c.addi s4, -20
- nop
- lui s11, 430337
- c.addi a5, 14
- c.xor a4, a5
- c.addi s7, -17
- lui t1, 200003
- remu s7, zero, a2
- auipc s3, 181959
- c.addi s10, -25
- auipc s6, 58417
- mulh t3, s4, t5
- auipc s10, 526315
- c.addi s9, -31
- c.srai a1, 26
- bltu t2, s4, 41f
-41: c.lui a2, 12
- c.srai a3, 16
- c.srai a3, 22
- c.addi s9, 6
- c.srli a4, 9
- c.srli a0, 7
- c.addi a2, 18
- c.srli a3, 16
- c.addi a0, -1
- c.or s1, a1
- add a4, gp, t6
- c.srai s1, 8
- c.addi gp, 7
- srai a4, s11, 27
- c.addi t4, 10
- c.addi a4, -12
- lui t3, 557311
- c.xor a5, a2
- auipc s2, 840535
- srl s5, a4, s8
- srli s8, t0, 29
- c.srli s1, 10
- c.beqz a1, 67f
- ori a5, s2, 901
- c.addi s4, 1
- c.slli s2, 19
-67: auipc a4, 297044
- c.lui a2, 12
- lui t4, 249957
- c.lui s9, 26
- c.srai s0, 31
- c.lui a1, 14
- c.and a1, a5
- c.slli a4, 1
- c.srli a4, 4
- c.lui s4, 4
- lui a0, 332598
- c.add s0, a4
- xor s6, s1, ra
- lui s8, 572853
- auipc t3, 515534
- auipc a2, 8152
- lw ra, 4(sp)
- lw t0, 8(sp)
- addi sp, sp, 32
- and zero, s1, s0
-95: ret
-sub_3: bge a4, s7, sub_3_stack_p
- c.addi gp, 8
-sub_3_stack_p: addi sp, sp, -8
- sw ra, 4(sp)
- sw t0, 8(sp)
- c.addi a1, -22
- srai t5, a0, 4
- c.lui t2, 27
- c.li s7, 30
- auipc s9, 101509
- c.sub s1, a2
- auipc s2, 231216
- c.addi s1, 22
- lui s1, 575378
- ori s10, a3, -15
- c.lui s3, 11
- auipc t5, 1041768
- la t2, data_page_0+1379 #start riscv_load_store_rand_instr_stream_1
- lb t6, 1622(t2)
- sb a7, 1328(t2)
- c.addi a0, -5
- auipc s8, 328032
- and t5, a4, s5
- ori s11, t6, -718
- c.addi s4, -6
- sb a7, 1990(t2)
- lb s4, 1124(t2)
- c.addi s0, 3
- lb a6, -46(t2)
- lbu t1, 935(t2)
- lh zero, -1253(t2)
- sh s6, 877(t2)
- lb s7, -1374(t2)
- c.srai a2, 28
- lb s3, -1144(t2)
- lbu t5, -12(t2)
- lb a3, 128(t2)
- c.addi s8, -9
- sw sp, 1645(t2)
- lui t4, 696624
- sw ra, 773(t2)
- sb s8, -778(t2)
- lbu zero, 1627(t2)
- lbu a3, -190(t2)
- lb a1, -371(t2)
- lb s11, -950(t2)
- lb s6, 1823(t2)
- lw t6, 81(t2)
- mul zero, s2, s11
- sub gp, s9, s11
- c.srai a4, 1
- c.srai a4, 24
- lui s9, 83037
- lh gp, -723(t2)
- c.lui s1, 25
- sh a5, -1019(t2)
- lbu s1, 1033(t2)
- lb s9, 1102(t2)
- lbu gp, -84(t2)
- c.addi a7, -3
- lb s1, -77(t2) #end riscv_load_store_rand_instr_stream_1
- ori a4, tp, -246
- blt a2, a3, j_sub_3_sub_5_6 #branch to jump instr
- c.andi s0, -28
- c.slli s4, 21
- c.addi a6, 8
- c.srai a5, 2
- lui t4, 951737
- lui a6, 820046
- auipc s4, 334962
- lui s4, 143866
- add s0, a1, s1
- c.srai a3, 26
-j_sub_3_sub_5_6: jal ra, sub_5
- c.srli s0, 11
- c.addi s4, 6
- c.addi s7, 8
- auipc a5, 645482
- c.addi s5, -29
- sltu t2, sp, a5
- divu a6, t5, s4
- auipc s8, 526093
- c.addi a5, 19
- auipc s7, 381776
- c.addi s1, -23
- bltu zero, a7, 37f
- lui s2, 1004920
- lui a2, 48561
- lui t4, 633592
- lui s6, 732041
- c.lui gp, 25
- c.lui a0, 9
- c.addi s6, 4
- c.lui a6, 17
- auipc a3, 746543
- auipc s2, 656075
- c.lui s8, 15
- c.addi s11, -22
- auipc a1, 155999
- c.addi a4, 9
-37: lui t3, 969968
- c.srli s1, 3
- c.srai s0, 26
- c.srli a2, 6
- c.lui t5, 1
- c.slli s5, 12
- lui s5, 587403
- auipc s2, 99719
- c.addi a7, 18
- fence.i
- c.slli a0, 14
- c.addi a4, 9
- c.srli a3, 2
- c.addi a5, -20
- c.or a3, a2
- auipc s10, 72271
- sra a5, a0, s10
- c.addi s9, 28
- lui t6, 901922
- c.srli s0, 11
- c.srli a3, 4
- lui s10, 906039
- c.srai a0, 9
- bltu zero, s2, 79f
- lui a6, 355663
- c.addi t3, 24
- c.addi a4, 18
- beq s0, s9, 70f
- lui s0, 831429
- c.srai s1, 12
- auipc a6, 406575
- andi s9, a7, 725
- c.addi s3, 28
-70: c.srai a5, 24
- lui s8, 584434
- c.srai a3, 13
- la a4, data_page_19+1880 #start riscv_load_store_rand_instr_stream_5
- sh sp, 1858(a4)
- lb a5, 1180(a4)
- lui s8, 250105
- lui s9, 360161
- c.addi s10, 9
- auipc zero, 760437
- c.addi s6, 3
- lbu t5, -27(a4)
- lbu s8, 593(a4)
- c.addi s10, -3
- lb a1, -1467(a4)
- sb t1, -283(a4)
- c.addi s0, -13
- lbu t4, -1215(a4)
- lb s11, -1475(a4)
- slti s0, t0, 1009
- lb a6, 445(a4)
- sb s10, -1519(a4)
- sb s10, -1325(a4)
- sh s0, 176(a4)
- auipc s10, 322745
- lb a6, 425(a4)
- sra s1, gp, a2
- c.addi s6, 8
- lh a7, 236(a4)
- lb a0, -1638(a4)
- sh s1, -848(a4)
- lh s4, -1154(a4)
- c.srli s0, 22
- lbu t4, -76(a4)
- c.srai s1, 14
- sb a1, -265(a4)
- lui s5, 2893
- lui s10, 551903
- sb s6, 1673(a4)
- sb s9, -1272(a4) #end riscv_load_store_rand_instr_stream_5
- sra gp, gp, a4
- c.addi s2, -15
- c.slli a3, 11
- c.addi s0, 31
- c.addi s3, 5
- auipc a4, 220373
-79: c.slli t2, 12
- c.lui s2, 31
- lui zero, 1012934
- c.addi s5, -21
- c.addi a6, -22
- c.li s3, 17
- mul a6, s2, a4
- c.srli a1, 3
- lui t6, 405270
- xor s10, s8, s11
- auipc t3, 488855
- c.addi s8, 12
- c.andi a3, 25
- c.addi s7, 6
- c.addi s11, -25
- bne t0, a6, 97f
- c.slli a7, 5
- c.addi t3, 17
-97: auipc t6, 245455
- c.slli s2, 26
- c.lui a2, 10
- c.addi s8, -5
- c.addi s7, 6
- auipc a2, 43698
- auipc t4, 260786
- c.addi s7, -20
- lui s3, 865718
- sltu a4, s5, s9
- mulhu s4, s8, t1
- and t1, a3, zero
- auipc t3, 754564
- c.addi a7, -31
- lui a1, 281010
- c.lui s6, 4
- lui a1, 293452
- c.addi s2, -10
- c.slli a5, 30
- lui a1, 556719
- c.addi s9, -16
- c.srli a0, 12
- c.addi s3, -28
- auipc t4, 928387
- c.srli s1, 8
- xor a0, a6, a1
- c.lui a1, 5
- c.sub a0, a0
- c.add a4, a4
- c.addi a5, -10
- bltu gp, s3, 141f
- c.addi a2, -11
- remu a5, t1, s9
- slti s7, s6, -955
- slli s1, t0, 22
- slt s8, a3, s5
- c.li t5, 10
- auipc t5, 874042
- c.slli s4, 25
- c.lui a1, 19
- lui s1, 804289
- auipc t4, 725054
- c.sub a2, s1
- lui t4, 470429
-141: c.addi t3, 26
- c.srai s0, 1
- c.lui s2, 14
- remu t3, t4, s4
- c.addi t1, 17
- lui t3, 104081
- c.addi t6, 1
- c.srai a5, 20
- c.beqz a0, 154f
- or s6, t4, s0
- c.lui a6, 5
- sra a1, ra, a5
- c.addi a7, -12
-154: c.srai s0, 24
- addi s10, t2, 388
- bgeu t4, t6, 171f
- c.addi gp, 2
- la t4, data_page_15+1572 #start riscv_load_store_rand_instr_stream_6
- c.lui s9, 28
- c.addi a5, 10
- fence
- lhu s4, 1990(t4)
- lbu a5, 546(t4)
- c.slli s3, 28
- lb t2, 719(t4)
- lb s0, -161(t4)
- sh t3, -32(t4)
- lb t5, -201(t4)
- auipc s6, 734144
- ori t6, s3, -644
- lhu zero, -758(t4)
- c.and s1, a5
- lb a3, -305(t4)
- c.lui a3, 13
- lui s5, 918336
- lb t5, -513(t4)
- slli s9, s0, 20
- sb s6, -1009(t4) #end riscv_load_store_rand_instr_stream_6
- c.addi s10, -24
- lui zero, 287927
- c.nop
- bltu a5, t3, 175f
- c.addi s7, -4
- c.lui t3, 29
- lui a6, 923072
- c.addi a4, 25
- auipc s3, 328394
- c.slli a2, 11
- c.addi t4, -29
- c.sub a0, a2
- c.addi gp, 26
-171: c.srli a4, 26
- c.addi s2, 15
- c.lui a6, 21
- c.bnez a0, 190f
-175: auipc a1, 262661
- la s5, data_page_13+1761 #start riscv_load_store_rand_instr_stream_3
- sb t3, -1544(s5)
- lbu a5, -1287(s5)
- lbu a7, 1496(s5)
- lbu s0, -1474(s5)
- lb t5, 533(s5)
- sb a1, 390(s5)
- c.addi a2, -5
- lb t6, -623(s5)
- c.slli a7, 19
- sb t1, 869(s5)
- c.slli s9, 6
- lhu gp, -1539(s5)
- lui s7, 717549
- lbu a5, 850(s5)
- lb a7, -70(s5)
- srai t4, s3, 11
- c.addi a6, -30
- auipc t2, 494813
- lhu s3, 1943(s5)
- lh s1, -823(s5)
- auipc a5, 991481
- or t6, s1, a4
- lb a5, -234(s5)
- lb gp, 1514(s5)
- lb s1, 889(s5)
- sh a5, 1549(s5)
- sb a5, -619(s5)
- lb s7, 1528(s5)
- xori s10, a1, -419
- sb a0, -887(s5)
- c.addi s6, 7
- sb s11, -824(s5)
- lb s7, -91(s5) #end riscv_load_store_rand_instr_stream_3
- c.srli a5, 23
- c.srai s0, 25
- c.srli s0, 7
- c.srli a2, 24
- c.addi s11, -5
- c.addi t6, 4
- c.addi t2, 22
- c.addi t4, 16
- slti s6, s10, -273
- c.addi gp, -26
- c.addi s8, 29
- auipc t4, 964108
- slli s9, zero, 1
- lui a0, 278493
-190: lui s8, 383759
- c.srli a4, 17
- c.addi t4, 10
- auipc s4, 662058
- fence
- c.xor s1, s0
- lui s11, 361583
- fence.i
- auipc a7, 364570
- auipc s7, 233272
- c.lui t1, 9
- lui t5, 672259
- c.addi s11, -27
- c.srai a0, 7
- c.addi gp, -5
- c.li t6, -16
- c.nop
- auipc s0, 519828
- c.and a3, a2
- c.addi t3, -14
- c.mv a4, s8
- c.addi s3, 25
- c.addi a1, 25
- and s1, t1, s8
- c.addi a3, -13
- sltu a3, s8, t4
- c.slli gp, 30
- c.addi s9, 4
- c.lui t3, 4
- auipc t1, 739270
- c.addi s6, -19
- c.addi s1, 20
- auipc s3, 731421
- c.slli s5, 21
- lui gp, 523605
- lui a0, 756905
- c.addi s8, 13
- c.lui t6, 6
- divu s10, a7, sp
- c.srai a2, 13
- c.addi t3, -13
- c.addi a1, -17
- lui s3, 681602
- auipc s8, 329123
- c.li s11, 4
- lui s1, 771795
- c.addi a0, -4
- c.addi t2, 22
- c.srli a4, 26
- auipc s10, 131571
- la a1, sub_4
- c.addi s1, 18
- addi a1, a1, 315
- auipc a0, 555967
- c.and s0, a0
-j_sub_3_sub_4_5: jalr ra, a1, -315
- slt s7, t3, a4
- auipc a7, 775849
- c.addi t4, 6
- bgeu t3, a4, 240f
- auipc t3, 519968
- c.addi t2, 11
- or s7, a5, a5
-240: c.srai a2, 17
- c.slli t4, 3
- c.lui s10, 1
- lui a7, 797985
- c.srli a2, 30
- c.srai a2, 5
- auipc t6, 227102
- c.lui s2, 31
- lui s11, 688608
- c.addi s4, -27
- c.andi a4, -16
- lui a4, 33670
- c.slli s7, 18
- c.addi a1, 1
- c.addi t1, 5
- lui s7, 736706
- c.addi s7, -29
- c.srli a3, 10
- c.addi s7, -8
- c.slli s7, 30
- bltu t0, s10, 264f
- lui s1, 232064
- c.or a5, a0
- c.addi s5, -14
-264: c.lui t4, 14
- c.addi s8, 9
- c.addi t5, -3
- c.srli s0, 28
- c.addi s7, -21
- lui a7, 164039
- c.lui a0, 12
- c.srai a3, 20
- c.addi t4, 25
- c.srai a1, 27
- c.srli s1, 10
- c.slli s7, 31
- c.addi t6, -20
- c.slli a1, 8
- c.addi t4, 24
- slti s11, s10, 412
- c.lui a3, 2
- c.addi s10, -10
- bltu a7, a6, 287f
- sltiu a7, s8, -284
- lui s3, 456025
- mul t1, t2, a0
- c.srai a4, 31
-287: nop
- c.srli a5, 22
- c.addi t1, -22
- lui s4, 322073
- c.add s0, s0
- c.slli t5, 13
- mul s0, a5, a3
- auipc s0, 502688
- auipc s1, 432453
- c.srli a5, 13
- lui t5, 296095
- auipc a5, 941318
- bgeu s10, s0, 306f
- c.addi s10, -29
- lui s2, 937496
- auipc t3, 959272
- c.addi t6, 4
- srli t5, s0, 29
- c.addi s6, 19
-306: auipc t1, 293799
- c.addi a2, 21
- c.xor a1, s0
- lui s5, 189574
- auipc s3, 429591
- lui gp, 599774
- c.and a4, a2
- c.slli a3, 2
- mul a5, t1, zero
- c.srai a3, 25
- c.addi s2, 2
- c.slli s1, 6
- c.addi s6, 15
- lui s10, 311608
- c.slli t5, 7
- and t5, zero, a4
- c.addi s3, -31
- rem t6, s4, a2
- c.lui s6, 6
- c.addi a5, -2
- c.addi a2, 14
- beq s3, a1, 344f
- c.addi s10, 16
- lui s9, 389868
- c.addi t4, 1
- c.addi a2, 23
- lui s3, 120087
- c.mv a7, a3
- slt s0, a2, s1
- c.xor s0, s1
- c.addi s9, 28
- lui t5, 372966
- lui gp, 244150
- c.andi a4, -6
- addi a7, zero, -277
- c.xor s1, a0
- c.srli a5, 19
- lui a4, 332212
-344: c.lui t3, 14
- auipc s10, 148952
- divu gp, s10, s5
- c.addi s4, 25
- auipc a1, 525981
- add zero, a1, s3
- c.addi a5, -26
- c.srai a3, 30
- bgeu s1, a6, j_sub_3_sub_5_7 #branch to jump instr
- c.srai s1, 16
- ori t4, t3, -820
- c.srli s0, 14
-j_sub_3_sub_5_7: jal ra, sub_5
- c.addi s9, 9
- auipc a2, 106145
- c.addi t3, -18
- slli s10, s3, 16
- auipc a6, 817856
- auipc s1, 72706
- slt t3, ra, a1
- lui s10, 630859
- c.srli a3, 22
- c.addi a2, -14
- c.addi a5, 2
- bltu a5, t0, 373f
- lui a6, 353448
- c.srai a4, 22
- c.srai s0, 20
- c.srli a2, 4
- auipc gp, 555318
- c.addi s9, 27
- xor a3, sp, s9
- c.srli a3, 14
- c.slli t6, 5
- auipc t1, 38402
- lui a2, 182163
- c.addi a1, 5
- c.addi s3, 15
- bltu a6, t0, 385f
-373: c.srli a3, 6
- c.addi s0, 4
- c.lui s11, 8
- c.addi t4, -1
- andi a3, a5, 929
- mulhsu gp, s2, s4
- c.addi s3, 28
- lui s1, 307114
- c.addi a7, 15
- c.addi s7, 4
- auipc zero, 5983
- lui s11, 862047
-385: c.srai a4, 22
- c.addi s5, 11
- lui t1, 456943
- c.lui a5, 3
- div t3, t4, s6
- lui s3, 814637
- c.lui a5, 23
- sltu t6, s0, t4
- lui gp, 673130
- c.slli s3, 28
- c.srli a5, 4
- la t3, data_page_19+1583 #start riscv_load_store_rand_instr_stream_4
- c.srli a3, 29
- lb s2, 1914(t3)
- c.srli a4, 26
- c.srai a1, 27
- lb t2, -924(t3)
- sb a7, -1060(t3)
- lb t4, 1179(t3)
- lb s11, 616(t3)
- lui t6, 333627
- c.addi a3, 28
- mul a1, t2, a1
- lbu a0, 1264(t3)
- auipc a0, 3046
- lw s11, 1169(t3)
- lbu t4, 876(t3)
- c.slli t6, 22
- c.srai s1, 10
- lbu t2, 1047(t3)
- or s6, a0, s5
- sb gp, 36(t3)
- lhu s1, 1471(t3)
- lbu a7, 1196(t3)
- c.andi a5, -11
- sub t6, a1, a0
- and t5, s11, a1
- lhu t5, -875(t3) #end riscv_load_store_rand_instr_stream_4
- slt a5, a4, a5
- lui s8, 642772
- c.addi s2, -15
- auipc s8, 133081
- c.sub a4, a2
- c.addi s6, -18
- auipc a4, 167112
- c.nop
- c.lui s2, 27
- lui a1, 716408
- c.srai a0, 19
- c.addi a5, 31
- auipc a5, 129719
- c.add a5, a5
- c.addi s6, -2
- slti s3, tp, -569
- bge t4, zero, 415f
- auipc t4, 373355
- c.srai a3, 1
-415: c.and s1, s0
- auipc s3, 1008224
- auipc s10, 371102
- c.srai s0, 12
- lui a6, 16284
- nop
- sltiu t4, s2, -501
- c.addi s1, -29
- sltu a6, t1, t6
- c.addi s9, 5
- lui s8, 87848
- auipc gp, 782480
- c.lui s2, 13
- c.addi gp, 22
- c.slli s7, 5
- mulh a5, s7, s9
- c.addi a0, 19
- bge s6, sp, 447f
- c.addi s6, -18
- c.srai a3, 6
- lui a6, 625541
- c.addi a2, -18
- c.slli t3, 18
- c.srli s1, 21
- sra a3, s5, zero
- c.addi s1, 22
- c.addi a2, -3
- lui a5, 489344
- auipc t4, 561433
- c.addi s11, 16
- sub s9, t1, t5
- c.addi a4, 19
-447: c.addi s5, -5
- c.addi s1, -26
- c.addi a4, 30
- lui a1, 412691
- c.slli t4, 24
- lui zero, 512415
- sltu a6, ra, a6
- mulhu s0, sp, t1
- c.addi a4, 4
- lui t1, 1019163
- c.addi a5, 1
- c.slli a1, 12
- c.srai a4, 5
- c.addi a5, -11
- andi t6, a7, -243
- c.addi s1, 18
- auipc a7, 147155
- lui s5, 454912
- c.slli t1, 10
- c.srai a0, 26
- c.slli s0, 25
- auipc t2, 566273
- c.lui a4, 26
- slti s5, s11, 296
- c.slli s3, 10
- auipc gp, 217267
- c.srai s1, 28
- lui s6, 61789
- c.srli a3, 1
- srli t1, s0, 27
- c.srai s1, 19
- lui t3, 191696
- c.addi t5, 4
- lui a3, 331330
- bge t3, a7, 496f
- c.addi t3, -7
- c.addi t3, -8
- add t4, zero, s7
- lui s10, 285355
- c.addi s7, -23
- c.srai a5, 13
- auipc s1, 735056
- lui a5, 461008
- c.lui a1, 10
- c.xor a5, a4
- auipc t4, 801316
- auipc t4, 814477
- c.slli s7, 16
- c.addi t5, -16
-496: c.addi a6, -8
- c.srai s1, 5
- c.addi s11, -13
- c.slli t3, 18
- c.addi a6, 14
- c.addi t5, -28
- c.mv s7, a2
- c.srli a5, 17
- remu t3, gp, s10
- c.addi a1, -6
- c.srai a5, 24
- c.srai s1, 18
- c.lui t6, 16
- auipc s2, 367622
- c.srai a5, 8
- and t2, a7, s11
- c.slli s8, 27
- c.mv a7, gp
- auipc s10, 1040772
- c.addi t6, -28
- c.addi t5, -18
- auipc t6, 742965
- srli s5, s0, 8
- c.addi s0, -14
- c.addi t5, 14
- c.addi t6, 18
- c.srli a2, 11
- c.sub a0, a0
- sltiu t3, s1, -556
- lui zero, 300560
- c.slli t3, 17
- la t3, data_page_8+1564 #start riscv_load_store_rand_instr_stream_0
- c.slli s8, 25
- c.addi s3, -17
- c.addi s10, -13
- slli s0, t2, 1
- sb zero, 823(t3)
- lb a5, -1399(t3)
- xor zero, a2, s9
- addi a2, s10, 96
- c.srai a4, 11
- sh t1, -1214(t3)
- lb a6, 1505(t3)
- lb s8, -1339(t3)
- c.srli a2, 21
- lui a7, 935374
- sw s4, 268(t3)
- auipc zero, 725819
- lb s7, 222(t3)
- c.addi s10, 9
- sb a5, 623(t3)
- lh a2, 96(t3)
- c.srli a2, 7
- c.xor a3, a0
- lui t6, 513208
- lh a4, -906(t3)
- lhu s3, 1648(t3)
- auipc t6, 54593
- lb a5, -1229(t3)
- lhu s4, 1784(t3)
- lbu t6, 1483(t3)
- c.slli s9, 6
- sb ra, 1991(t3)
- sb s7, 1280(t3)
- lbu s6, 268(t3)
- mulh t4, t4, a0
- lb s6, 1241(t3)
- slli s8, gp, 4
- lui t2, 794686
- lhu t2, -130(t3)
- c.addi gp, 2
- lb a7, -413(t3)
- lbu s10, 1570(t3)
- sb t5, -211(t3)
- lbu a3, 1757(t3)
- lui zero, 713784
- lbu t1, 1289(t3)
- c.lui s5, 30
- lw a3, -332(t3)
- xori s1, gp, -291
- lbu s4, 1945(t3) #end riscv_load_store_rand_instr_stream_0
- c.addi s0, -1
- c.srai s1, 28
- c.addi t5, 26
- lui a4, 113149
- auipc t2, 1004973
- c.addi a0, 20
- c.and s1, a0
- c.addi t6, 22
- auipc t1, 386324
- srl a4, s2, t6
- c.addi t1, -29
- c.addi s0, -10
- c.addi s7, -1
- c.mv a6, a2
- ori s2, t2, -84
- blt a2, t4, 557f
- auipc s5, 343868
- rem s3, a0, ra
- c.srli s0, 22
- c.slli s3, 6
- c.addi t2, 3
- slt s1, t6, s11
- auipc s5, 474997
- auipc a1, 793680
- c.addi s9, 31
- c.addi t4, 23
- srli s3, s5, 27
- c.addi a5, 3
- c.addi s0, -18
- c.slli s5, 16
-557: bltu s1, s5, 560f
- c.addi t3, 18
- c.addi t2, -17
-560: c.sub s1, s1
- fence
- auipc a7, 373758
- c.slli t4, 26
- auipc t3, 393135
- srli a3, s10, 22
- sll s1, a1, s5
- c.xor a0, s1
- c.srli a2, 6
- c.lui t4, 16
- srli s0, s4, 18
- slli a1, a7, 23
- c.addi gp, 11
- auipc s2, 546700
- sra a0, t4, s11
- auipc s4, 973706
- c.srli s1, 2
- lui a0, 220242
- c.addi s0, -15
- beq a7, t1, 599f
- auipc s10, 797465
- auipc s11, 45570
- mulhsu s11, s9, s4
- auipc s5, 426877
- sltu s5, gp, a6
- c.lui s7, 2
- c.addi a0, -31
- auipc a4, 896143
- c.slli s6, 3
- c.srai s1, 12
- sra gp, s10, s2
- c.slli s0, 12
- auipc s0, 329959
- sltiu s8, ra, -513
- c.srai a4, 24
- c.lui s1, 8
- srli s5, s0, 2
- c.srli a3, 28
- auipc gp, 303955
-599: xor t1, s0, a7
- c.slli t1, 5
- c.lui t4, 9
- c.addi a7, 16
- sll s3, s10, a4
- beq t4, t5, 619f
- ori s6, s2, 434
- slt s10, t3, t0
- c.srai a2, 13
- slt s9, tp, a2
- auipc t5, 867259
- c.slli a1, 8
- c.lui a6, 13
- c.slli s5, 18
- slti s7, s9, -321
- c.addi s4, -24
- c.slli a1, 26
- auipc t3, 731496
- lui s0, 273146
- c.slli t2, 14
-619: c.sub a5, a5
- slti s2, s11, -402
- bge s7, t1, 626f
- c.lui s6, 14
- c.addi s4, -22
- la gp, data_page_10+2057 #start riscv_load_store_rand_instr_stream_2
- c.xor s0, s0
- auipc a4, 664178
- lb zero, -791(gp)
- mulhu s6, s4, a0
- c.addi a2, 26
- lbu s10, -1906(gp)
- lb s4, -158(gp)
- c.srai a5, 3
- sltu a1, t6, s1
- c.lui a2, 30
- c.addi s9, -21
- sh a7, -1985(gp)
- sb a6, 1866(gp)
- c.addi s7, 20
- lhu a5, -963(gp)
- sb s6, -478(gp)
- auipc s0, 322921
- lbu a3, -1450(gp)
- lb a0, 346(gp)
- c.addi s7, -18
- lbu s7, 1940(gp)
- lbu t2, 1470(gp)
- c.addi a3, 13
- divu t3, a1, a5
- sh s9, -1215(gp)
- lb s1, 520(gp)
- lb a4, -24(gp)
- lb t5, -978(gp)
- lb a4, -1380(gp)
- auipc s10, 612374
- lb s8, 956(gp)
- c.addi t4, -10
- lbu zero, 275(gp)
- c.addi s1, 23
- sb s4, 1887(gp)
- lbu s6, 356(gp)
- slti a6, a0, -201
- srl t2, s8, t3
- c.srli s0, 16
- c.lui s0, 21
- c.lui t6, 12
- lui zero, 327133
- and a3, t4, a1
- c.srai a2, 17
- lbu zero, -324(gp)
- c.addi s2, -31
- lbu s4, -1456(gp)
- c.lui s2, 24
- sb t3, 1500(gp)
- c.addi s3, 6
- rem a7, a1, s7
- lhu s8, 991(gp)
- c.addi s0, 15
- xori zero, a7, 899
- lb a0, -1370(gp)
- lbu t5, -1922(gp)
- sb a5, -1128(gp)
- lbu s3, 1755(gp) #end riscv_load_store_rand_instr_stream_2
- auipc a6, 1031447
- c.addi s1, 10
-626: lui a7, 727377
- lui a5, 831510
- c.xor s0, a0
- c.addi a0, 4
- c.srli a0, 2
- c.mv a2, s9
- lui a0, 625227
- c.slli s7, 20
- lui s2, 1036134
- bgeu t1, t4, 638f
- c.srai a3, 29
- c.addi t2, -22
-638: auipc a2, 1009391
- c.slli s8, 12
- auipc s6, 1016218
- auipc t5, 863999
- c.slli a5, 4
- c.lui a0, 15
- c.srai a1, 23
- c.or a2, a4
- c.addi t2, -11
- c.addi a5, 23
- c.addi gp, 21
- c.addi a4, 14
- slti a6, t3, 870
- c.addi a7, -15
- c.lui a6, 20
- sltiu t2, t0, -448
- c.addi t1, 9
- divu s11, s11, a1
- bltu t4, t1, 662f
- lui t2, 43998
- c.slli a7, 15
- c.srli s0, 4
- c.slli a1, 17
- auipc t2, 607634
-662: c.srai a0, 15
- lui s2, 678585
- c.srai a2, 21
- c.slli a0, 31
- lui s10, 353964
- c.addi a4, -20
- c.addi a4, -18
- auipc t3, 480520
- c.or a1, a4
- c.addi t6, 10
- c.addi a3, 13
- c.slli s6, 27
- c.slli s11, 13
- c.srli a2, 28
- nop
- c.andi a2, 10
- c.addi t1, 14
- c.addi t3, -5
- mul t2, s1, sp
- mulhsu a7, s5, t0
- lui zero, 93029
- lui a3, 968242
- auipc s9, 943104
- auipc t2, 226656
- lui s3, 1040578
- lui t2, 677108
- lui a5, 207614
- c.slli a3, 19
- c.srli a2, 30
- xori a2, s11, -323
- c.addi a6, 23
- ori t6, s11, -22
- c.addi a6, -29
- sra s10, a2, a6
- c.srai a0, 13
- auipc t2, 700284
- c.addi a2, -10
- c.lui s1, 12
- auipc a5, 672877
- lui t6, 49380
- c.addi a0, -8
- c.srai a0, 2
- c.mv a7, s6
- mulh a5, s7, a5
- lui s10, 184018
- c.addi s3, -9
- lui t2, 953562
- c.addi t1, -22
- c.lui gp, 15
- rem s7, a7, a4
- auipc s6, 216542
- lui s5, 72950
- sltu s3, s3, sp
- lui s3, 43960
- auipc zero, 649148
- c.lui s6, 9
- c.addi s5, -30
- lui zero, 179333
- fence
- auipc t5, 660296
- bne zero, a5, 726f
- c.addi a5, 22
- c.addi a6, -1
- lui s3, 615047
-726: c.srai a3, 16
- lui t6, 603049
- c.addi t4, -21
- c.addi s1, 25
- c.srli a4, 8
- c.addi a4, -3
- c.slli s2, 20
- c.addi t5, -23
- divu s8, s7, s3
- auipc s4, 129635
- auipc t1, 796248
- sra t2, s7, a6
- fence.i
- c.srli a4, 9
- c.lui s0, 10
- c.beqz a0, 742f
-742: lui s9, 733657
- auipc s9, 116464
- lui s8, 857005
- c.slli s4, 7
- c.srai a4, 24
- lw ra, 4(sp)
- c.addi t2, -10
- lw t0, 8(sp)
- auipc t5, 887765
- addi sp, sp, 8
- c.slli s11, 6
- lui a6, 52278
- c.addi t2, 12
- c.srli s0, 10
-1070: ret
-sub_4: blt t0, s2, sub_4_stack_p
- lui s9, 1003359
- c.addi s2, -30
-sub_4_stack_p: addi sp, sp, -12
- sw ra, 4(sp)
- c.addi s0, -27
- sw t0, 8(sp)
- c.andi a4, 18
- mulhsu t3, s0, s7
- lui s6, 869071
- addi t1, s10, -280
- c.slli s3, 15
- c.addi a4, -1
- or zero, s2, a3
- c.addi s0, -2
- lui t4, 786330
- mul a1, t3, a4
- bne s3, s4, 22f
- lui a2, 141835
- c.slli a0, 8
- c.addi gp, 7
- sra s8, t4, s5
- c.addi t3, 22
- c.addi s5, -12
- xori s8, s0, -170
- c.addi a5, -20
- c.addi a4, 24
- fence.i
- c.addi t4, 5
- c.srai a2, 19
-22: c.addi t5, -5
- bge t3, zero, 37f
- ori zero, t1, -500
- c.addi t4, -11
- c.addi t4, -14
- mulhu t4, s1, zero
- c.srai a2, 25
- c.addi s7, 30
- auipc a2, 862859
- c.addi a3, 12
- and a5, s8, gp
- c.addi a2, 14
- c.addi s5, 8
- c.addi s5, -25
- lui t3, 909957
-37: bge s9, s0, 51f
- c.addi a2, -3
- c.addi t2, 20
- c.addi t5, 5
- c.addi a4, -7
- c.addi a3, -3
- auipc a3, 633683
- c.addi a5, 13
- lui s10, 739741
- c.addi a1, -26
- and s11, a4, a7
- srl a7, s7, ra
- c.slli s4, 9
- c.addi t3, -15
-51: lui s6, 335992
- lui a7, 283967
- lui s1, 383868
- c.srai a4, 7
- c.slli s1, 25
- c.addi t2, -30
- c.srai a4, 3
- div s1, sp, a5
- c.addi t3, -16
- auipc t2, 332004
- c.srli a2, 6
- divu a5, s6, s4
- c.srai a5, 26
- auipc t2, 392645
- ori t3, a5, 387
- lui zero, 583380
- c.addi s11, 27
- divu a7, a4, s4
- auipc s1, 510298
- c.addi s5, -27
- c.addi a2, 30
- lui a7, 130859
- lui a2, 853013
- lui gp, 689685
- c.lui a3, 16
- c.slli s6, 1
- c.addi a3, -13
- c.lui s4, 20
- srai s4, s1, 27
- bgeu t2, t2, 95f
- c.addi s4, -5
- auipc s11, 474474
- c.lui s8, 12
- lui a4, 567697
- divu t3, ra, s4
- rem gp, s6, s6
- c.andi s1, -12
- blt s8, s0, 103f
- c.lui s6, 18
- lui t5, 80039
- c.slli s5, 19
- fence
- fence.i
- c.xor a3, s0
-95: c.lui s11, 9
- c.srai a1, 2
- auipc zero, 967291
- lui a4, 882532
- auipc s5, 827466
- c.srai a0, 10
- c.lui a2, 27
- sltiu s1, s10, 172
-103: c.srli a0, 2
- c.srli a1, 9
- lui s9, 119899
- c.srli a4, 1
- xor s1, s11, s0
- c.slli t1, 29
- lui a7, 715840
- c.srli a5, 16
- auipc a4, 952235
- auipc a6, 433720
- lui t5, 471272
- c.lui s7, 29
- c.bnez a2, 123f
- c.addi s11, -26
- c.addi a3, -23
- c.addi a0, -2
- andi t1, tp, -261
- divu s3, a5, a5
- fence
- c.addi s2, -31
-123: c.addi s2, 8
- c.addi s7, 8
- c.srli s0, 19
- c.srai a2, 9
- auipc s5, 105190
- divu s7, a5, s9
- lui a2, 640192
- c.addi a3, 17
- auipc a7, 593147
- lui t4, 675580
- lui s6, 897409
- c.srai a3, 23
- c.addi a6, 23
- lui t4, 229395
- c.andi a3, 9
- c.srai a1, 26
- c.srli a0, 13
- auipc a7, 727283
- c.srai s1, 2
- mulhu s1, s6, ra
- c.lui s2, 10
- c.addi t1, 6
- c.addi t6, -17
- lui a6, 161595
- fence
- c.addi t2, -7
- lui t2, 315581
- c.slli s11, 5
- auipc zero, 737983
- lui t1, 417967
- c.addi a6, -13
- c.lui a0, 31
- auipc s7, 219164
- c.addi a5, -30
- c.slli s5, 17
- nop
- c.addi a0, 13
- c.addi s7, 30
- divu a5, a5, s5
- nop
- c.addi s8, -12
- c.addi s6, 13
- auipc s2, 365609
- c.addi s2, 6
- c.addi a0, -26
- lui s11, 704705
- c.addi s2, 10
- lui t1, 628287
- sra a6, t1, s5
- srl s8, s2, s6
- srl a7, t2, t1
- auipc s1, 741630
- slti s9, s7, -360
- c.addi a7, 3
- mul a5, s7, s8
- remu s10, s4, tp
- c.lui a7, 7
- c.srai s0, 22
- c.addi a4, 4
- c.addi t4, 24
- c.addi a7, 23
- c.slli s1, 29
- c.addi t4, -5
- c.addi s7, -23
- c.addi t1, -29
- auipc s8, 459137
- lui s11, 263425
- c.srai a2, 31
- c.addi s11, -7
- lui t3, 502942
- lui s2, 962844
- beq a5, t1, 195f
-195: c.mv a1, s11
- ori s11, s11, -622
- c.lui a6, 17
- lui a5, 475373
- nop
- c.slli t1, 30
- sltu t4, a6, s0
- sub s3, s10, zero
- c.addi s3, 19
- c.slli s6, 21
- c.add a4, a1
- lui s11, 858139
- lui a5, 75817
- c.srli s0, 14
- mul a0, t1, a7
- remu zero, a2, a0
- c.srli a2, 22
- bge s9, s11, 222f
- c.addi a1, -17
- sltiu s1, t6, 62
- c.srli a4, 29
- c.addi s0, 20
- c.srai a4, 31
- nop
- c.and a5, a0
- c.srai a3, 2
- c.addi s9, 7
-222: auipc a5, 446636
- c.srai s1, 25
- c.srai a1, 24
- c.addi gp, -24
- sub s5, t0, s4
- lui s7, 418689
- c.addi t1, -32
- srai gp, s11, 6
- c.addi s6, -14
- bgeu gp, a6, 232f
-232: lui s1, 382145
- c.addi s10, 7
- c.lui s4, 31
- sra t4, a1, tp
- c.or a1, a3
- auipc t4, 363029
- c.srai a1, 23
- c.addi s4, -9
- c.addi a3, 3
- c.lui s9, 15
- beq t1, t0, 250f
- add t6, t2, a6
- beq a1, t4, 262f
- c.srli s1, 6
- c.lui gp, 28
- la t3, data_page_18+1722 #start riscv_load_store_rand_instr_stream_5
- c.add a1, a0
- sb sp, 119(t3)
- c.srai a4, 21
- c.slli gp, 13
- lui t2, 291962
- sb s5, -947(t3)
- c.addi s5, 14
- lhu t5, 1740(t3)
- sh t3, 616(t3)
- lui a5, 489599
- lb s10, -1043(t3)
- c.addi a0, 29
- lbu s0, -599(t3)
- lbu t6, -247(t3)
- lw s4, 674(t3)
- c.addi a4, -4
- lhu s7, 1662(t3)
- lb s8, 1891(t3)
- auipc t5, 91677
- lhu a0, -1642(t3)
- lb gp, 927(t3)
- auipc a6, 746671
- sltiu s11, s3, -951
- lbu s9, -387(t3)
- lb s3, -1285(t3)
- mulhu t5, s5, s5
- c.slli a0, 7
- c.xor s1, s1
- lb t5, -407(t3)
- c.srai s0, 23
- lui a7, 885291
- mul a7, t5, s6
- lbu t5, -821(t3)
- c.lui a5, 20
- lui t4, 151297
- c.srai a4, 13
- and s9, sp, t4
- c.srli a0, 7
- c.lui a2, 16
- c.slli a3, 10
- c.addi t6, 29
- andi s10, s4, -41
- sh s1, -1076(t3)
- c.lui s2, 12
- lui t2, 955927
- lui s3, 294016
- lbu s11, 740(t3)
- lb s0, 179(t3)
- lb s0, 1966(t3) #end riscv_load_store_rand_instr_stream_5
- sltiu a4, t5, -39
- c.srai a2, 16
- c.addi s11, -1
-250: lui t2, 432808
- beq s6, s3, 267f
- c.slli a3, 19
- auipc gp, 113656
- lui s1, 130430
- c.srai a3, 19
- c.addi gp, 20
- c.addi t1, -17
- c.srai a1, 3
- ori t4, s9, 837
- c.srli a1, 15
- c.addi s6, -27
-262: lui a6, 519567
- c.slli s6, 3
- xori s8, s3, -87
- c.srai s0, 18
- c.lui s9, 29
-267: lui gp, 724988
- c.srli a2, 31
- andi a0, s9, -298
- mulhsu s6, a7, a4
- auipc a6, 1005681
- c.addi s8, 5
- c.addi s6, -16
- c.srli a0, 13
- lui s2, 463491
- lui t1, 1034333
- auipc s2, 362489
- c.srli a0, 29
- auipc gp, 754792
- sub t6, t2, a3
- auipc t3, 701162
- c.and s1, a2
- xor s7, s3, s3
- c.srai a0, 28
- c.xor a1, a5
- c.addi a3, 11
- c.sub a4, a2
- auipc zero, 803641
- auipc a6, 461791
- c.addi a7, 14
- c.addi t1, 13
- c.addi a1, -15
- c.lui t2, 15
- c.lui gp, 10
- mul a0, t6, a2
- auipc s10, 639140
- c.beqz a0, 301f
- c.srai a1, 7
- sltu s9, s3, a6
- lui s11, 67310
-301: lui s4, 817080
- lui a1, 390754
- c.slli s7, 25
- bgeu tp, s8, 312f
- c.addi s3, 14
- c.addi t3, 22
- c.lui t5, 9
- c.addi s1, -17
- mulhu s8, a0, s7
- c.slli t4, 12
- c.srli a4, 14
-312: sltu a6, a5, s4
- c.addi s1, 16
- auipc t6, 78105
- c.addi s0, 16
- c.addi t1, -15
- fence
- lui s10, 279619
- c.srai a2, 13
- c.lui s7, 21
- c.srli s1, 18
- c.srli s1, 16
- c.addi a3, -5
- auipc s7, 785024
- add t2, s4, a2
- c.addi s3, -5
- c.addi s0, -3
- srl t4, s9, a5
- c.addi a0, -22
- c.addi a7, 25
- srl s4, sp, a0
- c.addi a4, -26
- add a0, s6, t6
- fence
- lui a5, 545023
- lui a6, 228307
- lui s4, 196452
- addi s2, s2, 290
- c.srai a0, 11
- c.srai s0, 7
- ori s7, s0, -471
- mulh s0, s11, t5
- auipc t2, 21876
- lui s9, 550489
- c.addi s9, -24
- c.addi s9, -6
- div a2, t0, s10
- c.addi s7, -23
- c.addi t5, 12
- lui zero, 372433
- bgeu s1, tp, 365f
- c.li a4, -17
- c.slli a3, 5
- c.addi s9, 27
- c.addi s11, -21
- c.addi a1, -11
- lui s8, 469798
- fence
- c.lui s3, 13
- lui s4, 50781
- c.addi t5, -23
- auipc s5, 676469
- mulhu a2, s4, t3
- c.beqz a1, 380f
-365: c.srai s0, 18
- lui s7, 296428
- nop
- auipc s2, 88947
- auipc t1, 850417
- lui a6, 422862
- c.addi t4, 30
- c.addi t2, 16
- lui s1, 917071
- c.addi s11, 5
- c.lui s0, 13
- c.srai a4, 28
- auipc t3, 429069
- c.slli a7, 30
- la a1, data_page_16+2685 #start riscv_load_store_rand_instr_stream_0
- slti a0, s7, 862
- c.addi s4, -30
- lb a6, 313(a1)
- c.srli a0, 5
- sh s3, 993(a1)
- lhu a5, 693(a1)
- fence
- lbu s11, 1386(a1)
- lbu t3, 1198(a1)
- rem t1, s1, zero
- lb s6, -358(a1)
- sb t6, -854(a1)
- lhu s6, -1081(a1)
- sw s6, 167(a1)
- c.srai a5, 26
- lb s9, -1924(a1)
- lbu s7, -370(a1)
- lbu t4, -411(a1)
- c.slli a0, 25
- lbu t2, -626(a1)
- sb t5, -310(a1)
- lbu zero, -1392(a1)
- c.slli a3, 9
- auipc s11, 657471
- srai t1, a0, 30
- divu t3, s9, tp
- auipc a3, 536494
- lui zero, 481417
- c.slli s8, 7
- c.addi a7, 19
- sb t6, 1052(a1)
- lh s7, -1055(a1)
- c.addi s0, 25
- lb a2, 524(a1)
- c.srli a2, 30
- lhu t3, 93(a1) #end riscv_load_store_rand_instr_stream_0
- c.addi a4, 5
-380: bgeu a1, t3, 389f
- c.addi t5, -1
- c.lui s7, 23
- add a0, t0, a2
- c.addi s7, -22
- bgeu s3, ra, 397f
- c.srai a3, 4
- lui t3, 16927
- auipc t6, 983309
-389: c.or a0, a0
- c.lui t2, 10
- lui t2, 647244
- c.slli gp, 26
- c.slli gp, 19
- mulh t3, a3, t3
- or t2, s9, t6
- xor s7, s1, s2
-397: c.lui t4, 28
- c.slli a1, 13
- remu s8, a1, ra
- rem a4, t4, s1
- c.andi s0, 11
- auipc s2, 229898
- ori t2, s1, 711
- c.addi a5, -6
- auipc s8, 909537
- srli s6, a6, 27
- c.lui a0, 5
- auipc t5, 340650
- c.addi a5, -29
- lui t3, 711905
- auipc s0, 361591
- lui t6, 484083
- lui s8, 208235
- c.addi s3, -1
- c.slli a4, 11
- lui a6, 120297
- c.addi s11, -16
- lui s10, 53779
- c.addi s4, -10
- div s4, s8, a2
- sub t4, s8, s1
- c.lui gp, 30
- lui s0, 807970
- c.add a4, s0
- c.srli a2, 25
- lui s3, 347440
- c.addi s8, -3
- divu s10, a7, a0
- c.addi t1, -15
- c.addi s2, -1
- c.addi s8, -22
- c.addi t3, 25
- xori t1, ra, 444
- c.addi s1, 18
- blt a2, s1, 438f
- c.sub a2, a0
- lui s7, 401662
-438: c.lui a4, 26
- add s0, t1, a3
- remu t1, t2, a5
- c.bnez a4, 449f
- c.srli a4, 18
- sltiu t5, t2, -521
- c.mv t2, s10
- c.addi s3, 9
- c.addi s8, -7
- c.addi s5, -11
- rem s1, t3, gp
-449: c.lui a1, 6
- lui t4, 7983
- srai a4, sp, 0
- la s3, data_page_14+1564 #start riscv_load_store_rand_instr_stream_7
- mulh s4, a6, s5
- lb a7, -315(s3)
- sw sp, 1740(s3)
- c.add a4, a0
- sh s10, -1262(s3)
- lb gp, 86(s3)
- c.addi t3, 22
- lb s4, 1301(s3)
- c.slli a6, 25
- sw s7, 232(s3)
- c.addi a3, -27
- c.addi s5, -5
- lbu s8, -509(s3)
- c.addi s8, 21
- c.or s1, a3
- c.slli a1, 31
- lh s0, -830(s3)
- lb s2, 745(s3)
- sh a0, -550(s3)
- lhu s5, 84(s3)
- c.addi a6, 19
- c.srli a4, 27
- lbu a4, -871(s3)
- lui a0, 124024
- lbu a5, 1439(s3)
- sh s5, -260(s3)
- sh ra, -630(s3)
- lbu a5, 1067(s3)
- c.addi t5, -23
- lbu s10, 1077(s3)
- lbu zero, -892(s3)
- sb s9, 201(s3)
- lb s6, 826(s3)
- sb zero, -882(s3)
- lui gp, 1006709
- lbu a4, 1581(s3)
- c.srai a0, 11
- lhu t5, 1878(s3) #end riscv_load_store_rand_instr_stream_7
- mulhsu s8, t2, t0
- c.slli t4, 29
- c.addi s7, -13
- c.addi a6, -11
- c.addi s0, -9
- c.addi a1, -25
- mulhsu s10, a3, s0
- c.addi s3, -27
- c.addi a6, 10
- sra s10, s2, a7
- c.addi t5, -6
- lui a6, 414392
- c.li a6, 22
- c.addi t3, 22
- c.addi gp, -13
- auipc s8, 398286
- c.slli a4, 3
- auipc s5, 479478
- c.slli s2, 11
- auipc t5, 575843
- c.slli s5, 19
- auipc a1, 1048098
- c.addi s8, 21
- c.addi a0, 6
- mul s2, t2, s3
- c.addi s5, 27
- c.srli a0, 10
- srl t6, t2, t2
- c.addi s10, 1
- mulhsu s1, s2, zero
- auipc a0, 438777
- c.slli gp, 7
- c.addi t4, 29
- c.slli s3, 3
- c.addi a5, -29
- c.lui s4, 27
- or a5, s11, t5
- c.addi s4, 16
- c.slli s3, 27
- c.srli a4, 6
- c.addi s8, 26
- lui t3, 292240
- c.addi s1, -4
- auipc s7, 196896
- c.beqz a4, 505f
- mulhu a7, a1, s8
- c.addi s8, 22
- lui s11, 83536
- rem a1, a7, a0
- c.addi a1, -11
- bne s6, ra, 518f
- auipc s8, 966196
- c.add a0, a1
-505: c.srai s0, 12
- c.addi s10, -24
- c.slli s0, 19
- c.addi s3, 14
- c.addi s7, 31
- c.addi a4, -16
- auipc s10, 558750
- lui s6, 821164
- c.addi t5, -23
- c.lui s8, 8
- c.addi s10, 4
- c.addi a4, -8
- bge a2, s9, 530f
-518: lui a5, 783407
- c.slli gp, 4
- c.addi t4, 28
- xor a7, a7, s6
- lui zero, 1045934
- c.addi t1, 27
- c.srai a1, 19
- c.slli t2, 21
- auipc t2, 53966
- c.lui s7, 23
- c.addi t4, 27
- c.addi t1, -28
-530: c.addi a2, 5
- c.addi a7, 4
- c.addi s4, 19
- lui s0, 667356
- c.srli a1, 26
- c.nop
- sra a5, t3, t3
- andi s1, sp, 321
- lui t3, 744761
- divu t1, a1, s8
- c.lui gp, 4
- c.slli t3, 17
- auipc a0, 74014
- auipc t2, 466230
- srl t5, s4, s8
- divu s7, zero, s3
- auipc zero, 1041196
- c.addi a7, -19
- auipc s1, 186061
- c.srai a2, 24
- lui s7, 797397
- c.addi s11, -5
- sll s2, s1, s10
- c.lui t6, 20
- c.srli a3, 5
- lui s7, 535720
- c.addi a1, 27
- la a5, data_page_6+2002 #start riscv_load_store_rand_instr_stream_3
- sb t4, -1708(a5)
- lbu a4, -739(a5)
- lui t5, 595348
- lb t3, -1363(a5)
- c.addi t4, -17
- lbu a4, 297(a5)
- fence
- lb t6, -1853(a5)
- sb s8, -289(a5)
- lb t2, 249(a5)
- c.xor s1, a2
- lb s6, 646(a5)
- sb a5, -1051(a5)
- lbu a2, 1740(a5)
- c.addi a2, 8
- lhu a0, 1224(a5)
- c.addi t4, 27
- lhu zero, -1662(a5)
- lbu t6, -776(a5)
- c.addi s10, -31
- lui a4, 390523
- c.li s8, 4
- lbu s7, 1976(a5)
- lbu a4, 997(a5)
- lb s3, -951(a5)
- addi s1, gp, 392
- c.addi a1, 21
- c.srai a4, 7
- sh s6, -1140(a5)
- c.slli s0, 16
- c.lui a2, 15
- c.addi t6, -30
- c.addi s11, 8
- auipc s9, 355217
- lui t5, 76055
- c.addi s1, 7
- lbu s9, -297(a5)
- lhu a7, 824(a5)
- lb s11, 1347(a5)
- mulhu s8, ra, s11
- c.srli s1, 28
- lui a0, 980902
- lb a0, 669(a5)
- lb s6, 1296(a5)
- lb s11, 13(a5)
- lb t1, -1951(a5)
- lbu a4, -1594(a5)
- c.srli a4, 6
- c.addi a0, -4
- ori gp, a4, 583
- lw a3, -34(a5) #end riscv_load_store_rand_instr_stream_3
- c.addi a2, 3
- c.nop
- c.addi s10, -8
- lui a2, 437898
- c.srai a4, 23
- auipc a1, 539497
- c.addi a4, 18
- c.srli a3, 6
- slt t6, a6, s8
- c.addi t6, 19
- mulhsu zero, t6, t1
- blt zero, tp, 586f
- c.addi t4, -6
- auipc gp, 730875
- sltiu s3, t6, 234
- c.sub a2, a2
- auipc s3, 925479
- c.addi t4, 1
- c.srai a2, 8
- c.srai a5, 4
- c.addi a5, -20
- c.srli a1, 31
- c.addi t5, -21
- c.srai a1, 28
- divu a2, ra, s0
- auipc t3, 6114
- lui s8, 445826
- auipc s4, 404243
- c.slli s8, 8
-586: c.addi s0, 17
- c.addi s11, 20
- c.addi a7, 15
- auipc a7, 1023155
- c.addi s11, -28
- auipc a3, 311244
- c.lui t5, 14
- or s7, t5, s6
- c.srli a0, 5
- auipc t3, 780430
- lui zero, 324160
- lui a3, 506197
- c.li a7, 4
- c.lui s8, 31
- c.addi s8, 2
- srli a1, t6, 28
- slt t2, a4, t5
- c.lui a0, 6
- xori s3, s2, -647
- c.addi a2, 23
- addi s1, s4, 327
- c.addi a7, 28
- c.addi s1, 18
- c.addi a2, -32
- c.srai s1, 21
- remu t4, a0, a2
- auipc a0, 567135
- slti s6, a6, -171
- bne zero, t2, 623f
- blt a2, s7, 630f
- xori a5, t2, -640
- c.addi a5, 19
- auipc s10, 859858
- lui s10, 339418
- c.srli a1, 1
- lui s10, 328536
- auipc a4, 164687
-623: slli s11, s2, 23
- auipc a2, 512486
- lui a0, 124200
- andi t6, t1, -689
- c.srli a1, 17
- c.srai s0, 7
- srli s6, sp, 30
-630: c.srli s0, 17
- auipc zero, 429632
- c.addi s11, 3
- c.slli s1, 17
- c.addi s11, -4
- sra t6, s2, s7
- c.srli a4, 17
- lui t2, 453633
- auipc s0, 777782
- c.addi a0, -25
- lui s7, 687681
- c.beqz a5, 644f
- c.addi s11, 11
- c.addi s3, 4
-644: c.addi t2, -21
- c.lui t3, 15
- nop
- lui a3, 609362
- c.lui s9, 1
- c.addi a5, 5
- auipc s4, 57490
- fence
- c.addi s3, -32
- c.lui t5, 24
- div a1, t5, t5
- sll t1, s3, a5
- c.srli a1, 26
- and t3, s9, a0
- mulh a2, s7, s7
- lui s8, 239631
- auipc s7, 939366
- lui s9, 566573
- c.srai a4, 31
- lui s8, 404577
- lui t2, 47408
- c.srai s1, 29
- c.slli a0, 9
- c.srai a0, 31
- auipc a1, 280864
- c.addi s3, 22
- c.addi a5, 29
- c.srai a1, 9
- auipc a1, 446561
- c.addi s3, -3
- lui s2, 155917
- auipc t2, 182609
- c.srli a1, 10
- c.addi a0, 25
- auipc a6, 436276
- c.slli s6, 4
- c.li s4, -1
- c.lui gp, 12
- bgeu t0, s2, 687f
- div a1, s7, tp
- c.slli s10, 30
- c.addi s6, -2
- lui zero, 763213
-687: lui s9, 345463
- c.srai s1, 24
- c.srai s1, 27
- auipc a2, 611758
- bltu t1, s10, 708f
- auipc s5, 27325
- auipc a1, 711645
- c.addi s7, -3
- c.addi s0, -8
- auipc s9, 863646
- auipc a1, 832079
- c.xor a0, s1
- lui t4, 24000
- c.addi s11, -25
- auipc s10, 904574
- auipc a7, 882469
- auipc s1, 190078
- lui a6, 562098
- or a2, a5, a2
- c.addi s7, -25
- c.addi a1, -15
-708: div gp, s4, a6
- c.lui s6, 6
- auipc s9, 169208
- sra a6, gp, a2
- c.srai a3, 8
- c.addi s2, -23
- lui zero, 233691
- c.srai a4, 26
- c.addi s4, 20
- c.or a3, a2
- mulhsu t5, a6, a5
- auipc s4, 480356
- c.srai a4, 23
- mulh a1, a4, gp
- rem s8, s9, a1
- lui s4, 969318
- addi s4, s7, 455
- c.lui a2, 2
- c.addi s10, -31
- sltu s2, s0, a1
- sltu zero, a6, sp
- fence
- c.sub a3, a3
- c.lui s2, 5
- c.sub a0, a3
- c.addi s4, 18
- auipc s9, 1027615
- c.srai a2, 26
- auipc a6, 430066
- add a5, zero, s0
- auipc s1, 159832
- c.addi s6, -15
- c.addi t2, -6
- div s3, a3, a6
- lui a7, 11733
- auipc a5, 604819
- c.mv a1, t1
- lui t6, 731495
- c.lui t2, 19
- c.addi s3, 31
- lui t2, 363118
- lui s8, 679734
- la s1, data_page_5+2106 #start riscv_load_store_rand_instr_stream_4
- lb gp, -1461(s1)
- lb t5, -1811(s1)
- c.srai a5, 8
- c.addi t6, 6
- c.srai a5, 12
- lbu t6, 1694(s1)
- c.slli t5, 11
- c.addi s7, -21
- lhu t5, -526(s1)
- c.andi a5, 14
- lui s9, 602578
- c.addi s7, 23
- mulhsu a2, tp, a4
- c.addi s2, 24
- sw t4, 502(s1)
- c.srai a1, 3
- c.lui t4, 31
- c.srai a3, 5
- lhu t5, -320(s1)
- c.srai a0, 13
- c.addi t1, -18
- c.lui a1, 4
- lb s0, 553(s1)
- lh a1, -1288(s1)
- xor t3, s0, s1
- auipc a4, 608697
- add t3, t1, a1
- c.srai a3, 29
- fence
- sb s4, -751(s1)
- lui s9, 704727
- c.addi a2, 29
- c.srai a1, 5
- c.addi t5, -3
- lhu s9, -1216(s1)
- c.addi a1, -4
- c.srli a3, 9
- sw t4, 834(s1) #end riscv_load_store_rand_instr_stream_4
- sll s0, s4, t2
- lui t6, 946335
- divu zero, sp, a4
- lui s6, 461882
- auipc a7, 492520
- c.addi s2, -21
- c.nop
- c.srai s1, 11
- c.srli a3, 17
- c.addi a6, 30
- lui s7, 451674
- c.xor a1, s1
- andi zero, s1, 277
- lui gp, 388248
- c.slli s6, 14
- xor t6, sp, tp
- c.addi a5, 3
- c.addi s0, 19
- c.srai s1, 7
- blt a5, a0, 773f
- c.addi a3, 26
- c.mv s4, t2
- auipc s11, 79118
-773: c.lui s5, 15
- auipc s11, 706152
- c.addi gp, -27
- c.srai a2, 23
- c.andi a0, 4
- sra a1, t3, s0
- auipc a5, 613343
- auipc a6, 8736
- la s2, data_page_8+1603 #start riscv_load_store_rand_instr_stream_1
- lbu s11, -656(s2)
- mulh a6, a2, s3
- sb a5, 1516(s2)
- c.slli a5, 2
- addi a4, t2, 245
- remu s10, a3, a2
- andi s8, s3, -146
- c.lui a1, 20
- lw a7, -1455(s2)
- lbu t5, 724(s2)
- srli s7, a7, 18
- sra t1, t1, s1
- c.lui gp, 9
- sltu s8, a2, tp
- lb s9, 2009(s2)
- lui a6, 531050
- lb t6, 1106(s2)
- auipc a2, 628197
- sh sp, -1541(s2)
- lbu s5, 83(s2)
- c.addi a6, -21
- lbu s6, -832(s2)
- lhu t4, -659(s2)
- lb a6, 1825(s2)
- lb s6, 928(s2)
- sltiu s3, a7, 22
- lb t2, -482(s2)
- lb t1, 1576(s2)
- sll s4, s6, a1
- sb a3, -1510(s2)
- lui s5, 338991
- c.srai s0, 14
- mulhu s10, a4, a7
- c.srli a5, 21
- c.addi s11, -9
- lb s8, -448(s2)
- sb s4, -698(s2)
- sb t0, -1352(s2)
- lh a2, 1333(s2)
- c.and a5, a0
- sh sp, -627(s2)
- lb a7, 95(s2)
- sb t3, 870(s2)
- c.addi s10, 1
- auipc s7, 686508
- xori a1, s4, 732
- lui a2, 969573
- lbu t3, -1337(s2)
- lbu a5, -1123(s2)
- sb s9, 182(s2)
- fence
- c.addi s1, -19
- lbu t3, -756(s2)
- sll a5, gp, s3
- lb s5, 1026(s2)
- lui t6, 789026
- lbu s8, -22(s2) #end riscv_load_store_rand_instr_stream_1
- lui t6, 656235
- c.addi t4, 23
- c.addi s8, 22
- srai a4, a6, 14
- lui s2, 733595
- nop
- bgeu t3, s2, 793f
- auipc s11, 482826
- c.slli t1, 13
- lui a7, 507436
- c.addi s7, 23
- c.slli t5, 14
-793: c.lui a7, 15
- la s7, data_page_16+1532 #start riscv_load_store_rand_instr_stream_2
- auipc s2, 295817
- sb a7, -1262(s7)
- c.slli a6, 27
- lui gp, 956017
- mulhu a4, t2, t2
- c.slli s3, 27
- sb a2, 815(s7)
- lw a3, -848(s7)
- sub t2, a5, tp
- sb a4, -24(s7)
- lhu s10, 130(s7)
- c.srai s1, 20
- sb s5, 909(s7)
- c.srli a2, 30
- c.addi s10, 29
- remu s8, gp, a2
- c.slli s11, 22
- addi s6, t4, 364
- lbu zero, 597(s7)
- rem s9, s6, t4
- lh s9, -680(s7)
- c.addi a0, -17
- auipc a6, 304819
- lui s4, 863689
- lb gp, -1093(s7)
- c.addi a0, 20
- c.addi a1, 2
- c.srli s1, 13
- lui s11, 420094
- lui t5, 768157
- c.lui a2, 24
- c.srli s0, 30
- lh a5, 522(s7)
- add a0, a6, s7
- c.addi a1, -32
- c.addi t2, 10
- c.slli s8, 9
- mulhu s1, s9, t0
- auipc s11, 622143
- lui s9, 593778
- lh a5, 1010(s7) #end riscv_load_store_rand_instr_stream_2
- c.srli a2, 6
- c.lui s7, 13
- c.addi s0, -6
- c.lui s7, 8
- c.addi t4, 15
- c.addi a6, -1
- c.addi s9, 28
- c.addi t4, -30
- auipc s6, 321189
- c.li t3, 9
- lui s10, 416364
- c.addi a7, -22
- c.lui s3, 4
- lui s0, 1002896
- auipc t5, 707159
- c.addi t5, -2
- c.slli gp, 25
- lui s0, 363118
- c.addi s7, 23
- lui s0, 497990
- c.add s1, a5
- c.addi s9, 2
- c.addi a2, -32
- c.addi s1, 16
- sltiu s9, t6, 175
- lui s3, 941123
- c.addi s11, -15
- c.srli a2, 14
- c.slli a7, 5
- c.addi t4, 4
- lui s9, 296275
- div t2, ra, s7
- c.srli a4, 28
- lui a2, 154571
- c.addi a5, -12
- c.addi t6, 9
- slti s5, t2, 488
- bgeu s1, s4, 835f
- bgeu sp, t0, 833f
-833: slti s3, s3, -546
- c.addi s11, 12
-835: c.addi t4, -29
- c.slli a0, 15
- c.lui a7, 15
- slt s8, s3, a7
- la s4, data_page_8+1914 #start riscv_load_store_rand_instr_stream_6
- lh s2, 1848(s4)
- lh gp, -106(s4)
- lbu t5, -1651(s4)
- lb t6, 125(s4)
- lbu a0, 589(s4)
- c.addi s6, 1
- c.addi s1, -27
- lui s5, 408305
- lh s10, 942(s4)
- auipc a3, 76968
- auipc t4, 41440
- sb s1, 1666(s4)
- lw zero, 1682(s4)
- sh t2, 1008(s4)
- c.srli s0, 12
- sra s6, ra, t0
- c.addi a3, 15
- c.srai a2, 1
- lbu s5, -1349(s4)
- sb s7, 987(s4)
- c.slli a4, 14
- lbu t1, 381(s4)
- c.addi t5, -29
- c.slli t3, 7
- lb s3, -1385(s4)
- c.addi a3, 29
- auipc s2, 241224
- lui t3, 697796
- sb s6, -1129(s4)
- sb t5, 1153(s4)
- c.add s1, s0
- auipc s11, 497814
- lhu s9, 284(s4)
- c.srli a4, 23
- c.srai a3, 15
- sltiu s9, t0, -34
- lbu s2, -1487(s4)
- mulh a4, s5, t1
- lw t6, -138(s4)
- lh a0, 1224(s4)
- sb ra, 790(s4)
- lw s0, -1442(s4)
- sb a1, 1539(s4)
- sh a4, -1468(s4) #end riscv_load_store_rand_instr_stream_6
- lui s10, 93247
- c.addi s8, 11
- nop
- lw ra, 4(sp)
- c.srli a5, 16
- xor s9, ra, s7
- lw t0, 8(sp)
- srli t5, ra, 28
- lui s7, 489441
- c.lui a7, 12
- lui gp, 977950
- addi sp, sp, 12
- lui s3, 398188
- c.or a5, a4
-1223: ret
-sub_2: c.addi s8, 24
- addi sp, sp, -52
- sw ra, 4(sp)
- c.srai s0, 1
- sw t0, 8(sp)
- and t2, sp, a5
- bne s4, s6, 13f
- c.addi a0, 5
- auipc s2, 294055
- c.slli s8, 10
- auipc a5, 919610
- div s2, sp, a7
- auipc a0, 61255
- addi zero, zero, 837
- lui s11, 735493
- fence.i
- c.srli a0, 17
- c.addi t6, -5
- lui t1, 369023
-13: mulhsu t5, ra, t1
- auipc t1, 1021732
- lui s7, 101891
- c.srli a2, 11
- c.addi t6, -26
- c.srli a1, 24
- c.srli a0, 6
- auipc a3, 618039
- sub t2, t4, s5
- c.slli s4, 6
- lui t6, 644219
- fence.i
- auipc t3, 239341
- bge t3, a7, 40f
- c.addi s11, 1
- auipc s4, 532772
- auipc a4, 983874
- c.srai a4, 12
- add a2, t5, a1
- auipc t1, 140184
- c.addi a7, -12
- c.slli a6, 3
- c.addi a1, 29
- lui a3, 888512
- c.slli t1, 1
- sll zero, t4, s0
- auipc s5, 560976
-40: auipc s5, 425284
- c.addi t4, -1
- slti s5, a4, 90
- auipc t1, 185586
- blt a5, a1, 57f
- bge s6, s3, 59f
- c.srli a0, 28
- c.addi s7, -32
- c.srli a5, 24
- c.addi a5, -2
- addi t2, t4, 161
- lui s4, 565411
- c.andi a2, 24
- nop
- sltiu s4, a3, -243
- bne t5, s11, j_sub_2_sub_3_4 #branch to jump instr
- c.addi s10, 17
- c.lui s3, 22
- c.srli s1, 3
- c.addi a1, 27
-j_sub_2_sub_3_4: jal ra, sub_3
- c.addi t3, 15
- c.srli s0, 3
- c.addi t4, -14
- lui gp, 695883
- c.addi t5, -21
-57: c.lui s9, 30
- c.addi a1, 11
-59: c.beqz a4, 75f
- c.addi t5, 25
- c.lui s2, 5
- c.lui a2, 15
- lui zero, 580532
- c.srli s1, 25
- c.lui t3, 19
- mulhu s6, s10, a7
- lui a4, 68259
- c.addi t5, 13
- lui a1, 888147
- c.slli a3, 13
- andi t4, s1, 804
- sll s1, t4, a3
- c.addi s11, -20
- auipc s4, 86342
-75: lui a4, 588383
- c.mv a1, t4
- c.srai a1, 15
- bge s0, s4, 85f
- c.addi s1, -11
- lui a3, 373043
- c.addi a5, -27
- c.srai a3, 11
- lui s10, 716826
- c.addi s7, 2
-85: auipc t5, 75055
- div t4, s1, t4
- lw ra, 4(sp)
- slti t2, t2, -375
- lw t0, 8(sp)
- c.and a4, a5
- c.addi s6, -18
- c.slli s9, 8
- addi sp, sp, 52
- c.srli a4, 10
- c.lui a2, 24
- c.addi gp, 27
- lui t2, 427688
-113: ret
-sub_5: c.addi s10, 17
- ori t6, s7, 668
- addi sp, sp, -24
- c.addi t3, -24
- sw ra, 4(sp)
- auipc s4, 609837
- lui t2, 198958
- c.addi s9, 26
- c.addi a6, 11
- sw t0, 8(sp)
- c.slli s8, 29
- c.addi s3, 29
- c.addi s8, 18
- c.addi t2, -21
- c.slli t5, 2
- c.addi a4, 12
- c.addi gp, 24
- c.slli a2, 15
- c.addi s6, -24
- rem a0, t0, s7
- c.srai s0, 11
- c.srli a3, 24
- c.addi s2, 7
- lui a0, 652615
- c.srli a1, 27
- c.srli a5, 6
- c.srli a5, 2
- remu t4, sp, t6
- lui t3, 223018
- fence.i
- auipc a2, 1000328
- bgeu s2, zero, 21f
-21: lui s7, 474112
- c.add a1, a2
- mul t4, a5, t1
- bge a5, t4, 25f
-25: c.slli s8, 18
- bge t5, s5, 46f
- auipc zero, 828307
- c.slli s3, 30
- c.addi s9, -28
- auipc a4, 941833
- c.srai a5, 26
- lui t6, 906393
- c.slli s9, 12
- c.lui s10, 25
- addi a6, ra, 355
- c.srai a3, 6
- c.srai a2, 14
- c.slli a4, 1
- auipc t2, 984037
- c.slli t2, 11
- lui s10, 312443
- c.addi a7, 24
- c.addi t5, 5
- c.srai a5, 26
- c.addi gp, 18
-46: lui s9, 793662
- ori gp, t4, -949
- lui s5, 742865
- c.lui gp, 12
- auipc s0, 92681
- c.addi t3, 24
- la s3, data_page_16+2405 #start riscv_load_store_rand_instr_stream_6
- lbu s9, -507(s3)
- lb zero, -543(s3)
- sw s11, 79(s3)
- remu a3, t1, tp
- c.addi s4, -6
- c.addi a1, -24
- and t5, a3, zero
- c.lui a4, 9
- lh s5, -1805(s3)
- lb s7, -500(s3)
- c.addi a1, -29
- lbu a6, 844(s3)
- lb t5, 662(s3)
- c.srli a0, 22
- auipc t4, 403778
- c.addi t4, 31
- slti s6, a4, 145
- c.addi s8, -29
- c.lui s9, 15
- c.lui a6, 23
- c.slli a7, 28
- auipc s5, 1007528
- lbu s0, -1035(s3)
- mulh a0, ra, t6
- c.srai a0, 14
- lbu s10, -1378(s3)
- lui zero, 657450
- c.srli a1, 1
- c.srli a1, 11
- lh s1, -505(s3)
- c.addi s11, -8
- sb gp, 1083(s3)
- sb gp, 1188(s3)
- lbu s4, -1186(s3)
- sb s1, -1512(s3)
- sb s11, 1416(s3)
- sh t0, -719(s3)
- sb s10, -586(s3)
- sb t4, -798(s3)
- lb a2, -1984(s3)
- c.slli a1, 31
- lhu t5, -1437(s3)
- sb a3, 1474(s3)
- sb a2, 722(s3)
- c.addi a1, 13
- c.lui t4, 26
- lbu t6, 702(s3)
- c.srai a0, 23
- sb gp, 1395(s3) #end riscv_load_store_rand_instr_stream_6
- mulhu s1, s7, a0
- c.srai a3, 26
- c.lui t3, 4
- la s0, data_page_3+1965 #start riscv_load_store_rand_instr_stream_1
- lui s1, 665129
- c.addi s8, 12
- c.srli a4, 3
- xori t5, zero, -680
- c.lui t2, 4
- lui s7, 458478
- sb a0, 131(s0)
- c.addi s5, -17
- c.addi s11, -16
- lui s6, 877433
- c.srli a3, 22
- sh a4, 1133(s0)
- lb t2, 599(s0)
- lh zero, 1809(s0)
- sb a0, 98(s0)
- lui s6, 309908
- lh s1, 1431(s0)
- c.srai a5, 9
- lbu gp, -1773(s0)
- auipc s10, 355095
- c.srai s1, 12
- auipc t2, 274497
- sw s11, -33(s0)
- lb a6, 1187(s0)
- ori s8, t5, 310
- lb t2, 700(s0)
- lh zero, -1135(s0)
- lui a3, 915641
- c.slli s7, 13
- c.srli s1, 7
- c.srai a1, 1
- rem a1, ra, s2
- fence
- c.addi a3, -18
- lbu s6, -244(s0)
- c.srai a4, 11
- or t4, a6, gp
- sb a4, 1239(s0)
- c.addi s4, 8
- c.lui a3, 3
- lb a3, -1634(s0)
- lui s1, 988625
- lh gp, 437(s0) #end riscv_load_store_rand_instr_stream_1
- c.srli a5, 5
- c.srai a5, 9
- c.addi s8, -13
- remu a2, s11, tp
- lui a2, 1014521
- c.addi gp, -27
- andi s7, t4, -53
- auipc t4, 122026
- c.slli s11, 18
- c.srai a2, 31
- c.andi s1, -27
- lui s2, 646566
- c.srli s1, 15
- c.addi s11, 18
- c.srai a2, 14
- c.addi s10, -10
- c.addi s2, -29
- c.addi a6, 15
- c.lui a4, 20
- auipc gp, 559339
- sub a3, s0, ra
- c.addi a1, -23
- lui t2, 180921
- c.bnez a2, 83f
- c.addi s5, -32
- c.addi s6, 16
- lui a5, 344534
- c.addi s2, -13
-83: c.srli a4, 18
- addi t6, s9, 587
- c.srai s1, 6
- lui s5, 431271
- auipc a6, 470890
- auipc s9, 735481
- lui a2, 978383
- c.slli s7, 9
- c.srli a3, 6
- auipc s1, 637575
- auipc s4, 597479
- c.addi s6, -24
- c.addi s2, -25
- c.addi s3, 2
- lui zero, 150506
- c.lui a4, 1
- lui a3, 66510
- lui s3, 403130
- c.lui s8, 18
- auipc s9, 654632
- auipc t3, 551872
- c.addi t3, -28
- lui t3, 760732
- fence
- xori s5, s1, -1007
- c.addi t1, 25
- c.lui s6, 13
- lui s4, 1044207
- auipc t5, 955243
- c.lui s5, 30
- c.xor s1, a2
- lui a6, 79413
- c.addi a5, -29
- c.srai a2, 17
- c.addi s8, -8
- andi a2, a7, -371
- c.addi s1, 29
- c.slli s10, 8
- lui s6, 940230
- c.slli s10, 25
- auipc zero, 540412
- slti t6, s7, 227
- c.xor a1, a5
- lui s10, 525618
- lui s5, 612274
- c.lui t5, 2
- auipc gp, 86686
- c.slli t2, 13
- c.addi s10, 31
- c.srai a2, 23
- c.addi s5, 2
- sltu a6, a5, t0
- c.addi gp, 20
- c.addi a4, -10
- c.addi s9, -26
- c.slli s2, 15
- lui s3, 286923
- auipc s1, 85485
- c.srai a0, 9
- auipc s10, 18287
- c.addi t6, -1
- c.addi a2, -5
- auipc s10, 338274
- c.slli s10, 29
- c.slli a1, 29
- c.nop
- c.srli s1, 12
- lui t1, 267640
- bne s0, a1, 165f
- c.addi t2, -23
- c.addi a2, -7
- c.srli s1, 22
- divu t5, a3, t1
- auipc t6, 62340
- rem a1, s2, s7
- slli a7, s4, 28
- div a3, t6, a0
- c.addi t4, -23
- c.slli s10, 29
- auipc s7, 347135
- c.addi s6, 16
- c.lui a5, 29
-165: c.srli a2, 2
- auipc t4, 381701
- c.addi t3, -20
- c.slli t1, 9
- lui t1, 516526
- remu s2, s0, s5
- c.addi a0, 22
- c.addi s5, 12
- c.addi t3, -7
- bge gp, t2, 186f
- auipc s7, 635521
- c.addi t5, -22
- lui gp, 76888
- c.lui s11, 12
- c.srai s0, 17
- c.xor a0, s0
- c.or s1, s1
- c.srli a3, 26
- auipc t3, 889782
- slti s11, a4, -574
- c.lui gp, 10
-186: auipc s9, 506578
- c.lui s3, 12
- auipc s6, 952240
- auipc s3, 43033
- c.addi t5, -29
- divu t1, a0, s6
- c.addi a5, 16
- c.nop
- c.addi t5, 23
- c.addi t1, -3
- auipc a6, 724928
- c.lui a1, 26
- srai a5, t3, 11
- andi gp, a4, -204
- auipc s11, 154027
- c.addi s7, -5
- c.lui t6, 18
- c.addi a5, -32
- auipc s0, 896057
- c.lui s9, 28
- c.srai a3, 11
- c.lui s7, 10
- c.addi s7, -24
- c.nop
- nop
- c.or s0, s0
- srli a5, zero, 28
- c.srli s1, 5
- c.addi a6, 18
- lui s5, 468288
- c.beqz a0, 222f
- lui s5, 310311
- fence
- xor a5, t5, s1
- nop
- sll s2, s0, s1
-222: lui s6, 805233
- c.addi s0, 7
- sltu s1, s0, a6
- c.slli a4, 31
- bgeu s7, a6, 240f
- add a4, ra, s9
- lui a6, 845203
- lui t4, 643507
- c.srli s1, 4
- or zero, s6, s4
- c.srli a3, 18
- auipc t1, 644217
- c.addi s3, 26
- lui s7, 362071
- sra s8, t6, t1
- c.addi s10, 6
- c.lui s1, 25
- c.srai a1, 27
-240: c.srai a5, 30
- add s0, gp, a0
- c.srai a0, 19
- lui s1, 377734
- auipc t6, 278530
- c.addi a0, 8
- c.addi s10, -19
- ori t5, s3, 903
- c.addi t6, -26
- beq s11, s11, 261f
- c.srai s1, 28
- slt t3, s8, s6
- lui a2, 733610
- ori t4, sp, 448
- sltiu s3, s3, 854
- auipc s11, 647843
- mul gp, zero, s9
- c.lui s7, 15
- auipc s7, 485989
- lui s6, 539843
- auipc gp, 913414
-261: lui a0, 54403
- c.slli s5, 12
- c.addi s5, 14
- div t5, t1, sp
- c.addi a2, 10
- bgeu s11, s0, 270f
- c.srli a0, 12
- auipc a5, 575684
- auipc s0, 67259
-270: auipc t4, 696606
- mulhu a1, s2, ra
- fence
- lui a5, 47442
- c.addi s8, 11
- auipc gp, 1008031
- lui s9, 1028111
- auipc s9, 171505
- c.srli a0, 10
- lui s2, 639816
- srli s3, a0, 14
- c.addi s4, -24
- xor s7, t0, s4
- auipc s3, 796407
- auipc s1, 912636
- c.addi a4, -22
- c.lui s10, 24
- lui t4, 196519
- c.srai s1, 1
- c.addi s2, 30
- lui a1, 314718
- c.addi s1, 27
- c.slli s6, 11
- fence.i
- c.addi a4, -26
- addi s7, a1, 136
- c.srai a3, 28
- c.addi s10, -28
- c.srai a0, 2
- c.slli t2, 24
- lui t5, 29
- rem t6, a1, a3
- c.slli s9, 15
- c.addi t1, -26
- c.addi s7, 25
- lui s7, 58169
- la t6, data_page_6+2369 #start riscv_load_store_rand_instr_stream_4
- lbu s5, 1662(t6)
- lb t1, -376(t6)
- c.addi t2, -14
- lui a5, 53772
- c.addi s5, 30
- c.addi s11, -9
- div a6, a5, t0
- lb t5, -1231(t6)
- c.addi s4, -28
- c.lui s2, 23
- mulhu s10, s1, t5
- lbu s7, -130(t6)
- lb a6, 294(t6)
- sb s1, 662(t6)
- lbu s6, -1188(t6)
- lbu a3, 615(t6)
- sb ra, -1732(t6)
- sb s8, 1641(t6)
- c.slli s5, 16
- lbu s3, 1142(t6)
- c.slli a2, 13
- lui zero, 655601
- lb s4, 1196(t6)
- c.srai s0, 11
- lui s10, 827865
- c.addi t1, -8
- lhu t3, 1253(t6)
- lb s10, 130(t6)
- lb a7, 1409(t6)
- sb a2, -1898(t6)
- auipc t1, 276922
- auipc a4, 360448
- lhu t1, 355(t6)
- c.addi t4, -28
- auipc s1, 316578
- auipc gp, 379533
- lb s8, 1614(t6)
- remu s0, a5, gp
- c.srai a2, 6
- lhu s3, 949(t6)
- divu t1, s3, t3
- lbu a3, 851(t6)
- sb a1, -758(t6)
- xori a7, s6, -765
- lbu a7, 293(t6) #end riscv_load_store_rand_instr_stream_4
- c.addi s7, 6
- auipc s10, 449337
- lui t3, 952062
- c.srai s1, 27
- lui s10, 111213
- c.addi a4, -18
- lui s8, 602305
- c.srai a3, 18
- c.srli a4, 8
- lui a1, 74113
- lui t4, 420645
- mulhu s11, a3, a5
- c.slli t6, 12
- xori t3, s8, 792
- c.srli a0, 31
- c.addi gp, 3
- c.srli s1, 12
- c.addi s3, 28
- c.addi a6, 21
- c.srli a2, 18
- c.addi s9, 19
- lui gp, 221168
- lui t5, 383961
- c.li t5, -26
- c.andi a5, -6
- c.addi a1, -30
- ori s9, t2, -233
- c.srai a3, 19
- c.srli a1, 11
- auipc s10, 874763
- c.srli a2, 29
- c.addi t2, 26
- c.addi a4, -25
- c.srai a1, 16
- c.srai a2, 17
- c.addi s8, 19
- auipc t5, 508950
- bge s3, tp, 346f
- c.addi a3, -2
- c.addi a4, 20
-346: sltu s7, tp, s2
- c.addi s3, -11
- lui t1, 788799
- c.nop
- rem s6, s5, s4
- c.slli a1, 9
- lui s7, 630037
- c.srli s1, 31
- c.addi a5, -27
- c.addi a0, 23
- c.andi s0, -29
- lui s2, 752773
- auipc a5, 1036298
- srai a7, a4, 25
- sltiu a0, s2, -750
- auipc t5, 790094
- auipc a3, 516756
- c.slli gp, 19
- auipc s9, 415043
- c.addi a7, -12
- c.lui s5, 25
- c.slli s1, 8
- xor s7, s3, s9
- c.addi s0, -8
- c.slli a0, 9
- c.addi s8, 8
- c.lui a2, 22
- fence
- c.srli a0, 7
- c.addi t2, -31
- c.addi t1, -8
- c.addi s3, 16
- c.addi s3, 23
- mulhu a3, a6, s4
- xor s0, gp, s9
- c.srai a1, 27
- auipc t2, 378304
- c.lui s0, 14
- c.addi a7, -12
- sltiu zero, t4, 376
- c.srai s0, 24
- c.addi s2, -9
- c.slli s4, 21
- lui s1, 593795
- c.slli s0, 25
- c.addi gp, -16
- or a1, t4, sp
- add t3, t3, s0
- c.slli t6, 31
- auipc a1, 474962
- c.sub a2, s1
- xori s10, s10, 579
- c.lui t1, 28
- c.addi a3, 4
- c.li s9, -30
- slti t5, t2, 142
- c.srli a1, 31
- mul a3, a2, t4
- c.addi s2, -5
- c.addi s3, 11
- c.addi s5, 30
- c.addi a6, 27
- slt s4, s0, a5
- c.slli s10, 5
- c.addi a3, -2
- c.addi s1, 29
- c.addi a4, 13
- c.addi t6, 1
- c.addi a3, 31
- slli gp, a0, 17
- mul s10, a0, s9
- mul t4, t5, t0
- lui t4, 382843
- srl s6, s11, gp
- lui s1, 373058
- lui s0, 3016
- xor a6, t3, zero
- auipc s7, 63813
- c.lui a1, 2
- c.slli s3, 23
- c.srli a0, 10
- auipc s8, 113666
- fence.i
- auipc s10, 599169
- c.addi t4, 7
- c.lui a3, 11
- lui s9, 34008
- bne a3, s10, 435f
- auipc a7, 724833
-435: c.addi s4, -19
- c.addi gp, 24
- divu t1, a0, t1
- c.addi a1, -13
- lui a0, 453520
- c.addi s3, 5
- andi a7, s5, 609
- c.addi t5, 26
- c.addi a2, -4
- c.srai a5, 14
- bne s7, s4, 460f
- c.srli a3, 31
- auipc a3, 174758
- c.srli a2, 24
- auipc a5, 973182
- auipc s0, 421984
- c.lui a6, 16
- c.addi a4, 28
- c.addi s11, -6
- c.nop
- c.li gp, 12
- c.srai a1, 15
- c.xor a1, a3
- c.addi a5, -7
- c.nop
-460: lui a1, 300750
- la a1, data_page_19+2481 #start riscv_load_store_rand_instr_stream_8
- auipc a5, 191283
- lhu t4, -1053(a1)
- sh a1, -1565(a1)
- c.addi t2, 21
- c.lui a7, 9
- lbu s0, -1360(a1)
- lb s6, -899(a1)
- auipc s8, 884444
- auipc s6, 862922
- lb s4, 108(a1)
- lui s9, 198615
- sb a5, -486(a1)
- lb s3, -1160(a1)
- sltiu a6, ra, 819
- sh a0, -381(a1)
- c.addi t5, 15
- lh a0, 1407(a1)
- sb a1, 238(a1)
- c.addi s9, 10
- lb s10, -788(a1)
- c.srli a2, 27
- sw tp, -597(a1)
- lh t5, -1599(a1)
- sb a6, -759(a1)
- sb s0, -1675(a1)
- lb s4, 1082(a1)
- lhu t6, 1173(a1)
- c.lui s11, 13
- lb t3, -1379(a1)
- sb t0, -1288(a1)
- mulhsu t3, s4, t4
- c.addi t5, 21
- lb s5, 586(a1)
- c.srli a3, 7
- lb s9, 604(a1)
- lui s1, 589244
- div t2, s8, t0
- lb t3, -1347(a1)
- c.addi s9, -15
- lb t4, 1288(a1)
- sb s11, -1210(a1)
- c.addi a3, 21
- and s4, s1, a5
- c.lui s9, 3
- lh s8, 105(a1)
- sb a6, -1293(a1)
- lbu zero, -1232(a1)
- sh ra, -899(a1)
- lhu t5, -1495(a1)
- lb s2, 832(a1) #end riscv_load_store_rand_instr_stream_8
- c.slli s5, 1
- auipc s5, 4404
- c.srli a2, 5
- c.addi s2, 1
- lui s0, 667360
- c.sub s1, a0
- c.addi a1, 4
- mulh s0, s5, a4
- c.srai a3, 12
- divu s1, a0, t6
- lui s8, 252068
- lui t4, 551972
- c.srli s0, 5
- slti a0, s9, 620
- lui s7, 401881
- lui a5, 695918
- sltu s3, zero, a3
- c.addi t3, 16
- c.srli a3, 3
- lui s0, 777712
- c.addi s11, -17
- c.addi a0, 13
- c.slli s10, 5
- c.srai a0, 21
- bge s1, t6, 486f
-486: lui s4, 982320
- c.srli s1, 12
- auipc s5, 946946
- c.addi t6, 29
- c.addi s0, -32
- auipc t2, 554370
- c.srli a0, 20
- c.addi s3, -21
- c.srli a3, 5
- lui a1, 347988
- c.addi s1, 29
- c.srli a3, 31
- auipc s11, 888273
- sltu s9, s8, tp
- auipc a4, 821068
- c.srai a2, 9
- c.srai a0, 23
- srli t1, a7, 25
- auipc t5, 637433
- auipc t6, 1047547
- c.slli s1, 3
- auipc a6, 775678
- lui t2, 539869
- c.slli s9, 22
- sltiu s7, s0, -463
- c.lui s6, 24
- auipc s3, 370108
- c.srli a4, 24
- c.srli s0, 9
- c.addi s6, -15
- auipc t2, 124264
- andi s1, tp, 411
- c.lui t4, 20
- auipc s2, 93541
- c.srai a3, 7
- and s11, t4, a3
- c.addi a2, -13
- c.addi s10, -5
- lui a4, 813346
- c.addi a5, 5
- c.addi a2, -20
- c.addi a6, -11
- c.srli a5, 10
- c.srai a2, 14
- lui s3, 1033014
- c.srai a0, 17
- c.xor a1, a1
- c.addi s1, -25
- c.lui t2, 21
- c.lui t5, 28
- c.addi a1, -13
- c.nop
- lui a3, 790744
- c.addi t1, -5
- c.slli a3, 17
- c.lui s3, 26
- c.srli s0, 25
- c.bnez a2, 546f
- c.addi t5, 15
- c.slli a7, 23
-546: and s8, s2, a3
- beq s10, tp, 553f
- auipc a4, 931209
- c.slli s10, 30
- c.bnez a4, 568f
- c.addi a1, 25
- lui a6, 1017795
-553: c.slli a6, 4
- lui gp, 348999
- c.addi s11, 23
- fence
- c.slli s5, 15
- c.srai a4, 20
- c.lui t3, 16
- c.slli a4, 27
- divu s9, gp, a2
- slli a3, s9, 9
- c.addi t4, -2
- c.lui a7, 27
- c.addi gp, 6
- la s0, data_page_12+2214 #start riscv_load_store_rand_instr_stream_3
- c.lui s9, 6
- lb t1, -655(s0)
- c.slli t6, 10
- c.srli a0, 28
- sb a7, -945(s0)
- divu a2, zero, sp
- lhu a4, -170(s0)
- lb s4, 1644(s0)
- sw s1, -302(s0)
- c.sub a1, a5
- lh a7, 1412(s0)
- auipc s6, 571158
- lbu t4, -1735(s0)
- c.srai a2, 30
- c.addi t5, -10
- c.addi s8, 10
- c.addi a3, -6
- auipc s4, 846
- addi t4, s0, 686
- lhu a0, -80(s0)
- c.lui a3, 20
- c.addi t4, 10
- slti a1, s3, -764
- c.lui a0, 27
- sb s8, -490(s0)
- lui s8, 440069
- lb s8, 169(s0)
- c.srli s1, 15
- remu t1, t2, a0
- lw t2, -1694(s0)
- lui a1, 308156
- c.srai a2, 27
- sb s0, -1268(s0)
- lh a5, 1466(s0)
- c.lui a7, 19
- c.addi a4, 25
- lbu s6, 116(s0)
- c.addi s5, 19
- srl a3, t1, s8
- lui t5, 186129
- auipc s10, 953418
- c.addi s9, -4
- lbu t5, 1338(s0)
- sb s2, 867(s0)
- sltiu zero, s9, 206
- sra s9, t6, s9
- sb zero, -81(s0)
- lbu a3, 1344(s0) #end riscv_load_store_rand_instr_stream_3
- and a4, zero, a4
- c.addi s2, 29
-568: c.addi s7, 6
- c.addi s2, -20
- c.srli a2, 29
- xori t6, t5, 242
- c.addi a1, 25
- c.addi s7, 21
- c.beqz a1, 594f
- c.addi t5, -11
- lui t5, 301793
- srli t3, t0, 17
- lui t3, 817177
- c.slli t2, 29
- divu a5, s2, a1
- c.addi t3, -30
- c.addi s11, -18
- c.andi a1, -12
- c.xor s0, a4
- c.beqz s0, 605f
- c.addi s5, -14
- c.addi t4, -9
- c.srai a5, 30
- c.lui a5, 31
- addi a7, a0, 798
- c.addi gp, 26
- c.addi a2, 3
- c.addi s2, 5
-594: c.addi t3, -32
- nop
- sra zero, t4, s11
- lui a3, 197611
- c.lui a4, 22
- fence
- auipc s11, 953963
- srli a3, s3, 15
- c.slli s1, 26
- auipc s6, 369227
- beq t1, s0, 623f
-605: c.lui s5, 9
- ori a0, tp, 91
- c.addi a5, 21
- lui s7, 718281
- c.addi s10, -22
- addi s1, a5, -253
- auipc s10, 636489
- lui s10, 1030968
- lui gp, 862362
- c.lui a2, 12
- c.sub a1, a5
- c.lui t4, 25
- c.srli a5, 13
- c.addi s9, 16
- c.addi s7, -5
- lui gp, 384321
- c.srli a0, 11
- lui s9, 600434
- la s0, data_page_14+2468 #start riscv_load_store_rand_instr_stream_7
- sb a5, 1277(s0)
- auipc s10, 994330
- c.srli a5, 5
- c.sw s1, 60(s0)
- lbu t5, -1433(s0)
- lb t6, -770(s0)
- lbu t6, -1788(s0)
- lui s9, 267173
- lw t6, 1152(s0)
- c.addi s9, 6
- addi zero, t3, 694
- lb a7, -1863(s0)
- c.srai a5, 8
- lb a2, 1413(s0)
- sb t5, 33(s0)
- sw a7, 1620(s0)
- c.addi a3, 29
- lui zero, 87130
- c.srai s1, 5
- c.lw a3, 100(s0)
- lb a2, 1222(s0)
- sh s9, -1130(s0)
- sb zero, -1995(s0)
- lb t3, 1357(s0)
- lb t4, -1821(s0)
- sltu t3, a6, a6
- lh zero, 312(s0)
- c.srli a1, 30
- sb s5, 103(s0)
- lbu s6, -1226(s0) #end riscv_load_store_rand_instr_stream_7
-623: c.slli a1, 31
- c.addi gp, 10
- c.srli a4, 26
- lui s4, 666080
- c.srai a0, 6
- c.mv s8, ra
- c.srai a3, 20
- c.srli s1, 28
- c.slli s11, 29
- c.addi s7, -9
- c.lui a1, 15
- c.addi s8, 25
- c.srai a3, 9
- c.srli s0, 3
- c.srli a1, 5
- c.li a5, 12
- c.addi t4, -13
- auipc s6, 468969
- auipc s1, 259499
- la t4, data_page_6+2683 #start riscv_load_store_rand_instr_stream_0
- lui s0, 210517
- lb s6, -1578(t4)
- sb s3, 1020(t4)
- sltu a4, a1, s1
- lui s4, 418110
- auipc s6, 1026683
- c.slli s9, 26
- auipc s8, 1034627
- c.li a4, 14
- c.lui t2, 21
- c.addi a2, -14
- c.slli a7, 4
- c.addi a5, 11
- sub a1, t1, s11
- auipc s1, 168359
- auipc s3, 705571
- c.addi a3, 19
- lhu a7, 629(t4)
- lui s11, 95510
- c.addi a0, 16
- c.slli s3, 6
- c.srai s0, 5
- lb s1, -318(t4)
- lbu s0, 1392(t4)
- c.addi s3, 24
- c.srai a1, 26
- auipc t5, 190162
- c.addi t3, 19
- lb s4, -958(t4)
- lbu a5, -1451(t4)
- lui a5, 107854
- c.lui s0, 6
- c.addi a6, -5
- sb zero, 269(t4)
- lui s10, 399921
- sb s2, -1414(t4)
- sb s2, 432(t4) #end riscv_load_store_rand_instr_stream_0
- lui a7, 140159
- lui t6, 142506
- slti s2, ra, -705
- lui s1, 702685
- c.or s0, a1
- c.lui s11, 26
- c.addi s8, -16
- auipc s7, 135311
- auipc a2, 719063
- xor a6, sp, gp
- c.lui t5, 20
- c.slli a2, 14
- mulh s5, t6, a5
- c.addi t6, -7
- rem a6, s5, a4
- c.and a1, s1
- c.srli a2, 18
- auipc s1, 279791
- fence.i
- c.slli t3, 6
- c.srli a0, 4
- c.lui gp, 12
- c.srli a0, 11
- c.addi s6, 6
- slti t6, a1, 460
- lui s5, 191580
- add s7, s10, s0
- c.srai a2, 14
- c.addi a1, 13
- c.addi a5, -25
- lui t3, 951345
- c.lui a2, 23
- c.bnez s1, 682f
- lui t3, 459971
- div gp, t0, t0
- lui s8, 853177
- c.addi s7, 8
- ori a7, s11, 1021
- divu t1, zero, a7
- c.addi a6, -3
-682: c.addi a0, -26
- lui s1, 1015170
- auipc t1, 714368
- srl s3, s8, t0
- auipc s8, 59292
- c.slli a5, 22
- divu t6, s1, s5
- c.addi s0, 21
- c.lui t1, 31
- mulh t6, s1, a5
- c.slli a6, 20
- c.slli s5, 26
- c.srai s0, 14
- andi s6, s9, 166
- la gp, data_page_11+2517 #start riscv_load_store_rand_instr_stream_10
- sb gp, -1335(gp)
- c.addi a3, -7
- lui a2, 264901
- lbu t3, 625(gp)
- c.lui t2, 12
- lui s11, 818141
- sb a1, -887(gp)
- sb t1, 1521(gp)
- lui a6, 241328
- sb zero, 814(gp)
- sb s5, -1988(gp)
- auipc t4, 826958
- lb a6, -345(gp)
- auipc a4, 499204
- c.srli a0, 23
- sb a3, 1466(gp)
- sb s5, 986(gp)
- c.addi s11, -26
- lb s6, -1716(gp)
- c.lui t2, 2
- auipc t1, 324575
- c.addi s2, -12
- divu t4, a3, s2
- auipc t5, 851210
- lw zero, -97(gp)
- divu a6, s7, s11
- sh a7, -541(gp)
- lbu a4, -520(gp)
- sh a0, 1105(gp)
- lbu a4, -154(gp)
- sb s7, -754(gp)
- lbu a3, 570(gp)
- lbu a6, 1008(gp)
- sb s3, 549(gp)
- lb zero, -2040(gp)
- lb s9, -894(gp)
- c.addi s6, -20
- sb a1, -594(gp)
- c.lui s9, 28
- lhu a0, -1833(gp)
- lbu a3, -1565(gp)
- lhu s6, -87(gp)
- sb s8, 653(gp)
- c.slli a2, 19
- sb a1, 177(gp)
- c.srli a2, 10
- c.addi s2, -23
- c.srai s0, 19
- sb s7, 161(gp)
- lb s1, -736(gp)
- sb a5, -1978(gp) #end riscv_load_store_rand_instr_stream_10
- c.lui s6, 9
- slti s0, a5, -329
- auipc s8, 671326
- c.addi gp, 11
- c.srai a2, 9
- c.slli s0, 17
- c.andi s1, 26
- c.lui a6, 18
- c.srli s0, 8
- c.srli a0, 27
- auipc zero, 94912
- auipc s2, 429313
- c.srai a3, 6
- lui a3, 73132
- c.sub a3, s0
- and s8, t6, t6
- lui a2, 838514
- lui s11, 91999
- lui s1, 363789
- c.addi s3, 14
- c.andi a1, 23
- c.addi t4, 2
- c.nop
- auipc s4, 435059
- lui t6, 418643
- c.addi t5, 28
- auipc s2, 244757
- fence.i
- c.srai a4, 2
- beq t0, s3, 729f
- c.lui a2, 25
- c.addi t4, 29
- auipc a0, 329504
-729: c.slli t3, 13
- c.addi s6, -24
- c.srli a2, 30
- c.andi s1, 21
- c.mv s3, s1
- lui s2, 441743
- auipc a4, 256952
- c.srli s1, 25
- auipc a0, 380780
- c.addi s2, 6
- lui s2, 21214
- auipc s5, 760982
- auipc s6, 798681
- c.slli a3, 8
- c.addi a7, 2
- c.srli a1, 20
- c.lui s4, 23
- c.addi s4, -30
- c.addi gp, -15
- mulhsu s5, s6, a6
- c.lui a0, 25
- c.lui t2, 8
- blt s7, zero, 769f
- add t5, s0, s0
- lui s2, 113600
- auipc s2, 703225
- c.srli a4, 21
- mulhsu a7, s8, t4
- sub s1, t3, s6
- sll a5, s1, s7
- lui a4, 58276
- lui s4, 41495
- c.slli s9, 5
- c.or a3, a3
- c.addi gp, 30
- c.nop
- c.lui a6, 2
- c.addi gp, 10
- c.addi s6, -10
- c.addi t4, 26
-769: mulhu a5, t6, t5
- auipc t4, 158209
- or a4, s5, s10
- c.addi a1, 15
- auipc a1, 808002
- bge s3, zero, 782f
- and t2, s0, t3
- c.addi s7, 17
- c.addi a2, 8
- la t4, data_page_19+1386 #start riscv_load_store_rand_instr_stream_9
- auipc s1, 92293
- sb a4, 534(t4)
- c.srli a4, 29
- lui s0, 427202
- sb s0, 1175(t4)
- lb s10, 1650(t4)
- sb zero, -1307(t4)
- sh ra, 300(t4)
- lui t2, 574006
- lhu zero, 844(t4)
- slt s1, s1, s3
- lh a6, 56(t4)
- sh sp, 1862(t4)
- lw a6, 470(t4)
- lui s5, 796712
- c.srai a2, 15
- lui t5, 296372
- lh gp, 116(t4)
- c.addi s4, -25
- auipc t5, 109422
- c.addi a0, -10
- lb s6, 988(t4)
- c.srai a2, 6
- lui s5, 648961
- c.slli s1, 13
- sb a4, 43(t4)
- lb s8, 501(t4)
- lbu s9, 324(t4)
- lb a2, -337(t4)
- c.add a1, s0
- lhu s10, 950(t4)
- lh a0, -686(t4)
- and s6, t6, a7
- sh a0, -798(t4)
- add t3, s5, t5
- auipc a1, 136849
- div gp, a6, a1
- mulhu s4, s4, a6
- c.srai a5, 29
- lui s1, 322865
- lbu a5, 1366(t4)
- sb a1, 1191(t4)
- lbu a5, 743(t4) #end riscv_load_store_rand_instr_stream_9
- c.addi s5, 22
- c.addi a3, 29
- c.addi gp, -18
- c.mv s3, a5
-782: bne t4, s0, 794f
- auipc t4, 420366
- mul a4, s7, a7
- auipc gp, 1000316
- auipc a5, 955631
- sll s6, ra, a1
- auipc a6, 29054
- c.or s0, a5
- c.bnez s0, 805f
- c.srli a1, 13
- c.addi t5, -24
- c.lui a3, 26
-794: c.addi gp, 3
- div zero, t4, a2
- c.andi a5, -16
- c.addi a6, -31
- c.addi s6, 18
- auipc s6, 712142
- add gp, a2, a1
- c.slli a5, 22
- sub t1, a3, s7
- c.addi a1, 3
- c.srai a0, 20
-805: c.srai a0, 6
- c.addi t1, -5
- c.addi a2, 19
- c.lui s7, 2
- lui s5, 986505
- c.addi t3, -23
- bgeu tp, sp, 825f
- lui a3, 560411
- c.slli t5, 6
- c.addi a5, 30
- c.addi s1, -1
- c.slli t4, 12
- beq ra, a2, 821f
- auipc zero, 644120
- lui a7, 929037
- mulhu t1, a6, t1
-821: auipc a0, 659441
- c.addi s5, -13
- c.and s1, a4
- c.lui a2, 16
-825: c.srli a4, 24
- c.mv s10, t2
- c.lui a1, 20
- c.addi a2, 6
- ori s3, s5, 672
- remu s11, s2, s2
- c.addi s8, 10
- c.addi t6, -23
- lui s4, 34579
- auipc t4, 787194
- c.addi s7, 10
- auipc t2, 277338
- auipc zero, 66789
- lui gp, 572861
- lui s4, 231713
- c.bnez a2, 858f
- c.srli a2, 14
- c.addi t6, -26
- auipc a7, 405994
- mulhu s2, a7, a1
- c.addi s4, 7
- srai a6, s10, 19
- auipc s9, 230715
- c.addi a5, -32
- c.addi t5, -31
- bgeu s4, s11, 858f
- lui a4, 144163
- lui s2, 592796
- c.slli s11, 22
- c.srli a0, 20
- auipc gp, 190133
- c.slli a5, 3
- c.or s1, a4
-858: srli s6, t4, 29
- c.addi s3, 4
- c.addi s10, -6
- c.addi s3, -20
- c.addi a6, -18
- auipc s0, 356994
- lui s8, 74376
- c.andi s1, -21
- c.addi t1, -21
- c.lui a2, 24
- c.srli a0, 23
- c.srli a0, 2
- c.addi a1, 18
- c.slli s10, 20
- mulh t2, t3, zero
- c.and a4, s0
- c.and a2, a5
- lui gp, 838147
- c.or s1, a4
- lui s0, 112447
- c.srai a1, 2
- lui t2, 549559
- auipc t1, 570371
- mulh a1, a6, t2
- c.addi s7, 25
- auipc t4, 735893
- c.addi a7, -31
- c.slli a6, 11
- c.addi s8, 9
- c.addi a4, -6
- c.srai a2, 17
- c.srli a5, 28
- add s8, t1, t2
- sltiu t2, s1, 881
- auipc t1, 157160
- slt t1, t4, t6
- c.srai a0, 8
- slt s2, gp, s4
- divu s3, s6, sp
- c.li gp, -32
- c.slli a3, 10
- c.addi a6, 25
- c.slli a7, 8
- c.addi s10, 10
- or s5, s3, a2
- addi t4, a7, 285
- lui a7, 547233
- lui s8, 432116
- c.srli a3, 4
- c.srai s1, 26
- c.srli a4, 27
- sltiu t5, a3, -95
- c.lui a4, 30
- c.or a3, a4
- c.srai a1, 30
- c.slli a6, 21
- c.lui a6, 7
- auipc t3, 638464
- auipc a0, 688798
- c.lui s10, 31
- remu s1, s8, t3
- lui a0, 706906
- fence.i
- c.srli s1, 12
- c.addi s1, 31
- c.nop
- c.addi s3, 18
- and s7, s9, s7
- c.addi s7, -13
- c.slli s9, 14
- auipc s9, 800182
- auipc s6, 528664
- lui s10, 120824
- c.srli a4, 25
- auipc s7, 320182
- c.addi a6, 9
- bgeu s6, t1, 939f
- srai t5, gp, 14
- c.srli a5, 25
- c.addi s1, 30
- c.slli t6, 31
-939: div a3, t5, s2
- c.and a1, a3
- c.add s0, a4
- c.lui s10, 7
- c.slli s9, 25
- auipc t2, 270788
- auipc a6, 800165
- lui t5, 971953
- c.bnez a5, 950f
- bltu tp, s5, 967f
- srai s11, a6, 30
-950: lui zero, 705352
- c.lui s2, 29
- c.slli t6, 12
- c.slli s2, 9
- la a3, data_page_13+1933 #start riscv_load_store_rand_instr_stream_5
- sw t6, -141(a3)
- lb s10, 1925(a3)
- auipc t3, 396639
- sb s4, 1998(a3)
- c.addi t3, -10
- c.or a1, a2
- sb a1, 431(a3)
- lb s11, 952(a3)
- sw gp, -1425(a3)
- lb a1, 245(a3)
- lb a5, -1392(a3)
- lbu t4, 384(a3)
- sb s3, -1088(a3)
- remu s6, a2, a2
- lbu a6, -712(a3)
- sb s8, 863(a3)
- c.addi gp, 9
- c.slli t5, 18
- lb t1, -1124(a3)
- lui a0, 841237
- lw t4, -1829(a3)
- lb s3, 1634(a3)
- sb s1, 1389(a3)
- sb a6, -1833(a3)
- lbu a7, 1642(a3)
- lb a6, 1367(a3)
- sub t5, s6, zero
- andi s6, sp, 415
- lhu a5, -1579(a3)
- c.srai a0, 23
- lb a2, -1192(a3)
- sh s9, 1507(a3)
- lbu a0, 922(a3)
- lbu t4, 366(a3)
- auipc zero, 411753
- lw s4, 263(a3)
- sb s2, 1422(a3)
- c.slli t2, 18
- sb ra, -1196(a3)
- lh a7, 491(a3)
- c.or a1, s1
- lb t3, 1938(a3) #end riscv_load_store_rand_instr_stream_5
- c.addi s8, -30
- auipc a7, 129552
- c.addi s7, -7
- c.addi s7, -8
- fence
- c.srai a2, 1
- c.addi a3, 20
- auipc t2, 902484
- c.lui a6, 26
- c.srai a3, 31
- auipc a2, 84707
- auipc t2, 295356
- c.lui a2, 30
-967: lui s1, 151341
- lui gp, 990002
- c.addi a1, -2
- remu a6, a5, a2
- auipc s8, 692726
- c.addi t1, 31
- c.srli a3, 25
- c.slli s4, 30
- lui a3, 743252
- c.addi s4, 4
- c.lui s8, 4
- c.addi a2, 23
- lui a1, 344571
- bltu s10, t6, 988f
- auipc s2, 199215
- c.addi a3, -16
- lui zero, 58022
- c.addi a5, 14
- auipc a3, 625863
- c.addi t2, 14
- auipc a4, 689965
-988: c.addi gp, 19
- c.lui t4, 22
- c.srli a4, 26
- c.lui a0, 29
- lui gp, 171972
- c.slli s3, 7
- c.addi a5, 19
- c.addi s2, -32
- c.srai a0, 26
- divu s10, gp, a7
- c.srai a1, 16
- c.addi s1, -17
- c.srli s0, 5
- c.srli a1, 23
- auipc zero, 420876
- c.lui s8, 26
- c.srai a0, 28
- auipc s8, 424396
- c.addi s2, 25
- lui a7, 271594
- c.addi s1, 5
- bge s8, ra, 1011f
- auipc s3, 111701
-1011: c.slli t2, 25
- c.addi t5, 21
- c.lui s2, 21
- c.addi a5, -26
- c.lui s10, 5
- c.lui s9, 27
- mulhu s3, a2, a4
- c.addi gp, 14
- beq a7, t6, 1032f
- auipc s6, 397841
- srli t6, s0, 30
- c.srli a5, 9
- lui s7, 899350
- fence.i
- c.addi s5, -29
- c.slli s10, 6
- srai a2, s2, 28
- slli a3, s10, 0
- c.srai s0, 28
- c.addi s4, -32
- mul gp, t1, tp
-1032: lui a7, 66735
- auipc a1, 646217
- c.addi s4, -6
- auipc zero, 51508
- c.addi gp, 10
- c.lui s2, 7
- c.addi t5, -24
- c.slli s9, 12
- srl s11, sp, s4
- c.addi s4, -18
- auipc t3, 971276
- c.srli a3, 23
- auipc a1, 987132
- xori gp, a3, -67
- c.lui s7, 23
- xori a2, gp, -16
- c.lui s5, 21
- c.addi s9, -21
- c.addi t1, -31
- c.slli s5, 13
- addi s1, a5, -85
- auipc s11, 34531
- auipc a7, 38922
- c.lui a5, 18
- c.addi t5, -19
- c.srai a0, 18
- mulhu s10, t1, t1
- c.lui t6, 2
- auipc a7, 326963
- lui s9, 659275
- c.srli a4, 2
- auipc a2, 557043
- auipc t4, 755606
- lui a4, 877548
- c.lui s3, 31
- fence
- lui s1, 945955
- c.srai s0, 16
- c.addi s8, 2
- lui s1, 404259
- slt s1, s10, s3
- sltiu t5, t6, 763
- c.addi s10, 2
- srli t5, a1, 2
- c.addi t5, -2
- lui t3, 830401
- c.addi s4, -6
- lui t5, 639418
- ori s7, a4, 27
- c.slli t4, 10
- auipc s8, 421192
- c.srli s1, 6
- add s4, ra, t5
- c.srai a5, 18
- sltu s9, a3, a5
- c.slli s8, 15
- auipc a3, 806516
- c.addi s11, -16
- sll s3, t4, s5
- c.addi s6, 20
- lui t5, 425495
- c.nop
- c.slli a4, 14
- c.li a0, -10
- c.srai a3, 24
- lui s0, 50202
- c.addi s1, 24
- c.or a4, a4
- divu s10, s6, t6
- la s9, data_page_1+1793 #start riscv_load_store_rand_instr_stream_2
- c.addi s8, -1
- c.addi t1, 25
- lhu s5, -521(s9)
- lbu s11, 1539(s9)
- andi s1, a1, 115
- lb s4, 558(s9)
- lbu s1, -1574(s9)
- lb t1, 1378(s9)
- lb s3, 393(s9)
- lb s1, 2030(s9)
- sh t1, -801(s9)
- sb s10, -860(s9)
- lh a1, 933(s9)
- ori a4, a5, 783
- c.addi s11, 13
- c.or a2, a3
- c.addi t2, 18
- sltu a2, s8, s5
- c.slli t6, 5
- lb a3, 1210(s9)
- sb sp, -794(s9)
- sltu t5, sp, s7
- rem t1, a5, s6
- lui s10, 669637
- sb a5, 1072(s9)
- lbu zero, -138(s9)
- sb gp, 288(s9)
- srli s1, tp, 23
- lbu s7, 1888(s9)
- c.lui a6, 8
- auipc t6, 650938
- c.addi a0, 5
- c.srai a0, 19
- c.slli a2, 8
- lui a0, 797472
- sb a5, -1406(s9)
- c.addi a1, -21
- lhu s1, -779(s9)
- c.srli a0, 3
- sltiu t1, s8, 223
- c.srli s1, 30
- sll s1, t2, a2
- sh s9, 1215(s9)
- c.srli a3, 14
- lbu t5, -11(s9)
- lh t1, 243(s9)
- lbu t2, -68(s9) #end riscv_load_store_rand_instr_stream_2
- c.addi a6, -8
- mulhsu t5, s10, sp
- lui s0, 692758
- lui a4, 125600
- auipc a0, 1041390
- c.addi s0, -30
- c.slli a5, 31
- c.andi s1, 6
- c.addi s2, 30
- c.addi t1, -7
- c.srai a0, 19
- bne s7, tp, 1131f
- lui a0, 267637
- c.addi a6, 27
- c.slli s4, 16
- c.srai a4, 25
- c.srai a5, 26
- c.addi a1, -3
- c.addi a3, -11
- c.srli s0, 16
- c.srai a2, 10
- xori a3, s0, 793
- c.lui t1, 8
- c.srai a5, 1
- c.slli a0, 25
- sltiu a3, s1, 210
- c.addi s1, -14
- c.srai a2, 9
- slti s10, s6, -177
- auipc s3, 724233
-1131: lui a4, 850562
- c.or a1, a1
- c.lui s1, 17
- c.srli a2, 12
- c.addi s4, 23
- and a1, s10, s3
- lui t5, 560417
- c.slli s10, 30
- lui s6, 816578
- c.addi t2, -25
- lui s3, 740890
- c.srli a0, 21
- auipc t2, 585615
- c.slli s10, 20
- and t4, s10, a1
- lui s3, 717872
- c.and s1, a0
- auipc t3, 36024
- c.addi s7, -6
- srl s5, s10, t0
- c.addi t1, 6
- c.addi s2, -19
- c.bnez s0, 1160f
- lui a6, 314327
- auipc zero, 234042
- c.andi a5, -14
- div a6, t6, a5
- c.addi t6, -13
- divu s6, t2, s9
-1160: c.addi s10, 26
- c.srli a2, 25
- auipc s4, 57376
- fence
- auipc s5, 533101
- bne a7, a3, 1171f
- c.addi s7, 8
- mulhu s8, t4, s4
- c.addi t5, -7
- lui s8, 132279
- c.addi s0, -28
-1171: c.addi s4, -17
- auipc s4, 421931
- c.addi s2, 25
- lui a7, 961171
- c.srai a1, 19
- c.addi s2, 6
- c.addi a7, -30
- c.addi a1, -28
- xor t6, sp, zero
- srli a0, a7, 1
- c.lui s1, 14
- slt s7, t6, s2
- c.srli s0, 13
- lui s9, 150906
- c.sub a1, a4
- c.srai a2, 3
- c.addi s5, 2
- c.addi s5, -31
- c.srai a1, 16
- c.srai a2, 6
- lw ra, 4(sp)
- lw t0, 8(sp)
- addi sp, sp, 24
- add a0, s11, a6
- c.srai a0, 19
- auipc t3, 997852
- c.addi t6, 8
- c.srai a0, 17
-1706: ret
-init_machine_mode:
- li a0, 0x581900
- csrw 0x300, a0 # MSTATUS
- li a0, 0x0
- csrw 0x304, a0 # MIE
- mret
-write_tohost:
- sw gp, tohost, t5
-
-_exit:
- j write_tohost
-
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-.word 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000
-.word 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000
-.word 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000
-.word 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000
-.word 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000
-.word 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000
-.word 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000
-.word 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000
-.word 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000
-.word 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000
-.word 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000
-.word 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000
-.word 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000
-.word 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000
-.word 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000
-.word 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000
-.word 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000
-.word 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000
-.word 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000
-.word 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000
-.word 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000
-.word 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000
-.word 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000
-.word 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000
-.word 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000
-.word 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000
-.word 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000
-.word 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000
-.word 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000
-.word 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000
-.word 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000
-.word 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000
-.word 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000
-.word 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000
-.word 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000
-.align 4;
-.align 5
-_user_stack_start:
-.rept 4999
-.4byte 0x0
-.endr
-_user_stack_end:
-.4byte 0x0
-_kernel_start: .align 12
-smode_accessible_umode_program:beq a0, tp, smode_accessible_umode_program_stack_p
-smode_accessible_umode_program_stack_p:addi sp, sp, -16
- slti s9, s2, 285
- sw ra, 4(sp)
- sw t0, 8(sp)
- c.srli a4, 27
- c.and a0, a2
- c.mv gp, a1
- and t2, zero, s10
- c.addi s5, 2
- andi s11, t0, -859
- c.add a3, a0
- c.addi a1, 26
- slt t1, s4, t2
- c.addi a7, -8
- bltu s7, ra, 21f
- c.addi s10, -31
- auipc a0, 708382
- auipc s9, 115845
- lui a4, 517715
- c.srai s1, 17
- auipc s6, 944678
- c.srai s0, 25
- c.bnez a2, 32f
- c.lui t5, 4
- c.lui s5, 9
- auipc t6, 1000076
- c.srli a2, 9
- c.addi t1, -28
- addi s5, gp, -263
- nop
-21: c.addi s7, -10
- c.addi s10, 27
- c.srli a4, 26
- c.addi t2, 4
- c.lui s3, 12
- c.srai s1, 4
- lui s8, 377736
- lui s10, 12008
- slli s8, a1, 29
- c.srai a3, 31
- c.srli a0, 5
-32: c.addi s0, 5
- lui s10, 112575
- c.slli t6, 2
- auipc a1, 796427
- c.addi t2, -26
- c.srli s1, 26
- blt s1, a0, 40f
- c.addi s6, 13
-40: c.srai s1, 18
- c.slli t6, 31
- lui s7, 732899
- mulhu a7, sp, zero
- c.addi t4, 21
- c.li s1, -16
- c.slli s2, 4
- xori a2, s6, -549
- c.addi a7, 5
- c.addi s9, 21
- c.addi a7, 9
- c.addi a4, -1
- auipc t4, 656888
- c.addi a5, -19
- and s11, sp, zero
- c.slli s4, 3
- nop
- c.addi t5, -22
- c.srli a0, 5
- c.slli t3, 8
- auipc a2, 381305
- lui s1, 792774
- c.slli s0, 1
- c.addi a2, -29
- c.addi a6, 28
- c.lui a2, 7
- c.beqz s0, 73f
- beq s11, ra, 84f
- c.srai a3, 14
- lui s6, 471083
- auipc s1, 777529
- bne t0, t6, 86f
- sltu a4, a4, t6
-73: sub t4, s5, t3
- c.srai a4, 15
- c.srli a0, 23
- xori a5, zero, -580
- c.lui s8, 16
- c.srli a0, 8
- c.xor a4, a1
- c.addi t5, 12
- c.addi t5, -30
- auipc s10, 201137
- c.addi s9, 27
-84: lui s3, 30957
- lui zero, 30375
-86: c.addi a5, 25
- bne tp, s7, 88f
-88: c.addi gp, 22
- or zero, t3, s11
- c.addi s4, 24
- c.slli t3, 15
- c.addi s0, -24
- c.addi a4, 15
- lui s0, 622620
- and s2, a6, s7
- auipc t1, 321490
- c.addi a6, 22
- c.srli a2, 24
- lui s6, 326530
- lui s4, 364587
- c.addi s11, -20
- lui t4, 964916
- auipc a6, 761314
- lui a7, 819076
- c.addi t5, -9
- c.addi a3, 16
- c.slli s8, 23
- div s6, s0, s11
- c.slli a2, 2
- c.srai a2, 3
- la a7, kernel_data_page_0+1464 #start riscv_load_store_rand_instr_stream_0
- sh a7, 1774(a7)
- auipc t4, 522543
- c.add a0, s1
- lbu t6, -1456(a7)
- c.srli s1, 30
- lb t2, -809(a7)
- lbu s9, -935(a7)
- c.addi t2, 23
- auipc s3, 163451
- c.srai s0, 2
- c.lui s8, 6
- lbu s7, 1314(a7)
- c.lui gp, 26
- remu s5, a7, s0
- lui s10, 155164
- lh s9, 1158(a7)
- lh gp, -322(a7)
- c.srli a4, 22
- c.addi s5, 18
- c.addi s9, 18
- auipc zero, 689249
- lui t2, 988798
- c.addi a6, 15
- auipc t1, 409029
- c.and a4, s0
- xori a5, s8, -624
- lh s4, 26(a7)
- sh s10, 1120(a7)
- c.srli a4, 24
- c.lui t5, 22
- c.lui s1, 9
- auipc a5, 206043
- c.addi a0, -17
- andi t6, a1, -290
- c.addi a1, 9
- sll s1, s5, ra
- lbu s8, 1643(a7) #end riscv_load_store_rand_instr_stream_0
- c.addi s8, -9
- auipc s8, 410673
- c.slli s3, 13
- mulh s4, a2, gp
- c.addi s9, -20
- c.lui s11, 13
- c.lui a0, 26
- c.li t1, -27
- c.andi a2, 23
- xori s8, s1, -711
- beq s6, s8, 132f
- c.srai a4, 18
- c.srai a5, 28
- xori t1, a7, 270
- sub a3, s4, a0
- sub zero, s0, a2
- beq s8, s5, 132f
- xor t6, s3, tp
- auipc a4, 272489
- c.srai s0, 16
- c.addi t2, 27
-132: c.addi s3, 22
- srli s3, a7, 17
- c.addi a0, 21
- c.addi a0, 29
- auipc t4, 248703
- c.addi s11, -16
- sltiu a2, s2, 648
- c.addi a7, 12
- rem s11, t1, s4
- c.addi s7, 27
- divu gp, s1, a6
- srai s10, a3, 21
- c.addi a3, -13
- blt s6, sp, 165f
- auipc a7, 314790
- c.addi t6, -22
- slt a6, t4, s7
- auipc a1, 146879
- sra t2, tp, s7
- rem s1, a6, sp
- lui s5, 688607
- c.srli s1, 15
- c.srai a2, 25
- auipc t3, 193745
- c.lui s11, 22
- c.srai a1, 12
- lui a5, 259171
- c.slli a3, 25
- lui s11, 241725
- c.slli s2, 13
- c.addi gp, 8
- xor s3, zero, a6
- c.srai s1, 18
-165: c.srli a4, 11
- auipc t5, 444694
- divu s1, s4, s0
- c.srai s0, 23
- xor s11, a1, s10
- c.lui s11, 11
- c.srai a3, 21
- c.addi s0, -29
- c.addi s5, -1
- c.slli a4, 25
- c.lui a4, 26
- lui t6, 550287
- c.addi s1, 3
- c.addi a6, -21
- c.addi t3, 2
- auipc s1, 1011668
- auipc a5, 698744
- c.lui t5, 25
- c.lui t6, 13
- c.srli a5, 23
- rem a1, s0, s1
- c.addi s2, -18
- c.addi a3, 22
- c.srli s1, 2
- sub s5, ra, s0
- c.srai s1, 5
- bge a0, sp, 193f
- sub a2, s0, a4
-193: lui s11, 962634
- c.addi s10, -11
- or zero, t3, s8
- c.srai a0, 12
- la a4, kernel_data_page_1+2745 #start riscv_load_store_rand_instr_stream_3
- srli s10, t6, 10
- lbu t4, 636(a4)
- sb s3, 373(a4)
- c.srli a2, 26
- c.or s1, s1
- c.addi s1, 6
- c.addi t5, 31
- auipc t2, 668207
- c.addi a7, 1
- lh a7, 985(a4)
- c.srli a0, 28
- lb zero, -1814(a4)
- sltu a1, t6, s2
- lh t5, -1843(a4)
- lb a6, 885(a4)
- lb zero, -1805(a4)
- c.addi a7, -15
- c.slli s11, 2
- sb s2, -1790(a4)
- c.addi s2, 31
- fence
- andi a5, a2, 698
- lhu s0, -2039(a4)
- c.srai a5, 28
- sb t5, 509(a4)
- mul s9, s0, s2
- c.addi a2, 28
- c.slli s7, 27
- c.addi t4, -2
- c.addi s3, -20
- c.addi a3, 15
- c.addi t2, -1
- lb s8, -936(a4)
- sb t6, -34(a4)
- c.srai a0, 14
- c.lui a0, 4
- sh s9, -647(a4)
- lui s1, 645195
- sh s8, -297(a4)
- lui a6, 249393
- lhu t5, 1221(a4) #end riscv_load_store_rand_instr_stream_3
- c.lui t6, 18
- c.lui a6, 22
- auipc s11, 436868
- c.slli t5, 28
- rem t2, s5, a3
- c.or a3, a4
- addi t1, t6, -904
- sll s5, t6, t5
- slli s10, s8, 3
- lui s3, 645628
- c.srai a1, 19
- c.addi s3, 4
- c.addi s6, 25
- la a3, kernel_data_page_0+2537 #start riscv_load_store_rand_instr_stream_2
- lbu a0, 1533(a3)
- lb a5, -762(a3)
- sb s2, 144(a3)
- c.or a0, a3
- sltu a7, t0, gp
- lbu s4, -1956(a3)
- add s8, t1, tp
- lb s7, -1654(a3)
- sb s8, -765(a3)
- lh s4, -1997(a3)
- lb s1, 1002(a3)
- c.slli a6, 4
- c.addi t1, 6
- sb tp, -802(a3)
- c.srai a4, 23
- lui a4, 262474
- lb s10, -586(a3)
- lbu s1, 292(a3)
- lb s11, -757(a3)
- sh t3, -799(a3)
- sw t4, -105(a3)
- lb s0, 346(a3)
- lbu a0, -1971(a3)
- c.addi a2, -31
- c.lui s6, 14
- lui s8, 860298
- lb t3, 1418(a3) #end riscv_load_store_rand_instr_stream_2
- lui s1, 344664
- auipc a2, 904143
- c.addi t3, -21
- c.addi t5, -23
- auipc s11, 343901
- add s6, zero, a5
- slti a6, s4, 37
- auipc a1, 631189
- c.srai s1, 15
- la s7, kernel_data_page_1+2281 #start riscv_load_store_rand_instr_stream_1
- c.addi t4, -8
- auipc s6, 198280
- auipc s0, 800727
- c.lui s5, 19
- auipc a6, 728725
- sb sp, 268(s7)
- c.slli s5, 26
- lb zero, -652(s7)
- c.addi t4, -11
- lb a6, -214(s7)
- sb s10, 1668(s7)
- c.srai a1, 26
- auipc t1, 306634
- c.mv s3, s2
- c.addi a7, -14
- c.addi s8, 24
- c.and s1, s0
- lbu t1, 556(s7)
- c.xor a0, s1
- lbu t2, -1372(s7)
- c.addi s9, 24
- sb t0, 188(s7)
- c.slli s6, 11
- sb s1, -249(s7)
- c.addi t5, -14
- c.li a6, 21
- sb s8, -745(s7)
- c.srai a4, 15
- auipc s5, 597192
- add s5, a3, a3
- lh a7, -1005(s7)
- auipc zero, 349376
- sub a4, a6, a0
- lbu a3, 53(s7)
- auipc a1, 323523
- c.addi a0, 21
- c.addi s6, -6
- lui s10, 339222
- c.addi a6, 17
- lh s11, -1935(s7)
- lbu s8, -1008(s7)
- lb a4, -426(s7) #end riscv_load_store_rand_instr_stream_1
- auipc s7, 731599
- lui zero, 342309
- c.addi s9, -4
- auipc a2, 209561
- auipc s6, 172073
- c.addi t5, -2
- lui a3, 541333
- andi t2, s2, -735
- c.lui t4, 11
- bge s6, s9, 244f
- auipc s10, 988590
- xori s7, s2, 861
- c.add a2, a4
- c.nop
- auipc s3, 618873
- c.lui s10, 30
- auipc a7, 411801
- c.srai a1, 5
- auipc s11, 94283
- c.addi s8, 12
- c.srli a3, 27
- lui s6, 391376
- srli a6, t1, 23
- c.srli a5, 20
- auipc t4, 249893
-244: c.sub a5, a5
- auipc s1, 985670
- c.lui s0, 1
- c.addi a5, -8
- c.addi a2, 22
- fence
- c.addi a3, 26
- sub gp, zero, t1
- c.lui a6, 15
- c.srli a2, 5
- auipc s3, 810267
- auipc a4, 372737
- lui t1, 173595
- addi s11, s9, 144
- c.srli a2, 1
- lui gp, 785757
- c.srai a2, 9
- c.lui t2, 11
- c.addi s3, 2
- sltiu t3, s1, 574
- c.slli t4, 21
- lui t3, 466465
- slt a2, s11, t5
- c.xor a3, a0
- c.li t3, 31
- c.lui t3, 2
- div a2, a1, tp
- c.lui s0, 12
- lui a1, 598810
- c.addi a1, 23
- auipc a2, 840977
- c.addi t5, -25
- auipc s0, 1013910
- c.addi s4, -2
- c.lui s5, 9
- c.nop
- srai t2, s4, 30
- c.xor a5, a1
- c.lui a6, 18
- divu s9, zero, s4
- lui s2, 5037
- bne s8, t0, 305f
- c.lui s10, 4
- c.lui t1, 24
- auipc a0, 287641
- c.slli s6, 17
- auipc t5, 10161
- rem t5, t5, t0
- xor s0, s2, s6
- c.srai a1, 8
- c.srai s0, 23
- c.add a4, a2
- auipc s5, 941473
- c.addi a4, -15
- c.addi s0, 6
- c.addi s3, 27
- lui s5, 132551
- c.srli a4, 16
- lui a7, 455126
- or a5, a3, a2
- add t6, a6, a1
-305: c.addi s8, 25
- auipc s7, 177074
- add a0, gp, s3
- c.addi s9, -27
- lui s7, 998327
- auipc s10, 334964
- andi t3, s4, 468
- c.addi a4, 10
- c.addi s10, -18
- lui t4, 540712
- c.addi t4, -3
- c.xor a0, s1
- lui t1, 756499
- c.srli a5, 22
- c.srai s0, 23
- c.srai s1, 3
- c.srli s1, 20
- auipc a1, 571505
- c.addi a4, -19
- lui s6, 901152
- auipc s0, 924399
- auipc s11, 115717
- c.addi s8, -4
- c.srli a2, 25
- lui t3, 94061
- c.addi s1, -20
- lui gp, 320155
- c.srli s0, 24
- c.addi a1, 3
- c.srli a1, 19
- auipc t1, 785078
- c.addi t4, -20
- lui a0, 792132
- c.addi t6, -19
- c.addi a5, -1
- c.addi s6, 3
- bge t1, a7, 345f
- bltu ra, s4, 362f
- c.srli a2, 15
- c.add a3, s1
-345: c.addi t4, 14
- slti a3, t5, -305
- lui a5, 771065
- sll a3, t6, a4
- lui s5, 689013
- bne a5, t0, 365f
- c.addi s3, 2
- auipc a6, 611057
- auipc a4, 931667
- c.addi a3, 4
- bge s1, t1, 371f
- auipc a2, 990094
- lui s2, 217172
- c.srli a2, 14
- lui a7, 827276
- c.addi t2, 31
- lui s3, 536402
-362: fence
- lui a0, 496235
- auipc s10, 187410
-365: lui a6, 81873
- c.addi t1, -26
- c.add a5, a1
- c.addi t3, -7
- c.slli s11, 2
- c.slli a3, 13
-371: c.srai a4, 18
- c.addi s11, 19
- auipc a0, 806565
- andi s1, a4, 69
- or a7, tp, a7
- auipc s3, 602867
- auipc t2, 995397
- c.addi t4, -26
- c.addi t6, 5
- c.slli a4, 29
- c.addi a1, -31
- c.lui t1, 23
- c.addi s10, 1
- lui s8, 434256
- c.lui t5, 7
- c.slli s2, 11
- xori s7, tp, -60
- c.srai a1, 8
- c.addi s4, -6
- auipc a3, 666992
- c.slli a3, 23
- c.lui t5, 26
- lui t2, 540186
- c.lui t5, 10
- sll s7, s1, t2
- c.and a2, s0
- c.lui s5, 2
- auipc a2, 424092
- c.slli a3, 1
- lw ra, 4(sp)
- lw t0, 8(sp)
- c.srai a4, 16
- sub s6, t6, t3
- c.lui gp, 3
- addi sp, sp, 16
- lui a6, 359866
-568: ret
-smode_program: c.lui s3, 22
- addi sp, sp, -28
- sw ra, 4(sp)
- c.srai a4, 12
- sw t0, 8(sp)
- auipc s5, 1037305
- sub s0, tp, t5
- c.srai a2, 7
- c.addi t4, 23
- lui t6, 970756
- lui t5, 775092
- mulhu s7, s0, t5
- srl a0, t0, t3
- c.addi a0, -8
- blt s9, a1, 13f
- lui s4, 826922
- auipc s3, 476110
- c.srli s0, 3
- auipc s2, 4639
-13: c.lui a7, 22
- c.addi t6, -24
- auipc s11, 102019
- c.addi s2, 3
- sra s8, t5, t4
- sub t5, tp, s1
- c.addi s8, -24
- c.addi a6, 10
- c.addi t1, -28
- c.addi s7, 11
- lui s9, 29154
- c.lui t3, 20
- c.addi a7, -23
- auipc s9, 216368
- c.srli a5, 1
- c.addi s3, -15
- lui s7, 675665
- lui s10, 542476
- c.srai a3, 16
- c.srli a1, 13
- c.slli t6, 25
- auipc a0, 56741
- auipc s0, 473303
- c.sub a4, a5
- c.srli a0, 25
- auipc s5, 674872
- bne a2, t5, 46f
- bge a2, zero, 51f
- c.addi a6, 20
- c.addi a3, 24
- c.add a5, a2
- c.addi s3, -7
- c.slli t3, 4
-46: c.addi s7, 5
- c.srli a3, 16
- c.addi s6, -7
- sltu a6, a7, a1
- auipc a3, 135879
-51: c.addi s8, -20
- auipc a4, 186409
- c.slli t2, 13
- c.addi a2, -8
- c.addi gp, 29
- c.addi s5, 10
- sub t5, s6, zero
- c.srli a1, 9
- c.addi a0, 26
- c.slli s9, 8
- c.srai s1, 30
- lui s11, 94082
- lui s10, 177632
- c.addi s5, 19
- c.addi s6, 4
- c.beqz a1, 81f
- c.srli a3, 6
- fence.i
- c.lui t6, 1
- sll a5, s7, s11
- c.addi a4, -19
- bgeu a1, s5, 76f
- lui a6, 692146
- c.slli a2, 25
- c.addi s2, 20
-76: c.srai s0, 14
- c.srai s0, 27
- c.srli a5, 24
- c.addi t2, -28
- c.lui s10, 23
-81: c.addi s10, -19
- c.addi t5, -8
- c.addi s9, 15
- c.slli s5, 29
- c.or s1, a1
- rem a3, t5, s6
- auipc t1, 161159
- c.slli a1, 11
- bgeu a3, s9, 98f
- c.addi s6, 10
- c.srli a4, 25
- c.slli s4, 16
- c.and a4, a2
- c.addi s9, 2
- mulh t6, a6, gp
- c.addi t1, 18
- c.addi gp, -10
-98: c.slli a5, 18
- sltiu s0, t4, -796
- lui t4, 725426
- srli s5, a7, 16
- c.addi t5, 17
- c.slli a6, 1
- auipc a0, 9977
- remu a3, a0, s11
- xor a5, zero, a3
- lui s10, 352214
- c.lui t3, 30
- c.slli a0, 21
- c.addi a4, 1
- c.addi a3, 30
- lui t6, 766527
- c.srli a3, 29
- c.addi a3, -14
- nop
- and a3, s5, a5
- c.addi s1, -21
- bltu t5, s4, 123f
- c.lui s8, 14
- ori t5, t6, -164
- sltu s11, t5, t3
- c.addi a4, 21
-123: c.srai s1, 21
- c.srli a5, 31
- c.srli a1, 8
- andi a0, a1, 633
- divu s5, a2, s3
- fence
- auipc a3, 462317
- c.slli s2, 26
- lui s5, 752404
- auipc t2, 374602
- la s8, kernel_data_page_0+2002 #start riscv_load_store_rand_instr_stream_3
- sb a2, 391(s8)
- c.slli t2, 31
- c.srai a0, 26
- lbu t4, -1132(s8)
- c.lui a7, 25
- c.addi s2, 13
- lbu s5, 1413(s8)
- auipc a4, 546436
- rem t6, s5, a7
- c.addi s5, -27
- lw s3, -722(s8)
- c.addi s3, -10
- c.and a3, s0
- auipc a3, 730366
- sb zero, 1821(s8)
- c.lui a3, 22
- lb a6, -851(s8)
- lb s0, -1828(s8)
- sw gp, 1426(s8)
- c.lui s1, 5
- lw a1, 1110(s8)
- lbu t4, 803(s8)
- lb t1, 1700(s8)
- c.addi a4, -8
- lb a6, 1241(s8)
- sb s7, -1739(s8)
- c.addi a5, -4
- c.addi s7, -2
- c.srli a0, 11
- lhu s4, -1020(s8)
- lbu s2, -657(s8)
- sltiu t1, s1, 336
- lbu t1, 69(s8)
- lbu s11, 277(s8)
- c.addi s0, -31
- sh sp, -1556(s8)
- lui s7, 619794
- lb s2, 277(s8)
- xor a7, a5, s7
- c.srli s0, 10
- c.srli a1, 13
- lb a0, -1925(s8) #end riscv_load_store_rand_instr_stream_3
- c.addi t4, -20
- bge s6, zero, 136f
- c.bnez a2, 142f
-136: beq sp, s2, 137f
-137: c.srai a1, 31
- c.srai s0, 25
- slli s3, zero, 8
- c.addi a5, -11
- lui s3, 5433
-142: auipc t2, 297040
- auipc s2, 212751
- c.slli s1, 26
- c.addi a6, -5
- c.slli a0, 13
- lui a1, 888920
- c.addi a5, -18
- c.slli s10, 13
- c.addi s1, -26
- c.addi s10, -20
- lui a4, 1046828
- xori t5, a6, -219
- c.addi s7, 15
- c.beqz a2, 165f
- c.addi s2, -19
- c.or a5, a2
- c.addi a6, -25
- c.addi a1, 4
- c.slli gp, 30
- c.addi s10, 1
- lui s10, 928340
- slli s6, s10, 1
- auipc t1, 321084
-165: c.addi a2, 10
- slt a5, tp, t4
- sub s3, tp, sp
- auipc s5, 168951
- lui s3, 605837
- c.beqz s0, 176f
- auipc gp, 731510
- c.addi s1, -17
- c.addi a7, 23
- auipc t4, 840696
- c.srai a3, 12
-176: or t6, tp, s11
- lui s3, 899602
- rem s3, t6, t0
- c.addi s10, 19
- auipc a0, 863481
- auipc s5, 844234
- c.srli a1, 28
- sra t4, s5, s9
- c.srai a5, 24
- sra s3, s7, s9
- lui s3, 142006
- c.addi a7, -17
- lui s2, 617024
- auipc s10, 691485
- lui a4, 343649
- divu a3, a4, gp
- c.addi a1, -26
- c.addi a7, 15
- fence
- sub a2, a6, a4
- auipc s6, 285892
- c.srai a5, 20
- c.slli a5, 8
- auipc t6, 358266
- c.addi a5, -9
- c.add a3, s1
- beq s2, t3, 213f
- c.slli a5, 1
- c.addi a3, 25
- c.srai a5, 20
- c.addi s9, -21
- auipc s5, 1022214
- c.addi t3, -25
- lui a4, 111769
- c.lui s1, 25
- c.srli a1, 30
- c.or s1, s0
-213: c.slli s0, 20
- auipc zero, 274584
- c.addi s8, 7
- c.addi t2, 26
- c.addi s1, -21
- c.addi s2, -16
- fence
- auipc s11, 878135
- bge s10, t4, 237f
- auipc s0, 439613
- mul s7, s9, a1
- mul s8, a7, s5
- lui s1, 450101
- c.srai a3, 10
- c.addi t5, -20
- c.addi t1, -21
- c.addi a1, 27
- mulhu s10, a3, ra
- c.addi t3, -28
- mulhsu t1, s3, t2
- c.addi s0, 3
- srli t4, a6, 13
- c.slli t4, 20
- lui s11, 455114
-237: c.srli a2, 3
- c.addi a2, 30
- c.addi a3, -14
- xor s3, s10, s6
- c.srli a4, 25
- c.slli a1, 1
- c.srli a3, 20
- c.lui a1, 30
- c.addi s9, 1
- sra s4, s9, t2
- lui t3, 396236
- auipc s2, 707596
- c.srli a5, 10
- c.addi a3, 24
- c.lui s0, 7
- c.srai a4, 6
- la a5, kernel_data_page_0+1787 #start riscv_load_store_rand_instr_stream_0
- lb s10, 1612(a5)
- lbu s4, 242(a5)
- c.slli a0, 10
- nop
- c.srli a3, 3
- c.lui a6, 3
- c.lui t3, 22
- c.addi s6, 20
- lui a0, 508582
- c.addi s0, -10
- lbu s7, -1430(a5)
- c.srli a4, 10
- lbu s7, -1734(a5)
- lui s10, 58698
- auipc s1, 119437
- sh a5, 467(a5)
- c.lui s2, 23
- lhu s1, 113(a5)
- div s10, sp, a1
- sb t2, -1488(a5)
- nop
- sh gp, -1509(a5)
- lb a7, 1036(a5)
- c.addi a7, -26
- c.addi s4, -8
- lhu a6, -709(a5)
- or s8, s7, s7
- c.slli gp, 5
- c.addi s8, -5
- lui s9, 447944
- c.srai s1, 20
- c.srli a2, 5
- c.slli s5, 28
- c.srai s0, 27
- auipc s11, 904047
- c.srai a3, 15
- lbu s11, 1009(a5)
- lb s3, 1929(a5) #end riscv_load_store_rand_instr_stream_0
- lui a4, 929818
- c.srli a5, 27
- c.bnez s1, 274f
- c.addi a4, 22
- c.addi s1, -7
- c.addi t2, -31
- c.li s10, 0
- lui s6, 89265
- c.addi a0, -14
- c.srai s1, 24
- c.addi s8, -13
- lui t6, 451359
- c.and a5, s0
- bgeu tp, t0, 270f
- lui t4, 580146
- c.addi a6, -12
- c.addi t2, -5
-270: c.addi t2, -22
- c.addi t3, 7
- c.srli s1, 29
- c.addi s4, -3
-274: bge s6, sp, 291f
- c.addi s1, 12
- auipc s6, 1038806
- c.addi s6, -4
- c.addi s4, 16
- auipc s0, 92163
- lui a2, 757430
- remu s10, gp, s1
- lui t6, 486181
- c.srai a5, 16
- c.addi t4, -12
- c.addi s9, 6
- c.lui gp, 23
- lui a0, 824894
- auipc a2, 726770
- c.addi a6, 29
- c.lui a6, 29
-291: c.addi t4, 1
- c.srai a4, 16
- lui t4, 23609
- sltiu s5, s2, 656
- c.srai s0, 7
- la s5, kernel_data_page_1+1220 #start riscv_load_store_rand_instr_stream_1
- lui s10, 954890
- c.and s1, a2
- lui a5, 485728
- lw s7, -948(s5)
- sw a6, 1804(s5)
- auipc t6, 993810
- lb s2, 1523(s5)
- sb t1, 715(s5)
- sb t6, 775(s5)
- c.addi a1, 15
- auipc s9, 877148
- lhu s9, 752(s5)
- c.addi s3, -26
- c.and s1, a5
- mulhu s1, s6, s7
- lbu t5, -611(s5)
- sb a2, 1720(s5)
- auipc a6, 773986
- srai s9, tp, 21
- c.or s0, a4
- c.addi s7, 28
- or t2, zero, tp
- c.xor a1, a4
- auipc t3, 311531
- lh t1, -672(s5)
- lh s10, 1552(s5)
- lb a6, 245(s5)
- c.mv s3, s0
- sra t1, s3, t0
- auipc a4, 510224
- lhu s11, -1082(s5)
- lui s9, 77963
- auipc t4, 572054
- lbu s2, -483(s5)
- auipc s3, 902637
- sb ra, 2023(s5)
- c.srli a2, 10
- sltiu a7, a5, 78
- c.srai a3, 29
- sb s0, 137(s5) #end riscv_load_store_rand_instr_stream_1
- auipc t1, 139925
- lui s1, 715750
- auipc t4, 752277
- lui s2, 422756
- c.lui t4, 5
- remu zero, a0, s0
- lui s2, 399740
- slli s7, a5, 23
- blt t3, a0, 311f
- lui t6, 1047014
- c.lui s9, 25
- sll s7, s8, s5
- c.srli s0, 16
- c.addi a3, -3
- c.lui s3, 19
-311: slli a6, s6, 2
- c.srai a3, 19
- bge s5, s10, 329f
- c.addi t4, -6
- c.addi a0, 19
- c.srli a1, 27
- auipc a0, 68806
- c.addi a4, -13
- lui t1, 967159
- c.addi a5, 2
- c.srai a3, 24
- andi a2, t5, 552
- c.addi s1, 27
- nop
- c.addi s9, 30
- lui s5, 81954
- c.nop
- c.addi a5, -26
-329: xor s8, t2, gp
- slli s9, a1, 24
- c.addi s7, 24
- ori a3, s3, -85
- c.addi t1, 4
- c.xor a2, a0
- add s7, ra, a4
- slt gp, s10, s10
- c.srli a5, 9
- c.slli s8, 3
- lui a4, 1023096
- c.addi a4, -29
- c.li t5, -10
- lui s7, 981347
- auipc t3, 253618
- div a6, t5, gp
- auipc t4, 196771
- auipc s5, 741845
- div a7, s3, a7
- auipc s7, 224360
- lui s0, 549848
- c.srai a3, 9
- or s1, s8, t6
- c.addi s6, -14
- c.addi t6, -14
- lui t4, 236555
- c.srai a5, 6
- lui s7, 311862
- sub s4, a6, t5
- c.addi s7, -4
- c.lui s4, 2
- and t1, t6, s9
- lui a0, 75957
- c.addi a5, -30
- auipc zero, 175502
- lui a2, 466881
- lui s2, 24063
- divu t6, s5, a4
- la s10, kernel_data_page_0+2143 #start riscv_load_store_rand_instr_stream_2
- rem t2, t5, t4
- xor gp, a6, gp
- sra t5, s7, t6
- nop
- auipc a4, 58689
- c.srli a1, 17
- sb gp, -2044(s10)
- c.lui a0, 17
- lw a7, 1489(s10)
- auipc s5, 203657
- sb tp, -1262(s10)
- sh s8, 1413(s10)
- lb a2, -1477(s10)
- lbu a4, 1910(s10)
- sll a0, a0, t4
- auipc s9, 890883
- lb t4, 1888(s10)
- lb t4, -1603(s10)
- sh s11, 787(s10)
- lbu s3, -1113(s10)
- c.srai a0, 1
- sh ra, 1753(s10)
- lb a0, -1614(s10)
- c.addi s6, 15
- lb gp, 1677(s10)
- lhu s3, -1493(s10)
- c.addi a5, -1
- sb s8, 1008(s10)
- c.or a2, s0
- c.addi t1, 19
- srl a2, s7, t2
- lhu s1, 359(s10)
- auipc s11, 1028714
- fence.i
- lb s6, -1546(s10)
- sb s3, 880(s10)
- lbu gp, 1260(s10) #end riscv_load_store_rand_instr_stream_2
- sra gp, a5, a7
- c.lui s10, 11
- auipc t2, 556397
- c.addi a3, -24
- auipc s8, 321650
- c.addi t1, -7
- c.addi a3, 13
- c.lui a3, 21
- c.addi a4, -8
- c.addi gp, -16
- c.lui t5, 16
- bge zero, zero, 380f
- sra gp, s2, s8
-380: addi a2, s10, -862
- c.srli a2, 21
- auipc a1, 680635
- c.srli a3, 4
- divu a6, s6, t3
- auipc gp, 679090
- lui s4, 1029578
- c.srli a2, 26
- c.srai s0, 14
- c.addi t4, 15
- c.srli s1, 3
- c.srai a3, 31
- c.addi a5, -10
- remu s8, gp, t0
- c.addi a1, 20
- c.lui s4, 23
- lui s1, 638756
- c.addi s3, -11
- c.addi a2, 12
- slli a6, s6, 4
- c.srai a3, 11
- lui a6, 408342
- auipc gp, 113507
- lw ra, 4(sp)
- c.srai a3, 1
- lw t0, 8(sp)
- addi sp, sp, 28
- c.srli a5, 20
- or t3, s10, t5
- c.srli a3, 30
- sltiu a4, t6, 46
- c.srli a1, 12
-579: ret
-smode_ls_umem_program:bne a4, s3, smode_ls_umem_program_stack_p
- auipc s6, 319544
-smode_ls_umem_program_stack_p:addi sp, sp, -56
- sw ra, 4(sp)
- c.slli a6, 15
- sw t0, 8(sp)
- srl s8, zero, ra
- c.lui t2, 27
- c.srai a4, 11
- c.addi a0, -1
- c.addi s9, -31
- lui s9, 889383
- c.slli s8, 20
- c.lui s4, 19
- c.slli a0, 16
- auipc s11, 324830
- lui t4, 62171
- c.srai a4, 25
- fence.i
- mulhu zero, a4, t0
- c.srli a1, 29
- c.addi a5, 10
- c.slli a6, 21
- c.addi s8, -25
- c.addi a6, -23
- c.addi a5, 28
- c.addi a3, 2
- c.slli s2, 13
- c.srli a4, 19
- c.add a1, a2
- auipc gp, 970329
- lui a6, 424558
- c.addi a3, 30
- c.addi s6, 17
- lui a5, 384221
- c.addi t5, 10
- lui s8, 853827
- c.addi a3, 4
- c.slli a1, 5
- c.addi s9, -4
- c.mv s7, s2
- c.lui gp, 17
- fence.i
- c.slli a1, 23
- lui zero, 836261
- blt s7, ra, 43f
- c.lui t5, 25
- srai s11, t4, 10
- div gp, s8, a5
- addi s8, t4, -253
- c.addi s6, -11
-43: bltu a6, a2, 57f
- c.srai s0, 20
- auipc s0, 534619
- c.andi a4, -11
- c.addi s1, 5
- c.srai s1, 21
- c.srai a1, 31
- slt a3, a3, ra
- c.addi s1, 23
- c.srli a4, 4
- c.slli a2, 14
- c.addi s6, 4
- bgeu t1, gp, 74f
- lui t6, 16790
-57: c.slli t4, 22
- c.addi s10, 5
- lui a6, 277040
- c.slli t3, 28
- c.slli a0, 24
- slti a3, s3, -820
- lui s0, 208965
- c.srai a3, 17
- auipc a7, 98462
- auipc a0, 1023559
- c.addi a0, 16
- c.addi s5, 9
- sltu a6, a7, s10
- mulhu s8, a6, zero
- lui t4, 1000117
- lui a5, 436226
- c.addi t5, -23
-74: c.srai a2, 18
- lui s6, 1037687
- div s6, a0, a0
- c.addi a2, 7
- sltiu s1, a5, -906
- sra s1, t6, s6
- c.addi s9, -30
- auipc a7, 733681
- c.add a0, a1
- c.addi t5, 14
- c.addi t3, -26
- auipc s7, 308369
- xor s9, t1, t0
- c.add a2, a2
- lui t1, 1025608
- lui t4, 863360
- c.addi s5, 13
- c.srai a4, 30
- auipc t6, 631840
- ori s5, s7, -462
- fence
- c.slli a2, 2
- c.addi a4, 2
- c.srai s0, 30
- c.addi s7, 13
- c.srai a1, 17
- auipc s5, 123438
- auipc t3, 642928
- lui s4, 761911
- divu s4, a2, t3
- c.addi s0, 15
- c.srli a5, 29
- c.srai a2, 1
- auipc a0, 1039052
- auipc s3, 590015
- divu t3, sp, t4
- mulhu a1, s11, gp
- c.srli a3, 27
- nop
- sltiu s4, zero, 306
- mul s3, gp, s10
- lui t3, 205731
- la s6, kernel_data_page_0+1184 #start riscv_load_store_rand_instr_stream_1
- lhu t4, -146(s6)
- lui t6, 569171
- c.addi s7, -15
- lw a2, -668(s6)
- c.srli a4, 27
- c.srai a5, 3
- lui s3, 935624
- c.or a2, s1
- lbu t2, -886(s6)
- sll t1, a6, s0
- nop
- c.slli s0, 8
- srai t2, s3, 17
- c.lui t6, 3
- lui s11, 293045
- lb a0, -1119(s6)
- lhu s1, -1022(s6)
- c.srai a4, 25
- lbu t2, 767(s6)
- c.lui s11, 16
- c.slli t2, 21
- lui s5, 728792
- addi a6, a0, -757
- c.addi gp, 25
- auipc t6, 84758
- lh t2, 1608(s6)
- sb a0, 207(s6)
- c.addi s4, 7
- lb s9, 1954(s6)
- addi s2, a4, -353
- c.srli s0, 12
- sb t3, 2039(s6)
- c.addi s8, -27
- lb a6, 432(s6)
- srli a4, s6, 19
- lbu a6, 1630(s6)
- c.addi s0, -23
- ori s5, s1, 497
- sb t5, -319(s6)
- c.addi s1, -14
- c.srli a5, 31
- lb t2, 1298(s6) #end riscv_load_store_rand_instr_stream_1
- lui s4, 556939
- auipc s0, 130454
- auipc s10, 391449
- c.addi t3, -16
- c.slli a7, 17
- auipc a7, 595694
- c.slli t3, 27
- c.slli s5, 16
- auipc a2, 563380
- lui s10, 108975
- blt s4, s2, 127f
-127: c.addi a2, 1
- c.srai a5, 13
- c.srli a4, 1
- c.addi a3, -1
- andi s3, s5, -302
- c.slli a1, 28
- lui t3, 53241
- c.lui t4, 11
- c.or a5, a4
- c.addi a6, 2
- lui s1, 832189
- lui s9, 73927
- c.addi a3, -27
- c.addi s7, -15
- lui a7, 700114
- c.srli a4, 17
- sra s0, s1, s10
- c.addi t5, 1
- c.slli a5, 12
- andi a5, s6, -985
- bgeu gp, t6, 167f
- addi a2, a2, -607
- auipc s11, 503040
- c.addi t4, -1
- lui a3, 436025
- c.addi t5, -15
- c.addi gp, -17
- c.mv s10, tp
- c.srli a1, 4
- c.srai s1, 30
- c.addi a1, -18
- c.addi t3, 24
- auipc a2, 113320
- c.lui gp, 19
- fence
- c.addi s10, -9
- sll s7, s4, s0
- c.lui t5, 24
- lui s2, 872195
- c.srli a1, 17
-167: lui t5, 588025
- srl s0, a6, a1
- c.srli a3, 20
- xor zero, a6, t2
- lui s8, 596859
- c.lui a7, 8
- auipc a6, 532888
- auipc t4, 258271
- auipc s6, 366145
- c.addi s3, 26
- c.lui a4, 13
- auipc s6, 66244
- lui s9, 221853
- c.addi a1, 13
- auipc s3, 228780
- c.addi a7, -17
- c.slli s8, 18
- remu s6, ra, zero
- c.slli t4, 31
- c.addi s11, -21
- c.slli t6, 12
- c.addi s10, -22
- srai a7, t5, 16
- c.addi t3, -15
- c.srli a3, 5
- bne gp, t1, 205f
- c.addi a3, 3
- c.addi t4, 22
- c.slli s11, 11
- c.addi s11, 13
- c.srli a0, 21
- c.addi gp, 24
- c.addi t4, -21
- c.srai a0, 27
- divu s8, t3, s5
- sra s11, a4, a2
- lui a0, 559336
- auipc s4, 862930
- la s3, kernel_data_page_0+1250 #start riscv_load_store_rand_instr_stream_0
- sltiu s5, zero, 678
- c.addi s9, -15
- lbu a6, 1620(s3)
- lw s9, 1794(s3)
- lbu gp, 1533(s3)
- and zero, t6, s11
- c.addi s5, -12
- lb a0, 1527(s3)
- sb a6, 1129(s3)
- auipc s4, 275900
- lui s8, 768375
- c.add a5, a0
- c.lui s8, 12
- sb s10, -1153(s3)
- sh ra, 818(s3)
- lb s8, 1432(s3)
- auipc s6, 515841
- c.slli a6, 28
- sb s4, -229(s3)
- lbu s5, 555(s3)
- c.srai a1, 9
- c.addi s4, 24
- c.srai s0, 24
- c.srli a1, 22
- c.lui t5, 14
- lui a1, 985078
- lb s0, 532(s3)
- c.addi a1, -28
- remu s5, a4, t0
- lbu s8, 796(s3)
- ori s7, t1, 159
- lbu t2, -55(s3)
- lb t6, 1899(s3)
- lui t5, 70725
- lh a4, 1828(s3)
- lbu a0, 1680(s3)
- lbu a1, 1496(s3)
- lhu a2, 236(s3)
- c.addi a6, -3
- c.slli s11, 3
- lb a7, -435(s3)
- c.addi a6, -21
- c.addi s9, -23
- c.addi s0, -3
- lbu a6, 1465(s3) #end riscv_load_store_rand_instr_stream_0
-205: c.addi t6, -17
- lui a3, 323779
- beq s6, s8, 208f
-208: auipc t3, 300808
- lui zero, 182377
- bne zero, a7, 224f
- divu a5, s8, t2
- auipc zero, 425330
- c.addi t1, 20
- bne s1, s8, 229f
- lui s7, 885352
- fence.i
- c.addi t1, -27
- sltu s1, s10, a3
- lui s0, 387937
- c.andi a3, -12
- lui s10, 159508
- auipc t5, 198946
- sltiu a1, a4, 734
-224: auipc t1, 405215
- xori s3, s10, -109
- andi zero, a2, 567
- c.addi s9, -11
- c.addi a3, 9
-229: lui s6, 879168
- lui t3, 139610
- c.lui s7, 16
- auipc s8, 375273
- addi s10, s6, -275
- c.srli a2, 22
- auipc a0, 292090
- c.addi s4, -13
- c.addi a0, -12
- c.addi a3, -20
- c.addi s3, 24
- srai s3, s5, 10
- lui s7, 378631
- blt t3, a4, 244f
- c.addi gp, -29
-244: lui a5, 1036742
- lui s6, 310929
- c.lui s8, 19
- c.srli a2, 20
- c.addi t1, -2
- c.addi s5, -23
- c.addi s7, -3
- lui a0, 1002582
- lui a3, 130125
- c.addi t4, -28
- sll s1, s6, s0
- mul s2, s4, a0
- c.addi t3, 28
- c.addi s7, 19
- lui a6, 388435
- lui s2, 681049
- c.srai a1, 15
- c.slli a1, 21
- mul s10, s7, t0
- c.srai s0, 22
- lui a4, 368207
- remu a7, a5, t5
- c.and a4, s1
- div s5, s6, zero
- c.srai a1, 23
- auipc a3, 102118
- c.addi s10, -14
- c.addi a5, -10
- auipc s4, 858449
- c.addi t2, -25
- c.addi t6, 23
- divu a0, s6, s1
- auipc a5, 508030
- c.slli a7, 1
- c.srli a5, 30
- c.addi t6, -23
- c.add s1, a5
- c.addi a3, 26
- c.srli a0, 17
- fence
- ori s5, s3, -752
- c.srai s0, 9
- c.addi t1, 19
- mulhu t4, a6, a4
- c.slli t6, 5
- mulhu s8, s10, t3
- lui s10, 965917
- bltu s6, s2, 295f
- c.addi a0, -5
- c.addi s7, -5
- auipc t6, 977943
-295: c.srai s1, 23
- c.addi a7, 17
- c.slli s1, 30
- auipc s2, 724487
- srai a7, s11, 25
- c.srli s0, 3
- c.addi gp, 23
- c.and a3, a4
- fence
- fence
- lui gp, 474128
- auipc t1, 747784
- auipc s2, 607717
- c.sub s0, s0
- add a7, s9, t6
- lui a5, 74285
- c.sub a5, a4
- c.addi t1, 18
- c.slli s3, 4
- c.addi s3, -2
- mulh a1, ra, s11
- la s6, kernel_data_page_0+2071 #start riscv_load_store_rand_instr_stream_2
- lb a4, 1022(s6)
- lbu s11, -1829(s6)
- c.lui a1, 15
- c.lui a5, 15
- lw t6, 1921(s6)
- lbu s8, 942(s6)
- nop
- lbu t4, 1048(s6)
- lbu a6, 1260(s6)
- c.srli a0, 22
- lb s4, 478(s6)
- remu s1, a7, s9
- lhu s0, -541(s6)
- c.lui t4, 8
- lb s7, 11(s6)
- sw s1, 1913(s6)
- lhu a4, 1163(s6)
- lui s11, 334221
- c.addi gp, 17
- lh s1, -1073(s6)
- c.or a0, s0
- c.lui t1, 16
- c.srai s1, 12
- lb s10, 90(s6)
- lbu s5, -819(s6)
- c.addi s11, -30
- c.addi s2, 15
- c.xor a5, a2
- lbu t4, 86(s6)
- lbu a5, 1204(s6)
- lb s10, 382(s6)
- c.srai a3, 30
- lh t2, 1207(s6)
- sb t0, -910(s6)
- lbu a1, 1237(s6)
- lb a6, -544(s6)
- lb s3, -148(s6)
- c.addi gp, 6
- c.addi s1, 15
- c.addi t6, -10
- auipc s10, 1006281
- lbu t4, 226(s6)
- lui a1, 149225
- sh tp, -2015(s6)
- lbu s7, 791(s6) #end riscv_load_store_rand_instr_stream_2
- lui gp, 830315
- slti s4, s9, -618
- auipc s10, 948712
- c.lui s7, 2
- lui t4, 976982
- c.addi s7, -28
- lui s2, 41485
- lui a7, 281498
- c.nop
- auipc a4, 354139
- lui a7, 456507
- lui s7, 152167
- c.addi t1, 16
- c.lui s0, 11
- divu a2, a2, zero
- c.addi s0, 17
- auipc a1, 54552
- auipc t6, 401709
- c.addi s2, 31
- c.mv a3, s6
- c.addi t5, -7
- c.addi a2, -3
- c.srli a0, 20
- bne t2, a3, 356f
- lui gp, 553987
- c.addi s7, -26
- lui t2, 653027
- srl zero, t0, s0
- lui t3, 932721
- c.slli s4, 24
- c.addi s10, 23
- c.slli s6, 26
- c.srli a1, 19
- lui s9, 75522
- lui a1, 776604
- c.lui s6, 20
- c.addi s6, 19
- c.lui a7, 7
- lui a0, 841653
- c.andi s1, -29
-356: srai a3, t1, 8
- mulhsu a3, a7, s0
- c.lui s10, 7
- lui t2, 784820
- c.slli s7, 31
- lui t5, 356513
- slli s1, ra, 27
- lui t2, 925729
- c.srai a0, 10
- c.srli a4, 1
- auipc s10, 726799
- c.srai a1, 21
- lui s0, 940379
- c.addi s11, 21
- lui a2, 727277
- lui a3, 221342
- c.lui s1, 3
- c.slli s2, 18
- auipc t3, 371865
- sll s4, a4, s3
- c.srli a4, 10
- c.addi t3, 9
- c.srli a1, 4
- lui a2, 1039633
- c.srli a5, 16
- sltiu t4, s3, 819
- blt a0, a5, 387f
- xori a0, s5, -829
- c.slli a6, 14
- lui t2, 222631
- la a7, kernel_data_page_1+2343 #start riscv_load_store_rand_instr_stream_3
- lui a1, 554261
- sh a7, -267(a7)
- sb zero, 1524(a7)
- lhu t2, 763(a7)
- lhu s7, 639(a7)
- lbu s0, -226(a7)
- c.srli a5, 24
- sb t3, 1537(a7)
- sb t3, -280(a7)
- c.addi t3, 5
- sb s7, -646(a7)
- lbu t4, 308(a7)
- lbu t4, -1860(a7)
- lb t2, 1048(a7)
- sb ra, 278(a7)
- c.srai s0, 7
- sb t6, -1698(a7)
- lb a5, -186(a7)
- sh s1, -701(a7)
- lui a4, 169766
- lb t2, -220(a7)
- lb t1, -1326(a7)
- lb a3, -1329(a7)
- sh s8, 209(a7)
- c.srli a5, 14
- lbu zero, 1532(a7)
- lbu s4, -890(a7)
- sh t1, 1387(a7)
- c.slli gp, 12
- lb s1, 798(a7)
- sb ra, -179(a7)
- lb gp, 902(a7)
- sltiu t3, t6, -138
- lbu s10, -2041(a7)
- c.addi t3, -32
- c.slli t5, 4
- sh s7, -953(a7)
- c.addi a5, 8
- lb s3, 166(a7)
- sb s7, -1191(a7) #end riscv_load_store_rand_instr_stream_3
- lui s7, 518449
-387: auipc a4, 689994
- auipc t4, 920306
- c.addi a3, -15
- remu a5, s3, tp
- c.addi s2, 25
- auipc s11, 366492
- c.srai s1, 23
- c.addi a3, 19
- slti gp, a1, -988
- c.slli t1, 30
- mulhu a0, s6, a4
- c.addi a7, -7
- mulh t3, sp, zero
- c.addi a6, -30
- c.addi s3, 25
- mulh s3, t3, a7
- c.srli a2, 26
- lw ra, 4(sp)
- c.slli s0, 18
- lw t0, 8(sp)
- c.srai a0, 21
- xori t1, gp, -289
- c.addi a1, 30
- c.addi t2, -32
- addi sp, sp, 56
- lui t5, 33875
-597: ret
-.align 12
-mtvec_handler:
- csrrw sp, 0x340, sp
- add sp, tp, zero
- 1: addi sp, sp, -128
- sw x0, 0(sp)
- sw x1, 4(sp)
- sw x2, 8(sp)
- sw x3, 12(sp)
- sw x4, 16(sp)
- sw x5, 20(sp)
- sw x6, 24(sp)
- sw x7, 28(sp)
- sw x8, 32(sp)
- sw x9, 36(sp)
- sw x10, 40(sp)
- sw x11, 44(sp)
- sw x12, 48(sp)
- sw x13, 52(sp)
- sw x14, 56(sp)
- sw x15, 60(sp)
- sw x16, 64(sp)
- sw x17, 68(sp)
- sw x18, 72(sp)
- sw x19, 76(sp)
- sw x20, 80(sp)
- sw x21, 84(sp)
- sw x22, 88(sp)
- sw x23, 92(sp)
- sw x24, 96(sp)
- sw x25, 100(sp)
- sw x26, 104(sp)
- sw x27, 108(sp)
- sw x28, 112(sp)
- sw x29, 116(sp)
- sw x30, 120(sp)
- sw x31, 124(sp)
- csrr a1, 0x342 # MCAUSE
- srli a1, a1, 31
- bne a1, x0, mmode_intr_handler
- csrr a1, 0x342 # MCAUSE
- csrr x31, 0x341 # MEPC
- csrr x29, 0x300 # MSTATUS
- li a2, 0x8 # ECALL_UMODE
- beq a1, a2, ecall_handler
- li a2, 0x9 # ECALL_SMODE
- beq a1, a2, ecall_handler
- li a2, 0xb # ECALL_MMODE
- beq a1, a2, ecall_handler
- li a2, 0x1
- beq a1, a2, pt_fault_handler
- li a2, 0x5
- beq a1, a2, pt_fault_handler
- li a2, 0x7
- beq a1, a2, pt_fault_handler
- li a2, 0xc
- beq a1, a2, pt_fault_handler
- li a2, 0xd
- beq a1, a2, pt_fault_handler
- li a2, 0xf
- beq a1, a2, pt_fault_handler
- li a2, 0x2 # ILLEGAL_INSTRUCTION
- beq a1, a2, illegal_instr_handler
- csrr x30, 0x343 # MTVAL
- 1: jal x1, test_done
-
-ecall_handler:
- j write_tohost
-illegal_instr_handler:
- csrr x31, mepc
- addi x31, x31, 4
- csrw mepc, x31
- lw x0, 0(sp)
- lw x1, 4(sp)
- lw x2, 8(sp)
- lw x3, 12(sp)
- lw x4, 16(sp)
- lw x5, 20(sp)
- lw x6, 24(sp)
- lw x7, 28(sp)
- lw x8, 32(sp)
- lw x9, 36(sp)
- lw x10, 40(sp)
- lw x11, 44(sp)
- lw x12, 48(sp)
- lw x13, 52(sp)
- lw x14, 56(sp)
- lw x15, 60(sp)
- lw x16, 64(sp)
- lw x17, 68(sp)
- lw x18, 72(sp)
- lw x19, 76(sp)
- lw x20, 80(sp)
- lw x21, 84(sp)
- lw x22, 88(sp)
- lw x23, 92(sp)
- lw x24, 96(sp)
- lw x25, 100(sp)
- lw x26, 104(sp)
- lw x27, 108(sp)
- lw x28, 112(sp)
- lw x29, 116(sp)
- lw x30, 120(sp)
- lw x31, 124(sp)
- addi sp, sp, 128
- add tp, sp, zero
- csrrw sp, 0x340, sp
- mret
-
-pt_fault_handler:
- nop
-
-.align 12
-mmode_intr_handler:
- csrr a1, 0x300 # MSTATUS;
- csrr a1, 0x304 # MIE;
- csrr a1, 0x344 # MIP;
- csrrc a1, 0x344, a1 # MIP;
- lw x0, 0(sp)
- lw x1, 4(sp)
- lw x2, 8(sp)
- lw x3, 12(sp)
- lw x4, 16(sp)
- lw x5, 20(sp)
- lw x6, 24(sp)
- lw x7, 28(sp)
- lw x8, 32(sp)
- lw x9, 36(sp)
- lw x10, 40(sp)
- lw x11, 44(sp)
- lw x12, 48(sp)
- lw x13, 52(sp)
- lw x14, 56(sp)
- lw x15, 60(sp)
- lw x16, 64(sp)
- lw x17, 68(sp)
- lw x18, 72(sp)
- lw x19, 76(sp)
- lw x20, 80(sp)
- lw x21, 84(sp)
- lw x22, 88(sp)
- lw x23, 92(sp)
- lw x24, 96(sp)
- lw x25, 100(sp)
- lw x26, 104(sp)
- lw x27, 108(sp)
- lw x28, 112(sp)
- lw x29, 116(sp)
- lw x30, 120(sp)
- lw x31, 124(sp)
- addi sp, sp, 128
- add tp, sp, zero
- csrrw sp, 0x340, sp
- mret;
-
-.data
-.align 4;
-kernel_data_page_0:
-.align 12
-.word 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000
-.word 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000
-.word 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000
-.word 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000
-.word 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000
-.word 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000
-.word 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000
-.word 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000
-.word 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000
-.word 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000
-.word 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000
-.word 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000
-.word 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000
-.word 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000
-.word 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000
-.word 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000
-.word 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000
-.word 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000
-.word 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000
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-.word 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000
-.word 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000
-.word 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000
-.word 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000
-.word 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000
-.word 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000
-.word 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000
-.word 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000
-.align 4;
-.align 5
-_kernel_stack_start:
-.rept 4999
-.4byte 0x0
-.endr
-_kernel_stack_end:
-.4byte 0x0
-_kernel_end: nop
diff --git a/hw/vendor/lowrisc_ibex/vendor/google_riscv-dv/scripts/gen_csr_test.py b/hw/vendor/lowrisc_ibex/vendor/google_riscv-dv/scripts/gen_csr_test.py
index a1604cf..9ab72e4 100644
--- a/hw/vendor/lowrisc_ibex/vendor/google_riscv-dv/scripts/gen_csr_test.py
+++ b/hw/vendor/lowrisc_ibex/vendor/google_riscv-dv/scripts/gen_csr_test.py
@@ -279,7 +279,7 @@
csr_map = copy.deepcopy(original_csr_map)
source_reg, dest_reg = [f"x{i}" for i in random.sample(range(1, 16), 2)]
csr_list = list(csr_map.keys())
- with open(f"{out}/riscv_csr_test.{i}.S", "w") as csr_test_file:
+ with open(f"{out}/riscv_csr_test_{i}.S", "w") as csr_test_file:
gen_setup(csr_test_file)
for csr in csr_list:
csr_address, csr_val, csr_write_mask, csr_read_mask = csr_map.get(csr)
diff --git a/hw/vendor/lowrisc_ibex/vendor/google_riscv-dv/scripts/instr_trace_compare.py b/hw/vendor/lowrisc_ibex/vendor/google_riscv-dv/scripts/instr_trace_compare.py
index ead4f5c..8614233 100644
--- a/hw/vendor/lowrisc_ibex/vendor/google_riscv-dv/scripts/instr_trace_compare.py
+++ b/hw/vendor/lowrisc_ibex/vendor/google_riscv-dv/scripts/instr_trace_compare.py
@@ -201,6 +201,8 @@
def check_update_gpr(rd, rd_val, gpr):
gpr_state_change = 0
+ if rd == '':
+ return gpr_state_change
if rd in gpr:
if rd_val != gpr[rd]:
gpr_state_change = 1
diff --git a/hw/vendor/lowrisc_ibex/vendor/google_riscv-dv/scripts/lib.py b/hw/vendor/lowrisc_ibex/vendor/google_riscv-dv/scripts/lib.py
index 1037680..92a91ca 100644
--- a/hw/vendor/lowrisc_ibex/vendor/google_riscv-dv/scripts/lib.py
+++ b/hw/vendor/lowrisc_ibex/vendor/google_riscv-dv/scripts/lib.py
@@ -24,6 +24,22 @@
import yaml
import logging
+def setup_logging(verbose):
+ """Setup the root logger.
+
+ Args:
+ verbose: Verbose logging
+ """
+ if verbose:
+ logging.basicConfig(format="%(asctime)s %(filename)s:%(lineno)-5s %(levelname)-8s %(message)s",
+ datefmt='%a, %d %b %Y %H:%M:%S',
+ level=logging.DEBUG)
+ else:
+ logging.basicConfig(format="%(asctime)s %(levelname)-8s %(message)s",
+ datefmt='%a, %d %b %Y %H:%M:%S',
+ level=logging.INFO)
+
+
def read_yaml(yaml_file):
""" Read YAML file to a dictionary
@@ -59,6 +75,15 @@
return val
+def check_riscv_dv_setting():
+ """Check the RISCV-DV directory setting, default "."
+ """
+ try:
+ val = os.environ["RISCV_DV_ROOT"]
+ except KeyError:
+ os.environ["RISCV_DV_ROOT"] = "."
+
+
def get_seed(seed):
"""Get the seed to run the generator
@@ -83,6 +108,7 @@
Returns:
command output
"""
+ logging.debug(cmd)
try:
ps = subprocess.Popen(cmd,
shell=True,
diff --git a/hw/vendor/lowrisc_ibex/vendor/google_riscv-dv/scripts/link.ld b/hw/vendor/lowrisc_ibex/vendor/google_riscv-dv/scripts/link.ld
index 73b5485..df08889 100644
--- a/hw/vendor/lowrisc_ibex/vendor/google_riscv-dv/scripts/link.ld
+++ b/hw/vendor/lowrisc_ibex/vendor/google_riscv-dv/scripts/link.ld
@@ -19,13 +19,15 @@
SECTIONS
{
. = 0x80000000;
- .text.init : { *(.text.init) }
+ .text : { *(.text) }
. = ALIGN(0x1000);
.tohost : { *(.tohost) }
. = ALIGN(0x1000);
- .text : { *(.text) }
- . = ALIGN(0x1000);
+ .page_table : { *(.page_table) }
.data : { *(.data) }
+ .user_stack : { *(.user_stack) }
+ .kernel_data : { *(.kernel_data) }
+ .kernel_stack : { *(.kernel_stack) }
.bss : { *(.bss) }
_end = .;
}
diff --git a/hw/vendor/lowrisc_ibex/vendor/google_riscv-dv/scripts/riscv_trace_csv.py b/hw/vendor/lowrisc_ibex/vendor/google_riscv-dv/scripts/riscv_trace_csv.py
index 4dfd104..79daa54 100644
--- a/hw/vendor/lowrisc_ibex/vendor/google_riscv-dv/scripts/riscv_trace_csv.py
+++ b/hw/vendor/lowrisc_ibex/vendor/google_riscv-dv/scripts/riscv_trace_csv.py
@@ -34,6 +34,7 @@
self.instr_str = ""
self.instr = ""
self.privileged_mode = ""
+ self.csr = ""
def get_trace_string(self):
"""Return a short string of the trace entry"""
@@ -54,7 +55,7 @@
def start_new_trace(self):
"""Create a CSV file handle for a new trace"""
fields = ["instr", "rd", "rd_val", "rs1", "rs1_val", "rs2", "rs2_val",
- "imm", "str", "addr", "binary", "mode"]
+ "imm", "str", "addr", "binary", "csr", "mode"]
self.csv_writer = csv.DictWriter(self.csv_fd, fieldnames=fields)
self.csv_writer.writeheader()
@@ -85,8 +86,8 @@
'addr' : entry.addr,
'instr' : entry.instr,
'imm' : entry.imm,
- 'binary' : entry.binary,
- 'addr' : entry.addr})
+ 'csr' : entry.csr,
+ 'binary' : entry.binary})
def gpr_to_abi(gpr):
diff --git a/hw/vendor/lowrisc_ibex/vendor/google_riscv-dv/scripts/spike_log_to_trace_csv.py b/hw/vendor/lowrisc_ibex/vendor/google_riscv-dv/scripts/spike_log_to_trace_csv.py
index 45a23f8..a64c204 100644
--- a/hw/vendor/lowrisc_ibex/vendor/google_riscv-dv/scripts/spike_log_to_trace_csv.py
+++ b/hw/vendor/lowrisc_ibex/vendor/google_riscv-dv/scripts/spike_log_to_trace_csv.py
@@ -25,8 +25,21 @@
sys.path.insert(0, os.path.dirname(os.path.realpath(__file__)))
from riscv_trace_csv import *
+from lib import *
-def process_spike_sim_log(spike_log, csv):
+RD_RE = re.compile(r"(?P<pri>\d) 0x(?P<addr>[a-f0-9]+?) " \
+ "\((?P<bin>.*?)\) x\s*(?P<reg>\d*?) 0x(?P<val>[a-f0-9]+)")
+CORE_RE = re.compile(r"core.*0x(?P<addr>[a-f0-9]+?) \(0x(?P<bin>.*?)\) (?P<instr>.*?)$")
+INSTR_RE = re.compile(r"(?P<instr>[a-z\.0-9]+?)(\s+?)(?P<operand>.*)")
+GPR_RE = re.compile(r"^[a-z][0-9a-z]$")
+ILLE_RE = re.compile(r"trap_illegal_instruction")
+ADDR_RE = re.compile(r"(?P<imm>[\-0-9]+?)\((?P<rs1>.*)\)")
+PC_RE = re.compile(r"pc+")
+HEX_RE = re.compile(r"^0x")
+
+LOGGER = logging.getLogger()
+
+def process_spike_sim_log(spike_log, csv, full_trace = 0):
"""Process SPIKE simulation log.
Extract instruction and affected register information from spike simulation
@@ -36,14 +49,6 @@
instr_cnt = 0
spike_instr = ""
- RD_RE = re.compile(r"(?P<pri>\d) 0x(?P<addr>[a-f0-9]+?) " \
- "\((?P<bin>.*?)\) x\s*(?P<reg>\d*?) 0x(?P<val>.*)")
- CORE_RE = re.compile(r"core.*0x(?P<addr>[a-f0-9]+?) \(0x(?P<bin>.*?)\) (?P<instr>.*?)$")
- INSTR_RE = re.compile(r"(?P<instr>[a-z\.]+?)(\s+?)(?P<operand>.*)")
- GPR_RE = re.compile(r"^[a-z][0-9a-z]$")
- CSR_RE = re.compile(r"csr")
- ILLE_RE = re.compile(r"trap_illegal_instruction")
-
# Remove all the init spike boot instructions
cmd = ("sed -i '/core.*0x0000000000001010/,$!d' %s" % spike_log)
os.system(cmd)
@@ -61,7 +66,8 @@
# Extract instruction infromation
m = CORE_RE.search(line)
if m:
- spike_instr = m.group("instr")
+ spike_instr = m.group("instr").replace("pc + ", "")
+ spike_instr = spike_instr.replace("pc - ", "-")
rv_instr_trace = RiscvInstructiontTraceEntry()
rv_instr_trace.instr_str = spike_instr
rv_instr_trace.addr = m.group("addr")
@@ -81,46 +87,309 @@
rv_instr_trace.rd_val = m.group("val")
rv_instr_trace.privileged_mode = m.group("pri")
gpr[rv_instr_trace.rd] = rv_instr_trace.rd_val
- s = INSTR_RE.search(spike_instr)
- if s:
- rv_instr_trace.instr = s.group("instr")
- operand_str = s.group("operand").replace(" ", "")
- if operand_str != "" :
+ else:
+ # If full trace is not enabled, skip the entry that doesn't have
+ # architectural state update.
+ if not full_trace:
+ continue
+ if full_trace:
+ s = INSTR_RE.search(spike_instr)
+ if s:
+ rv_instr_trace.instr = s.group("instr")
+ operand_str = s.group("operand").replace(" ", "")
operands = operand_str.split(",")
- if CSR_RE.search(s.group("instr")):
- # CSR instruction
- operand = operands[-1]
- if GPR_RE.search(operand) or operand == "zero":
- rv_instr_trace.rs1 = operand
- rv_instr_trace.rs1_val = gpr[operand]
- else:
- rv_instr_trace.imm = operand
- else:
- # Non CSR instruction
- for i in range(1, len(operands)):
- operand = operands[i]
- if GPR_RE.search(operand) or operand == "zero":
- if i == 1:
- rv_instr_trace.rs1 = operand
- rv_instr_trace.rs1_val = gpr[operand]
- else:
- rv_instr_trace.rs2 = operands[i]
- rv_instr_trace.rs2_val = gpr[operand]
- else:
- rv_instr_trace.imm = operand
- trace_csv.write_trace_entry(rv_instr_trace)
+ assign_operand(rv_instr_trace, operands, gpr)
+ else:
+ rv_instr_trace.instr = spike_instr
+ else:
+ rv_instr_trace.instr = spike_instr
+ trace_csv.write_trace_entry(rv_instr_trace)
logging.info("Processed instruction count : %d" % instr_cnt)
+ logging.info("CSV saved to : %s" % csv)
+def sint_to_hex(val):
+ """Signed integer to hex conversion"""
+ return str(hex((val + (1 << 32)) % (1 << 32)))
+
+
+def get_imm_hex_val(imm):
+ """Get the hex representation of the imm value"""
+ if imm[0] == '-':
+ is_negative = 1
+ imm = imm[1:]
+ else:
+ is_negative = 0
+ imm_val = int(imm, 0)
+ if is_negative:
+ imm_val = -imm_val
+ hexstr = sint_to_hex(imm_val)
+ return hexstr[2:]
+
+
+def assign_operand(trace, operands, gpr):
+ #logging.debug("-> [%0s] %0s" % (trace.instr, trace.instr_str))
+ if trace.instr in ['lb', 'lh', 'lw', 'lbu', 'lhu', 'ld', 'lq', 'lwu', 'ldu',
+ 'c.lw', 'c.ld', 'c.lq', 'c.lwsp', 'c.ldsp', 'c.lqsp']:
+ # TODO: Support regular load/store format
+ m = ADDR_RE.search(operands[1])
+ # Load instruction
+ trace.rd = operands[0]
+ trace.rd_val = gpr[trace.rd]
+ if m:
+ trace.imm = get_imm_hex_val(m.group('imm'))
+ trace.rs1 = m.group('rs1')
+ trace.rs1_val = gpr[trace.rs1]
+ else:
+ logging.info("Unexpected load address %0s", operands[1])
+ elif trace.instr in ['sb', 'sh', 'sw', 'sd', 'sq', 'c.sw', 'c.sd', 'c.sq',
+ 'c.swsp', 'c.sdsp', 'c.sqsp']:
+ # Store instruction
+ m = ADDR_RE.search(operands[1])
+ # Load instruction
+ trace.rs2 = operands[0]
+ trace.rs2_val = gpr[trace.rs2]
+ if m:
+ trace.imm = get_imm_hex_val(m.group('imm'))
+ trace.rs1 = m.group('rs1')
+ trace.rs1_val = gpr[trace.rs1]
+ else:
+ logging.info("Unexpected store address %0s", operands[1])
+ elif trace.instr in ['mul', 'mulh', 'mulhsu', 'mulhu', 'div', 'divu', 'rem', 'remu',
+ 'mulw', 'muld', 'divw', 'divuw', 'divd', 'remw', 'remd', 'remuw',
+ 'remud', 'sll', 'srl', 'sra', 'add', 'sub', 'xor', 'or', 'and',
+ 'slt', 'sltu', 'sllw', 'slld', 'srlw', 'srld', 'sraw', 'srad',
+ 'addw', 'addd', 'subw', 'subd']:
+ # R type instruction
+ trace.rd = operands[0]
+ trace.rd_val = gpr[trace.rd]
+ trace.rs1 = operands[1]
+ trace.rs1_val = gpr[trace.rs1]
+ trace.rs2 = operands[2]
+ trace.rs2_val = gpr[trace.rs2]
+ elif trace.instr in ['c.add', 'c.addw', 'c.mv', 'c.sub', 'c.jr', 'c.and', 'c.or',
+ 'c.xor', 'c.subw']:
+ # CR type
+ trace.rd = operands[0]
+ trace.rd_val = gpr[trace.rd]
+ trace.rs1 = operands[0]
+ trace.rs1_val = gpr[trace.rs1]
+ trace.rs2 = operands[1]
+ trace.rs2_val = gpr[trace.rs2]
+ elif trace.instr in ['slli', 'srli', 'srai', 'addi', 'xori', 'ori', 'andi', 'slti',
+ 'sltiu', 'slliw', 'sllid', 'srliw', 'srlid', 'sraiw', 'sraid',
+ 'addiw', 'addid']:
+ # I type instruction
+ trace.rd = operands[0]
+ trace.rd_val = gpr[trace.rd]
+ trace.rs1 = operands[1]
+ trace.rs1_val = gpr[trace.rs1]
+ trace.imm = get_imm_hex_val(operands[2])
+ elif trace.instr in ['c.addi', 'c.addiw', 'c.addi16sp', 'c.addi4spn', 'c.li', 'c.lui',
+ 'c.slli', 'c.srai', 'c.srli', 'c.andi']:
+ # CI/CIW type
+ trace.rd = operands[0]
+ trace.rd_val = gpr[trace.rd]
+ trace.imm = get_imm_hex_val(operands[-1])
+ elif trace.instr in ['beq', 'bne', 'blt', 'bge', 'bltu', 'bgeu']:
+ # SB type instruction
+ trace.rs1 = operands[0]
+ trace.rs1_val = gpr[trace.rs1]
+ trace.rs2 = operands[1]
+ trace.rs2_val = gpr[trace.rs2]
+ trace.imm = get_imm_hex_val(operands[2])
+ elif trace.instr in ['c.beqz', 'c.bnez']:
+ # CB type instruction
+ trace.rs1 = operands[0]
+ trace.rs1_val = gpr[trace.rs1]
+ trace.imm = get_imm_hex_val(operands[1])
+ elif trace.instr in ['csrrw', 'csrrs', 'csrrc']:
+ trace.rd = operands[0]
+ trace.rd_val = gpr[trace.rd]
+ trace.csr = operands[1]
+ trace.rs1 = operands[2]
+ trace.rs1_val = gpr[trace.rs1]
+ elif trace.instr in ['csrrwi', 'csrrsi', 'csrrci']:
+ trace.rd = operands[0]
+ trace.rd_val = gpr[trace.rd]
+ trace.csr = operands[1]
+ trace.imm = get_imm_hex_val(operands[2])
+ elif trace.instr in ['scall', 'sbreak', 'fence', 'fence.i', 'ecall', 'ebreak', 'wfi',
+ 'sfence.vma', 'c.ebreak', 'nop', 'c.nop']:
+ trace.rd = 'zero'
+ trace.rs1 = 'zero'
+ trace.rs2 = 'zero'
+ trace.rd_val = '0'
+ trace.rs1_val = '0'
+ trace.rs2_val = '0'
+ trace.imm = get_imm_hex_val('0')
+ elif trace.instr in ['lui', 'auipc']:
+ trace.rd = operands[0]
+ trace.rd_val = gpr[trace.rd]
+ trace.imm = get_imm_hex_val(operands[1])
+ elif trace.instr in ['jal']:
+ if len(operands) == 1:
+ trace.imm = get_imm_hex_val(operands[0])
+ else:
+ trace.imm = get_imm_hex_val(operands[1])
+ elif trace.instr in ['jalr']:
+ if len(operands) == 1:
+ trace.rs1 = operands[0]
+ trace.rs1_val = gpr[trace.rs1]
+ trace.imm = get_imm_hex_val('0')
+ else:
+ trace.rs1 = operands[1]
+ trace.rs1_val = gpr[trace.rs1]
+ trace.imm = get_imm_hex_val(operands[2])
+ elif trace.instr in ['c.j', 'c.jal']:
+ trace.imm = get_imm_hex_val(operands[0])
+ # Pseudo instruction convertion below
+ elif trace.instr in ['mv']:
+ trace.instr = 'addi'
+ trace.rd = operands[0]
+ trace.rd_val = gpr[trace.rd]
+ trace.rs1 = operands[1]
+ trace.rs1_val = gpr[trace.rs1]
+ trace.imm = get_imm_hex_val('0')
+ elif trace.instr in ['not']:
+ trace.instr = 'xori'
+ trace.rd = operands[0]
+ trace.rd_val = gpr[trace.rd]
+ trace.rs1 = operands[1]
+ trace.rs1_val = gpr[trace.rs1]
+ trace.imm = get_imm_hex_val('-1')
+ elif trace.instr in ['neg']:
+ trace.instr = 'sub'
+ trace.rd = operands[0]
+ trace.rd_val = gpr[trace.rd]
+ trace.rs1 = 'zero'
+ trace.rs1_val = '0'
+ trace.rs1 = operands[1]
+ trace.rs1_val = gpr[trace.rs1]
+ elif trace.instr in ['negw']:
+ trace.instr = 'subw'
+ trace.rd = operands[0]
+ trace.rd_val = gpr[trace.rd]
+ trace.rs1 = 'zero'
+ trace.rs1_val = '0'
+ trace.rs2 = operands[1]
+ trace.rs2_val = gpr[trace.rs2]
+ elif trace.instr in ['sext.w']:
+ trace.instr = 'addiw'
+ trace.rd = operands[0]
+ trace.rd_val = gpr[trace.rd]
+ trace.rs1 = operands[1]
+ trace.rs1_val = gpr[trace.rs1]
+ trace.imm = get_imm_hex_val('0')
+ elif trace.instr in ['seqz']:
+ trace.instr = 'sltiu'
+ trace.rd = operands[0]
+ trace.rd_val = gpr[trace.rd]
+ trace.rs1 = operands[1]
+ trace.rs1_val = gpr[trace.rs1]
+ trace.imm = get_imm_hex_val('1')
+ elif trace.instr in ['snez']:
+ trace.instr = 'sltu'
+ trace.rd = operands[0]
+ trace.rd_val = gpr[trace.rd]
+ trace.rs1 = 'zero'
+ trace.rs1_val = '0'
+ trace.rs2 = operands[1]
+ trace.rs2_val = gpr[trace.rs2]
+ elif trace.instr in ['sltz']:
+ trace.instr = 'slt'
+ trace.rd = operands[0]
+ trace.rd_val = gpr[trace.rd]
+ trace.rs1 = operands[1]
+ trace.rs1_val = gpr[trace.rs1]
+ trace.rs2 = 'zero'
+ trace.rs2_val = '0'
+ elif trace.instr in ['sgtz']:
+ trace.instr = 'slt'
+ trace.rd = operands[0]
+ trace.rd_val = gpr[trace.rd]
+ trace.rs1 = 'zero'
+ trace.rs1_val = '0'
+ trace.rs2 = operands[1]
+ trace.rs2_val = gpr[trace.rs2]
+ elif trace.instr in ['beqz', 'bnez', 'bgez', 'bltz']:
+ trace.instr = trace.instr[0:3]
+ trace.rs1 = operands[0]
+ trace.rs1_val = gpr[trace.rs1]
+ trace.rs2 = 'zero'
+ trace.rs2_val = '0'
+ trace.imm = get_imm_hex_val(operands[1])
+ elif trace.instr in ['blez']:
+ trace.instr = 'bge'
+ trace.rs1 = 'zero'
+ trace.rs1_val = '0'
+ trace.rs2 = operands[0]
+ trace.rs2_val = gpr[trace.rs2]
+ trace.imm = get_imm_hex_val(operands[1])
+ elif trace.instr in ['bgtz']:
+ trace.instr = 'blt'
+ trace.rs1 = 'zero'
+ trace.rs1_val = '0'
+ trace.rs2 = operands[0]
+ trace.rs2_val = gpr[trace.rs2]
+ trace.imm = get_imm_hex_val(operands[1])
+ elif trace.instr in ['csrr']:
+ trace.instr = 'csrrw'
+ trace.rd = operands[0]
+ trace.rd_val = gpr[trace.rd]
+ trace.csr = operands[1]
+ trace.rs1 = 'zero'
+ trace.rs1_val = '0'
+ elif trace.instr in ['csrw', 'csrs', 'csrc']:
+ trace.instr = 'csrr' + trace.instr[-1]
+ trace.csr = operands[0]
+ trace.rs1 = operands[1]
+ trace.rs1_val = gpr[trace.rs1]
+ trace.rd = 'zero'
+ trace.rd_val = '0'
+ elif trace.instr in ['csrwi', 'csrsi', 'csrci']:
+ trace.instr = 'csrr' + trace.instr[-2:]
+ trace.rd = 'zero'
+ trace.rd_val = '0'
+ trace.csr = operands[0]
+ trace.imm = get_imm_hex_val(operands[1])
+ elif trace.instr in ['j']:
+ trace.instr = 'jal'
+ trace.rd = 'zero'
+ trace.rd_val = '0'
+ trace.imm = get_imm_hex_val(operands[0])
+ elif trace.instr in ['jr']:
+ trace.instr = 'jal'
+ trace.rd = 'zero'
+ trace.rd_val = '0'
+ trace.rs1 = operands[0]
+ if trace.rs1 in gpr:
+ trace.rs1_val = gpr[trace.rs1]
+ elif trace.instr in ['li']:
+ trace.instr = 'li'
+ elif trace.instr[0:2] in ['lr', 'am', 'sc']:
+ # TODO: Support A-extension
+ pass
+ else:
+ # TODO: Support other instructions
+ logging.info("Unsupported instr : %s" % trace.instr)
+
def main():
instr_trace = []
# Parse input arguments
parser = argparse.ArgumentParser()
parser.add_argument("--log", type=str, help="Input spike simulation log")
parser.add_argument("--csv", type=str, help="Output trace csv_buf file")
+ parser.add_argument("-f", "--full_trace", dest="full_trace", action="store_true",
+ help="Generate the full trace")
+ parser.add_argument("-v", "--verbose", dest="verbose", action="store_true",
+ help="Verbose logging")
+ parser.set_defaults(full_trace=False)
+ parser.set_defaults(verbose=False)
args = parser.parse_args()
+ setup_logging(args.verbose)
# Process spike log
- process_spike_sim_log(args.log, args.csv)
+ process_spike_sim_log(args.log, args.csv, args.full_trace)
if __name__ == "__main__":
diff --git a/hw/vendor/lowrisc_ibex/vendor/google_riscv-dv/setting/riscv_core_setting.sv b/hw/vendor/lowrisc_ibex/vendor/google_riscv-dv/setting/riscv_core_setting.sv
index 5ca55e0..c481c5f 100644
--- a/hw/vendor/lowrisc_ibex/vendor/google_riscv-dv/setting/riscv_core_setting.sv
+++ b/hw/vendor/lowrisc_ibex/vendor/google_riscv-dv/setting/riscv_core_setting.sv
@@ -35,6 +35,10 @@
// Interrupt mode support
mtvec_mode_t supported_interrupt_mode[$] = {DIRECT, VECTORED};
+// The number of interrupt vectors to be generated, only used if VECTORED interrupt mode is
+// supported
+int max_interrupt_vector_num = 16;
+
// Debug mode support
bit support_debug_mode = 0;
@@ -44,54 +48,12 @@
// Support sfence.vma instruction
bit support_sfence = 1;
-// Cache line size (in bytes)
-// If processor does not support caches, set to XLEN/8
-int dcache_line_size_in_bytes = 128;
-
-// Number of data section
-// For processor that doesn't have data TLB, this can be set to 1
-// For processor that supports data TLB, this should be set to be larger than the number
-// of entries of dTLB to cover dTLB hit/miss scenario
-int num_of_data_pages = 40;
-
-// Data section byte size
-// For processor with no dTLB and data cache, keep the value below 10K
-// For processor with dTLB support, set it to the physical memory size that covers one entry
-// of the dTLB
-int data_page_size = 4096;
-int data_page_alignment = $clog2(data_page_size);
-
-// The maximum data section byte size actually used by load/store instruction
-// Set to this value to be smaller than data_page_size. If there's data cache in the system,
-// this value should be set large enough to be able to hit cache hit/miss scenario within a data
-// section. Don't set this to too big as it will introduce a very large binary.
-int max_used_data_page_size = 512;
-
-// Stack section word length
-int stack_len = 5000;
-
-//-----------------------------------------------------------------------------
-// Kernel section setting, used by supervisor mode programs
-//-----------------------------------------------------------------------------
-
-// Number of kernel data pages
-int num_of_kernel_data_pages = 5;
-
-// Byte size of kernel data pages
-int kernel_data_page_size = 4096;
-
-// Kernel Stack section word length
-int kernel_stack_len = 5000;
-
-// Number of instructions for each kernel program
-int kernel_program_instr_cnt = 400;
-
// ----------------------------------------------------------------------------
// Previleged CSR implementation
// ----------------------------------------------------------------------------
// Implemented previlieged CSR list
-privileged_reg_t implemented_csr[$] = {
+parameter privileged_reg_t implemented_csr[] = {
// User mode CSR
USTATUS, // User status
UIE, // User interrupt-enable register
diff --git a/hw/vendor/lowrisc_ibex/vendor/google_riscv-dv/src/riscv_amo_instr_lib.sv b/hw/vendor/lowrisc_ibex/vendor/google_riscv-dv/src/riscv_amo_instr_lib.sv
index f16fe58..ba60035 100644
--- a/hw/vendor/lowrisc_ibex/vendor/google_riscv-dv/src/riscv_amo_instr_lib.sv
+++ b/hw/vendor/lowrisc_ibex/vendor/google_riscv-dv/src/riscv_amo_instr_lib.sv
@@ -15,14 +15,14 @@
*/
// Base class for AMO instruction stream
-class riscv_amo_base_instr_stream extends riscv_directed_instr_stream;
+class riscv_amo_base_instr_stream extends riscv_mem_access_stream;
rand int unsigned num_amo;
rand int unsigned num_mixed_instr;
rand int base;
rand riscv_reg_t rs1_reg;
- riscv_reg_t reserved_rd[$];
rand int unsigned data_page_id;
+ rand int max_load_store_offset;
// User can specify a small group of available registers to generate various hazard condition
rand riscv_reg_t avail_regs[];
@@ -48,58 +48,23 @@
function new(string name = "");
super.new(name);
- instr_list.rand_mode(0);
endfunction
function void post_randomize();
gen_amo_instr();
// rs1 cannot be modified by other instructions
if(!(rs1_reg inside {reserved_rd})) begin
- reserved_rd.push_back(rs1_reg);
+ reserved_rd = {reserved_rd, rs1_reg};
end
- add_mixed_instr();
- add_rs1_init_la_instr();
+ add_mixed_instr(num_mixed_instr);
+ add_rs1_init_la_instr(rs1_reg, data_page_id);
super.post_randomize();
endfunction
- // Use "la" instruction to initialize the base regiseter
- virtual function void add_rs1_init_la_instr();
- riscv_pseudo_instr la_instr;
- la_instr = riscv_pseudo_instr::type_id::create("la_instr");
- `DV_CHECK_RANDOMIZE_WITH_FATAL(la_instr,
- pseudo_instr_name == LA;
- rd == rs1_reg;,
- "Cannot randomize la_instr")
- if(access_u_mode_mem) begin
- la_instr.imm_str = $sformatf("data_page_%0d+%0d", data_page_id, base);
- end else begin
- la_instr.imm_str = $sformatf("kernel_data_page_%0d+%0d", data_page_id, base);
- end
- instr_list.push_front(la_instr);
- endfunction
-
// AMO instruction generation
virtual function void gen_amo_instr();
endfunction
- // Insert some other instructions to mix with load/store instruction
- virtual function void add_mixed_instr();
- riscv_rand_instr rand_instr;
- for(int i = 0; i < num_mixed_instr; i ++) begin
- rand_instr = riscv_rand_instr::type_id::create("rand_instr");
- rand_instr.cfg = cfg;
- rand_instr.reserved_rd = reserved_rd;
- `DV_CHECK_RANDOMIZE_WITH_FATAL(rand_instr,
- if(avail_regs.size() > 0) {
- rs1 inside {avail_regs};
- rd inside {avail_regs};
- }
- !(category inside {LOAD, STORE, BRANCH, JUMP});,
- "Cannot randomize instruction")
- insert_instr(rand_instr);
- end
- endfunction
-
endclass
// A pair of LR/SC instruction
@@ -159,10 +124,17 @@
amo_instr[i] = riscv_rand_instr::type_id::create($sformatf("amo_instr_%0d", i));
amo_instr[i].cfg = cfg;
amo_instr[i].disable_a_extension_c.constraint_mode(0);
- `DV_CHECK_RANDOMIZE_WITH_FATAL(amo_instr[i],
- rs1 == rs1_reg;
- rd != rs1_reg;
- category == AMO;)
+ `ifdef DSIM
+ `DV_CHECK_RANDOMIZE_WITH_FATAL(amo_instr[i],
+ rs1 == rs1_reg;
+ rd != rs1_reg;
+ instr_name inside {[AMOSWAP_W:AMOMAXU_D]};)
+ `else
+ `DV_CHECK_RANDOMIZE_WITH_FATAL(amo_instr[i],
+ rs1 == rs1_reg;
+ rd != rs1_reg;
+ category == AMO;)
+ `endif
instr_list.push_front(amo_instr[i]);
end
endfunction
diff --git a/hw/vendor/lowrisc_ibex/vendor/google_riscv-dv/src/riscv_asm_program_gen.sv b/hw/vendor/lowrisc_ibex/vendor/google_riscv-dv/src/riscv_asm_program_gen.sv
index 9011cb9..b72821c 100644
--- a/hw/vendor/lowrisc_ibex/vendor/google_riscv-dv/src/riscv_asm_program_gen.sv
+++ b/hw/vendor/lowrisc_ibex/vendor/google_riscv-dv/src/riscv_asm_program_gen.sv
@@ -29,8 +29,6 @@
// User mode programs
riscv_instr_sequence main_program;
riscv_instr_sequence sub_program[];
- // Program in binary format, stored in the data section, used to inject illegal/HINT instruction
- riscv_instr_sequence bin_program;
riscv_instr_sequence debug_program;
riscv_instr_sequence debug_sub_program[];
string instr_binary[$];
@@ -70,30 +68,12 @@
gen_program_header();
// Initialize general purpose registers
init_gpr();
- setup_misa();
- // Create all page tables
- create_page_table();
- // Setup privileged mode registers and enter target privileged mode
- pre_enter_privileged_mode();
- // Generate sub program in binary format
- // Illegal instruction and hint instruction cannot pass compilation, need to directly generate
- // the instruction in binary format and store in data section to skip compilation.
- if(cfg.enable_illegal_instruction || cfg.enable_hint_instruction) begin
- bin_program = riscv_instr_sequence::type_id::create("bin_program");
- bin_program.instr_cnt = cfg.bin_program_instr_cnt;
- bin_program.is_debug_program = 0;
- bin_program.label_name = bin_program.get_name();
- bin_program.cfg = cfg;
- if (cfg.enable_illegal_instruction) begin
- bin_program.illegal_instr_pct = $urandom_range(5, 20);
- end
- if (cfg.enable_hint_instruction) begin
- bin_program.hint_instr_pct = $urandom_range(5, 20);
- end
- `DV_CHECK_RANDOMIZE_FATAL(bin_program)
- bin_program.gen_instr(.is_main_program(0));
- bin_program.post_process_instr();
- bin_program.generate_binary_stream(instr_binary);
+ if (!cfg.bare_program_mode) begin
+ setup_misa();
+ // Create all page tables
+ create_page_table();
+ // Setup privileged mode registers and enter target privileged mode
+ pre_enter_privileged_mode();
end
// Init section
gen_init_section();
@@ -113,16 +93,17 @@
main_program.gen_instr(1);
// Setup jump instruction among main program and sub programs
gen_callstack(main_program, sub_program, sub_program_name, cfg.num_of_sub_program);
- if (bin_program != null) begin
- main_program.insert_jump_instr("sub_bin", 0);
- end
+ `uvm_info(`gfn, "Generating callstack...done", UVM_LOW)
main_program.post_process_instr();
+ `uvm_info(`gfn, "Post-processing main program...done", UVM_LOW)
main_program.generate_instr_stream();
+ `uvm_info(`gfn, "Generating main program instruction stream...done", UVM_LOW)
instr_stream = {instr_stream, main_program.instr_string_list};
// Test done section
gen_test_done();
// Shuffle the sub programs and insert to the instruction stream
insert_sub_program(sub_program, instr_stream);
+ `uvm_info(`gfn, "Inserting sub-programs...done", UVM_LOW)
// Reserve some space to copy instruction from data section
if (instr_binary.size() > 0) begin
instr_stream.push_back(".align 2");
@@ -132,45 +113,49 @@
instr_stream.push_back({indent, ".endr"});
instr_stream.push_back({indent, "ret"});
end
- // Privileged mode switch routine
- gen_privileged_mode_switch_routine();
+ `uvm_info(`gfn, "Main/sub program generation...done", UVM_LOW)
// Program end
gen_program_end();
- // Generate debug rom section
- gen_debug_rom();
- // Generate debug mode exception handler
- gen_debug_exception_handler();
+ if (!cfg.bare_program_mode) begin
+ // Privileged mode switch routine
+ gen_privileged_mode_switch_routine();
+ // Generate debug rom section
+ gen_debug_rom();
+ // Generate debug mode exception handler
+ gen_debug_exception_handler();
+ end
// Starting point of data section
gen_data_page_begin();
- // Generate the sub program in binary format
- gen_bin_program();
// Page table
- gen_page_table_section();
+ if (!cfg.bare_program_mode) begin
+ gen_page_table_section();
+ end
if(!cfg.no_data_page) begin
- // Data section
+ // Kernel data section
gen_data_page();
end
gen_data_page_end();
// Stack section
gen_stack_section();
- // Generate kernel program/data/stack section
- gen_kernel_sections();
+ if (!cfg.bare_program_mode) begin
+ // Generate kernel program/data/stack section
+ gen_kernel_sections();
+ end
endfunction
//---------------------------------------------------------------------------------------
// Generate kernel program/data/stack sections
//---------------------------------------------------------------------------------------
virtual function void gen_kernel_sections();
- instr_stream.push_back("_kernel_start: .align 12");
+ instr_stream.push_back("_kernel_instr_start: .align 12");
+ instr_stream.push_back(".text");
// Kernel programs
- if (cfg.init_privileged_mode != MACHINE_MODE) begin
+ if (cfg.virtual_addr_translation_on) begin
smode_accessible_umode_program = riscv_instr_sequence::type_id::
create("smode_accessible_umode_program");
gen_kernel_program(smode_accessible_umode_program);
- end
- smode_program = riscv_instr_sequence::type_id::create("smode_program");
- gen_kernel_program(smode_program);
- if (cfg.init_privileged_mode != MACHINE_MODE) begin
+ smode_program = riscv_instr_sequence::type_id::create("smode_program");
+ gen_kernel_program(smode_program);
smode_ls_umem_program = riscv_instr_sequence::type_id::create("smode_ls_umem_program");
gen_kernel_program(smode_ls_umem_program);
end
@@ -182,25 +167,29 @@
foreach(riscv_instr_pkg::supported_privileged_mode[i]) begin
gen_interrupt_handler_section(riscv_instr_pkg::supported_privileged_mode[i]);
end
- // Kernel data pages
- gen_kernel_data_page_begin();
- if(!cfg.no_data_page) begin
- // Data section
- gen_data_page(.is_kernel(1'b1));
+ instr_stream.push_back("_kernel_instr_end: nop");
+ // User stack and data pages may not be accessible when executing trap handling programs in
+ // machine/supervisor mode. Generate separate kernel data/stack sections to solve it.
+ if (cfg.virtual_addr_translation_on) begin
+ // Kernel data pages
+ instr_stream.push_back("_kernel_data_start: .align 12");
+ if(!cfg.no_data_page) begin
+ // Data section
+ gen_data_page(1'b1);
+ end
+ gen_data_page_end();
end
- gen_data_page_end();
// Kernel stack section
gen_kernel_stack_section();
- instr_stream.push_back("_kernel_end: nop");
endfunction
virtual function void gen_kernel_program(riscv_instr_sequence seq);
- seq.instr_cnt = riscv_instr_pkg::kernel_program_instr_cnt;
+ seq.instr_cnt = cfg.kernel_program_instr_cnt;
generate_directed_instr_stream(.label(seq.get_name()),
.original_instr_cnt(seq.instr_cnt),
.min_insert_cnt(0),
.instr_stream(seq.directed_instr),
- .access_u_mode_mem(1'b0));
+ .kernel_mode(1'b1));
seq.label_name = seq.get_name();
seq.is_debug_program = 0;
seq.cfg = cfg;
@@ -261,7 +250,7 @@
idx++;
pid = callstack_gen.program_h[i].sub_program_id[j] - 1;
`uvm_info(get_full_name(), $sformatf(
- "Gen jump instr %0d -> sub[%0d] %0d", i, j, pid+1), UVM_HIGH)
+ "Gen jump instr %0d -> sub[%0d] %0d", i, j, pid+1), UVM_LOW)
if(i == 0)
main_program.insert_jump_instr(sub_program_name[pid], idx);
else
@@ -290,10 +279,9 @@
//---------------------------------------------------------------------------------------
virtual function void gen_program_header();
- instr_stream.push_back(".macro init");
- instr_stream.push_back(".endm");
- instr_stream.push_back(".section .text.init");
+ instr_stream.push_back(".include \"user_define.h\"");
instr_stream.push_back(".globl _start");
+ instr_stream.push_back(".section .text");
instr_stream.push_back("_start:");
endfunction
@@ -309,12 +297,6 @@
instr_stream.push_back(".align 6; .global tohost; tohost: .dword 0;");
instr_stream.push_back(".align 6; .global fromhost; fromhost: .dword 0;");
instr_stream.push_back(".popsection;");
- instr_stream.push_back(".align 4;");
- endfunction
-
- virtual function void gen_kernel_data_page_begin();
- instr_stream.push_back(".data");
- instr_stream.push_back(".align 4;");
endfunction
virtual function void gen_data_page(bit is_kernel = 1'b0);
@@ -331,24 +313,28 @@
// Generate the user stack section
virtual function void gen_stack_section();
- instr_stream.push_back($sformatf(".align %0d", $clog2(XLEN)));
+ instr_stream.push_back(".pushsection .user_stack,\"aw\",@progbits;");
+ instr_stream.push_back(".align 12");
instr_stream.push_back("_user_stack_start:");
- instr_stream.push_back($sformatf(".rept %0d", riscv_instr_pkg::stack_len - 1));
+ instr_stream.push_back($sformatf(".rept %0d", cfg.stack_len - 1));
instr_stream.push_back($sformatf(".%0dbyte 0x0", XLEN/8));
instr_stream.push_back(".endr");
instr_stream.push_back("_user_stack_end:");
instr_stream.push_back($sformatf(".%0dbyte 0x0", XLEN/8));
+ instr_stream.push_back(".popsection;");
endfunction
// The kernal stack is used to save user program context before executing exception handling
virtual function void gen_kernel_stack_section();
- instr_stream.push_back($sformatf(".align %0d", $clog2(XLEN)));
+ instr_stream.push_back(".pushsection .kernel_stack,\"aw\",@progbits;");
+ instr_stream.push_back(".align 12");
instr_stream.push_back("_kernel_stack_start:");
- instr_stream.push_back($sformatf(".rept %0d", riscv_instr_pkg::kernel_stack_len - 1));
+ instr_stream.push_back($sformatf(".rept %0d", cfg.kernel_stack_len - 1));
instr_stream.push_back($sformatf(".%0dbyte 0x0", XLEN/8));
instr_stream.push_back(".endr");
instr_stream.push_back("_kernel_stack_end:");
instr_stream.push_back($sformatf(".%0dbyte 0x0", XLEN/8));
+ instr_stream.push_back(".popsection;");
endfunction
virtual function void gen_init_section();
@@ -399,10 +385,12 @@
// Write to the signature_addr with values to indicate to the core testbench
// that is safe to start sending interrupt and debug stimulus
virtual function void core_is_initialized();
+ string instr[$];
if (cfg.require_signature_addr) begin
if (cfg.signature_addr != 32'hdead_beef) begin
- string str;
- gen_signature_handshake(instr_stream, CORE_STATUS, INITIALIZED);
+ gen_signature_handshake(instr, CORE_STATUS, INITIALIZED);
+ format_section(instr);
+ instr_stream = {instr_stream, instr};
end else begin
`uvm_fatal(`gfn, "The signature_addr is not properly configured!")
end
@@ -434,7 +422,11 @@
string str = format_string("test_done:", LABEL_STR_LEN);
instr_stream.push_back(str);
instr_stream.push_back({indent, "li gp, 1"});
- instr_stream.push_back({indent, "ecall"});
+ if (cfg.bare_program_mode) begin
+ instr_stream.push_back({indent, "j write_tohost"});
+ end else begin
+ instr_stream.push_back({indent, "ecall"});
+ end
endfunction
// Dump all GPR to the starting point of the program
@@ -474,7 +466,7 @@
// Setup trap vector register
trap_vector_init();
// Initialize PTE (link page table based on their real physical address)
- if((SATP_MODE != BARE) && (cfg.init_privileged_mode != MACHINE_MODE)) begin
+ if(cfg.virtual_addr_translation_on) begin
page_table_list.process_page_table(instr);
gen_section("process_pt", instr);
end
@@ -486,6 +478,8 @@
privil_seq = riscv_privileged_common_seq::type_id::create("privil_seq");
foreach(riscv_instr_pkg::supported_privileged_mode[i]) begin
string instr[$];
+ string csr_handshake[$];
+ string ret_instr;
if(riscv_instr_pkg::supported_privileged_mode[i] < cfg.init_privileged_mode) continue;
`uvm_info(`gfn, $sformatf("Generating privileged mode routing for %0s",
riscv_instr_pkg::supported_privileged_mode[i].name()), UVM_LOW)
@@ -493,6 +487,27 @@
privil_seq.cfg = cfg;
`DV_CHECK_RANDOMIZE_FATAL(privil_seq)
privil_seq.enter_privileged_mode(riscv_instr_pkg::supported_privileged_mode[i], instr);
+ if (cfg.require_signature_addr) begin
+ ret_instr = instr.pop_back();
+ // Want to write the main system CSRs to the testbench before indicating that initialization
+ // is complete, for any initial state analysis
+ case(riscv_instr_pkg::supported_privileged_mode[i])
+ MACHINE_MODE: begin
+ gen_signature_handshake(.instr(csr_handshake), .signature_type(WRITE_CSR), .csr(MSTATUS));
+ gen_signature_handshake(.instr(csr_handshake), .signature_type(WRITE_CSR), .csr(MIE));
+ end
+ SUPERVISOR_MODE: begin
+ gen_signature_handshake(.instr(csr_handshake), .signature_type(WRITE_CSR), .csr(SSTATUS));
+ gen_signature_handshake(.instr(csr_handshake), .signature_type(WRITE_CSR), .csr(SIE));
+ end
+ USER_MODE: begin
+ gen_signature_handshake(.instr(csr_handshake), .signature_type(WRITE_CSR), .csr(USTATUS));
+ gen_signature_handshake(.instr(csr_handshake), .signature_type(WRITE_CSR), .csr(UIE));
+ end
+ endcase
+ format_section(csr_handshake);
+ instr = {instr, csr_handshake, ret_instr};
+ end
instr_stream = {instr_stream, instr};
end
endfunction
@@ -502,7 +517,7 @@
string instr[];
string mode_name;
instr = {"la x10, _init"};
- if(SATP_MODE != BARE && cfg.init_privileged_mode != MACHINE_MODE) begin
+ if(cfg.virtual_addr_translation_on) begin
// For supervisor and user mode, use virtual address instead of physical address.
// Virtual address starts from address 0x0, here only the lower 12 bits are kept
// as virtual address offset.
@@ -582,7 +597,7 @@
if (riscv_instr_pkg::supported_privileged_mode[i] < cfg.init_privileged_mode) continue;
tvec_name = trap_vec_reg.name();
instr = {instr, $sformatf("la a0, %0s_handler", tvec_name.tolower())};
- if(SATP_MODE != BARE && riscv_instr_pkg::supported_privileged_mode[i] != MACHINE_MODE) begin
+ if (SATP_MODE != BARE && riscv_instr_pkg::supported_privileged_mode[i] != MACHINE_MODE) begin
// For supervisor and user mode, use virtual address instead of physical address.
// Virtual address starts from address 0x0, here only the lower 20 bits are kept
// as virtual address offset.
@@ -607,12 +622,12 @@
if(riscv_instr_pkg::supported_privileged_mode[i] < cfg.init_privileged_mode) continue;
case(riscv_instr_pkg::supported_privileged_mode[i])
MACHINE_MODE:
- gen_trap_handler_section("m", MCAUSE, MTVEC, MTVAL, MEPC, MSCRATCH, MSTATUS);
+ gen_trap_handler_section("m", MCAUSE, MTVEC, MTVAL, MEPC, MSCRATCH, MSTATUS, MIE, MIP);
SUPERVISOR_MODE:
- gen_trap_handler_section("s", SCAUSE, STVEC, STVAL, SEPC, SSCRATCH, SSTATUS);
+ gen_trap_handler_section("s", SCAUSE, STVEC, STVAL, SEPC, SSCRATCH, SSTATUS, SIE, SIP);
USER_MODE:
if(riscv_instr_pkg::support_umode_trap)
- gen_trap_handler_section("u", UCAUSE, UTVEC, UTVAL, UEPC, USCRATCH, USTATUS);
+ gen_trap_handler_section("u", UCAUSE, UTVEC, UTVAL, UEPC, USCRATCH, USTATUS, UIE, UIP);
endcase
end
// Ebreak handler
@@ -621,6 +636,12 @@
gen_ecall_handler();
// Illegal instruction handler
gen_illegal_instr_handler();
+ // Instruction fault handler
+ gen_instr_fault_handler();
+ // Load fault handler
+ gen_load_fault_handler();
+ // Store fault handler
+ gen_store_fault_handler();
// Generate page table fault handling routine
// Page table fault is always handled in machine mode, as virtual address translation may be
// broken when page fault happens.
@@ -639,12 +660,13 @@
virtual function void gen_trap_handler_section(string mode,
privileged_reg_t cause, privileged_reg_t tvec,
privileged_reg_t tval, privileged_reg_t epc,
- privileged_reg_t scratch, privileged_reg_t status);
+ privileged_reg_t scratch, privileged_reg_t status,
+ privileged_reg_t ie, privileged_reg_t ip);
bit is_interrupt = 'b1;
string tvec_name;
string instr[$];
if (cfg.mtvec_mode == VECTORED) begin
- gen_interrupt_vector_table(mode, status, cause, scratch, instr);
+ gen_interrupt_vector_table(mode, status, cause, ie, ip, scratch, instr);
end else begin
// Push user mode GPR to kernel stack before executing exception handling, this is to avoid
// exception handling routine modify user program state unexpectedly
@@ -691,11 +713,11 @@
"beq a1, a2, ecall_handler",
// Page table fault or access fault conditions
$sformatf("li a2, 0x%0x", INSTRUCTION_ACCESS_FAULT),
- "beq a1, a2, pt_fault_handler",
+ "beq a1, a2, instr_fault_handler",
$sformatf("li a2, 0x%0x", LOAD_ACCESS_FAULT),
- "beq a1, a2, pt_fault_handler",
+ "beq a1, a2, load_fault_handler",
$sformatf("li a2, 0x%0x", STORE_AMO_ACCESS_FAULT),
- "beq a1, a2, pt_fault_handler",
+ "beq a1, a2, store_fault_handler",
$sformatf("li a2, 0x%0x", INSTRUCTION_PAGE_FAULT),
"beq a1, a2, pt_fault_handler",
$sformatf("li a2, 0x%0x", LOAD_PAGE_FAULT),
@@ -716,6 +738,8 @@
virtual function void gen_interrupt_vector_table(string mode,
privileged_reg_t status,
privileged_reg_t cause,
+ privileged_reg_t ie,
+ privileged_reg_t ip,
privileged_reg_t scratch,
ref string instr[$]);
@@ -727,22 +751,27 @@
instr = {instr, ".option norvc;",
$sformatf("j %0smode_exception_handler", mode)};
// Redirect the interrupt to the corresponding interrupt handler
- for (int i = 1; i < 16; i++) begin
+ for (int i = 1; i < max_interrupt_vector_num; i++) begin
instr.push_back($sformatf("j %0smode_intr_vector_%0d", mode, i));
end
instr = {instr, ".option rvc;"};
- for (int i = 1; i < 16; i++) begin
+ for (int i = 1; i < max_interrupt_vector_num; i++) begin
string intr_handler[$];
push_gpr_to_kernel_stack(status, scratch, cfg.mstatus_mprv, intr_handler);
- gen_signature_handshake(intr_handler, CORE_STATUS, HANDLING_IRQ);
+ gen_signature_handshake(.instr(intr_handler), .signature_type(CORE_STATUS), .core_status(HANDLING_IRQ));
intr_handler = {intr_handler,
- $sformatf("csrr a1, 0x%0x # %0s", cause, cause.name()),
- // Terminate the test if xCause[31] != 0 (indicating exception)
- $sformatf("bltz a1, 1f"),
- // TODO(taliu) write xCause to the signature address
+ $sformatf("csrr a1, 0x%0x # %0s", cause, cause.name()),
+ // Terminate the test if xCause[31] != 0 (indicating exception)
+ $sformatf("srli a1, a1, 0x%0x", XLEN-1),
+ $sformatf("beqz a1, 1f")};
+ gen_signature_handshake(.instr(intr_handler), .signature_type(WRITE_CSR), .csr(status));
+ gen_signature_handshake(.instr(intr_handler), .signature_type(WRITE_CSR), .csr(cause));
+ gen_signature_handshake(.instr(intr_handler), .signature_type(WRITE_CSR), .csr(ie));
+ gen_signature_handshake(.instr(intr_handler), .signature_type(WRITE_CSR), .csr(ip));
// Jump to commmon interrupt handling routine
- $sformatf("j %0smode_intr_handler", mode),
- "1: j test_done"};
+ intr_handler = {intr_handler,
+ $sformatf("j %0smode_intr_handler", mode),
+ "1: j test_done"};
gen_section($sformatf("%0smode_intr_vector_%0d", mode, i), intr_handler);
end
endfunction
@@ -768,9 +797,11 @@
// guarantees that epc + 4 is a valid instruction boundary
// TODO: Support random operations in debug mode
// TODO: Support ebreak exception delegation
+ // TODO: handshake the correct Xcause CSR based on delegation privil. mode
virtual function void gen_ebreak_handler();
string instr[$];
- gen_signature_handshake(instr, CORE_STATUS, HANDLING_EXCEPTION);
+ gen_signature_handshake(instr, CORE_STATUS, EBREAK_EXCEPTION);
+ gen_signature_handshake(.instr(instr), .signature_type(WRITE_CSR), .csr(MCAUSE));
instr = {instr,
"csrr x31, mepc",
"addi x31, x31, 4",
@@ -787,9 +818,11 @@
// know the illegal instruction is compressed or not. This hanlder just simply adds the PC by
// 4 and resumes execution. The way that the illegal instruction is injected guarantees that
// PC + 4 is a valid instruction boundary.
+ // TODO: handshake the corret Xcause CSR based on delegation setup
virtual function void gen_illegal_instr_handler();
string instr[$];
- gen_signature_handshake(instr, CORE_STATUS, HANDLING_EXCEPTION);
+ gen_signature_handshake(instr, CORE_STATUS, ILLEGAL_INSTR_EXCEPTION);
+ gen_signature_handshake(.instr(instr), .signature_type(WRITE_CSR), .csr(MCAUSE));
instr = {instr,
"csrr x31, mepc",
"addi x31, x31, 4",
@@ -800,6 +833,36 @@
gen_section("illegal_instr_handler", instr);
endfunction
+ // TODO: handshake correct csr based on delegation
+ virtual function void gen_instr_fault_handler();
+ string instr[$];
+ gen_signature_handshake(instr, CORE_STATUS, INSTR_FAULT_EXCEPTION);
+ gen_signature_handshake(.instr(instr), .signature_type(WRITE_CSR), .csr(MCAUSE));
+ pop_gpr_from_kernel_stack(MSTATUS, MSCRATCH, cfg.mstatus_mprv, instr);
+ instr.push_back("mret");
+ gen_section("instr_fault_handler", instr);
+ endfunction
+
+ // TODO: handshake correct csr based on delegation
+ virtual function void gen_load_fault_handler();
+ string instr[$];
+ gen_signature_handshake(instr, CORE_STATUS, LOAD_FAULT_EXCEPTION);
+ gen_signature_handshake(.instr(instr), .signature_type(WRITE_CSR), .csr(MCAUSE));
+ pop_gpr_from_kernel_stack(MSTATUS, MSCRATCH, cfg.mstatus_mprv, instr);
+ instr.push_back("mret");
+ gen_section("load_fault_handler", instr);
+ endfunction
+
+ // TODO: handshake correct csr based on delegation
+ virtual function void gen_store_fault_handler();
+ string instr[$];
+ gen_signature_handshake(instr, CORE_STATUS, STORE_FAULT_EXCEPTION);
+ gen_signature_handshake(.instr(instr), .signature_type(WRITE_CSR), .csr(MCAUSE));
+ pop_gpr_from_kernel_stack(MSTATUS, MSCRATCH, cfg.mstatus_mprv, instr);
+ instr.push_back("mret");
+ gen_section("store_fault_handler", instr);
+ endfunction
+
//---------------------------------------------------------------------------------------
// Page table setup
//---------------------------------------------------------------------------------------
@@ -810,7 +873,7 @@
// all the other super pages are link PTE.
virtual function void create_page_table();
string instr[];
- if((SATP_MODE != BARE) && (cfg.init_privileged_mode != MACHINE_MODE)) begin
+ if(cfg.virtual_addr_translation_on) begin
page_table_list = riscv_page_table_list#(SATP_MODE)::
type_id::create("page_table_list");
page_table_list.cfg = cfg;
@@ -830,10 +893,12 @@
virtual function void gen_page_table_section();
string page_table_section[$];
if(page_table_list != null) begin
+ instr_stream.push_back(".pushsection .page_table,\"aw\",@progbits;");
foreach(page_table_list.page_table[i]) begin
page_table_list.page_table[i].gen_page_table_section(page_table_section);
instr_stream = {instr_stream, page_table_section};
end
+ instr_stream.push_back(".popsection;");
end
endfunction
@@ -841,6 +906,10 @@
// In this case, the core will write to a specific location as the response to the interrupt, and
// external PLIC unit can detect this response and process the interrupt clean up accordingly.
virtual function void gen_plic_section(ref string interrupt_handler_instr[$]);
+ // Utilize the memory mapped handshake scheme to signal the testbench that the interrupt
+ // handling has been completed and we are about to xRET out of the handler
+ gen_signature_handshake(.instr(interrupt_handler_instr), .signature_type(CORE_STATUS),
+ .core_status(FINISHED_IRQ));
endfunction
// Interrupt handler routine
@@ -924,6 +993,11 @@
// Dump performance CSRs if applicable
virtual function void dump_perf_stats();
+ foreach(implemented_csr[i]) begin
+ if (implemented_csr[i] inside {[MCYCLE:MHPMCOUNTER31H]}) begin
+ gen_signature_handshake(.instr(instr_stream), .signature_type(WRITE_CSR), .csr(implemented_csr[i]));
+ end
+ end
endfunction
// Write the generated program to a file
@@ -943,39 +1017,34 @@
input signature_type_t signature_type,
core_status_t core_status = INITIALIZED,
test_result_t test_result = TEST_FAIL,
- privileged_reg_t csr = MSCRATCH);
+ privileged_reg_t csr = MSCRATCH,
+ string addr_label = "");
if (cfg.require_signature_addr) begin
- string str;
- str = $sformatf("li x%0d, 0x%0h", cfg.signature_addr_reg, cfg.signature_addr);
- instr.push_back(str);
+ string str[$];
+ str = {$sformatf("li x%0d, 0x%0h", cfg.signature_addr_reg, cfg.signature_addr)};
+ instr = {instr, str};
case (signature_type)
// A single data word is written to the signature address.
// Bits [7:0] contain the signature_type of CORE_STATUS, and the upper
// XLEN-8 bits contain the core_status_t data.
CORE_STATUS: begin
- str = $sformatf("li x%0d, 0x%0h", cfg.signature_data_reg, core_status);
- instr.push_back(str);
- str = $sformatf("slli x%0d, x%0d, 8", cfg.signature_data_reg, cfg.signature_data_reg);
- instr.push_back(str);
- str = $sformatf("addi x%0d, x%0d, 0x%0h", cfg.signature_data_reg,
- cfg.signature_data_reg, signature_type);
- instr.push_back(str);
- str = $sformatf("sw x%0d, 0(x%0d)", cfg.signature_data_reg, cfg.signature_addr_reg);
- instr.push_back(str);
+ str = {$sformatf("li x%0d, 0x%0h", cfg.signature_data_reg, core_status),
+ $sformatf("slli x%0d, x%0d, 8", cfg.signature_data_reg, cfg.signature_data_reg),
+ $sformatf("addi x%0d, x%0d, 0x%0h", cfg.signature_data_reg,
+ cfg.signature_data_reg, signature_type),
+ $sformatf("sw x%0d, 0(x%0d)", cfg.signature_data_reg, cfg.signature_addr_reg)};
+ instr = {instr, str};
end
// A single data word is written to the signature address.
// Bits [7:0] contain the signature_type of TEST_RESULT, and the upper
// XLEN-8 bits contain the test_result_t data.
TEST_RESULT: begin
- str = $sformatf("li x%0d, 0x%0h", cfg.signature_data_reg, test_result);
- instr.push_back(str);
- str = $sformatf("slli x%0d, x%0d, 8", cfg.signature_data_reg, cfg.signature_data_reg);
- instr.push_back(str);
- str = $sformatf("addi x%0d, x%0d, 0x%0h", cfg.signature_data_reg,
- cfg.signature_data_reg, signature_type);
- instr.push_back(str);
- str = $sformatf("sw x%0d, 0(x%0d)", cfg.signature_data_reg, cfg.signature_addr_reg);
- instr.push_back(str);
+ str = {$sformatf("li x%0d, 0x%0h", cfg.signature_data_reg, test_result),
+ $sformatf("slli x%0d, x%0d, 8", cfg.signature_data_reg, cfg.signature_data_reg),
+ $sformatf("addi x%0d, x%0d, 0x%0h", cfg.signature_data_reg,
+ cfg.signature_data_reg, signature_type),
+ $sformatf("sw x%0d, 0(x%0d)", cfg.signature_data_reg, cfg.signature_addr_reg)};
+ instr = {instr, str};
end
// The first write to the signature address contains just the
// signature_type of WRITE_GPR.
@@ -983,13 +1052,12 @@
// each writing the data contained in one GPR, starting from x0 as the
// first write, and ending with x31 as the 32nd write.
WRITE_GPR: begin
- str = $sformatf("li x%0d, 0x%0h", cfg.signature_data_reg, signature_type);
- instr.push_back(str);
- str = $sformatf("sw x%0d, 0(x%0d)", cfg.signature_data_reg, cfg.signature_addr_reg);
- instr.push_back(str);
+ str = {$sformatf("li x%0d, 0x%0h", cfg.signature_data_reg, signature_type),
+ $sformatf("sw x%0d, 0(x%0d)", cfg.signature_data_reg, cfg.signature_addr_reg)};
+ instr = {instr, str};
for(int i = 0; i < 32; i++) begin
- str = $sformatf("sw x%0x, 0(x%0d)", i, cfg.signature_addr_reg);
- instr.push_back(str);
+ str = {$sformatf("sw x%0x, 0(x%0d)", i, cfg.signature_addr_reg)};
+ instr = {instr, str};
end
end
// The first write to the signature address contains the
@@ -998,19 +1066,14 @@
// It is followed by a second write to the signature address,
// containing the data stored in the specified CSR.
WRITE_CSR: begin
- str = $sformatf("li x%0d, 0x%0h", cfg.signature_data_reg, csr);
- instr.push_back(str);
- str = $sformatf("slli x%0d, x%0d, 8", cfg.signature_data_reg, cfg.signature_data_reg);
- instr.push_back(str);
- str = $sformatf("addi x%0d, x%0d, 0x%0h", cfg.signature_data_reg,
- cfg.signature_data_reg, signature_type);
- instr.push_back(str);
- str = $sformatf("sw x%0d, 0(x%0d)", cfg.signature_data_reg, cfg.signature_addr_reg);
- instr.push_back(str);
- str = $sformatf("csrr x%0d, 0x%0h", cfg.signature_data_reg, csr);
- instr.push_back(str);
- str = $sformatf("sw x%0d, 0(x%0d)", cfg.signature_data_reg, cfg.signature_addr_reg);
- instr.push_back(str);
+ str = {$sformatf("li x%0d, 0x%0h", cfg.signature_data_reg, csr),
+ $sformatf("slli x%0d, x%0d, 8", cfg.signature_data_reg, cfg.signature_data_reg),
+ $sformatf("addi x%0d, x%0d, 0x%0h", cfg.signature_data_reg,
+ cfg.signature_data_reg, signature_type),
+ $sformatf("sw x%0d, 0(x%0d)", cfg.signature_data_reg, cfg.signature_addr_reg),
+ $sformatf("csrr x%0d, 0x%0h", cfg.signature_data_reg, csr),
+ $sformatf("sw x%0d, 0(x%0d)", cfg.signature_data_reg, cfg.signature_addr_reg)};
+ instr = {instr, str};
end
default: begin
`uvm_fatal(`gfn, "signature_type is not defined")
@@ -1025,6 +1088,7 @@
virtual function void add_directed_instr_stream(string name, int unsigned ratio);
directed_instr_stream_ratio[name] = ratio;
+ `uvm_info(`gfn, $sformatf("Adding directed instruction stream:%0s ratio:%0d/1000", name, ratio), UVM_LOW)
endfunction
virtual function void get_directed_instr_stream();
@@ -1048,7 +1112,7 @@
virtual function void generate_directed_instr_stream(input string label,
input int unsigned original_instr_cnt,
input int unsigned min_insert_cnt = 0,
- input bit access_u_mode_mem = 1,
+ input bit kernel_mode = 0,
output riscv_instr_stream instr_stream[]);
uvm_object object_h;
riscv_rand_instr_stream new_instr_stream;
@@ -1062,6 +1126,14 @@
if(instr_insert_cnt <= min_insert_cnt) begin
instr_insert_cnt = min_insert_cnt;
end
+ `ifdef DSIM
+ // Temporarily skip loop instruction for dsim as it cannot support dynamic array
+ // randomization
+ if (uvm_is_match("*loop*", instr_stream_name)) begin
+ `uvm_info(`gfn, $sformatf("%0s is skipped", instr_stream_name), UVM_LOW)
+ continue;
+ end
+ `endif
`uvm_info(get_full_name(), $sformatf("Insert directed instr stream %0s %0d/%0d times",
instr_stream_name, instr_insert_cnt, original_instr_cnt), UVM_LOW)
for(int i = 0; i < instr_insert_cnt; i++) begin
@@ -1073,7 +1145,7 @@
if($cast(new_instr_stream, object_h)) begin
new_instr_stream.cfg = cfg;
new_instr_stream.label = $sformatf("%0s_instr_%0d", label, idx);
- new_instr_stream.access_u_mode_mem = access_u_mode_mem;
+ new_instr_stream.kernel_mode = kernel_mode;
`DV_CHECK_RANDOMIZE_FATAL(new_instr_stream)
instr_stream = {instr_stream, new_instr_stream};
end else begin
@@ -1085,45 +1157,84 @@
instr_stream.shuffle();
endfunction
- // Generate sub-program in binary format, this is needed for illegal and HINT instruction
- function void gen_bin_program();
- if (bin_program != null) begin
- string str;
- instr_stream.push_back("instr_bin:");
- instr_stream.push_back(".align 12");
- foreach (instr_binary[i]) begin
- if (((i+1) % 8 == 0) || (i == instr_binary.size() - 1)) begin
- if (str != "")
- instr_stream.push_back($sformatf(".word %0s, %0s", str, instr_binary[i]));
- else
- instr_stream.push_back($sformatf(".word %0s", instr_binary[i]));
- str = "";
- end else begin
- if (str != "") begin
- str = {str, ", ", instr_binary[i]};
- end else begin
- str = instr_binary[i];
- end
- end
- end
- end
- endfunction
+ //---------------------------------------------------------------------------------------
+ // Generate the debug rom, and any related programs
+ //---------------------------------------------------------------------------------------
// Generate the program in the debug ROM
// Processor will fetch instruction from here upon receiving debug request from debug module
virtual function void gen_debug_rom();
- string push_gpr[$];
- string pop_gpr[$];
string instr[$];
+ string debug_end[$];
string dret;
string debug_sub_program_name[$] = {};
+ string str[$];
if (riscv_instr_pkg::support_debug_mode) begin
- // Signal that the core entered the debug rom regardless of whether the
- // main debug rom program has been generated
- gen_signature_handshake(instr, CORE_STATUS, IN_DEBUG_MODE);
- format_section(instr);
+ dret = {format_string(" ", LABEL_STR_LEN), "dret"};
// The main debug rom
- if (cfg.gen_debug_section) begin
+ if (!cfg.gen_debug_section) begin
+ // If the debug section should not be generated, we just populate it
+ // with a dret instruction.
+ instr = {dret};
+ gen_section("debug_rom", instr);
+ end else begin
+ if (cfg.enable_ebreak_in_debug_rom) begin
+ // As execution of ebreak in D mode causes core to
+ // re-enter D mode, this directed sequence will be a loop that ensures the
+ // ebreak instruction will only be executed once to prevent infinitely
+ // looping back to the beginning of the debug rom.
+ // Write dscratch to random GPR and branch to debug_end if greater
+ // than 0, for ebreak loops.
+ // Use dscratch1 to store original GPR value.
+ str = {$sformatf("csrw 0x%0x, x%0d", DSCRATCH1, cfg.scratch_reg),
+ $sformatf("csrr x%0d, 0x%0x", cfg.scratch_reg, DSCRATCH0)};
+ instr = {instr, str};
+ // send dpc and dcsr to testbench, as this handshake will be
+ // executed twice due to the ebreak loop, there should be no change
+ // in their values as by the Debug Mode Spec Ch. 4.1.8
+ gen_signature_handshake(.instr(instr), .signature_type(WRITE_CSR), .csr(DCSR));
+ gen_signature_handshake(.instr(instr), .signature_type(WRITE_CSR), .csr(DPC));
+ str = {$sformatf("beq x%0d, x0, 1f", cfg.scratch_reg),
+ $sformatf("j debug_end"),
+ $sformatf("1: csrr x%0d, 0x%0x", cfg.scratch_reg, DSCRATCH1)};
+ instr = {instr, str};
+ end
+ // Need to save off GPRs to avoid modifying program flow
+ push_gpr_to_kernel_stack(MSTATUS, MSCRATCH, cfg.mstatus_mprv, instr);
+ // Signal that the core entered debug rom only if the rom is actually
+ // being filled with random instructions to prevent stress tests from
+ // having to execute unnecessary push/pop of GPRs on the stack ever
+ // time a debug request is sent
+ gen_signature_handshake(instr, CORE_STATUS, IN_DEBUG_MODE);
+ if (cfg.set_dcsr_ebreak) begin
+ // We want to set dcsr.ebreak(m/s/u) to 1'b1, depending on what modes
+ // are available.
+ // TODO(udinator) - randomize the dcsr.ebreak setup
+ gen_dcsr_ebreak(instr);
+ end
+ // Check dcsr.cause, and update dpc by 0x4 if the cause is ebreak, as
+ // ebreak will set set dpc to its own address, which will cause an
+ // infinite loop.
+ str = {$sformatf("csrr x%0d, 0x%0x", cfg.scratch_reg, DCSR),
+ $sformatf("slli x%0d, x%0d, 0x17", cfg.scratch_reg, cfg.scratch_reg),
+ $sformatf("srli x%0d, x%0d, 0x1d", cfg.scratch_reg, cfg.scratch_reg),
+ $sformatf("li x%0d, 0x1", cfg.signature_data_reg),
+ $sformatf("bne x%0d, x%0d, 2f", cfg.scratch_reg, cfg.signature_data_reg)};
+ instr = {instr, str};
+ increment_csr(DPC, 4, instr);
+ str = {"2: nop"};
+ instr = {instr, str};
+ // write DCSR to the testbench for any analysis
+ gen_signature_handshake(.instr(instr), .signature_type(WRITE_CSR), .csr(DCSR));
+ // Increment dscratch0 by 1 to update the loop counter for all ebreak
+ // tests
+ if (cfg.enable_ebreak_in_debug_rom || cfg.set_dcsr_ebreak) begin
+ // Add 1 to dscratch0
+ increment_csr(DSCRATCH0, 1, instr);
+ str = {$sformatf("csrr x%0d, 0x%0x", cfg.scratch_reg, DSCRATCH1)};
+ instr = {instr, str};
+ end
+ format_section(instr);
gen_sub_program(debug_sub_program, debug_sub_program_name,
cfg.num_debug_sub_program, 1'b1, "debug_sub");
debug_program = riscv_instr_sequence::type_id::create("debug_program");
@@ -1136,17 +1247,28 @@
cfg.num_debug_sub_program);
debug_program.post_process_instr();
debug_program.generate_instr_stream(.no_label(1'b1));
- // Need to save off GPRs to avoid modifying program flow
- push_gpr_to_kernel_stack(MSTATUS, MSCRATCH, cfg.mstatus_mprv, push_gpr);
- format_section(push_gpr);
- pop_gpr_from_kernel_stack(MSTATUS, MSCRATCH, cfg.mstatus_mprv, pop_gpr);
- format_section(pop_gpr);
- instr = {push_gpr, instr, debug_program.instr_string_list, pop_gpr};
insert_sub_program(debug_sub_program, instr_stream);
+ instr = {instr, debug_program.instr_string_list};
+ gen_section("debug_rom", instr);
+ // Set dscratch0 back to 0x0 to prepare for the next entry into debug
+ // mode, and write dscratch0 and dcsr to the testbench for any
+ // analysis
+ if (cfg.enable_ebreak_in_debug_rom) begin
+ str = {$sformatf("csrwi 0x%0x, 0x0", DSCRATCH0)};
+ debug_end = {debug_end, str};
+ end
+ pop_gpr_from_kernel_stack(MSTATUS, MSCRATCH, cfg.mstatus_mprv, debug_end);
+ // We have been using dscratch1 to store the
+ // value of our given scratch register for use in ebreak loop, so we
+ // need to restore its value before returning from D mode
+ if (cfg.enable_ebreak_in_debug_rom) begin
+ str = {$sformatf("csrr x%0d, 0x%0x", cfg.scratch_reg, DSCRATCH1)};
+ debug_end = {debug_end, str};
+ end
+ format_section(debug_end);
+ debug_end = {debug_end, dret};
+ gen_section("debug_end", debug_end);
end
- dret = {format_string(" ", LABEL_STR_LEN), "dret"};
- instr = {instr, dret};
- gen_section("debug_rom", instr);
end
endfunction
@@ -1159,4 +1281,38 @@
end
endfunction
+ // Set dcsr.ebreak(m/s/u)
+ // TODO(udinator) - randomize the setup for these fields
+ virtual function void gen_dcsr_ebreak(ref string instr[$]);
+ string str;
+ if (MACHINE_MODE inside {riscv_instr_pkg::supported_privileged_mode}) begin
+ str = $sformatf("li x%0d, 0x8000", cfg.scratch_reg);
+ instr.push_back(str);
+ str = $sformatf("csrs dcsr, x%0d", cfg.scratch_reg);
+ instr.push_back(str);
+ end
+ if (SUPERVISOR_MODE inside {riscv_instr_pkg::supported_privileged_mode}) begin
+ str = $sformatf("li x%0d, 0x2000", cfg.scratch_reg);
+ instr.push_back(str);
+ str = $sformatf("csrs dcsr, x%0d", cfg.scratch_reg);
+ instr.push_back(str);
+ end
+ if (USER_MODE inside {riscv_instr_pkg::supported_privileged_mode}) begin
+ str = $sformatf("li x%0d, 0x1000", cfg.scratch_reg);
+ instr.push_back(str);
+ str = $sformatf("csrs dcsr, x%0d", cfg.scratch_reg);
+ instr.push_back(str);
+ end
+ endfunction
+
+ virtual function void increment_csr(privileged_reg_t csr, int val, ref string instr[$]);
+ string str;
+ str = $sformatf("csrr x%0d, 0x%0x", cfg.scratch_reg, csr);
+ instr.push_back(str);
+ str = $sformatf("addi x%0d, x%0d, 0x%0x", cfg.scratch_reg, cfg.scratch_reg, val);
+ instr.push_back(str);
+ str = $sformatf("csrw 0x%0x, x%0d", csr, cfg.scratch_reg);
+ instr.push_back(str);
+ endfunction
+
endclass
diff --git a/hw/vendor/lowrisc_ibex/vendor/google_riscv-dv/src/riscv_callstack_gen.sv b/hw/vendor/lowrisc_ibex/vendor/google_riscv-dv/src/riscv_callstack_gen.sv
index 31f4235..6acd90f 100644
--- a/hw/vendor/lowrisc_ibex/vendor/google_riscv-dv/src/riscv_callstack_gen.sv
+++ b/hw/vendor/lowrisc_ibex/vendor/google_riscv-dv/src/riscv_callstack_gen.sv
@@ -78,12 +78,16 @@
riscv_program program_h[];
// Maximum call stack level
int max_stack_level = 50;
+`ifdef DSIM
+ // Call stack level of each program
+ bit[10:0] stack_level[];
+`else
// Call stack level of each program
rand bit[10:0] stack_level[];
constraint program_stack_level_c {
- stack_level.size() == program_cnt;
// The stack level is assigned in ascending order to avoid call loop
+ stack_level.size() == program_cnt;
stack_level[0] == 0;
foreach(stack_level[i]) {
if(i > 0) {
@@ -95,6 +99,8 @@
}
}
+`endif
+
`uvm_object_utils(riscv_callstack_gen)
function new (string name = "");
@@ -114,7 +120,16 @@
// implemented with post randomize rather than constraints for performance considerations.
// Solving a complex call stack with SV constraint could take considerable time for the solver.
function void post_randomize();
- int last_level = stack_level[program_cnt-1];
+ int last_level;
+ `ifdef DSIM
+ stack_level = new[program_cnt];
+ foreach (stack_level[i]) begin
+ if (i > 0) begin
+ stack_level[i] = stack_level[i-1] + $urandom_range(0,1);
+ end
+ end
+ `endif
+ last_level = stack_level[program_cnt-1];
foreach(program_h[i]) begin
program_h[i].program_id = i;
program_h[i].call_stack_level = stack_level[i];
@@ -128,8 +143,14 @@
int sub_program_id_pool[];
int sub_program_cnt[];
int idx;
- program_list = stack_level.find_index() with (item == i);
- next_program_list = stack_level.find_index() with (item == i+1);
+ for (int j=0; j<program_cnt; j++) begin
+ if (stack_level[j] == i) begin
+ program_list.push_back(j);
+ end
+ if (stack_level[j] == i+1) begin
+ next_program_list.push_back(j);
+ end
+ end
// Randmly duplicate some sub programs in the pool to create a case that
// one sub program is called by multiple caller. Also it's possible to call
// the same sub program in one program multiple times.
@@ -147,19 +168,18 @@
sub_program_id_pool.shuffle();
sub_program_cnt = new[program_list.size()];
`uvm_info(get_full_name(), $sformatf("%0d programs @Lv%0d-> %0d programs at next level",
- program_list.size(), i, sub_program_id_pool.size()), UVM_HIGH)
+ program_list.size(), i, sub_program_id_pool.size()), UVM_LOW)
// Distribute the programs of the next level among the programs of current level
// Make sure all program has a caller so that no program is obsolete.
- `DV_CHECK_STD_RANDOMIZE_WITH_FATAL(sub_program_cnt,
- sub_program_cnt.sum() == sub_program_id_pool.size();
- foreach(sub_program_cnt[j]) {
- sub_program_cnt[j] inside {[0: sub_program_id_pool.size()]};
- })
+ foreach (sub_program_id_pool[j]) begin
+ int caller_id = $urandom_range(0, sub_program_cnt.size()-1);
+ sub_program_cnt[caller_id]++;
+ end
foreach(program_list[j]) begin
int id = program_list[j];
program_h[id].sub_program_id = new[sub_program_cnt[j]];
`uvm_info(get_full_name(), $sformatf("%0d sub programs are assigned to program[%0d]",
- sub_program_cnt[j], id), UVM_HIGH)
+ sub_program_cnt[j], id), UVM_LOW)
foreach(program_h[id].sub_program_id[k]) begin
program_h[id].sub_program_id[k] = sub_program_id_pool[idx];
idx++;
diff --git a/hw/vendor/lowrisc_ibex/vendor/google_riscv-dv/src/riscv_data_page_gen.sv b/hw/vendor/lowrisc_ibex/vendor/google_riscv-dv/src/riscv_data_page_gen.sv
index bb0c67f..e80ab35 100644
--- a/hw/vendor/lowrisc_ibex/vendor/google_riscv-dv/src/riscv_data_page_gen.sv
+++ b/hw/vendor/lowrisc_ibex/vendor/google_riscv-dv/src/riscv_data_page_gen.sv
@@ -23,6 +23,7 @@
riscv_instr_gen_config cfg;
string data_page_str[$];
+ mem_region_t mem_region_setting[$];
`uvm_object_utils(riscv_data_page_gen)
@@ -48,29 +49,48 @@
end
endfunction
- // Generate the assembly code for the data section
+ // Generate data pages for all memory regions
function void gen_data_page(data_pattern_t pattern, bit is_kernel = 1'b0);
string tmp_str;
bit [7:0] tmp_data[];
int page_cnt;
int page_size;
data_page_str = {};
- page_cnt = is_kernel ? riscv_instr_pkg::num_of_kernel_data_pages :
- riscv_instr_pkg::num_of_data_pages;
- page_size = is_kernel ? riscv_instr_pkg::kernel_data_page_size :
- riscv_instr_pkg::data_page_size;
- for(int section_idx = 0; section_idx < page_cnt; section_idx++) begin
- if(is_kernel) begin
- data_page_str.push_back($sformatf("kernel_data_page_%0d:", section_idx));
- end else begin
- data_page_str.push_back($sformatf("data_page_%0d:", section_idx));
+ if (is_kernel) begin
+ mem_region_setting = cfg.s_mem_region;
+ end else begin
+ mem_region_setting = cfg.mem_region;
+ end
+ if (is_kernel) begin
+ // All kernel data pages in the same section
+ data_page_str.push_back(".pushsection .kernel_data,\"aw\",@progbits;");
+ end
+ foreach (mem_region_setting[i]) begin
+ `uvm_info(`gfn, $sformatf("Generate data section: %0s size:0x%0x xwr:0x%0x]",
+ mem_region_setting[i].name,
+ mem_region_setting[i].size_in_bytes,
+ mem_region_setting[i].xwr), UVM_LOW)
+ if (!is_kernel) begin
+ data_page_str.push_back($sformatf(".pushsection .%0s,\"aw\",@progbits;",
+ mem_region_setting[i].name));
end
- data_page_str.push_back($sformatf(".align %0d", riscv_instr_pkg::data_page_alignment));
+ data_page_str.push_back($sformatf("%0s:", mem_region_setting[i].name));
+ page_size = mem_region_setting[i].size_in_bytes;
for(int i = 0; i < page_size; i+= 32) begin
- gen_data(.idx(i), .pattern(pattern), .num_of_bytes(32), .data(tmp_data));
+ if (page_size-i >= 32) begin
+ gen_data(.idx(i), .pattern(pattern), .num_of_bytes(32), .data(tmp_data));
+ end else begin
+ gen_data(.idx(i), .pattern(pattern), .num_of_bytes(page_size-i), .data(tmp_data));
+ end
tmp_str = format_string($sformatf(".word %0s", format_data(tmp_data)), LABEL_STR_LEN);
data_page_str.push_back(tmp_str);
end
+ if (!is_kernel) begin
+ data_page_str.push_back(".popsection;");
+ end
+ end
+ if (is_kernel) begin
+ data_page_str.push_back(".popsection;");
end
endfunction
diff --git a/hw/vendor/lowrisc_ibex/vendor/google_riscv-dv/src/riscv_directed_instr_lib.sv b/hw/vendor/lowrisc_ibex/vendor/google_riscv-dv/src/riscv_directed_instr_lib.sv
index bd86547..3835832 100644
--- a/hw/vendor/lowrisc_ibex/vendor/google_riscv-dv/src/riscv_directed_instr_lib.sv
+++ b/hw/vendor/lowrisc_ibex/vendor/google_riscv-dv/src/riscv_directed_instr_lib.sv
@@ -40,6 +40,51 @@
endclass
+// Base class for memory access stream
+class riscv_mem_access_stream extends riscv_directed_instr_stream;
+
+ int max_data_page_id;
+ mem_region_t data_page[$];
+
+ `uvm_object_utils(riscv_mem_access_stream)
+ `uvm_object_new
+
+ function void pre_randomize();
+ if(kernel_mode) begin
+ data_page = cfg.s_mem_region;
+ end else begin
+ data_page = cfg.mem_region;
+ end
+ max_data_page_id = data_page.size();
+ endfunction
+
+ // Use "la" instruction to initialize the base regiseter
+ virtual function void add_rs1_init_la_instr(riscv_reg_t gpr, int id, int base = 0);
+ riscv_pseudo_instr la_instr;
+ la_instr = riscv_pseudo_instr::type_id::create("la_instr");
+ la_instr.pseudo_instr_name = LA;
+ la_instr.rd = gpr;
+ if(kernel_mode) begin
+ la_instr.imm_str = $sformatf("%s+%0d", cfg.s_mem_region[id].name, base);
+ end else begin
+ la_instr.imm_str = $sformatf("%s+%0d", cfg.mem_region[id].name, base);
+ end
+ instr_list.push_front(la_instr);
+ endfunction
+
+ // Insert some other instructions to mix with mem_access instruction
+ virtual function void add_mixed_instr(int instr_cnt);
+ riscv_instr_base instr;
+ setup_allowed_instr(1, 1);
+ for(int i = 0; i < instr_cnt; i ++) begin
+ instr = riscv_instr_base::type_id::create("instr");
+ randomize_instr(instr);
+ insert_instr(instr);
+ end
+ endfunction
+
+endclass
+
// Create a infinte zero instruction loop, test if we can interrupt or
// enter debug mode while core is executing this loop
class riscv_infinte_loop_instr extends riscv_directed_instr_stream;
@@ -90,34 +135,23 @@
// For JAL, restore the stack before doing the jump
class riscv_jump_instr extends riscv_rand_instr_stream;
- rand riscv_instr_base jump;
- rand riscv_instr_base addi;
- rand riscv_pseudo_instr la;
- rand riscv_rand_instr branch;
- rand int imm;
- rand bit enable_branch;
- rand int mixed_instr_cnt;
- riscv_instr_base stack_exit_instr[];
- string target_program_label;
- int idx;
+ riscv_instr_base jump;
+ riscv_instr_base addi;
+ riscv_pseudo_instr la;
+ riscv_instr_base branch;
+ rand riscv_reg_t gpr;
+ rand int imm;
+ rand bit enable_branch;
+ rand int mixed_instr_cnt;
+ riscv_instr_base stack_exit_instr[];
+ string target_program_label;
+ int idx;
+ bit use_jalr;
constraint instr_c {
- solve jump.instr_name before addi.imm;
- solve jump.instr_name before addi.rs1;
- jump.instr_name dist {JAL := 1, JALR := 1};
- jump.rd == RA;
- !(addi.rs1 inside {cfg.reserved_regs, ZERO});
- addi.rs1 == la.rd;
- addi.rd == la.rd;
- // Avoid using negative offset -1024
- addi.imm != 'hFFFF_FC00;
- addi.imm != 1024;
- jump.imm == ~addi.imm + 1;
- jump.rs1 == addi.rd;
- addi.instr_name == ADDI;
- branch.category == BRANCH;
- la.pseudo_instr_name == LA;
- soft mixed_instr_cnt inside {[5:10]};
+ !(gpr inside {cfg.reserved_regs, ZERO});
+ imm inside {[-1023:1023]};
+ mixed_instr_cnt inside {[5:10]};
}
`uvm_object_utils(riscv_jump_instr)
@@ -127,21 +161,33 @@
jump = riscv_instr_base::type_id::create("jump");
la = riscv_pseudo_instr::type_id::create("la");
addi = riscv_instr_base::type_id::create("addi");
- branch = riscv_rand_instr::type_id::create("branch");
- instr_list.rand_mode(0);
- endfunction
-
- function void pre_randomize();
- branch.cfg = cfg;
+ branch = riscv_instr_base::type_id::create("branch");
endfunction
function void post_randomize();
riscv_instr_base instr[];
+ `DV_CHECK_RANDOMIZE_WITH_FATAL(jump,
+ (use_jalr) -> (instr_name == JALR);
+ instr_name dist {JAL := 1, JALR := 9};
+ rd == RA;
+ rs1 == gpr;
+ )
+ `DV_CHECK_RANDOMIZE_WITH_FATAL(addi,
+ rs1 == gpr;
+ instr_name == ADDI;
+ rd == gpr;
+ )
+ `DV_CHECK_RANDOMIZE_WITH_FATAL(branch,
+ instr_name inside {BEQ, BNE, BLT, BGE, BLTU, BGEU};)
+ la.pseudo_instr_name = LA;
+ la.imm_str = target_program_label;
+ la.rd = gpr;
// Generate some random instructions to mix with jump instructions
- reserved_rd = {addi.rs1};
+ reserved_rd = {gpr};
initialize_instr_list(mixed_instr_cnt);
gen_instr(1'b1);
- la.imm_str = target_program_label;
+ addi.imm_str = $sformatf("%0d", imm);
+ jump.imm_str = $sformatf("%0d", -imm);
// The branch instruction is always inserted right before the jump instruction to avoid
// skipping other required instructions like restore stack, load jump base etc.
// The purse of adding the branch instruction here is to cover branch -> jump scenario.
@@ -188,8 +234,9 @@
endfunction
function void init();
- // Save RA, T0 and all reserved loop regs
- saved_regs = {RA, T0, cfg.loop_regs};
+ // Save RA, T0
+ reserved_rd = {RA, T0};
+ saved_regs = {RA, T0};
num_of_reg_to_save = saved_regs.size();
if(num_of_reg_to_save * (XLEN/8) > stack_len) begin
`uvm_fatal(get_full_name(), $sformatf("stack len [%0d] is not enough to store %d regs",
@@ -232,8 +279,12 @@
// Cover jal -> branch scenario, the branch is added before push stack operation
branch_instr = riscv_rand_instr::type_id::create("branch_instr");
branch_instr.cfg = cfg;
- `DV_CHECK_RANDOMIZE_WITH_FATAL(branch_instr,
- category == BRANCH;)
+ `ifdef DSIM
+ `DV_CHECK_RANDOMIZE_WITH_FATAL(branch_instr,
+ instr_name inside {[BEQ:BGEU], C_BEQZ, C_BNEZ};)
+ `else
+ `DV_CHECK_RANDOMIZE_WITH_FATAL(branch_instr, category == BRANCH;)
+ `endif
branch_instr.imm_str = push_start_label;
branch_instr.branch_assigned = 1'b1;
push_stack_instr[0].label = push_start_label;
@@ -266,6 +317,7 @@
endfunction
function void init();
+ reserved_rd = {RA, T0};
num_of_reg_to_save = saved_regs.size();
if(num_of_reg_to_save * 4 > stack_len) begin
`uvm_fatal(get_full_name(), $sformatf("stack len [%0d] is not enough to store %d regs",
@@ -337,7 +389,8 @@
backward_branch_instr_stream.initialize_instr_list(branch_instr_stream_len);
endfunction
- virtual function void gen_instr(bit no_branch = 1'b0, bit no_load_store = 1'b1);
+ virtual function void gen_instr(bit no_branch = 1'b0, bit no_load_store = 1'b1,
+ bit is_debug_program = 1'b0);
int branch_offset;
super.gen_instr(1'b1);
forward_branch_instr_stream.gen_instr();
@@ -414,7 +467,6 @@
function new(string name = "");
super.new(name);
- instr_list.rand_mode(0);
li_instr = riscv_pseudo_instr::type_id::create("li_instr");
csr_instr = riscv_instr_base::type_id::create("csr_instr");
ip = riscv_privil_reg::type_id::create("ip");
diff --git a/hw/vendor/lowrisc_ibex/vendor/google_riscv-dv/src/riscv_illegal_instr.sv b/hw/vendor/lowrisc_ibex/vendor/google_riscv-dv/src/riscv_illegal_instr.sv
index 2cd25c6..b476433 100644
--- a/hw/vendor/lowrisc_ibex/vendor/google_riscv-dv/src/riscv_illegal_instr.sv
+++ b/hw/vendor/lowrisc_ibex/vendor/google_riscv-dv/src/riscv_illegal_instr.sv
@@ -39,9 +39,10 @@
7'b0100011,
7'b0110111,
7'b1100011,
+ 7'b0110011,
7'b1100111,
- 7'b1101111,
- 7'b1110011};
+ 7'b1110011,
+ 7'b1101111};
rand illegal_instr_type_e exception;
rand bit [31:0] instr_bin;
@@ -59,6 +60,8 @@
solve opcode before instr_bin;
solve func3 before instr_bin;
solve func7 before instr_bin;
+ solve c_msb before instr_bin;
+ solve c_op before instr_bin;
if (compressed) {
instr_bin[1:0] == c_op;
instr_bin[15:13] == c_msb;
@@ -108,10 +111,23 @@
constraint hint_instr_c {
if (exception == kHintInstr) {
+ // C.ADDI
((c_msb == 3'b000) && (c_op == 2'b01) && ({instr_bin[12], instr_bin[6:2]} == 6'b0)) ||
+ // C.LI
((c_msb == 3'b010) && (c_op == 2'b01) && (instr_bin[11:7] == 5'b0)) ||
- ((c_msb == 3'b011) && (c_op == 2'b01) && (instr_bin[11:7] == 5'b0)) ||
- ((c_msb == 3'b100) && (c_op == 2'b10) && (instr_bin[12:7] == 6'b0) &&
+ // C.SRAI64, C.SRLI64
+ ((c_msb == 3'b100) && (c_op == 2'b01) && (instr_bin[12:11] == 2'b00) &&
+ (instr_bin[6:2] == 5'b0)) ||
+ // C.LUI
+ ((c_msb == 3'b011) && (c_op == 2'b01) && (instr_bin[11:7] == 5'b0) &&
+ ({instr_bin[12], instr_bin[6:2]} != 6'b0)) ||
+ // C.SLLI
+ ((c_msb == 3'b000) && (c_op == 2'b10) && (instr_bin[11:7] == 5'b0)) ||
+ // C.SLLI64
+ ((c_msb == 3'b000) && (c_op == 2'b10) && (instr_bin[11:7] != 5'b0) && !instr_bin[12] &&
+ (instr_bin[6:2] == 0)) ||
+ // C.ADD
+ ((c_msb == 3'b100) && (c_op == 2'b10) && (instr_bin[11:7] == 5'b0) && instr_bin[12] &&
(instr_bin[6:2] != 0));
}
}
@@ -213,9 +229,6 @@
if (riscv_instr_pkg::RV32A inside {riscv_instr_pkg::supported_isa}) begin
legal_opcode = {legal_opcode, 7'b0101111};
end
- if (riscv_instr_pkg::RV32M inside {riscv_instr_pkg::supported_isa}) begin
- legal_opcode = {legal_opcode, 7'b0110011};
- end
if ((riscv_instr_pkg::RV64I inside {riscv_instr_pkg::supported_isa}) ||
riscv_instr_pkg::RV64M inside {riscv_instr_pkg::supported_isa}) begin
legal_opcode = {legal_opcode, 7'b0111011};
diff --git a/hw/vendor/lowrisc_ibex/vendor/google_riscv-dv/src/riscv_instr_base.sv b/hw/vendor/lowrisc_ibex/vendor/google_riscv-dv/src/riscv_instr_base.sv
index 9f9bf87..58f1046 100644
--- a/hw/vendor/lowrisc_ibex/vendor/google_riscv-dv/src/riscv_instr_base.sv
+++ b/hw/vendor/lowrisc_ibex/vendor/google_riscv-dv/src/riscv_instr_base.sv
@@ -92,6 +92,7 @@
imm_len == 8;
}
}
+ imm_len <= 20;
}
constraint imm_val_c {
@@ -113,7 +114,7 @@
if (instr_name == C_JR) {
rs1 != ZERO;
}
- if (instr_name == C_MV) {
+ if (instr_name inside {C_ADD, C_MV}) {
rs2 != ZERO;
}
}
@@ -128,21 +129,9 @@
}
}
- constraint fence_c {
- if (instr_name == FENCE) {
- rs1 == ZERO;
- rd == ZERO;
- imm == 0;
- }
- if (instr_name == FENCEI) {
- rs1 == ZERO;
- rd == ZERO;
- imm == 0;
- }
- }
-
// Cannot shift more than the width of the bus
constraint shift_imm_val_c {
+ solve category before imm;
if(category == SHIFT) {
if(group == RV64I) {
// The new instruction in RV64I only handles 32 bits value
@@ -237,13 +226,14 @@
`add_instr(JALR, I_FORMAT, JUMP, RV32I)
// SYNCH instructions
`add_instr(FENCE, I_FORMAT, SYNCH, RV32I)
- `add_instr(FENCEI, I_FORMAT, SYNCH, RV32I)
+ `add_instr(FENCE_I, I_FORMAT, SYNCH, RV32I)
// SYSTEM instructions
`add_instr(ECALL, I_FORMAT, SYSTEM, RV32I)
`add_instr(EBREAK, I_FORMAT, SYSTEM, RV32I)
`add_instr(URET, I_FORMAT, SYSTEM, RV32I)
`add_instr(SRET, I_FORMAT, SYSTEM, RV32I)
`add_instr(MRET, I_FORMAT, SYSTEM, RV32I)
+ `add_instr(DRET, I_FORMAT, SYSTEM, RV32I)
`add_instr(WFI, I_FORMAT, INTERRUPT, RV32I)
// CSR instructions
`add_instr(CSRRW, R_FORMAT, CSR, RV32I, UIMM)
@@ -330,7 +320,7 @@
`add_instr(C_LI, CI_FORMAT, ARITHMETIC, RV32C)
`add_instr(C_LUI, CI_FORMAT, ARITHMETIC, RV32C, NZUIMM)
`add_instr(C_SUB, CS_FORMAT, ARITHMETIC, RV32C)
- `add_instr(C_ADD, CS_FORMAT, ARITHMETIC, RV32C)
+ `add_instr(C_ADD, CR_FORMAT, ARITHMETIC, RV32C)
`add_instr(C_NOP, CI_FORMAT, ARITHMETIC, RV32C)
`add_instr(C_MV, CR_FORMAT, ARITHMETIC, RV32C)
`add_instr(C_ANDI, CB_FORMAT, LOGICAL, RV32C)
@@ -392,17 +382,17 @@
`add_instr(AMOMAXU_W, R_FORMAT, AMO, RV32A)
// RV64A
- `add_instr(LR_D, R_FORMAT, LOAD, RV32A)
- `add_instr(SC_D, R_FORMAT, STORE, RV32A)
- `add_instr(AMOSWAP_D, R_FORMAT, AMO, RV32A)
- `add_instr(AMOADD_D, R_FORMAT, AMO, RV32A)
- `add_instr(AMOAND_D, R_FORMAT, AMO, RV32A)
- `add_instr(AMOOR_D, R_FORMAT, AMO, RV32A)
- `add_instr(AMOXOR_D, R_FORMAT, AMO, RV32A)
- `add_instr(AMOMIN_D, R_FORMAT, AMO, RV32A)
- `add_instr(AMOMAX_D, R_FORMAT, AMO, RV32A)
- `add_instr(AMOMINU_D, R_FORMAT, AMO, RV32A)
- `add_instr(AMOMAXU_D, R_FORMAT, AMO, RV32A)
+ `add_instr(LR_D, R_FORMAT, LOAD, RV64A)
+ `add_instr(SC_D, R_FORMAT, STORE, RV64A)
+ `add_instr(AMOSWAP_D, R_FORMAT, AMO, RV64A)
+ `add_instr(AMOADD_D, R_FORMAT, AMO, RV64A)
+ `add_instr(AMOAND_D, R_FORMAT, AMO, RV64A)
+ `add_instr(AMOOR_D, R_FORMAT, AMO, RV64A)
+ `add_instr(AMOXOR_D, R_FORMAT, AMO, RV64A)
+ `add_instr(AMOMIN_D, R_FORMAT, AMO, RV64A)
+ `add_instr(AMOMAX_D, R_FORMAT, AMO, RV64A)
+ `add_instr(AMOMINU_D, R_FORMAT, AMO, RV64A)
+ `add_instr(AMOMAXU_D, R_FORMAT, AMO, RV64A)
// Supervisor Instructions
`add_instr(SFENCE_VMA, R_FORMAT,SYNCH,RV32I)
@@ -420,15 +410,21 @@
update_imm_str();
end
end
- if (format inside {R_FORMAT, S_FORMAT, B_FORMAT, CSS_FORMAT, CS_FORMAT}) begin
+ if (format inside {R_FORMAT, S_FORMAT, B_FORMAT, CSS_FORMAT, CS_FORMAT, CR_FORMAT}) begin
has_rs2 = 1'b1;
end
- if (!(format inside {J_FORMAT, U_FORMAT, CJ_FORMAT, CSS_FORMAT})) begin
+ if (!(format inside {J_FORMAT, U_FORMAT, CJ_FORMAT, CSS_FORMAT, CR_FORMAT, CI_FORMAT})) begin
has_rs1 = 1'b1;
end
if (!(format inside {CJ_FORMAT, CB_FORMAT, CS_FORMAT, CSS_FORMAT, B_FORMAT, S_FORMAT})) begin
has_rd = 1'b1;
end
+ if (category == CSR) begin
+ has_rs2 = 1'b0;
+ if (instr_name inside {CSRRWI, CSRRSI, CSRRCI}) begin
+ has_rs1 = 1'b0;
+ end
+ end
endfunction
function void mask_imm();
@@ -469,16 +465,35 @@
function riscv_reg_t gen_rand_gpr(riscv_reg_t included_reg[] = {},
riscv_reg_t excluded_reg[] = {});
riscv_reg_t gpr;
- `DV_CHECK_STD_RANDOMIZE_WITH_FATAL(gpr,
- if (is_compressed) {
- gpr inside {[S0:A5]};
- }
- if (excluded_reg.size() != 0) {
- !(gpr inside {excluded_reg});
- }
- if (included_reg.size() != 0) {
- gpr inside {included_reg};
- })
+ int unsigned i;
+ riscv_reg_t legal_gpr[$];
+ if (included_reg.size() > 0) begin
+ legal_gpr = included_reg;
+ while (is_compressed && (i < legal_gpr.size())) begin
+ if (legal_gpr[i] < S0 || legal_gpr[i] > A5) begin
+ legal_gpr.delete(i);
+ end else begin
+ i++;
+ end
+ end
+ end else if (is_compressed) begin
+ legal_gpr = riscv_instr_pkg::compressed_gpr;
+ end else begin
+ legal_gpr = riscv_instr_pkg::all_gpr;
+ end
+ if (excluded_reg.size() > 0) begin
+ i = 0;
+ while (i < legal_gpr.size()) begin
+ if (legal_gpr[i] inside {excluded_reg}) begin
+ legal_gpr.delete(i);
+ end else begin
+ i++;
+ end
+ end
+ end
+ `DV_CHECK_FATAL(legal_gpr.size() > 0)
+ `DV_CHECK_STD_RANDOMIZE_WITH_FATAL(i, i < legal_gpr.size();)
+ gpr = legal_gpr[i];
return gpr;
endfunction
@@ -521,9 +536,13 @@
I_FORMAT: // instr rd,rs1,imm
if(instr_name == NOP)
asm_str = "nop";
+ else if(instr_name == C_NOP)
+ asm_str = "c.nop";
+ else if(instr_name == WFI)
+ asm_str = "wfi";
else if(instr_name == FENCE)
asm_str = $sformatf("fence"); // TODO: Support all fence combinations
- else if(instr_name == FENCEI)
+ else if(instr_name == FENCE_I)
asm_str = "fence.i";
else if(category == LOAD) // Use psuedo instruction format
asm_str = $sformatf("%0s%0s, %0s(%0s)", asm_str, rd.name(), get_imm(), rs1.name());
@@ -599,10 +618,10 @@
MULH, MULHSU, MULHU, DIV, DIVU, REM, REMU : get_opcode = 7'b0110011;
ADDIW, SLLIW, SRLIW, SRAIW : get_opcode = 7'b0011011;
MULH, MULHSU, MULHU, DIV, DIVU, REM, REMU : get_opcode = 7'b0110011;
- FENCE, FENCEI : get_opcode = 7'b0001111;
+ FENCE, FENCE_I : get_opcode = 7'b0001111;
ECALL, EBREAK, CSRRW, CSRRS, CSRRC, CSRRWI, CSRRSI, CSRRCI : get_opcode = 7'b1110011;
ADDW, SUBW, SLLW, SRLW, SRAW, MULW, DIVW, DIVUW, REMW, REMUW : get_opcode = 7'b0111011;
- ECALL, EBREAK, URET, SRET, MRET, WFI, SFENCE_VMA : get_opcode = 7'b1110011;
+ ECALL, EBREAK, URET, SRET, MRET, DRET, WFI, SFENCE_VMA : get_opcode = 7'b1110011;
default : `uvm_fatal(`gfn, $sformatf("Unsupported instruction %0s", instr_name.name()))
endcase
endfunction
@@ -661,7 +680,7 @@
OR : get_func3 = 3'b110;
AND : get_func3 = 3'b111;
FENCE : get_func3 = 3'b000;
- FENCEI : get_func3 = 3'b001;
+ FENCE_I : get_func3 = 3'b001;
ECALL : get_func3 = 3'b000;
EBREAK : get_func3 = 3'b000;
CSRRW : get_func3 = 3'b001;
@@ -744,7 +763,7 @@
C_SWSP : get_func3 = 3'b110;
C_FSWSP : get_func3 = 3'b111;
C_SDSP : get_func3 = 3'b111;
- ECALL, EBREAK, URET, SRET, MRET, WFI, SFENCE_VMA : get_func3 = 3'b000;
+ ECALL, EBREAK, URET, SRET, MRET, DRET, WFI, SFENCE_VMA : get_func3 = 3'b000;
default : `uvm_fatal(`gfn, $sformatf("Unsupported instruction %0s", instr_name.name()))
endcase
endfunction
@@ -765,7 +784,7 @@
OR : get_func7 = 7'b0000000;
AND : get_func7 = 7'b0000000;
FENCE : get_func7 = 7'b0000000;
- FENCEI : get_func7 = 7'b0000000;
+ FENCE_I : get_func7 = 7'b0000000;
ECALL : get_func7 = 7'b0000000;
EBREAK : get_func7 = 7'b0000000;
SLLIW : get_func7 = 7'b0000000;
@@ -794,6 +813,7 @@
URET : get_func7 = 7'b0000000;
SRET : get_func7 = 7'b0001000;
MRET : get_func7 = 7'b0011000;
+ DRET : get_func7 = 7'b0111101;
WFI : get_func7 = 7'b0001000;
SFENCE_VMA: get_func7 = 7'b0001001;
default : `uvm_fatal(`gfn, $sformatf("Unsupported instruction %0s", instr_name.name()))
@@ -812,7 +832,7 @@
binary = $sformatf("%8h", {imm[31:12], rd, get_opcode()});
end
I_FORMAT: begin
- if(instr_name inside {FENCE, FENCEI})
+ if(instr_name inside {FENCE, FENCE_I})
binary = $sformatf("%8h", {17'b0, get_func3(), 5'b0, get_opcode()});
else if(category == CSR)
binary = $sformatf("%8h", {csr[10:0], imm[4:0], get_func3(), rd, get_opcode()});
@@ -820,6 +840,8 @@
binary = $sformatf("%8h", {get_func7(), 18'b0, get_opcode()});
else if(instr_name inside {URET, SRET, MRET})
binary = $sformatf("%8h", {get_func7(), 5'b10, 13'b0, get_opcode()});
+ else if(instr_name inside {DRET})
+ binary = $sformatf("%8h", {get_func7(), 5'b10010, 13'b0, get_opcode()});
else if(instr_name == EBREAK)
binary = $sformatf("%8h", {get_func7(), 5'b01, 13'b0, get_opcode()});
else if(instr_name == WFI)
diff --git a/hw/vendor/lowrisc_ibex/vendor/google_riscv-dv/src/riscv_instr_cov_item.sv b/hw/vendor/lowrisc_ibex/vendor/google_riscv-dv/src/riscv_instr_cov_item.sv
new file mode 100644
index 0000000..064e00c
--- /dev/null
+++ b/hw/vendor/lowrisc_ibex/vendor/google_riscv-dv/src/riscv_instr_cov_item.sv
@@ -0,0 +1,229 @@
+class riscv_instr_cov_item extends riscv_instr_base;
+
+ typedef enum bit[1:0] {
+ POSITIVE, NEGATIVE
+ } operand_sign_e;
+
+ typedef enum bit[1:0] {
+ EQUAL, LARGER, SMALLER
+ } compare_result_e;
+
+ typedef enum bit [1:0] {
+ IDENTICAL, OPPOSITE, SIMILAR, DIFFERENT
+ } logical_similarity_e;
+
+ typedef enum bit[2:0] {
+ NORMAL_VAL, MIN_VAL, MAX_VAL, ZERO_VAL
+ } special_val_e;
+
+ rand bit [XLEN-1:0] rs1_value;
+ rand bit [XLEN-1:0] rs2_value;
+ rand bit [XLEN-1:0] rd_value;
+ bit [31:0] binary;
+ bit [XLEN-1:0] pc;
+ bit [XLEN-1:0] mem_addr;
+
+ bit unaligned_pc;
+ bit unaligned_mem_access;
+ bit compressed;
+ bit branch_hit;
+ operand_sign_e rs1_sign;
+ operand_sign_e rs2_sign;
+ operand_sign_e imm_sign;
+ operand_sign_e rd_sign;
+ hazard_e gpr_hazard;
+ hazard_e lsu_hazard;
+ special_val_e rs1_special_val;
+ special_val_e rs2_special_val;
+ special_val_e rd_special_val;
+ special_val_e imm_special_val;
+ compare_result_e compare_result;
+ logical_similarity_e logical_similarity;
+ string trace;
+
+ `uvm_object_utils(riscv_instr_cov_item)
+ `uvm_object_new
+
+ virtual function void pre_sample();
+ unaligned_pc = (pc[1:0] != 2'b00);
+ rs1_sign = get_operand_sign(rs1_value);
+ rs2_sign = get_operand_sign(rs2_value);
+ rd_sign = get_operand_sign(rd_value);
+ imm_sign = get_imm_sign(imm);
+ rs1_special_val = get_operand_special_val(rs1_value);
+ rd_special_val = get_operand_special_val(rd_value);
+ rs2_special_val = get_operand_special_val(rs2_value);
+ if ((format != R_FORMAT) && (format != CR_FORMAT)) begin
+ imm_special_val = get_imm_special_val(imm);
+ end
+ if (category inside {COMPARE, BRANCH}) begin
+ compare_result = get_compare_result();
+ end
+ if (category inside {LOAD, STORE}) begin
+ unaligned_mem_access = is_unaligned_mem_access();
+ if (unaligned_mem_access) begin
+ `uvm_info(`gfn, $sformatf("Unaligned: %0s, mem_addr:%0x", instr_name.name(), mem_addr), UVM_LOW)
+ end
+ end
+ if (category == LOGICAL) begin
+ logical_similarity = get_logical_similarity();
+ end
+ if (category == BRANCH) begin
+ branch_hit = is_branch_hit();
+ end
+ endfunction
+
+ function operand_sign_e get_operand_sign(bit [XLEN-1:0] value);
+ if (value[XLEN-1]) begin
+ return NEGATIVE;
+ end else begin
+ return POSITIVE;
+ end
+ endfunction
+
+ function bit is_unaligned_mem_access();
+ if ((instr_name inside {LWU, LD, SD, C_LD, C_SD}) && (mem_addr % 8 != 0)) begin
+ return 1'b1;
+ end else if ((instr_name inside {LW, SW, C_LW, C_SW}) && (mem_addr % 4 != 0)) begin
+ return 1'b1;
+ end else if ((instr_name inside {LH, LHU, SH}) && (mem_addr % 2 != 0)) begin
+ return 1'b1;
+ end begin
+ return 1'b0;
+ end
+ endfunction
+
+ function operand_sign_e get_imm_sign(bit [31:0] value);
+ if (value[31]) begin
+ return NEGATIVE;
+ end else begin
+ return POSITIVE;
+ end
+ endfunction
+
+ function special_val_e get_operand_special_val(bit [XLEN-1:0] value);
+ if (value == 0) begin
+ return ZERO_VAL;
+ end else if (value == '1 << (XLEN-1)) begin
+ return MIN_VAL;
+ end else if (value == '1 >> 1) begin
+ return MAX_VAL;
+ end else begin
+ return NORMAL_VAL;
+ end
+ endfunction
+
+ function special_val_e get_imm_special_val(bit [31:0] value);
+ void'(randomize(imm_len));
+ if (value == 0) begin
+ return ZERO_VAL;
+ end else if (format == U_FORMAT) begin
+ // unsigend immediate value
+ bit [31:0] max_val;
+ max_val = (1 << imm_len)-1;
+ if (value == '0) begin
+ return MIN_VAL;
+ end
+ if (value == max_val) begin
+ return MAX_VAL;
+ end
+ end else begin
+ // signed immediate value
+ int signed max_val, min_val;
+ max_val = 2 ** (imm_len-1) - 1;
+ min_val = -2 ** (imm_len-1);
+ if (min_val == $signed(value)) begin
+ return MIN_VAL;
+ end
+ if (max_val == $signed(value)) begin
+ return MAX_VAL;
+ end
+ end
+ return NORMAL_VAL;
+ endfunction
+
+ function compare_result_e get_compare_result();
+ bit [XLEN-1:0] val1, val2;
+ val1 = rs1_value;
+ val2 = (format == I_FORMAT) ? imm : rs2_value;
+ if (val1 == val2) begin
+ return EQUAL;
+ end else if (val1 < val2) begin
+ return SMALLER;
+ end else begin
+ return LARGER;
+ end
+ endfunction
+
+ function bit is_branch_hit();
+ case(instr_name)
+ BEQ : is_branch_hit = (rs1_value == rs2_value);
+ C_BEQZ : is_branch_hit = (rs1_value == 0);
+ BNE : is_branch_hit = (rs1_value == rs2_value);
+ C_BNEZ : is_branch_hit = (rs1_value != 0);
+ BLT : is_branch_hit = ($signed(rs1_value) < $signed(rs2_value));
+ BGE : is_branch_hit = ($signed(rs1_value) > $signed(rs2_value));
+ BLTU : is_branch_hit = (rs1_value < rs2_value);
+ BGEU : is_branch_hit = (rs1_value > rs2_value);
+ BGEU : is_branch_hit = (rs1_value > rs2_value);
+ default: `uvm_error(get_name(), $sformatf("Unexpected instr %0s", instr_name.name()))
+ endcase
+ return is_branch_hit;
+ endfunction
+
+ function logical_similarity_e get_logical_similarity();
+ bit [XLEN-1:0] val1, val2;
+ int bit_difference;
+ val1 = rs1_value;
+ val2 = (format == I_FORMAT) ? imm : rs2_value;
+ bit_difference = $countones(val1 ^ val2);
+ if (val1 == val2)
+ return IDENTICAL;
+ else if (bit_difference == 32)
+ return OPPOSITE;
+ else if (bit_difference < 5)
+ return SIMILAR;
+ else
+ return DIFFERENT;
+ endfunction
+
+ function void check_hazard_condition(riscv_instr_cov_item pre_instr);
+ riscv_reg_t gpr;
+ if (pre_instr.has_rd) begin
+ if ((has_rs1 && (rs1 == pre_instr.rd)) || (has_rs2 && (rs2 == pre_instr.rd))) begin
+ gpr_hazard = RAW_HAZARD;
+ end else if (has_rd && (rd == pre_instr.rd)) begin
+ gpr_hazard = WAW_HAZARD;
+ end else if (has_rd && ((pre_instr.has_rs1 && (pre_instr.rs1 == rd)) ||
+ (pre_instr.has_rs2 && (pre_instr.rs2 == rd)))) begin
+ gpr_hazard = WAR_HAZARD;
+ end else begin
+ gpr_hazard = NO_HAZARD;
+ end
+ end
+ if (category == LOAD) begin
+ if ((pre_instr.category == STORE) && (pre_instr.mem_addr == mem_addr)) begin
+ lsu_hazard = RAW_HAZARD;
+ end else begin
+ lsu_hazard = NO_HAZARD;
+ end
+ end
+ if (category == STORE) begin
+ if ((pre_instr.category == STORE) && (pre_instr.mem_addr == mem_addr)) begin
+ lsu_hazard = WAW_HAZARD;
+ end else if ((pre_instr.category == LOAD) && (pre_instr.mem_addr == mem_addr)) begin
+ lsu_hazard = WAR_HAZARD;
+ end else begin
+ lsu_hazard = NO_HAZARD;
+ end
+ end
+ `uvm_info(`gfn, $sformatf("Pre:%0s, Cur:%0s, Hazard: %0s/%0s",
+ pre_instr.convert2asm(), this.convert2asm(),
+ gpr_hazard.name(), lsu_hazard.name()), UVM_FULL)
+ endfunction
+
+ virtual function void sample_cov();
+ pre_sample();
+ endfunction
+
+endclass
diff --git a/hw/vendor/lowrisc_ibex/vendor/google_riscv-dv/src/riscv_instr_cover_group.sv b/hw/vendor/lowrisc_ibex/vendor/google_riscv-dv/src/riscv_instr_cover_group.sv
new file mode 100644
index 0000000..5ac78ec
--- /dev/null
+++ b/hw/vendor/lowrisc_ibex/vendor/google_riscv-dv/src/riscv_instr_cover_group.sv
@@ -0,0 +1,924 @@
+`define INSTR_CG_BEGIN(INSTR_NAME) \
+ covergroup ``INSTR_NAME``_cg with function sample(riscv_instr_cov_item instr);
+
+`define R_INSTR_CG_BEGIN(INSTR_NAME) \
+ `INSTR_CG_BEGIN(INSTR_NAME) \
+ cp_rs1 : coverpoint instr.rs1; \
+ cp_rs2 : coverpoint instr.rs2; \
+ cp_rd : coverpoint instr.rd; \
+ cp_rs1_sign : coverpoint instr.rs1_sign; \
+ cp_rs2_sign : coverpoint instr.rs2_sign; \
+ cp_rd_sign : coverpoint instr.rd_sign; \
+ cp_gpr_harzard : coverpoint instr.gpr_hazard; \
+
+`define CMP_INSTR_CG_BEGIN(INSTR_NAME) \
+ `INSTR_CG_BEGIN(INSTR_NAME) \
+ cp_rs1 : coverpoint instr.rs1; \
+ cp_rd : coverpoint instr.rd; \
+ cp_rs1_sign : coverpoint instr.rs1_sign; \
+ cp_result : coverpoint instr.rd_value[0]; \
+ cp_gpr_harzard : coverpoint instr.gpr_hazard; \
+
+`define SB_INSTR_CG_BEGIN(INSTR_NAME) \
+ `INSTR_CG_BEGIN(INSTR_NAME) \
+ cp_rs1 : coverpoint instr.rs1; \
+ cp_rs2 : coverpoint instr.rs2; \
+ cp_rs1_sign : coverpoint instr.rs1_sign; \
+ cp_rs2_sign : coverpoint instr.rs2_sign; \
+ cp_imm_sign : coverpoint instr.imm_sign; \
+ cp_branch_hit : coverpoint instr.branch_hit; \
+ cp_sign_cross : cross cp_rs1_sign, cp_rs2_sign, cp_imm_sign; \
+ cp_gpr_harzard : coverpoint instr.gpr_hazard { \
+ bins valid_hazard[] = {NO_HAZARD, RAW_HAZARD}; \
+ }
+
+`define STORE_INSTR_CG_BEGIN(INSTR_NAME) \
+ `INSTR_CG_BEGIN(INSTR_NAME) \
+ cp_rs1 : coverpoint instr.rs1; \
+ cp_rs2 : coverpoint instr.rs2; \
+ cp_imm_sign : coverpoint instr.imm_sign; \
+ cp_gpr_harzard : coverpoint instr.gpr_hazard { \
+ bins valid_hazard[] = {NO_HAZARD, RAW_HAZARD}; \
+ } \
+ cp_lsu_harzard : coverpoint instr.lsu_hazard { \
+ bins valid_hazard[] = {NO_HAZARD, WAR_HAZARD, WAW_HAZARD}; \
+ }
+
+`define LOAD_INSTR_CG_BEGIN(INSTR_NAME) \
+ `INSTR_CG_BEGIN(INSTR_NAME) \
+ cp_rs1 : coverpoint instr.rs1; \
+ cp_rd : coverpoint instr.rd; \
+ cp_imm_sign : coverpoint instr.imm_sign; \
+ cp_gpr_harzard : coverpoint instr.gpr_hazard; \
+ cp_lsu_harzard : coverpoint instr.lsu_hazard { \
+ bins valid_hazard[] = {NO_HAZARD, RAW_HAZARD}; \
+ }
+
+`define I_INSTR_CG_BEGIN(INSTR_NAME) \
+ `INSTR_CG_BEGIN(INSTR_NAME) \
+ cp_rs1 : coverpoint instr.rs1; \
+ cp_rd : coverpoint instr.rd; \
+ cp_rs1_sign : coverpoint instr.rs1_sign; \
+ cp_rd_sign : coverpoint instr.rd_sign; \
+ cp_imm_sign : coverpoint instr.imm_sign; \
+ cp_gpr_harzard : coverpoint instr.gpr_hazard;
+
+`define U_INSTR_CG_BEGIN(INSTR_NAME) \
+ `INSTR_CG_BEGIN(INSTR_NAME) \
+ cp_rd : coverpoint instr.rd; \
+ cp_rd_sign : coverpoint instr.rd_sign; \
+ cp_imm_sign : coverpoint instr.imm_sign; \
+ cp_gpr_harzard : coverpoint instr.gpr_hazard;
+
+`define CSR_INSTR_CG_BEGIN(INSTR_NAME) \
+ `INSTR_CG_BEGIN(INSTR_NAME) \
+ cp_csr : coverpoint instr.csr { \
+ bins csr[] = cp_csr with (is_implemented_csr(item)); \
+ } \
+ cp_rs1 : coverpoint instr.rs1; \
+ cp_rd : coverpoint instr.rd; \
+ cp_gpr_harzard : coverpoint instr.gpr_hazard;
+
+`define CR_INSTR_CG_BEGIN(INSTR_NAME) \
+ `INSTR_CG_BEGIN(INSTR_NAME) \
+ cp_rs2 : coverpoint instr.rs2; \
+ cp_rd : coverpoint instr.rd; \
+ cp_rs2_sign : coverpoint instr.rs2_sign; \
+ cp_gpr_harzard : coverpoint instr.gpr_hazard;
+
+`define CI_INSTR_CG_BEGIN(INSTR_NAME) \
+ `INSTR_CG_BEGIN(INSTR_NAME) \
+ cp_rd : coverpoint instr.rd; \
+ cp_imm_sign : coverpoint instr.imm_sign; \
+ cp_gpr_harzard : coverpoint instr.gpr_hazard { \
+ bins valid_hazard[] = {NO_HAZARD, WAR_HAZARD, WAW_HAZARD}; \
+ }
+
+`define CSS_INSTR_CG_BEGIN(INSTR_NAME) \
+ `INSTR_CG_BEGIN(INSTR_NAME) \
+ cp_rs2 : coverpoint instr.rs2; \
+ cp_imm_sign : coverpoint instr.imm_sign; \
+ cp_rs2_sign : coverpoint instr.rs2_sign; \
+ cp_gpr_harzard : coverpoint instr.gpr_hazard { \
+ bins valid_hazard[] = {NO_HAZARD, RAW_HAZARD}; \
+ }
+
+`define CIW_INSTR_CG_BEGIN(INSTR_NAME) \
+ `INSTR_CG_BEGIN(INSTR_NAME) \
+ cp_imm_sign : coverpoint instr.imm_sign; \
+ cp_rd : coverpoint instr.rd { \
+ bins gpr[] = cp_rd with (is_compressed_gpr(riscv_reg_t'(item))); \
+ } \
+ cp_gpr_harzard : coverpoint instr.gpr_hazard { \
+ bins valid_hazard[] = {NO_HAZARD, WAR_HAZARD, WAW_HAZARD}; \
+ }
+
+`define CL_INSTR_CG_BEGIN(INSTR_NAME) \
+ `INSTR_CG_BEGIN(INSTR_NAME) \
+ cp_imm_sign : coverpoint instr.imm_sign; \
+ cp_rs1 : coverpoint instr.rs1 { \
+ bins gpr[] = cp_rs1 with (is_compressed_gpr(riscv_reg_t'(item))); \
+ } \
+ cp_rd : coverpoint instr.rd { \
+ bins gpr[] = cp_rd with (is_compressed_gpr(riscv_reg_t'(item))); \
+ } \
+ cp_gpr_harzard : coverpoint instr.gpr_hazard; \
+ cp_lsu_harzard : coverpoint instr.lsu_hazard { \
+ bins valid_hazard[] = {NO_HAZARD, RAW_HAZARD}; \
+ }
+
+`define CS_INSTR_CG_BEGIN(INSTR_NAME) \
+ `INSTR_CG_BEGIN(INSTR_NAME) \
+ cp_imm_sign : coverpoint instr.imm_sign; \
+ cp_rs1 : coverpoint instr.rs1 { \
+ bins gpr[] = cp_rs1 with (is_compressed_gpr(riscv_reg_t'(item))); \
+ } \
+ cp_rs2 : coverpoint instr.rs2 { \
+ bins gpr[] = cp_rs2 with (is_compressed_gpr(riscv_reg_t'(item))); \
+ } \
+ cp_gpr_harzard : coverpoint instr.gpr_hazard { \
+ bins valid_hazard[] = {NO_HAZARD, RAW_HAZARD}; \
+ } \
+ cp_lsu_harzard : coverpoint instr.lsu_hazard { \
+ bins valid_hazard[] = {NO_HAZARD, WAR_HAZARD, WAW_HAZARD}; \
+ }
+
+
+`define CB_INSTR_CG_BEGIN(INSTR_NAME) \
+ `INSTR_CG_BEGIN(INSTR_NAME) \
+ cp_imm_sign : coverpoint instr.imm_sign; \
+ cp_rs1 : coverpoint instr.rs1 { \
+ bins gpr[] = cp_rs1 with (is_compressed_gpr(riscv_reg_t'(item))); \
+ } \
+ cp_gpr_harzard : coverpoint instr.gpr_hazard { \
+ bins valid_hazard[] = {NO_HAZARD, RAW_HAZARD}; \
+ }
+
+`define CJ_INSTR_CG_BEGIN(INSTR_NAME) \
+ `INSTR_CG_BEGIN(INSTR_NAME) \
+ cp_imm_sign : coverpoint instr.imm_sign;
+
+`define CG_END endgroup
+
+class riscv_instr_cover_group#(privileged_reg_t implemented_pcsr[] =
+ riscv_instr_pkg::implemented_csr);
+
+ riscv_instr_gen_config cfg;
+ riscv_instr_cov_item cur_instr;
+ riscv_instr_cov_item pre_instr;
+ riscv_instr_name_t instr_list[$];
+ int unsigned instr_cnt;
+ int unsigned branch_instr_cnt;
+ bit [4:0] branch_hit_history; // The last 5 branch result
+ privileged_reg_t privil_csr[$];
+
+ ///////////// RV32I instruction functional coverage //////////////
+
+ // Arithmetic instructions
+ `R_INSTR_CG_BEGIN(add)
+ cp_sign_cross: cross cp_rs1_sign, cp_rs2_sign, cp_rd_sign;
+ `CG_END
+
+ `R_INSTR_CG_BEGIN(sub)
+ cp_sign_cross: cross cp_rs1_sign, cp_rs2_sign, cp_rd_sign;
+ `CG_END
+
+ `I_INSTR_CG_BEGIN(addi)
+ cp_sign_cross: cross cp_rs1_sign, cp_imm_sign, cp_rd_sign;
+ `CG_END
+
+ `U_INSTR_CG_BEGIN(lui)
+ cp_sign_cross: cross cp_imm_sign, cp_rd_sign;
+ `CG_END
+
+ `U_INSTR_CG_BEGIN(auipc)
+ cp_sign_cross: cross cp_imm_sign, cp_rd_sign;
+ `CG_END
+
+ // Shift instructions
+ `R_INSTR_CG_BEGIN(sra)
+ cp_sign_cross: cross cp_rs1_sign, cp_rs2_sign;
+ `CG_END
+
+ `R_INSTR_CG_BEGIN(sll)
+ cp_sign_cross: cross cp_rs1_sign, cp_rs2_sign;
+ `CG_END
+
+ `R_INSTR_CG_BEGIN(srl)
+ cp_sign_cross: cross cp_rs1_sign, cp_rs2_sign;
+ `CG_END
+
+ `I_INSTR_CG_BEGIN(srai)
+ cp_sign_cross: cross cp_rs1_sign, cp_imm_sign;
+ `CG_END
+
+ `I_INSTR_CG_BEGIN(slli)
+ cp_sign_cross: cross cp_rs1_sign, cp_imm_sign;
+ `CG_END
+
+ `I_INSTR_CG_BEGIN(srli)
+ cp_sign_cross: cross cp_rs1_sign, cp_imm_sign;
+ `CG_END
+
+ // Logical instructions
+ `R_INSTR_CG_BEGIN(xor)
+ cp_logical : coverpoint instr.logical_similarity;
+ cp_sign_cross: cross cp_rs1_sign, cp_rs2_sign;
+ `CG_END
+
+ `R_INSTR_CG_BEGIN(or)
+ cp_logical : coverpoint instr.logical_similarity;
+ cp_sign_cross: cross cp_rs1_sign, cp_rs2_sign;
+ `CG_END
+
+ `R_INSTR_CG_BEGIN(and)
+ cp_logical : coverpoint instr.logical_similarity;
+ cp_sign_cross: cross cp_rs1_sign, cp_rs2_sign;
+ `CG_END
+
+ `I_INSTR_CG_BEGIN(xori)
+ cp_logical : coverpoint instr.logical_similarity;
+ cp_sign_cross: cross cp_rs1_sign, cp_imm_sign;
+ `CG_END
+
+ `I_INSTR_CG_BEGIN(ori)
+ cp_logical : coverpoint instr.logical_similarity;
+ cp_sign_cross: cross cp_rs1_sign, cp_imm_sign;
+ `CG_END
+
+ `I_INSTR_CG_BEGIN(andi)
+ cp_logical : coverpoint instr.logical_similarity;
+ cp_sign_cross: cross cp_rs1_sign, cp_imm_sign;
+ `CG_END
+
+ // Compare instructions
+ `CMP_INSTR_CG_BEGIN(slt)
+ cp_rs2 : coverpoint instr.rs2;
+ cp_rs2_sign : coverpoint instr.rs2_sign;
+ cp_sign_cross : cross cp_rs1_sign, cp_rs2_sign;
+ `CG_END
+
+ `CMP_INSTR_CG_BEGIN(sltu)
+ cp_rs2 : coverpoint instr.rs2;
+ cp_rs2_sign : coverpoint instr.rs2_sign;
+ cp_sign_cross : cross cp_rs1_sign, cp_rs2_sign;
+ `CG_END
+
+ `CMP_INSTR_CG_BEGIN(slti)
+ cp_imm_sign : coverpoint instr.imm_sign;
+ cp_sign_cross : cross cp_rs1_sign, cp_imm_sign;
+ `CG_END
+
+ `CMP_INSTR_CG_BEGIN(sltiu)
+ cp_imm_sign : coverpoint instr.imm_sign;
+ cp_sign_cross : cross cp_rs1_sign, cp_imm_sign;
+ `CG_END
+
+ // Branch instruction
+ `SB_INSTR_CG_BEGIN(beq)
+ `CG_END
+
+ `SB_INSTR_CG_BEGIN(bne)
+ `CG_END
+
+ `SB_INSTR_CG_BEGIN(blt)
+ `CG_END
+
+ `SB_INSTR_CG_BEGIN(bge)
+ `CG_END
+
+ `SB_INSTR_CG_BEGIN(bltu)
+ `CG_END
+
+ `SB_INSTR_CG_BEGIN(bgeu)
+ `CG_END
+
+ // Load instructions
+ `LOAD_INSTR_CG_BEGIN(lb)
+ `CG_END
+
+ `LOAD_INSTR_CG_BEGIN(lh)
+ cp_align: coverpoint instr.unaligned_mem_access;
+ `CG_END
+
+ `LOAD_INSTR_CG_BEGIN(lw)
+ cp_align: coverpoint instr.unaligned_mem_access;
+ `CG_END
+
+ `LOAD_INSTR_CG_BEGIN(lbu)
+ `CG_END
+
+ `LOAD_INSTR_CG_BEGIN(lhu)
+ cp_align: coverpoint instr.unaligned_mem_access;
+ `CG_END
+
+ // Store instruction
+ `STORE_INSTR_CG_BEGIN(sb)
+ `CG_END
+
+ `STORE_INSTR_CG_BEGIN(sh)
+ cp_misalign: coverpoint instr.unaligned_mem_access;
+ `CG_END
+
+ `STORE_INSTR_CG_BEGIN(sw)
+ cp_misalign: coverpoint instr.unaligned_mem_access;
+ `CG_END
+
+ // CSR instructions
+ `CSR_INSTR_CG_BEGIN(csrrw)
+ cp_rs2 : coverpoint instr.rs1;
+ `CG_END
+
+ `CSR_INSTR_CG_BEGIN(csrrs)
+ cp_rs2 : coverpoint instr.rs1;
+ `CG_END
+
+ `CSR_INSTR_CG_BEGIN(csrrc)
+ cp_rs2 : coverpoint instr.rs1;
+ `CG_END
+
+ `CSR_INSTR_CG_BEGIN(csrrwi)
+ cp_imm_sign : coverpoint instr.imm_sign;
+ `CG_END
+
+ `CSR_INSTR_CG_BEGIN(csrrsi)
+ cp_imm_sign : coverpoint instr.imm_sign;
+ `CG_END
+
+ `CSR_INSTR_CG_BEGIN(csrrci)
+ cp_imm_sign : coverpoint instr.imm_sign;
+ `CG_END
+
+ // RV32M
+
+ `R_INSTR_CG_BEGIN(mul)
+ cp_sign_cross: cross cp_rs1_sign, cp_rs2_sign;
+ `CG_END
+
+ `R_INSTR_CG_BEGIN(mulh)
+ cp_sign_cross: cross cp_rs1_sign, cp_rs2_sign;
+ `CG_END
+
+ `R_INSTR_CG_BEGIN(mulhsu)
+ cp_sign_cross: cross cp_rs1_sign, cp_rs2_sign;
+ `CG_END
+
+ `R_INSTR_CG_BEGIN(mulhu)
+ cp_sign_cross: cross cp_rs1_sign, cp_rs2_sign;
+ `CG_END
+
+ `R_INSTR_CG_BEGIN(div)
+ cp_rs2_val : coverpoint instr.rs2_special_val;
+ cp_sign_cross: cross cp_rs1_sign, cp_rs2_sign;
+ `CG_END
+
+ `R_INSTR_CG_BEGIN(divu)
+ cp_rs2_val : coverpoint instr.rs2_special_val;
+ cp_sign_cross: cross cp_rs1_sign, cp_rs2_sign;
+ `CG_END
+
+ `R_INSTR_CG_BEGIN(rem)
+ cp_rs2_val : coverpoint instr.rs2_special_val;
+ cp_sign_cross: cross cp_rs1_sign, cp_rs2_sign;
+ `CG_END
+
+ `R_INSTR_CG_BEGIN(remu)
+ cp_rs2_val : coverpoint instr.rs2_special_val;
+ cp_sign_cross: cross cp_rs1_sign, cp_rs2_sign;
+ `CG_END
+
+ // RV64M
+
+ `R_INSTR_CG_BEGIN(mulw)
+ cp_sign_cross: cross cp_rs1_sign, cp_rs2_sign;
+ `CG_END
+
+ `R_INSTR_CG_BEGIN(divw)
+ cp_rs2_val : coverpoint instr.rs2_special_val;
+ cp_sign_cross: cross cp_rs1_sign, cp_rs2_sign;
+ `CG_END
+
+ `R_INSTR_CG_BEGIN(divuw)
+ cp_rs2_val : coverpoint instr.rs2_special_val;
+ cp_sign_cross: cross cp_rs1_sign, cp_rs2_sign;
+ `CG_END
+
+ `R_INSTR_CG_BEGIN(remw)
+ cp_rs2_val : coverpoint instr.rs2_special_val;
+ cp_sign_cross: cross cp_rs1_sign, cp_rs2_sign;
+ `CG_END
+
+ `R_INSTR_CG_BEGIN(remuw)
+ cp_rs2_val : coverpoint instr.rs2_special_val;
+ cp_sign_cross: cross cp_rs1_sign, cp_rs2_sign;
+ `CG_END
+
+ // RV64I
+ `LOAD_INSTR_CG_BEGIN(lwu)
+ cp_align: coverpoint instr.unaligned_mem_access;
+ `CG_END
+
+ `LOAD_INSTR_CG_BEGIN(ld)
+ cp_align: coverpoint instr.unaligned_mem_access;
+ `CG_END
+
+ `STORE_INSTR_CG_BEGIN(sd)
+ cp_misalign: coverpoint instr.unaligned_mem_access;
+ `CG_END
+
+ `R_INSTR_CG_BEGIN(sraw)
+ cp_sign_cross: cross cp_rs1_sign, cp_rs2_sign;
+ `CG_END
+
+ `R_INSTR_CG_BEGIN(sllw)
+ cp_sign_cross: cross cp_rs1_sign, cp_rs2_sign;
+ `CG_END
+
+ `R_INSTR_CG_BEGIN(srlw)
+ cp_sign_cross: cross cp_rs1_sign, cp_rs2_sign;
+ `CG_END
+
+ `I_INSTR_CG_BEGIN(sraiw)
+ cp_sign_cross: cross cp_rs1_sign, cp_imm_sign;
+ `CG_END
+
+ `I_INSTR_CG_BEGIN(slliw)
+ cp_sign_cross: cross cp_rs1_sign, cp_imm_sign;
+ `CG_END
+
+ `I_INSTR_CG_BEGIN(srliw)
+ cp_sign_cross: cross cp_rs1_sign, cp_imm_sign;
+ `CG_END
+
+ `R_INSTR_CG_BEGIN(addw)
+ cp_sign_cross: cross cp_rs1_sign, cp_rs2_sign, cp_rd_sign;
+ `CG_END
+
+ `R_INSTR_CG_BEGIN(subw)
+ cp_sign_cross: cross cp_rs1_sign, cp_rs2_sign, cp_rd_sign;
+ `CG_END
+
+ `I_INSTR_CG_BEGIN(addiw)
+ cp_sign_cross: cross cp_rs1_sign, cp_imm_sign, cp_rd_sign;
+ `CG_END
+
+ // RV32C
+
+ `CL_INSTR_CG_BEGIN(c_lw)
+ `CG_END
+
+ `CL_INSTR_CG_BEGIN(c_lwsp)
+ `CG_END
+
+ `CS_INSTR_CG_BEGIN(c_sw)
+ `CG_END
+
+ `CS_INSTR_CG_BEGIN(c_swsp)
+ `CG_END
+
+ `CIW_INSTR_CG_BEGIN(c_addi4spn)
+ `CG_END
+
+ `CI_INSTR_CG_BEGIN(c_addi)
+ `CG_END
+
+ `CI_INSTR_CG_BEGIN(c_addi16sp)
+ `CG_END
+
+ `CI_INSTR_CG_BEGIN(c_li)
+ `CG_END
+
+ `CI_INSTR_CG_BEGIN(c_lui)
+ `CG_END
+
+ `CS_INSTR_CG_BEGIN(c_sub)
+ `CG_END
+
+ `CR_INSTR_CG_BEGIN(c_add)
+ `CG_END
+
+ `CR_INSTR_CG_BEGIN(c_mv)
+ `CG_END
+
+ `CB_INSTR_CG_BEGIN(c_andi)
+ `CG_END
+
+ `CS_INSTR_CG_BEGIN(c_xor)
+ `CG_END
+
+ `CS_INSTR_CG_BEGIN(c_or)
+ `CG_END
+
+ `CS_INSTR_CG_BEGIN(c_and)
+ `CG_END
+
+ `CB_INSTR_CG_BEGIN(c_beqz)
+ `CG_END
+
+ `CB_INSTR_CG_BEGIN(c_bnez)
+ `CG_END
+
+ `CB_INSTR_CG_BEGIN(c_srli)
+ `CG_END
+
+ `CB_INSTR_CG_BEGIN(c_srai)
+ `CG_END
+
+ `CI_INSTR_CG_BEGIN(c_slli)
+ `CG_END
+
+ `CJ_INSTR_CG_BEGIN(c_j)
+ `CG_END
+
+ `CJ_INSTR_CG_BEGIN(c_jal)
+ `CG_END
+
+ `CR_INSTR_CG_BEGIN(c_jr)
+ `CG_END
+
+ `CR_INSTR_CG_BEGIN(c_jalr)
+ `CG_END
+
+ // RV64C
+
+ `CL_INSTR_CG_BEGIN(c_ld)
+ `CG_END
+
+ `CL_INSTR_CG_BEGIN(c_ldsp)
+ `CG_END
+
+ `CS_INSTR_CG_BEGIN(c_sd)
+ `CG_END
+
+ `CS_INSTR_CG_BEGIN(c_sdsp)
+ `CG_END
+
+ `CI_INSTR_CG_BEGIN(c_addiw)
+ `CG_END
+
+ `CS_INSTR_CG_BEGIN(c_subw)
+ `CG_END
+
+ `CR_INSTR_CG_BEGIN(c_addw)
+ `CG_END
+
+ `INSTR_CG_BEGIN(hint)
+ cp_hint : coverpoint instr.binary[15:0] {
+ wildcard bins addi = {16'b0000_1xxx_x000_0001,
+ 16'b0000_x1xx_x000_0001,
+ 16'b0000_xx1x_x000_0001,
+ 16'b0000_xxx1_x000_0001,
+ 16'b0000_xxxx_1000_0001};
+ wildcard bins li = {16'b010x_0000_0xxx_xx01};
+ wildcard bins lui = {16'b011x_0000_0xxx_xx01};
+ wildcard bins srli64 = {16'b1000_00xx_x000_0001};
+ wildcard bins srai64 = {16'b1000_01xx_x000_0001};
+ wildcard bins slli = {16'b000x_0000_0xxx_xx10};
+ wildcard bins slli64 = {16'b0000_xxxx_x000_0010};
+ wildcard bins mv = {16'b1000_0000_01xx_xx10,
+ 16'b1000_0000_0x1x_xx10,
+ 16'b1000_0000_0xx1_xx10,
+ 16'b1000_0000_0xxx_1x10,
+ 16'b1000_0000_0xxx_x110};
+ wildcard bins add = {16'b1001_0000_01xx_xx10,
+ 16'b1001_0000_0x1x_xx10,
+ 16'b1001_0000_0xx1_xx10,
+ 16'b1001_0000_0xxx_1x10,
+ 16'b1001_0000_0xxx_x110};
+ }
+ `CG_END
+
+ // Branch hit history
+ covergroup branch_hit_history_cg;
+ coverpoint branch_hit_history;
+ endgroup
+
+ // Instruction transition for all supported instructions
+ /* TODO: Refine the transition functional coverage, not all combinations are interesting
+ covergroup instr_trans_cg with function sample();
+ cp_instr: coverpoint instr_name {
+ bins instr[] = cp_instr with (is_supported_instr(riscv_instr_name_t'(item)));
+ }
+ cp_pre_instr: coverpoint pre_instr_name {
+ // This is a helper coverpoint for cross coverpoint below, it should not be counted when
+ // calculate the coverage score
+ type_option.weight = 0;
+ bins instr[] = cp_pre_instr with (is_supported_instr(riscv_instr_name_t'(item)));
+ }
+ cp_trans: cross cp_pre_instr, cp_instr {
+ // Cover all instruction transitions, except for below system instructions
+ ignore_bins ignore = binsof(cp_instr) intersect {ECALL, URET, SRET, SRET, DRET} ||
+ binsof(cp_pre_instr) intersect {ECALL, URET, SRET, SRET, DRET};
+ }
+ endgroup
+ */
+
+ // TODO: Add covergroup for various hazard conditions
+
+ function new(riscv_instr_gen_config cfg);
+ this.cfg = cfg;
+ cur_instr = riscv_instr_cov_item::type_id::create("cur_instr");
+ pre_instr = riscv_instr_cov_item::type_id::create("pre_instr");
+ build_instr_list();
+ hint_cg = new();
+ // RV32I instruction functional coverage instantiation
+ add_cg = new();
+ sub_cg = new();
+ addi_cg = new();
+ lui_cg = new();
+ auipc_cg = new();
+ sll_cg = new();
+ srl_cg = new();
+ sra_cg = new();
+ slli_cg = new();
+ srli_cg = new();
+ srai_cg = new();
+ and_cg = new();
+ or_cg = new();
+ xor_cg = new();
+ andi_cg = new();
+ ori_cg = new();
+ xori_cg = new();
+ slt_cg = new();
+ sltu_cg = new();
+ slti_cg = new();
+ sltiu_cg = new();
+ beq_cg = new();
+ bne_cg = new();
+ blt_cg = new();
+ bge_cg = new();
+ bgeu_cg = new();
+ bltu_cg = new();
+ lb_cg = new();
+ lh_cg = new();
+ lw_cg = new();
+ lbu_cg = new();
+ lhu_cg = new();
+ sb_cg = new();
+ sh_cg = new();
+ sw_cg = new();
+ csrrw_cg = new();
+ csrrs_cg = new();
+ csrrc_cg = new();
+ csrrwi_cg = new();
+ csrrsi_cg = new();
+ csrrci_cg = new();
+ // instr_trans_cg = new();
+ branch_hit_history_cg = new();
+ if (RV32M inside {supported_isa}) begin
+ mul_cg = new();
+ mulh_cg = new();
+ mulhsu_cg = new();
+ mulhu_cg = new();
+ div_cg = new();
+ divu_cg = new();
+ rem_cg = new();
+ end
+ if (RV64M inside {supported_isa}) begin
+ mulw_cg = new();
+ divw_cg = new();
+ divuw_cg = new();
+ remw_cg = new();
+ remuw_cg = new();
+ end
+ if (RV64I inside {supported_isa}) begin
+ lwu_cg = new();
+ ld_cg = new();
+ sd_cg = new();
+ sllw_cg = new();
+ slliw_cg = new();
+ srlw_cg = new();
+ srliw_cg = new();
+ sraw_cg = new();
+ sraiw_cg = new();
+ addw_cg = new();
+ addiw_cg = new();
+ subw_cg = new();
+ end
+ if (RV32C inside {supported_isa}) begin
+ c_lw_cg = new();
+ c_sw_cg = new();
+ c_lwsp_cg = new();
+ c_swsp_cg = new();
+ c_addi4spn_cg = new();
+ c_addi_cg = new();
+ c_addi16sp_cg = new();
+ c_li_cg = new();
+ c_lui_cg = new();
+ c_sub_cg = new();
+ c_add_cg = new();
+ c_mv_cg = new();
+ c_andi_cg = new();
+ c_xor_cg = new();
+ c_or_cg = new();
+ c_and_cg = new();
+ c_beqz_cg = new();
+ c_bnez_cg = new();
+ c_srli_cg = new();
+ c_srai_cg = new();
+ c_slli_cg = new();
+ c_j_cg = new();
+ c_jal_cg = new();
+ c_jr_cg = new();
+ c_jalr_cg = new();
+ end
+ if (RV64C inside {supported_isa}) begin
+ c_ld_cg = new();
+ c_sd_cg = new();
+ c_ldsp_cg = new();
+ c_sdsp_cg = new();
+ c_addiw_cg = new();
+ c_subw_cg = new();
+ c_addw_cg = new();
+ end
+ endfunction
+
+ function void sample(riscv_instr_cov_item instr);
+ instr_cnt += 1;
+ if (instr_cnt > 1) begin
+ instr.check_hazard_condition(pre_instr);
+ end
+ if (instr.binary[1:0] != 2'b11) begin
+ hint_cg.sample(instr);
+ end
+ case (instr.instr_name)
+ ADD : add_cg.sample(instr);
+ SUB : sub_cg.sample(instr);
+ ADDI : addi_cg.sample(instr);
+ LUI : lui_cg.sample(instr);
+ AUIPC : auipc_cg.sample(instr);
+ SLL : sll_cg.sample(instr);
+ SRL : srl_cg.sample(instr);
+ SRA : sra_cg.sample(instr);
+ SLLI : slli_cg.sample(instr);
+ SRLI : srli_cg.sample(instr);
+ SRAI : srai_cg.sample(instr);
+ AND : and_cg.sample(instr);
+ OR : or_cg.sample(instr);
+ XOR : xor_cg.sample(instr);
+ ANDI : andi_cg.sample(instr);
+ ORI : ori_cg.sample(instr);
+ XORI : xori_cg.sample(instr);
+ SLT : slt_cg.sample(instr);
+ SLTU : sltu_cg.sample(instr);
+ SLTI : slti_cg.sample(instr);
+ SLTIU : sltiu_cg.sample(instr);
+ BEQ : beq_cg.sample(instr);
+ BNE : bne_cg.sample(instr);
+ BLT : blt_cg.sample(instr);
+ BGE : bge_cg.sample(instr);
+ BLTU : bltu_cg.sample(instr);
+ BGEU : bgeu_cg.sample(instr);
+ LW : lw_cg.sample(instr);
+ LH : lh_cg.sample(instr);
+ LB : lb_cg.sample(instr);
+ LBU : lbu_cg.sample(instr);
+ LHU : lhu_cg.sample(instr);
+ SW : sw_cg.sample(instr);
+ SH : sh_cg.sample(instr);
+ SB : sb_cg.sample(instr);
+ CSRRW : csrrw_cg.sample(instr);
+ CSRRS : csrrs_cg.sample(instr);
+ CSRRC : csrrc_cg.sample(instr);
+ CSRRWI : csrrwi_cg.sample(instr);
+ CSRRSI : csrrsi_cg.sample(instr);
+ CSRRCI : csrrci_cg.sample(instr);
+ MUL : mul_cg.sample(instr);
+ MULH : mulh_cg.sample(instr);
+ MULHSU : mulhsu_cg.sample(instr);
+ MULHU : mulhu_cg.sample(instr);
+ DIV : div_cg.sample(instr);
+ DIVU : divu_cg.sample(instr);
+ REM : rem_cg.sample(instr);
+ MULW : mulw_cg.sample(instr);
+ DIVW : divw_cg.sample(instr);
+ DIVUW : divuw_cg.sample(instr);
+ REMW : remw_cg.sample(instr);
+ REMUW : remuw_cg.sample(instr);
+ LWU : lwu_cg.sample(instr);
+ LD : ld_cg.sample(instr);
+ SD : sd_cg.sample(instr);
+ SLLW : sllw_cg.sample(instr);
+ SLLIW : slliw_cg.sample(instr);
+ SRLW : srlw_cg.sample(instr);
+ SRLIW : srliw_cg.sample(instr);
+ SRAW : sraw_cg.sample(instr);
+ SRAIW : sraiw_cg.sample(instr);
+ ADDW : addw_cg.sample(instr);
+ ADDIW : addiw_cg.sample(instr);
+ SUBW : subw_cg.sample(instr);
+ C_LW : c_lw_cg.sample(instr);
+ C_SW : c_sw_cg.sample(instr);
+ C_LWSP : c_lwsp_cg.sample(instr);
+ C_SWSP : c_swsp_cg.sample(instr);
+ C_ADDI4SPN : c_addi4spn_cg.sample(instr);
+ C_ADDI : c_addi_cg.sample(instr);
+ C_ADDI16SP : c_addi16sp_cg.sample(instr);
+ C_LI : c_li_cg.sample(instr);
+ C_LUI : c_lui_cg.sample(instr);
+ C_SUB : c_sub_cg.sample(instr);
+ C_ADD : c_add_cg.sample(instr);
+ C_MV : c_mv_cg.sample(instr);
+ C_ANDI : c_andi_cg.sample(instr);
+ C_XOR : c_xor_cg.sample(instr);
+ C_OR : c_or_cg.sample(instr);
+ C_AND : c_and_cg.sample(instr);
+ C_BEQZ : c_beqz_cg.sample(instr);
+ C_BNEZ : c_bnez_cg.sample(instr);
+ C_SRLI : c_srli_cg.sample(instr);
+ C_SRAI : c_srai_cg.sample(instr);
+ C_SLLI : c_slli_cg.sample(instr);
+ C_J : c_j_cg.sample(instr);
+ C_JAL : c_jal_cg.sample(instr);
+ C_JR : c_jr_cg.sample(instr);
+ C_JALR : c_jalr_cg.sample(instr);
+ C_LD : c_ld_cg.sample(instr);
+ C_SD : c_sd_cg.sample(instr);
+ C_LDSP : c_ldsp_cg.sample(instr);
+ C_SDSP : c_sdsp_cg.sample(instr);
+ C_SUBW : c_subw_cg.sample(instr);
+ C_ADDW : c_addw_cg.sample(instr);
+ C_ADDIW : c_addiw_cg.sample(instr);
+ endcase
+ if (instr.category == BRANCH) begin
+ branch_hit_history = (branch_hit_history << 1) | instr.branch_hit;
+ branch_instr_cnt += 1;
+ if (branch_instr_cnt >= $bits(branch_hit_history)) begin
+ branch_hit_history_cg.sample();
+ end
+ end
+ if (instr_cnt > 1) begin
+ // instr_trans_cg.sample();
+ end
+ pre_instr.copy_base_instr(instr);
+ pre_instr.mem_addr = instr.mem_addr;
+ endfunction
+
+ // Check if the privileged CSR is implemented
+ virtual function bit is_implemented_csr(bit [11:0] pcsr);
+ if (pcsr inside {implemented_pcsr}) begin
+ return 1'b1;
+ end else begin
+ return 1'b0;
+ end
+ endfunction
+
+ // Check if the instruction is supported
+ virtual function bit is_supported_instr(riscv_instr_name_t name);
+ if (name inside {instr_list}) begin
+ return 1'b1;
+ end else begin
+ return 1'b0;
+ end
+ endfunction
+
+ // Check if the instruction is supported
+ virtual function bit is_compressed_gpr(riscv_reg_t gpr);
+ if (gpr inside {[S0:A5]}) begin
+ return 1'b1;
+ end else begin
+ return 1'b0;
+ end
+ endfunction
+
+ // Build the supported instruction list based on the core setting
+ virtual function void build_instr_list();
+ riscv_instr_name_t instr_name;
+ instr_name = instr_name.first;
+ foreach (riscv_instr_pkg::implemented_csr[i]) begin
+ privil_csr.push_back(riscv_instr_pkg::implemented_csr[i]);
+ end
+ do begin
+ riscv_instr_base instr;
+ if (!(instr_name inside {unsupported_instr}) && (instr_name != INVALID_INSTR)) begin
+ instr = riscv_instr_base::type_id::create("instr");
+ if (!instr.randomize() with {instr_name == local::instr_name;}) begin
+ `uvm_fatal("riscv_instr_cover_group",
+ $sformatf("Instruction %0s randomization failure", instr_name.name()))
+ end
+ if ((instr.group inside {supported_isa}) &&
+ (instr.group inside {RV32I, RV32M, RV64M, RV64I, RV32C, RV64C})) begin
+ if (((instr_name inside {URET}) && !support_umode_trap) ||
+ ((instr_name inside {SRET, SFENCE_VMA}) &&
+ !(SUPERVISOR_MODE inside {supported_privileged_mode})) ||
+ ((instr_name inside {DRET}) && !support_debug_mode)) begin
+ instr_name = instr_name.next;
+ continue;
+ end
+ `uvm_info("riscv_instr_cover_group", $sformatf("Adding [%s] %s to the list",
+ instr.group.name(), instr.instr_name.name()), UVM_HIGH)
+ instr_list.push_back(instr_name);
+ end
+ end
+ instr_name = instr_name.next;
+ end
+ while (instr_name != instr_name.first);
+ endfunction
+
+ function void reset();
+ instr_cnt = 0;
+ branch_instr_cnt = 0;
+ branch_hit_history = '0;
+ endfunction
+
+endclass
diff --git a/hw/vendor/lowrisc_ibex/vendor/google_riscv-dv/src/riscv_instr_gen_config.sv b/hw/vendor/lowrisc_ibex/vendor/google_riscv-dv/src/riscv_instr_gen_config.sv
index 7ce2bc9..74de574 100644
--- a/hw/vendor/lowrisc_ibex/vendor/google_riscv-dv/src/riscv_instr_gen_config.sv
+++ b/hw/vendor/lowrisc_ibex/vendor/google_riscv-dv/src/riscv_instr_gen_config.sv
@@ -39,9 +39,6 @@
// Pattern of data section: RAND_DATA, ALL_ZERO, INCR_VAL
rand data_pattern_t data_page_pattern;
- // Max depth for the nested loops
- rand bit [1:0] max_nested_loop;
-
// Associate array for delegation configuration for each exception and interrupt
// When the bit is 1, the corresponding delegation is enabled.
rand bit m_mode_exception_delegation[exception_cause_t];
@@ -52,6 +49,10 @@
// Priviledged mode after boot
rand privileged_mode_t init_privileged_mode;
+ rand bit[XLEN-1:0] mstatus, mie,
+ sstatus, sie,
+ ustatus, uie;
+
// Key fields in xSTATUS
// Memory protection bits
rand bit mstatus_mprv;
@@ -69,12 +70,44 @@
bit check_misa_init_val = 1'b0;
bit check_xstatus = 1'b1;
+ // Virtual address translation is on for this test
+ rand bit virtual_addr_translation_on;
+
+ //-----------------------------------------------------------------------------
+ // User space memory region and stack setting
+ //-----------------------------------------------------------------------------
+
+ mem_region_t mem_region[$] = '{
+ '{name:"region_0", size_in_bytes: 4096, xwr: 3'b111},
+ '{name:"region_1", size_in_bytes: 4096 * 4, xwr: 3'b111},
+ '{name:"region_2", size_in_bytes: 4096 * 2, xwr: 3'b111},
+ '{name:"region_3", size_in_bytes: 512, xwr: 3'b111},
+ '{name:"region_4", size_in_bytes: 4096, xwr: 3'b111}
+ };
+
+ // Stack section word length
+ int stack_len = 5000;
+
+ //-----------------------------------------------------------------------------
+ // Kernel section setting, used by supervisor mode programs
+ //-----------------------------------------------------------------------------
+
+ mem_region_t s_mem_region[$] = '{
+ '{name:"s_region_0", size_in_bytes: 4096, xwr: 3'b111},
+ '{name:"s_region_1", size_in_bytes: 4096, xwr: 3'b111}};
+
+ // Kernel Stack section word length
+ int kernel_stack_len = 4000;
+
+ // Number of instructions for each kernel program
+ int kernel_program_instr_cnt = 400;
+
//-----------------------------------------------------------------------------
// Instruction list based on the config, generate by build_instruction_template
//-----------------------------------------------------------------------------
riscv_instr_base instr_template[riscv_instr_name_t];
riscv_instr_name_t basic_instr[$];
- riscv_instr_name_t instr_group[riscv_instr_cateogry_t][$];
+ riscv_instr_name_t instr_group[riscv_instr_group_t][$];
riscv_instr_name_t instr_category[riscv_instr_cateogry_t][$];
//-----------------------------------------------------------------------------
@@ -88,16 +121,16 @@
// For tests doesn't involve load/store, the data section generation could be skipped
bit no_data_page;
// Options to turn off some specific types of instructions
- bit no_branch_jump; // No branch/jump instruction
- bit no_load_store; // No load/store instruction
- bit no_csr_instr; // No csr instruction
- bit no_ebreak = 1; // No ebreak instruction
- bit no_fence; // No fence instruction
- bit no_wfi = 1; // No WFI instruction
+ bit no_branch_jump; // No branch/jump instruction
+ bit no_load_store; // No load/store instruction
+ bit no_csr_instr; // No csr instruction
+ bit no_ebreak = 1; // No ebreak instruction
+ bit no_dret = 1; // No dret instruction
+ bit no_fence; // No fence instruction
+ bit no_wfi = 1; // No WFI instruction
bit enable_unaligned_load_store;
- bit enable_illegal_instruction;
- bit enable_hint_instruction;
- int bin_program_instr_cnt = 200;
+ int illegal_instr_ratio;
+ int hint_instr_ratio;
// Directed boot privileged mode, u, m, s
string boot_mode_opts;
int enable_page_table_exception;
@@ -106,10 +139,15 @@
string asm_test_suffix;
// Enable interrupt bit in MSTATUS (MIE, SIE, UIE)
int enable_interrupt;
+ // Generate a bare program without any init/exit/error handling/page table routines
+ // The generated program can be integrated with a larger program.
+ // Note that the bare mode program is not expected to run in standalone mode
+ bit bare_program_mode;
// Enable accessing illegal CSR instruction
// - Accessing non-existence CSR
// - Accessing CSR with wrong privileged mode
bit enable_illegal_csr_instruction;
+ bit randomize_csr = 0;
// sfence support
bit allow_sfence_exception = 0;
// Interrupt/Exception Delegation
@@ -123,16 +161,24 @@
bit require_signature_addr = 1'b0;
rand riscv_reg_t signature_addr_reg;
rand riscv_reg_t signature_data_reg;
- bit gen_debug_section = 1'b0;
+ // Register that will be used to handle any DCSR operations inside of the
+ // debug rom
+ rand riscv_reg_t scratch_reg;
// Enable a full or empty debug_rom section.
// Full debug_rom will contain random instruction streams.
// Empty debug_rom will contain just dret instruction and will return immediately.
// Will be empty by default.
- bit empty_debug_section = 1'b0;
+ bit gen_debug_section = 1'b0;
+ // Enable generation of a directed sequence of instructions containing
+ // ebreak inside the debug_rom.
+ // Disabled by default.
+ bit enable_ebreak_in_debug_rom = 1'b0;
+ // Enable setting dcsr.ebreak(m/s/u)
+ bit set_dcsr_ebreak = 1'b0;
// Number of sub programs in the debug rom
int num_debug_sub_program = 0;
// Stack space allocated to each program, need to be enough to store necessary context
- // Example: RA, SP, T0, loop registers
+ // Example: RA, SP, T0
int min_stack_len_per_program = 10 * (XLEN/8);
int max_stack_len_per_program = 16 * (XLEN/8);
// Maximum branch distance, avoid skipping large portion of the code
@@ -142,9 +188,6 @@
// Reserved registers
// Default reserved registers, only used by special instructions
riscv_reg_t default_reserved_regs[];
- // Reserve some registers for loop counter, make sure the loop can execute
- // in a determinstic way and not affected by other random instructions
- rand riscv_reg_t loop_regs[];
// All reserved regs
riscv_reg_t reserved_regs[];
@@ -153,17 +196,6 @@
constraint default_c {
sub_program_instr_cnt.size() == num_of_sub_program;
debug_sub_program_instr_cnt.size() == num_debug_sub_program;
- if (riscv_instr_pkg::support_debug_mode) {
- main_program_instr_cnt + sub_program_instr_cnt.sum()
- + debug_program_instr_cnt
- + debug_sub_program_instr_cnt.sum() == instr_cnt;
- debug_program_instr_cnt inside {[100 : 300]};
- foreach(debug_sub_program_instr_cnt[i]) {
- debug_sub_program_instr_cnt[i] inside {[100 : 300]};
- }
- } else {
- main_program_instr_cnt + sub_program_instr_cnt.sum() == instr_cnt;
- }
main_program_instr_cnt inside {[10 : instr_cnt]};
foreach(sub_program_instr_cnt[i]) {
sub_program_instr_cnt[i] inside {[10 : instr_cnt]};
@@ -180,6 +212,29 @@
}
}
+ constraint debug_mode_c {
+ if (riscv_instr_pkg::support_debug_mode) {
+ debug_program_instr_cnt inside {[100 : 300]};
+ foreach(debug_sub_program_instr_cnt[i]) {
+ debug_sub_program_instr_cnt[i] inside {[100 : 300]};
+ }
+ }
+ `ifndef DSIM
+ main_program_instr_cnt + sub_program_instr_cnt.sum() == instr_cnt;
+ `else
+ // dsim has some issue supporting sum(), use some approximate constraint to generate
+ // instruction cnt
+ if (num_of_sub_program > 0) {
+ main_program_instr_cnt inside {[10:instr_cnt/2]};
+ foreach (sub_program_instr_cnt[i]) {
+ sub_program_instr_cnt[i] inside {[10:instr_cnt/num_of_sub_program]};
+ }
+ } else {
+ main_program_instr_cnt == instr_cnt;
+ }
+ `endif
+ }
+
// Boot privileged mode distribution
constraint boot_privileged_mode_dist_c {
// Boot to higher privileged mode more often
@@ -232,7 +287,7 @@
// You can modify this constraint if your ISS support different set of delegations
constraint delegation_c {
foreach(m_mode_exception_delegation[i]) {
- if(!support_supervisor_mode) {
+ if(!support_supervisor_mode || no_delegation) {
m_mode_exception_delegation[i] == 0;
}
if(!(i inside {INSTRUCTION_ADDRESS_MISALIGNED, BREAKPOINT, ECALL_UMODE,
@@ -241,7 +296,7 @@
}
}
foreach(m_mode_interrupt_delegation[i]) {
- if(!support_supervisor_mode) {
+ if(!support_supervisor_mode || no_delegation) {
m_mode_interrupt_delegation[i] == 0;
}
if(!(i inside {S_SOFTWARE_INTR, S_TIMER_INTR, S_EXTERNAL_INTR})) {
@@ -250,23 +305,33 @@
}
}
- constraint reserved_reg_c {
- unique {loop_regs};
- foreach(loop_regs[i]) {
- !(loop_regs[i] inside {default_reserved_regs});
+ constraint reserve_scratch_reg_c {
+ scratch_reg != ZERO;
+ foreach (default_reserved_regs[i]) {
+ signature_data_reg != default_reserved_regs[i];
+ signature_addr_reg != default_reserved_regs[i];
}
- !(signature_addr_reg inside {ZERO, default_reserved_regs, loop_regs});
- !(signature_data_reg inside {ZERO, default_reserved_regs, loop_regs});
- signature_addr_reg != signature_data_reg;
}
- constraint legal_loop_regs_c {
- soft max_nested_loop != 0;
- // One register for loop counter, one for loop limit
- loop_regs.size() == max_nested_loop*2;
- unique {loop_regs};
- foreach(loop_regs[i]) {
- loop_regs[i] != ZERO;
+ constraint signature_addr_c {
+ if (require_signature_addr) {
+ foreach (default_reserved_regs[i]) {
+ signature_addr_reg != default_reserved_regs[i];
+ signature_data_reg != default_reserved_regs[i];
+ }
+ signature_data_reg != scratch_reg;
+ signature_addr_reg != scratch_reg;
+ signature_data_reg != ZERO;
+ signature_addr_reg != ZERO;
+ }
+ }
+
+ constraint addr_translaction_c {
+ solve init_privileged_mode before virtual_addr_translation_on;
+ if ((init_privileged_mode != MACHINE_MODE) && (SATP_MODE != BARE)) {
+ virtual_addr_translation_on == 1'b1;
+ } else {
+ virtual_addr_translation_on == 1'b0;
}
}
@@ -287,6 +352,7 @@
get_int_arg_value("+num_of_sub_program=", num_of_sub_program);
get_int_arg_value("+instr_cnt=", instr_cnt);
get_bool_arg_value("+no_ebreak=", no_ebreak);
+ get_bool_arg_value("+no_dret=", no_dret);
get_bool_arg_value("+no_wfi=", no_wfi);
get_bool_arg_value("+no_branch_jump=", no_branch_jump);
get_bool_arg_value("+no_load_store=", no_load_store);
@@ -297,17 +363,21 @@
get_bool_arg_value("+no_directed_instr=", no_directed_instr);
get_bool_arg_value("+no_fence=", no_fence);
get_bool_arg_value("+no_delegation=", no_delegation);
+ get_int_arg_value("+illegal_instr_ratio=", illegal_instr_ratio);
+ get_int_arg_value("+hint_instr_ratio=", hint_instr_ratio);
get_bool_arg_value("+enable_unaligned_load_store=", enable_unaligned_load_store);
- get_bool_arg_value("+enable_illegal_instruction=", enable_illegal_instruction);
- get_bool_arg_value("+enable_hint_instruction=", enable_hint_instruction);
get_bool_arg_value("+force_m_delegation=", force_m_delegation);
get_bool_arg_value("+force_s_delegation=", force_s_delegation);
get_bool_arg_value("+require_signature_addr=", require_signature_addr);
+ get_bool_arg_value("+randomize_csr=", randomize_csr);
if (this.require_signature_addr) begin
get_hex_arg_value("+signature_addr=", signature_addr);
end
get_bool_arg_value("+gen_debug_section=", gen_debug_section);
+ get_bool_arg_value("+bare_program_mode=", bare_program_mode);
get_int_arg_value("+num_debug_sub_program=", num_debug_sub_program);
+ get_bool_arg_value("+enable_ebreak_in_debug_rom=", enable_ebreak_in_debug_rom);
+ get_bool_arg_value("+set_dcsr_ebreak=", set_dcsr_ebreak);
if(inst.get_arg_value("+boot_mode=", boot_mode_opts)) begin
`uvm_info(get_full_name(), $sformatf(
"Got boot mode option - %0s", boot_mode_opts), UVM_LOW)
@@ -367,10 +437,8 @@
// Reserve below registers for special purpose instruction
// The other normal instruction cannot use them as destination register
virtual function void setup_default_reserved_regs();
- default_reserved_regs = {RA, // x1, return address
- SP, // x2, stack pointer (user stack)
- TP, // x4, thread pointer, used as kernel stack pointer
- T0 // x5, alternative link pointer
+ default_reserved_regs = {SP, // x2, stack pointer (user stack)
+ TP // x4, thread pointer, used as kernel stack pointer
};
endfunction
@@ -383,9 +451,9 @@
function void post_randomize();
// Setup the list all reserved registers
- reserved_regs = {default_reserved_regs, loop_regs};
+ reserved_regs = {default_reserved_regs, scratch_reg};
// Need to save all loop registers, and RA/T0
- min_stack_len_per_program = (max_nested_loop * 2 + 2) * (XLEN/8);
+ min_stack_len_per_program = 2 * (XLEN/8);
// Check if the setting is legal
check_setting();
endfunction
@@ -439,10 +507,13 @@
endfunction
// Build instruction template
- virtual function void build_instruction_template();
+ virtual function void build_instruction_template(bit skip_instr_exclusion = 0);
riscv_instr_name_t instr_name;
riscv_instr_name_t excluded_instr[$];
- get_excluded_instr(excluded_instr);
+ excluded_instr = {INVALID_INSTR};
+ if (!skip_instr_exclusion) begin
+ get_excluded_instr(excluded_instr);
+ end
instr_name = instr_name.first;
do begin
riscv_instr_base instr;
@@ -452,9 +523,6 @@
if (instr.group inside {supported_isa}) begin
`uvm_info(`gfn, $sformatf("Adding [%s] %s to the list",
instr.group.name(), instr.instr_name.name()), UVM_HIGH)
- if (instr.category inside {SHIFT, ARITHMETIC, LOGICAL, COMPARE}) begin
- basic_instr.push_back(instr_name);
- end
instr_group[instr.group].push_back(instr_name);
instr_category[instr.category].push_back(instr_name);
instr_template[instr_name] = instr;
@@ -463,14 +531,29 @@
instr_name = instr_name.next;
end
while (instr_name != instr_name.first);
+ endfunction
+
+ virtual function void build_instruction_list();
+ basic_instr = {instr_category[SHIFT], instr_category[ARITHMETIC],
+ instr_category[LOGICAL], instr_category[COMPARE]};
if (no_ebreak == 0) begin
basic_instr = {basic_instr, EBREAK};
+ foreach(riscv_instr_pkg::supported_isa[i]) begin
+ if (riscv_instr_pkg::supported_isa[i] inside {RV32C, RV64C, RV128C, RV32DC, RV32FC}) begin
+ basic_instr = {basic_instr, C_EBREAK};
+ break;
+ end
+ end
+ end
+ if (no_dret == 0) begin
+ basic_instr = {basic_instr, DRET};
end
if (no_fence == 0) begin
basic_instr = {basic_instr, instr_category[SYNCH]};
end
// TODO: Support CSR instruction in other mode
if ((no_csr_instr == 0) && (init_privileged_mode == MACHINE_MODE)) begin
+ `uvm_info(`gfn, $sformatf("Adding CSR instr, mode: %0s", init_privileged_mode.name()), UVM_LOW)
basic_instr = {basic_instr, instr_category[CSR]};
end
if (no_wfi == 0) begin
@@ -479,7 +562,6 @@
endfunction
virtual function void get_excluded_instr(ref riscv_instr_name_t excluded[$]);
- excluded = {excluded, INVALID_INSTR};
// Below instrutions will modify stack pointer, not allowed in normal instruction stream.
// It can be used in stack operation instruction stream.
excluded = {excluded, C_SWSP, C_SDSP, C_ADDI16SP};
@@ -487,7 +569,7 @@
excluded = {excluded, SFENCE_VMA};
end
if (no_fence) begin
- excluded = {excluded, FENCE, FENCEI, SFENCE_VMA};
+ excluded = {excluded, FENCE, FENCE_I, SFENCE_VMA};
end
// TODO: Support C_ADDI4SPN
excluded = {excluded, C_ADDI4SPN};
diff --git a/hw/vendor/lowrisc_ibex/vendor/google_riscv-dv/src/riscv_instr_pkg.sv b/hw/vendor/lowrisc_ibex/vendor/google_riscv-dv/src/riscv_instr_pkg.sv
index d76ae8a..187ffd2 100644
--- a/hw/vendor/lowrisc_ibex/vendor/google_riscv-dv/src/riscv_instr_pkg.sv
+++ b/hw/vendor/lowrisc_ibex/vendor/google_riscv-dv/src/riscv_instr_pkg.sv
@@ -14,17 +14,25 @@
* limitations under the License.
*/
+
package riscv_instr_pkg;
+ `include "dv_defines.svh"
+ `include "riscv_defines.svh"
+ `include "uvm_macros.svh"
+
import uvm_pkg::*;
import riscv_signature_pkg::*;
- `include "uvm_macros.svh"
- `include "dv_defines.svh"
- `include "riscv_defines.svh"
-
`define include_file(f) `include `"f`"
+ // Data section setting
+ typedef struct {
+ string name;
+ int unsigned size_in_bytes;
+ bit [2:0] xwr; // Excutable,Writable,Readale
+ } mem_region_t;
+
typedef enum bit [3:0] {
BARE = 4'b0000,
SV32 = 4'b0001,
@@ -114,7 +122,7 @@
AND,
NOP,
FENCE,
- FENCEI,
+ FENCE_I,
ECALL,
EBREAK,
CSRRW,
@@ -261,6 +269,7 @@
AMOMINU_D,
AMOMAXU_D,
// Supervisor instruction
+ DRET,
MRET,
URET,
SRET,
@@ -437,7 +446,7 @@
SIP = 'h144, // Supervisor interrupt pending
SATP = 'h180, // Supervisor address translation and protection
// Machine mode register
- MVENDORID = 'hF11, // Vendor ID
+ MVENDORID = 'hF11, // Vendor ID
MARCHID = 'hF12, // Architecture ID
MIMPID = 'hF13, // Implementation ID
MHARTID = 'hF14, // Hardware thread ID
@@ -535,6 +544,7 @@
MHPMCOUNTER29H = 'hB9D, // Upper 32 bits of HPMCOUNTER29, RV32I only
MHPMCOUNTER30H = 'hB9E, // Upper 32 bits of HPMCOUNTER30, RV32I only
MHPMCOUNTER31H = 'hB9F, // Upper 32 bits of HPMCOUNTER31, RV32I only
+ MCOUNTINHIBIT = 'h320, // Machine counter-inhibit register
MHPMEVENT3 = 'h323, // Machine performance-monitoring event selector
MHPMEVENT4 = 'h324, // Machine performance-monitoring event selector
MHPMEVENT5 = 'h325, // Machine performance-monitoring event selector
@@ -570,7 +580,8 @@
TDATA3 = 'h7A3, // Third Debug/Trace trigger data register
DCSR = 'h7B0, // Debug control and status register
DPC = 'h7B1, // Debug PC
- DSCRATCH = 'h7B2 // Debug scratch register
+ DSCRATCH0 = 'h7B2, // Debug scratch register
+ DSCRATCH1 = 'h7B3 // Debug scratch register
} privileged_reg_t;
typedef enum bit [5:0] {
@@ -589,7 +600,6 @@
} privileged_level_t;
typedef enum bit [1:0] {
- WIRI, // Reserved Writes Ignored, Reads Ignore Value
WPRI, // Reserved Writes Preserve Values, Reads Ignore Value
WLRL, // Write/Read Only Legal Values
WARL // Write Any Values, Reads Legal Values
@@ -675,11 +685,14 @@
MISA_EXT_Z
} misa_ext_t;
- `ifndef RISCV_CORE_SETTING
- `define RISCV_CORE_SETTING ../setting/riscv_core_setting.sv
- `endif
+ typedef enum bit [1:0] {
+ NO_HAZARD,
+ RAW_HAZARD,
+ WAR_HAZARD,
+ WAW_HAZARD
+ } hazard_e;
- `include_file(`RISCV_CORE_SETTING)
+ `include "riscv_core_setting.sv"
typedef bit [15:0] program_id_t;
@@ -688,10 +701,10 @@
parameter bit [XLEN - 1 : 0] SUM_BIT_MASK = 'h1 << 18;
parameter bit [XLEN - 1 : 0] MPP_BIT_MASK = 'h3 << 11;
- parameter IMM25_WIDTH = 25;
- parameter IMM12_WIDTH = 12;
- parameter INSTR_WIDTH = 32;
- parameter DATA_WIDTH = 32;
+ parameter IMM25_WIDTH = 25;
+ parameter IMM12_WIDTH = 12;
+ parameter INSTR_WIDTH = 32;
+ parameter DATA_WIDTH = 32;
// Parameters for output assembly program formatting
parameter MAX_INSTR_STR_LEN = 11;
@@ -772,10 +785,10 @@
instr.push_back($sformatf("srli sp, sp, %0d", XLEN - MAX_USED_VADDR_BITS));
end
end
- // Reserve space from kernel stack to save all 32 GPR
- instr.push_back($sformatf("1: addi sp, sp, -%0d", 32 * (XLEN/8)));
+ // Reserve space from kernel stack to save all 32 GPR except for x0
+ instr.push_back($sformatf("1: addi sp, sp, -%0d", 31 * (XLEN/8)));
// Push all GPRs to kernel stack
- for(int i = 0; i < 32; i++) begin
+ for(int i = 1; i < 32; i++) begin
instr.push_back($sformatf("%0s x%0d, %0d(sp)", store_instr, i, i * (XLEN/8)));
end
endfunction
@@ -787,11 +800,11 @@
ref string instr[$]);
string load_instr = (XLEN == 32) ? "lw" : "ld";
// Pop user mode GPRs from kernel stack
- for(int i = 0; i < 32; i++) begin
+ for(int i = 1; i < 32; i++) begin
instr.push_back($sformatf("%0s x%0d, %0d(sp)", load_instr, i, i * (XLEN/8)));
end
// Restore kernel stack pointer
- instr.push_back($sformatf("addi sp, sp, %0d", 32 * (XLEN/8)));
+ instr.push_back($sformatf("addi sp, sp, %0d", 31 * (XLEN/8)));
if (scratch inside {implemented_csr}) begin
// Move SP to TP
instr.push_back("add tp, sp, zero");
@@ -800,6 +813,12 @@
end
endfunction
+ riscv_reg_t all_gpr[] = {ZERO, RA, SP, GP, TP, T0, T1, T2, S0, S1, A0,
+ A1, A2, A3, A4, A5, A6, A7, S2, S3, S4, S5, S6,
+ S7, S8, S9, S10, S11, T3, T4, T5, T6};
+
+ riscv_reg_t compressed_gpr[] = {S0, S1, A0, A1, A2, A3, A4, A5};
+
`include "riscv_instr_base.sv"
`include "riscv_instr_gen_config.sv"
`include "riscv_illegal_instr.sv"
@@ -820,9 +839,8 @@
`include "riscv_amo_instr_lib.sv"
`include "riscv_instr_sequence.sv"
`include "riscv_asm_program_gen.sv"
-
- `ifdef RISCV_DV_EXT_FILE_LIST
- `include_file(`RISCV_DV_EXT_FILE_LIST)
- `endif
+ `include "riscv_instr_cov_item.sv"
+ `include "riscv_instr_cover_group.sv"
+ `include "user_extension.svh"
endpackage
diff --git a/hw/vendor/lowrisc_ibex/vendor/google_riscv-dv/src/riscv_instr_sequence.sv b/hw/vendor/lowrisc_ibex/vendor/google_riscv-dv/src/riscv_instr_sequence.sv
index b29be22..1e22677 100644
--- a/hw/vendor/lowrisc_ibex/vendor/google_riscv-dv/src/riscv_instr_sequence.sv
+++ b/hw/vendor/lowrisc_ibex/vendor/google_riscv-dv/src/riscv_instr_sequence.sv
@@ -78,7 +78,8 @@
instr_stream.instr_list.size()), UVM_LOW)
// Do not generate load/store instruction here
// The load/store instruction will be inserted as directed instruction stream
- instr_stream.gen_instr(.no_branch(no_branch), .no_load_store(1'b1));
+ instr_stream.gen_instr(.no_branch(no_branch), .no_load_store(1'b1),
+ .is_debug_program(is_debug_program));
if(!is_main_program) begin
gen_stack_enter_instr();
gen_stack_exit_instr();
@@ -132,7 +133,9 @@
virtual function void post_process_instr();
int i;
int label_idx;
- int branch_target[string] = '{default: 0};
+ int branch_cnt;
+ int unsigned branch_idx[];
+ int branch_target[int] = '{default: 0};
// Insert directed instructions, it's randomly mixed with the random instruction stream.
foreach (directed_instr[i]) begin
instr_stream.insert_instr_stream(directed_instr[i].instr_list);
@@ -169,6 +172,11 @@
end
end
// Generate branch target
+ branch_idx = new[30];
+ `DV_CHECK_STD_RANDOMIZE_WITH_FATAL(branch_idx,
+ foreach(branch_idx[i]) {
+ branch_idx[i] inside {[1:cfg.max_branch_step]};
+ })
while(i < instr_stream.instr_list.size()) begin
if((instr_stream.instr_list[i].category == BRANCH) &&
(!instr_stream.instr_list[i].branch_assigned) &&
@@ -179,11 +187,15 @@
// reserved loop registers
int branch_target_label;
int branch_byte_offset;
- `DV_CHECK_STD_RANDOMIZE_WITH_FATAL(branch_target_label,
- branch_target_label >= instr_stream.instr_list[i].idx+1;
- branch_target_label <= label_idx-1;
- branch_target_label <= instr_stream.instr_list[i].idx+cfg.max_branch_step;,
- "Cannot randomize branch_target_label")
+ branch_target_label = instr_stream.instr_list[i].idx + branch_idx[branch_cnt];
+ if (branch_target_label >= label_idx) begin
+ branch_target_label = label_idx-1;
+ end
+ branch_cnt++;
+ if (branch_cnt == branch_idx.size()) begin
+ branch_cnt = 0;
+ branch_idx.shuffle();
+ end
`uvm_info(get_full_name(),
$sformatf("Processing branch instruction[%0d]:%0s # %0d -> %0d",
i, instr_stream.instr_list[i].convert2asm(),
@@ -230,14 +242,11 @@
jump_instr.cfg = cfg;
jump_instr.label = label_name;
jump_instr.idx = idx;
- `DV_CHECK_RANDOMIZE_WITH_FATAL(jump_instr,
- if(is_main_program) {
- jump_instr.jump.rd == RA;
- },
- "Cannot randomize jump_instr")
+ jump_instr.use_jalr = is_main_program;
+ `DV_CHECK_RANDOMIZE_FATAL(jump_instr)
instr_stream.insert_instr_stream(jump_instr.instr_list);
`uvm_info(get_full_name(), $sformatf("%0s -> %0s...done",
- jump_instr.jump.instr_name.name(), label_name), UVM_LOW)
+ jump_instr.jump.instr_name.name(), target_label), UVM_LOW)
endfunction
// Convert the instruction stream to the string format.
@@ -266,6 +275,7 @@
str = {prefix, instr_stream.instr_list[i].convert2asm()};
instr_string_list.push_back(str);
end
+ insert_illegal_hint_instr();
prefix = format_string($sformatf("%0d:", i), LABEL_STR_LEN);
if(!is_main_program) begin
str = {prefix, "ret"};
@@ -273,53 +283,36 @@
end
endfunction
- // Convert the instruction stream to binary format
- function void generate_binary_stream(ref string binary[$]);
- string instr_bin;
- string remaining_bin;
+ function void insert_illegal_hint_instr();
+ int bin_instr_cnt;
+ int idx;
string str;
- illegal_instr.cfg = cfg;
- foreach (instr_stream.instr_list[i]) begin
- if (instr_stream.instr_list[i].is_illegal_instr) begin
- // Replace the original instruction with illegal instruction binary
+ illegal_instr.init(cfg);
+ bin_instr_cnt = instr_cnt * cfg.illegal_instr_ratio / 1000;
+ if (bin_instr_cnt >= 0) begin
+ `uvm_info(`gfn, $sformatf("Injecting %0d illegal instructions, ratio %0d/100",
+ bin_instr_cnt, cfg.illegal_instr_ratio), UVM_LOW)
+ repeat (bin_instr_cnt) begin
`DV_CHECK_RANDOMIZE_WITH_FATAL(illegal_instr,
- exception != kHintInstr;
- compressed == instr_stream.instr_list[i].is_compressed;)
- str = illegal_instr.get_bin_str();
- `uvm_info(`gfn, $sformatf("Inject %0s [%0d] %0s replaced with %0s",
- illegal_instr.exception.name(), i,
- instr_stream.instr_list[i].convert2bin() ,str), UVM_HIGH)
- end else if (instr_stream.instr_list[i].is_hint_instr) begin
- // Replace the original instruction with HINT instruction binary
- `DV_CHECK_RANDOMIZE_WITH_FATAL(illegal_instr,
- exception == kHintInstr;
- compressed == instr_stream.instr_list[i].is_compressed;)
- str = illegal_instr.get_bin_str();
- `uvm_info(`gfn, $sformatf("Inject %0s [%0d] %0s replaced with %0s",
- illegal_instr.exception.name(), i,
- instr_stream.instr_list[i].convert2bin() ,str), UVM_HIGH)
- end else begin
- str = instr_stream.instr_list[i].convert2bin();
+ exception != kHintInstr;)
+ str = {indent, $sformatf(".4byte 0x%s # %0s",
+ illegal_instr.get_bin_str(), illegal_instr.exception.name())};
+ idx = $urandom_range(0, instr_string_list.size());
+ instr_string_list.insert(idx, str);
end
- instr_bin = {str, remaining_bin};
- // Handle various instruction alignment
- if (instr_bin.len() == 8) begin
- binary.push_back({"0x", instr_bin});
- remaining_bin = "";
- end else if (instr_bin.len() == 12) begin
- binary.push_back({"0x", instr_bin.substr(4, 11)});
- remaining_bin = instr_bin.substr(0, 3);
- end else if (instr_bin.len() == 4) begin
- remaining_bin = instr_bin;
- end else begin
- `uvm_fatal(`gfn, $sformatf("Unexpected binary length :%0d", instr_bin.len()))
- end
- `uvm_info("BIN", $sformatf("%0s : %0s", instr_stream.instr_list[i].convert2bin(),
- instr_stream.instr_list[i].convert2asm()), UVM_HIGH)
end
- // Attach a C_NOP(0x0001) to make the last entry 32b
- if (remaining_bin != "") begin
- binary.push_back({"0x0001", remaining_bin});
+ bin_instr_cnt = instr_cnt * cfg.hint_instr_ratio / 1000;
+ if (bin_instr_cnt >= 0) begin
+ `uvm_info(`gfn, $sformatf("Injecting %0d HINT instructions, ratio %0d/100",
+ bin_instr_cnt, cfg.illegal_instr_ratio), UVM_LOW)
+ repeat (bin_instr_cnt) begin
+ `DV_CHECK_RANDOMIZE_WITH_FATAL(illegal_instr,
+ exception == kHintInstr;)
+ str = {indent, $sformatf(".2byte 0x%s # %0s",
+ illegal_instr.get_bin_str(), illegal_instr.exception.name())};
+ idx = $urandom_range(0, instr_string_list.size());
+ instr_string_list.insert(idx, str);
+ end
end
endfunction
diff --git a/hw/vendor/lowrisc_ibex/vendor/google_riscv-dv/src/riscv_instr_stream.sv b/hw/vendor/lowrisc_ibex/vendor/google_riscv-dv/src/riscv_instr_stream.sv
index 3441c7b..a412ee0 100644
--- a/hw/vendor/lowrisc_ibex/vendor/google_riscv-dv/src/riscv_instr_stream.sv
+++ b/hw/vendor/lowrisc_ibex/vendor/google_riscv-dv/src/riscv_instr_stream.sv
@@ -20,11 +20,14 @@
// instruction, mix two instruction streams etc.
class riscv_instr_stream extends uvm_object;
- rand riscv_instr_base instr_list[$];
+ riscv_instr_base instr_list[$];
int unsigned instr_cnt;
string label = "";
// User can specify a small group of available registers to generate various hazard condition
rand riscv_reg_t avail_regs[];
+ // Some additional reserved registers that should not be used as rd register
+ // by this instruction stream
+ riscv_reg_t reserved_rd[];
`uvm_object_utils(riscv_instr_stream)
`uvm_object_new
@@ -95,9 +98,17 @@
if(replace) begin
new_instr[0].label = instr_list[idx].label;
new_instr[0].has_label = instr_list[idx].has_label;
- instr_list = {instr_list[0:idx-1], new_instr, instr_list[idx+1:current_instr_cnt-1]};
+ if (idx == 0) begin
+ instr_list = {new_instr, instr_list[idx+1:current_instr_cnt-1]};
+ end else begin
+ instr_list = {instr_list[0:idx-1], new_instr, instr_list[idx+1:current_instr_cnt-1]};
+ end
end else begin
- instr_list = {instr_list[0:idx-1], new_instr, instr_list[idx:current_instr_cnt-1]};
+ if (idx == 0) begin
+ instr_list = {new_instr, instr_list[idx:current_instr_cnt-1]};
+ end else begin
+ instr_list = {instr_list[0:idx-1], new_instr, instr_list[idx:current_instr_cnt-1]};
+ end
end
endfunction
@@ -112,10 +123,10 @@
`DV_CHECK_STD_RANDOMIZE_WITH_FATAL(insert_instr_position,
foreach(insert_instr_position[i]) {
insert_instr_position[i] inside {[0:current_instr_cnt-1]};
- if(i > 0) {
- insert_instr_position[i] >= insert_instr_position[i-1];
- }
})
+ if (insert_instr_position.size() > 0) begin
+ insert_instr_position.sort();
+ end
if(contained) begin
insert_instr_position[0] = 0;
if(new_instr_cnt > 1)
@@ -144,23 +155,9 @@
class riscv_rand_instr_stream extends riscv_instr_stream;
riscv_instr_gen_config cfg;
- bit access_u_mode_mem = 1'b1;
- int max_load_store_offset;
- int max_data_page_id;
+ bit kernel_mode;
riscv_instr_name_t allowed_instr[$];
- // Some additional reserved registers that should not be used as rd register
- // by this instruction stream
- riscv_reg_t reserved_rd[];
-
- constraint avoid_reserved_rd_c {
- if(reserved_rd.size() > 0) {
- foreach(instr_list[i]) {
- !(instr_list[i].rd inside {reserved_rd});
- }
- }
- }
-
`uvm_object_utils(riscv_rand_instr_stream)
`uvm_object_new
@@ -172,17 +169,7 @@
end
endfunction
- function void pre_randomize();
- if(access_u_mode_mem) begin
- max_load_store_offset = riscv_instr_pkg::data_page_size;
- max_data_page_id = riscv_instr_pkg::num_of_data_pages;
- end else begin
- max_load_store_offset = riscv_instr_pkg::kernel_data_page_size;
- max_data_page_id = riscv_instr_pkg::num_of_kernel_data_pages;
- end
- endfunction
-
- virtual function setup_allowed_instr(bit no_branch = 1'b0, bit no_load_store = 1'b1);
+ virtual function void setup_allowed_instr(bit no_branch = 1'b0, bit no_load_store = 1'b1);
allowed_instr = cfg.basic_instr;
if (no_branch == 0) begin
allowed_instr = {allowed_instr, cfg.instr_category[BRANCH]};
@@ -192,10 +179,11 @@
end
endfunction
- virtual function void gen_instr(bit no_branch = 1'b0, bit no_load_store = 1'b1);
+ virtual function void gen_instr(bit no_branch = 1'b0, bit no_load_store = 1'b1,
+ bit is_debug_program = 1'b0);
setup_allowed_instr(no_branch, no_load_store);
foreach(instr_list[i]) begin
- randomize_instr(instr_list[i]);
+ randomize_instr(instr_list[i], is_debug_program);
end
// Do not allow branch instruction as the last instruction because there's no
// forward branch target
@@ -206,21 +194,30 @@
endfunction
function void randomize_instr(riscv_instr_base instr,
+ bit is_in_debug = 1'b0,
bit skip_rs1 = 1'b0,
bit skip_rs2 = 1'b0,
bit skip_rd = 1'b0,
bit skip_imm = 1'b0,
bit skip_csr = 1'b0);
riscv_instr_name_t instr_name;
- `DV_CHECK_STD_RANDOMIZE_WITH_FATAL(instr_name,
+ // if set_dcsr_ebreak is set, we do not want to generate any ebreak
+ // instructions inside the debug_rom
+ if (!cfg.enable_ebreak_in_debug_rom && is_in_debug) begin
+ `DV_CHECK_STD_RANDOMIZE_WITH_FATAL(instr_name,
+ instr_name inside {allowed_instr};
+ !(instr_name inside {EBREAK, C_EBREAK});)
+ end else begin
+ `DV_CHECK_STD_RANDOMIZE_WITH_FATAL(instr_name,
instr_name inside {allowed_instr};)
+ end
instr.copy_base_instr(cfg.instr_template[instr_name]);
`uvm_info(`gfn, $sformatf("%s: rs1:%0d, rs2:%0d, rd:%0d, imm:%0d",
instr.instr_name.name(),
instr.has_rs1,
instr.has_rs2,
instr.has_rd,
- instr.has_imm), UVM_HIGH)
+ instr.has_imm), UVM_FULL)
if (instr.has_imm && !skip_imm) begin
instr.gen_rand_imm();
end
diff --git a/hw/vendor/lowrisc_ibex/vendor/google_riscv-dv/src/riscv_load_store_instr_lib.sv b/hw/vendor/lowrisc_ibex/vendor/google_riscv-dv/src/riscv_load_store_instr_lib.sv
index f019616..4c570fc 100644
--- a/hw/vendor/lowrisc_ibex/vendor/google_riscv-dv/src/riscv_load_store_instr_lib.sv
+++ b/hw/vendor/lowrisc_ibex/vendor/google_riscv-dv/src/riscv_load_store_instr_lib.sv
@@ -16,70 +16,85 @@
// Base class for all load/store instruction stream
-class riscv_load_store_base_instr_stream extends riscv_directed_instr_stream;
+class riscv_load_store_base_instr_stream extends riscv_mem_access_stream;
+
+ typedef enum bit [1:0] {
+ NARROW,
+ HIGH,
+ MEDIUM,
+ SPARSE
+ } locality_e;
rand int unsigned num_load_store;
rand int unsigned num_mixed_instr;
rand int base;
- rand int offset[];
- rand int addr[];
+ int offset[];
+ int addr[];
rand int unsigned data_page_id;
rand riscv_reg_t rs1_reg;
+ rand locality_e locality;
+ rand int max_load_store_offset;
`uvm_object_utils(riscv_load_store_base_instr_stream)
- constraint size_c {
- offset.size() == num_load_store;
- addr.size() == num_load_store;
- }
-
constraint rs1_c {
!(rs1_reg inside {cfg.reserved_regs, reserved_rd, ZERO});
}
constraint addr_c {
+ solve data_page_id before max_load_store_offset;
+ solve max_load_store_offset before base;
data_page_id < max_data_page_id;
- base inside {[0 : max_load_store_offset-1]};
- foreach(offset[i]) {
- addr[i] == base + offset[i];
- // Make sure address is still valid
- addr[i] inside {[0 : max_load_store_offset - 1]};
- offset[i] inside {[-2048:2047]};
+ foreach (data_page[i]) {
+ if (i == data_page_id) {
+ max_load_store_offset == data_page[i].size_in_bytes;
+ }
}
+ base inside {[0 : max_load_store_offset-1]};
}
function new(string name = "");
super.new(name);
- instr_list.rand_mode(0);
+ endfunction
+
+ virtual function void randomize_offset();
+ int offset_, addr_;
+ offset = new[num_load_store];
+ addr = new[num_load_store];
+ for (int i=0; i<num_load_store; i++) begin
+ if (!std::randomize(offset_, addr_) with {
+ // Locality
+ if (locality == NARROW) {
+ soft offset_ inside {[-16:16]};
+ } else if (locality == HIGH) {
+ soft offset_ inside {[-64:64]};
+ } else if (locality == MEDIUM) {
+ soft offset_ inside {[-256:256]};
+ } else if (locality == SPARSE) {
+ soft offset_ inside {[-2048:2047]};
+ }
+ addr_ == base + offset_;
+ addr_ inside {[0 : max_load_store_offset - 1]};
+ }) begin
+ `uvm_fatal(`gfn, "Cannot randomize load/store offset")
+ end
+ offset[i] = offset_;
+ addr[i] = addr_;
+ end
endfunction
function void post_randomize();
+ randomize_offset();
// rs1 cannot be modified by other instructions
if(!(rs1_reg inside {reserved_rd})) begin
reserved_rd = {reserved_rd, rs1_reg};
end
gen_load_store_instr();
- add_mixed_instr();
- add_rs1_init_la_instr();
+ add_mixed_instr(num_mixed_instr);
+ add_rs1_init_la_instr(rs1_reg, data_page_id, base);
super.post_randomize();
endfunction
- // Use "la" instruction to initialize the base regiseter
- virtual function void add_rs1_init_la_instr();
- riscv_pseudo_instr la_instr;
- la_instr = riscv_pseudo_instr::type_id::create("la_instr");
- `DV_CHECK_RANDOMIZE_WITH_FATAL(la_instr,
- pseudo_instr_name == LA;
- rd == rs1_reg;,
- "Cannot randomize la_instr")
- if(access_u_mode_mem) begin
- la_instr.imm_str = $sformatf("data_page_%0d+%0d", data_page_id, base);
- end else begin
- la_instr.imm_str = $sformatf("kernel_data_page_%0d+%0d", data_page_id, base);
- end
- instr_list.push_front(la_instr);
- endfunction
-
// Generate each load/store instruction
virtual function void gen_load_store_instr();
bit enable_compressed_load_store;
@@ -105,7 +120,7 @@
allowed_instr = {LH, LHU, SH, allowed_instr};
end
if (!cfg.enable_unaligned_load_store) begin
- if (addr[i][1:0] == 2'b00) begin
+ if (addr[i] % 4 == 0) begin
allowed_instr = {LW, SW, allowed_instr};
if((offset[i] inside {[0:127]}) && (offset[i] % 4 == 0) &&
(RV32C inside {riscv_instr_pkg::supported_isa}) &&
@@ -113,7 +128,7 @@
allowed_instr = {C_LW, C_SW, allowed_instr};
end
end
- if ((XLEN >= 64) && (addr[i][2:0] == 3'b000)) begin
+ if ((XLEN >= 64) && (addr[i] % 8 == 0)) begin
allowed_instr = {LWU, LD, SD, allowed_instr};
if((offset[i] inside {[0:255]}) && (offset[i] % 8 == 0) &&
(RV64C inside {riscv_instr_pkg::supported_isa} &&
@@ -145,17 +160,6 @@
end
endfunction
- // Insert some other instructions to mix with load/store instruction
- virtual function void add_mixed_instr();
- riscv_instr_base instr;
- setup_allowed_instr(1, 1);
- for(int i = 0; i < num_mixed_instr; i ++) begin
- instr = riscv_instr_base::type_id::create("instr");
- randomize_instr(instr);
- insert_instr(instr);
- end
- endfunction
-
endclass
// A single load/store instruction
@@ -253,27 +257,11 @@
addr[i] = temp_addr;
end
endfunction
-
-endclass
-
-// Back-to-back access to the same cache line
-class riscv_cache_line_stress_instr_stream extends riscv_load_store_stress_instr_stream;
-
- constraint same_cache_line_c {
- base % riscv_instr_pkg::dcache_line_size_in_bytes == 0;
- foreach(offset[i]) {
- offset[i] inside {[0 : riscv_instr_pkg::dcache_line_size_in_bytes-1]};
- }
- }
-
- `uvm_object_utils(riscv_cache_line_stress_instr_stream)
- `uvm_object_new
-
endclass
// Back to back access to multiple data pages
// This is useful to test data TLB switch and replacement
-class riscv_multi_page_load_store_instr_stream extends riscv_directed_instr_stream;
+class riscv_multi_page_load_store_instr_stream extends riscv_mem_access_stream;
riscv_load_store_stress_instr_stream load_store_instr_stream[];
rand int unsigned num_of_instr_stream;
@@ -287,13 +275,17 @@
data_page_id.size() == num_of_instr_stream;
rs1_reg.size() == num_of_instr_stream;
unique {rs1_reg};
- unique {data_page_id};
- num_of_instr_stream inside {[1 : max_data_page_id]};
foreach(rs1_reg[i]) {
!(rs1_reg[i] inside {cfg.reserved_regs, ZERO});
}
}
+ constraint page_c {
+ solve num_of_instr_stream before data_page_id;
+ num_of_instr_stream inside {[1 : max_data_page_id]};
+ unique {data_page_id};
+ }
+
// Avoid accessing a large number of pages because we may run out of registers for rs1
// Each page access needs a reserved register as the base address of load/store instruction
constraint reasonable_c {
@@ -334,3 +326,20 @@
endfunction
endclass
+
+// Access the different locations of the same memory regions
+class riscv_mem_region_stress_test extends riscv_multi_page_load_store_instr_stream;
+
+ `uvm_object_utils(riscv_mem_region_stress_test)
+ `uvm_object_new
+
+ constraint page_c {
+ num_of_instr_stream inside {[2:5]};
+ foreach (data_page_id[i]) {
+ if (i > 0) {
+ data_page_id[i] == data_page_id[i-1];
+ }
+ }
+ }
+
+endclass
diff --git a/hw/vendor/lowrisc_ibex/vendor/google_riscv-dv/src/riscv_loop_instr.sv b/hw/vendor/lowrisc_ibex/vendor/google_riscv-dv/src/riscv_loop_instr.sv
index b0fe8e1..ea173de 100644
--- a/hw/vendor/lowrisc_ibex/vendor/google_riscv-dv/src/riscv_loop_instr.sv
+++ b/hw/vendor/lowrisc_ibex/vendor/google_riscv-dv/src/riscv_loop_instr.sv
@@ -25,8 +25,8 @@
rand int loop_step_val[];
rand int loop_limit_val[];
rand bit [2:0] num_of_nested_loop;
- rand riscv_instr_name_t branch_type[];
rand int num_of_instr_in_loop;
+ rand riscv_instr_name_t branch_type[];
riscv_instr_base loop_init_instr[];
riscv_instr_base loop_update_instr[];
riscv_instr_base loop_branch_instr[];
@@ -34,23 +34,37 @@
// Aggregated loop instruction stream
riscv_instr_base loop_instr[];
- constraint loop_c {
+ constraint legal_loop_regs_c {
solve num_of_nested_loop before loop_cnt_reg;
solve num_of_nested_loop before loop_limit_reg;
+ foreach (loop_cnt_reg[i]) {
+ loop_cnt_reg[i] != ZERO;
+ foreach (cfg.default_reserved_regs[j]) {
+ loop_cnt_reg[i] != cfg.default_reserved_regs[j];
+ }
+ }
+ foreach (loop_limit_reg[i]) {
+ loop_limit_reg[i] != ZERO;
+ foreach (cfg.default_reserved_regs[j]) {
+ loop_limit_reg[i] != cfg.default_reserved_regs[j];
+ }
+ }
+ unique {loop_cnt_reg, loop_limit_reg};
+ loop_cnt_reg.size() == num_of_nested_loop;
+ loop_limit_reg.size() == num_of_nested_loop;
+ }
+
+ constraint loop_c {
solve num_of_nested_loop before loop_init_val;
solve num_of_nested_loop before loop_step_val;
solve num_of_nested_loop before loop_limit_val;
num_of_instr_in_loop inside {[1:200]};
- num_of_nested_loop inside {[1:cfg.max_nested_loop]};
- loop_cnt_reg.size() == num_of_nested_loop;
- loop_limit_reg.size() == num_of_nested_loop;
+ num_of_nested_loop inside {[1:2]};
loop_init_val.size() == num_of_nested_loop;
loop_step_val.size() == num_of_nested_loop;
loop_limit_val.size() == num_of_nested_loop;
branch_type.size() == num_of_nested_loop;
foreach(loop_init_val[i]) {
- loop_cnt_reg[i] inside {cfg.loop_regs};
- loop_limit_reg[i] inside {cfg.loop_regs};
loop_init_val[i] inside {[-10:10]};
loop_limit_val[i] inside {[-20:20]};
loop_step_val[i] inside {[-10:10]};
@@ -74,13 +88,13 @@
branch_type[i] inside {BGEU, BNE, BGE, BEQ};
}
}
- unique {loop_cnt_reg, loop_limit_reg};
}
`uvm_object_utils(riscv_loop_instr)
`uvm_object_new
function void post_randomize();
+ reserved_rd = {loop_cnt_reg, loop_limit_reg};
// Generate instructions that mixed with the loop instructions
initialize_instr_list(num_of_instr_in_loop);
gen_instr(1'b1);
@@ -113,6 +127,7 @@
// Branch target instruction, can be anything
loop_branch_target_instr[i] = riscv_rand_instr::type_id::create("loop_branch_target_instr");
loop_branch_target_instr[i].cfg = cfg;
+ loop_branch_target_instr[i].reserved_rd = reserved_rd;
`DV_CHECK_RANDOMIZE_WITH_FATAL(loop_branch_target_instr[i],
!(category inside {LOAD, STORE, BRANCH, JUMP});,
"Cannot randomize branch target instruction")
diff --git a/hw/vendor/lowrisc_ibex/vendor/google_riscv-dv/src/riscv_page_table.sv b/hw/vendor/lowrisc_ibex/vendor/google_riscv-dv/src/riscv_page_table.sv
index 1f5d300..a7e7150 100644
--- a/hw/vendor/lowrisc_ibex/vendor/google_riscv-dv/src/riscv_page_table.sv
+++ b/hw/vendor/lowrisc_ibex/vendor/google_riscv-dv/src/riscv_page_table.sv
@@ -49,10 +49,9 @@
string str;
this.gen_page_table_binary();
// Align the page table to 4K boundary
- str = ".align 12";
- instr.push_back(str);
- str = $sformatf("%0s:", get_name());
- instr.push_back(str);
+ instr = {instr,
+ ".align 12",
+ $sformatf("%0s:", get_name())};
foreach(pte_binary[i]) begin
if (i % 8 == 0) begin
if (XLEN == 64) begin
diff --git a/hw/vendor/lowrisc_ibex/vendor/google_riscv-dv/src/riscv_page_table_list.sv b/hw/vendor/lowrisc_ibex/vendor/google_riscv-dv/src/riscv_page_table_list.sv
index 4a7b35d..1ce35ed 100644
--- a/hw/vendor/lowrisc_ibex/vendor/google_riscv-dv/src/riscv_page_table_list.sv
+++ b/hw/vendor/lowrisc_ibex/vendor/google_riscv-dv/src/riscv_page_table_list.sv
@@ -353,7 +353,8 @@
// Fix kernel leaf PTE
instr.push_back("fix_kernel_leaf_pte:");
// - Load the starting virtual address of the kernel space
- instr.push_back($sformatf("la x%0d, _kernel_start", tmp_reg));
+ instr.push_back($sformatf("la x%0d, _kernel_instr_start", tmp_reg));
+ // TODO: Fix kernel instruction/data pages separatedly
instr.push_back($sformatf("slli x%0d, x%0d, %0d", tmp_reg, tmp_reg,
XLEN - MAX_USED_VADDR_BITS));
instr.push_back($sformatf("srli x%0d, x%0d, %0d", tmp_reg, tmp_reg,
@@ -460,14 +461,14 @@
end
end
end
- // ---------------------------------------
- // Set the kernel page u bit to 0
- // ---------------------------------------
- // Load the start and end address of the kernel space
+ // ---------------------------------------------------------------------------
+ // Set the kernel page u bit to 0 for supervisor mode instruction/data pages
+ // ---------------------------------------------------------------------------
if (cfg.support_supervisor_mode) begin
instr = {instr,
- "la x20, _kernel_start",
- "la x21, _kernel_end",
+ // Process kernel instruction pages
+ "la x20, _kernel_instr_start",
+ "la x21, _kernel_instr_end",
// Get the VPN of the physical address
$sformatf("slli x20, x20, %0d", XLEN - MAX_USED_VADDR_BITS),
$sformatf("srli x20, x20, %0d", XLEN - MAX_USED_VADDR_BITS + 12),
@@ -480,7 +481,7 @@
"add x20, x22, x20",
"add x21, x22, x21",
$sformatf("li x22, 0x%0x", ubit_mask),
- "process_kernel_pte:",
+ "1:",
// Load the PTE from the memory
$sformatf("l%0s x23, 0(x20)", load_store_unit),
// Unset U bit
@@ -490,7 +491,30 @@
// Move to the next PTE
$sformatf("addi x20, x20, %0d", XLEN/8),
// If not the end of the kernel space, process the next PTE
- "ble x20, x21, process_kernel_pte"};
+ "ble x20, x21, 1b",
+ // Process kernel data pages
+ "la x20, _kernel_data_start",
+ // Get the VPN of the physical address
+ $sformatf("slli x20, x20, %0d", XLEN - MAX_USED_VADDR_BITS),
+ $sformatf("srli x20, x20, %0d", XLEN - MAX_USED_VADDR_BITS + 12),
+ $sformatf("slli x20, x20, %0d", $clog2(XLEN)),
+ // Starting from the first 4KB leaf page table
+ $sformatf("la x22, page_table_%0d", get_1st_4k_table_id()),
+ "add x20, x22, x20",
+ $sformatf("li x22, 0x%0x", ubit_mask),
+ // Assume 20 PTEs for kernel data pages
+ $sformatf("addi x20, x20, %0d", 20 * XLEN/8),
+ "2:",
+ // Load the PTE from the memory
+ $sformatf("l%0s x23, 0(x20)", load_store_unit),
+ // Unset U bit
+ "and x23, x23, x22",
+ // Save PTE back to memory
+ $sformatf("l%0s x23, 0(x20)", load_store_unit),
+ // Move to the next PTE
+ $sformatf("addi x20, x20, %0d", XLEN/8),
+ // If not the end of the kernel space, process the next PTE
+ "ble x20, x21, 2b"};
end
endfunction
diff --git a/hw/vendor/lowrisc_ibex/vendor/google_riscv-dv/src/riscv_privil_reg.sv b/hw/vendor/lowrisc_ibex/vendor/google_riscv-dv/src/riscv_privil_reg.sv
index 4ae206a..423865a 100644
--- a/hw/vendor/lowrisc_ibex/vendor/google_riscv-dv/src/riscv_privil_reg.sv
+++ b/hw/vendor/lowrisc_ibex/vendor/google_riscv-dv/src/riscv_privil_reg.sv
@@ -31,29 +31,29 @@
MISA: begin
privil_level = M_LEVEL;
add_field("WARL0", 26, WARL);
- add_field("WIRI", XLEN-28, WIRI);
+ add_field("WLRL", XLEN-28, WLRL);
add_field("MXL", 2, WARL);
end
// Machine Vendor ID Register
MVENDORID: begin
privil_level = M_LEVEL;
- add_field("OFFSET", 7, WIRI);
- add_field("BANK", XLEN-7, WIRI);
+ add_field("OFFSET", 7, WPRI);
+ add_field("BANK", XLEN-7, WPRI);
end
// Machine Architecture ID Register
MARCHID: begin
privil_level = M_LEVEL;
- add_field("ARCHITECTURE_ID", XLEN, WIRI);
+ add_field("ARCHITECTURE_ID", XLEN, WPRI);
end
// Machine Implementation ID Register
MIMPID: begin
privil_level = M_LEVEL;
- add_field("IMPLEMENTATION", XLEN, WIRI);
+ add_field("IMPLEMENTATION", XLEN, WPRI);
end
// Hart ID Register
MHARTID: begin
privil_level = M_LEVEL;
- add_field("HART_ID", XLEN, WIRI);
+ add_field("HART_ID", XLEN, WPRI);
end
// Machine Status Register
MSTATUS: begin
@@ -136,7 +136,7 @@
privil_level = M_LEVEL;
add_field("USIP", 1, WARL);
add_field("SSIP", 1, WARL);
- add_field("WIRI0", 1, WIRI);
+ add_field("WPRI0", 1, WPRI);
add_field("MSIP", 1, WARL);
add_field("UTIP", 1, WARL);
add_field("STIP", 1, WARL);
@@ -144,9 +144,9 @@
add_field("MTIP", 1, WARL);
add_field("UEIP", 1, WARL);
add_field("SEIP", 1, WARL);
- add_field("WIRI2", 1, WIRI);
+ add_field("WPRI2", 1, WPRI);
add_field("MEIP", 1, WARL);
- add_field("WIRI3", XLEN - 12, WIRI);
+ add_field("WPRI3", XLEN - 12, WPRI);
end
// Machine interrupt-enable register
MIE: begin
@@ -168,27 +168,27 @@
// Cycle Count Register
MCYCLE: begin
privil_level = M_LEVEL;
- add_field("MCYCLE", 64, WIRI);
+ add_field("MCYCLE", 64, WPRI);
end
// Instruction Count Register
MINSTRET: begin
privil_level = M_LEVEL;
- add_field("MINSTRET", 64, WIRI);
+ add_field("MINSTRET", 64, WPRI);
end
// Cycle Count Register - RV32I only
MCYCLEH: begin
privil_level = M_LEVEL;
- add_field("MCYCLEH", 32, WIRI);
+ add_field("MCYCLEH", 32, WPRI);
end
// Instruction Count Register - RV32I only
MINSTRETH: begin
privil_level = M_LEVEL;
- add_field("MINSTRETH", 32, WIRI);
+ add_field("MINSTRETH", 32, WPRI);
end
// Hardware Performance Monitor Counters
[MHPMCOUNTER3:MHPMCOUNTER31]: begin
privil_level = M_LEVEL;
- add_field($sformatf("%s", reg_name.name()), XLEN, WIRI);
+ add_field($sformatf("%s", reg_name.name()), XLEN, WARL);
end
// Hardware Performance Monitor Events
[MHPMEVENT3:MHPMEVENT31]: begin
@@ -201,7 +201,7 @@
`uvm_fatal(get_full_name(), $sformatf("Register %s is only in RV32I", reg_name.name()))
end
privil_level = M_LEVEL;
- add_field($sformatf("%s", reg_name.name()), 32, WIRI);
+ add_field($sformatf("%s", reg_name.name()), 32, WARL);
end
// Machine Counter Enable Register
MCOUNTEREN: begin
@@ -324,7 +324,7 @@
privil_level = M_LEVEL;
if(XLEN==64) begin
add_field("ADDRESS", 54, WARL);
- add_field("WIRI", 10, WIRI);
+ add_field("WARL", 10, WARL);
end else begin
add_field("ADDRESS", 32, WARL);
end
@@ -560,16 +560,6 @@
default:
`uvm_fatal(get_full_name(), $sformatf("reg %0s is not supported yet", reg_name.name()))
endcase
- set_wiri_wpri_fields();
- endfunction
-
- // Hardwire all WIRI and WPRI fields to '0
- virtual function void set_wiri_wpri_fields();
- foreach(fld[i]) begin
- if(fld[i].access_type inside {WIRI, WPRI}) begin
- set_field(fld[i].get_name(), '0, 1'b1);
- end
- end
endfunction
endclass
diff --git a/hw/vendor/lowrisc_ibex/vendor/google_riscv-dv/src/riscv_privileged_common_seq.sv b/hw/vendor/lowrisc_ibex/vendor/google_riscv-dv/src/riscv_privileged_common_seq.sv
index 9a8cffc..474b860 100644
--- a/hw/vendor/lowrisc_ibex/vendor/google_riscv-dv/src/riscv_privileged_common_seq.sv
+++ b/hw/vendor/lowrisc_ibex/vendor/google_riscv-dv/src/riscv_privileged_common_seq.sv
@@ -55,7 +55,15 @@
virtual function void setup_mmode_reg(privileged_mode_t mode, ref riscv_privil_reg regs[$]);
mstatus = riscv_privil_reg::type_id::create("mstatus");
mstatus.init_reg(MSTATUS);
- `DV_CHECK_RANDOMIZE_FATAL(mstatus, "cannot randomize mstatus");
+ if (cfg.randomize_csr) begin
+ mstatus.set_val({cfg.mstatus[XLEN-1:XLEN-21], cfg.mstatus_tvm, cfg.mstatus_mxr,
+ cfg.mstatus_sum, cfg.mstatus_mprv, cfg.mstatus[16:0]});
+ end else begin
+ mstatus.set_field("MPRV", cfg.mstatus_mprv);
+ mstatus.set_field("MXR", cfg.mstatus_mxr);
+ mstatus.set_field("SUM", cfg.mstatus_sum);
+ mstatus.set_field("TVM", cfg.mstatus_tvm);
+ end
if(XLEN==64) begin
mstatus.set_field("UXL", 2'b10);
mstatus.set_field("SXL", 2'b10);
@@ -64,16 +72,9 @@
mstatus.set_field("FS", 0);
mstatus.set_field("SD", 0);
mstatus.set_field("UIE", 0);
- mstatus.set_field("MPRV", cfg.mstatus_mprv);
- mstatus.set_field("MXR", cfg.mstatus_mxr);
- mstatus.set_field("SUM", cfg.mstatus_sum);
- mstatus.set_field("TVM", cfg.mstatus_tvm);
// Set the previous privileged mode as the target mode
mstatus.set_field("MPP", mode);
- if(mode == USER_MODE)
- mstatus.set_field("SPP", 0);
- else
- mstatus.set_field("SPP", 1);
+ mstatus.set_field("SPP", 0);
// Enable interrupt
mstatus.set_field("MPIE", cfg.enable_interrupt);
mstatus.set_field("MIE", cfg.enable_interrupt);
@@ -81,17 +82,27 @@
mstatus.set_field("SIE", cfg.enable_interrupt);
mstatus.set_field("UPIE", cfg.enable_interrupt);
mstatus.set_field("UIE", riscv_instr_pkg::support_umode_trap);
+ `uvm_info(`gfn, $sformatf("mstatus_val: 0x%0x", mstatus.get_val()), UVM_LOW)
regs.push_back(mstatus);
// Enable external and timer interrupt
if (MIE inside {implemented_csr}) begin
mie = riscv_privil_reg::type_id::create("mie");
mie.init_reg(MIE);
+ if (cfg.randomize_csr) begin
+ mie.set_val(cfg.mie);
+ end
mie.set_field("UEIE", cfg.enable_interrupt);
mie.set_field("SEIE", cfg.enable_interrupt);
mie.set_field("MEIE", cfg.enable_interrupt);
mie.set_field("USIE", cfg.enable_interrupt);
mie.set_field("SSIE", cfg.enable_interrupt);
mie.set_field("MSIE", cfg.enable_interrupt);
+ // TODO(udinator) - since full CSRs are being randomized, it's necessary to hardwire the xTIE
+ // fields to 1'b0, as it causes some timer interrupts to be triggered in Spike after a certain
+ // amount of simulation time.
+ mie.set_field("MTIE", 1'b0);
+ mie.set_field("STIE", 1'b0);
+ mie.set_field("UTIE", 1'b0);
regs.push_back(mie);
end
endfunction
@@ -100,6 +111,9 @@
sstatus = riscv_privil_reg::type_id::create("sstatus");
sstatus.init_reg(SSTATUS);
`DV_CHECK_RANDOMIZE_FATAL(sstatus, "cannot randomize sstatus")
+ if (cfg.randomize_csr) begin
+ sstatus.set_val(cfg.sstatus);
+ end
sstatus.set_field("SPIE", cfg.enable_interrupt);
sstatus.set_field("SIE", cfg.enable_interrupt);
sstatus.set_field("UPIE", cfg.enable_interrupt);
@@ -111,19 +125,21 @@
sstatus.set_field("FS", 0);
sstatus.set_field("SD", 0);
sstatus.set_field("UIE", 0);
- if(mode == USER_MODE)
- sstatus.set_field("SPP", 0);
- else
- sstatus.set_field("SPP", 1);
+ sstatus.set_field("SPP", 0);
regs.push_back(sstatus);
// Enable external and timer interrupt
if (SIE inside {implemented_csr}) begin
sie = riscv_privil_reg::type_id::create("sie");
sie.init_reg(SIE);
+ if (cfg.randomize_csr) begin
+ sie.set_val(cfg.sie);
+ end
sie.set_field("UEIE", cfg.enable_interrupt);
sie.set_field("SEIE", cfg.enable_interrupt);
sie.set_field("USIE", cfg.enable_interrupt);
sie.set_field("SSIE", cfg.enable_interrupt);
+ sie.set_field("STIE", 1'b0);
+ sie.set_field("UTIE", 1'b0);
regs.push_back(sie);
end
endfunction
@@ -132,14 +148,21 @@
ustatus = riscv_privil_reg::type_id::create("ustatus");
ustatus.init_reg(USTATUS);
`DV_CHECK_RANDOMIZE_FATAL(ustatus, "cannot randomize ustatus")
+ if (cfg.randomize_csr) begin
+ ustatus.set_val(cfg.ustatus);
+ end
ustatus.set_field("UIE", cfg.enable_interrupt);
ustatus.set_field("UPIE", cfg.enable_interrupt);
regs.push_back(ustatus);
if (UIE inside {implemented_csr}) begin
uie = riscv_privil_reg::type_id::create("uie");
uie.init_reg(UIE);
+ if (cfg.randomize_csr) begin
+ uie.set_val(cfg.uie);
+ end
uie.set_field("UEIE", cfg.enable_interrupt);
uie.set_field("USIE", cfg.enable_interrupt);
+ uie.set_field("UTIE", 1'b0);
regs.push_back(uie);
end
endfunction
diff --git a/hw/vendor/lowrisc_ibex/vendor/google_riscv-dv/src/riscv_rand_instr.sv b/hw/vendor/lowrisc_ibex/vendor/google_riscv-dv/src/riscv_rand_instr.sv
index b43f5fe..ce65c37 100644
--- a/hw/vendor/lowrisc_ibex/vendor/google_riscv-dv/src/riscv_rand_instr.sv
+++ b/hw/vendor/lowrisc_ibex/vendor/google_riscv-dv/src/riscv_rand_instr.sv
@@ -62,7 +62,7 @@
instr_name != SFENCE_VMA;
}
if(cfg.no_fence) {
- !(instr_name inside {FENCE, FENCEI, SFENCE_VMA});
+ !(instr_name inside {FENCE, FENCE_I, SFENCE_VMA});
}
// TODO: Support C_ADDI4SPN
instr_name != C_ADDI4SPN;
@@ -76,6 +76,9 @@
if(cfg.no_wfi) {
instr_name != WFI;
}
+ if(cfg.no_dret) {
+ instr_name != DRET;
+ }
// Below previleged instruction is not generated by default
!(instr_name inside {ECALL, URET, SRET, MRET});
if(cfg.no_load_store) {
diff --git a/hw/vendor/lowrisc_ibex/vendor/google_riscv-dv/src/riscv_reg.sv b/hw/vendor/lowrisc_ibex/vendor/google_riscv-dv/src/riscv_reg.sv
index 63d6e09..ea17cb2 100644
--- a/hw/vendor/lowrisc_ibex/vendor/google_riscv-dv/src/riscv_reg.sv
+++ b/hw/vendor/lowrisc_ibex/vendor/google_riscv-dv/src/riscv_reg.sv
@@ -153,7 +153,4 @@
end
endfunction
- virtual function void set_wiri_wpri_fields();
- endfunction
-
endclass
diff --git a/hw/vendor/lowrisc_ibex/vendor/google_riscv-dv/src/riscv_signature_pkg.sv b/hw/vendor/lowrisc_ibex/vendor/google_riscv-dv/src/riscv_signature_pkg.sv
index 45194d2..3a4c420 100644
--- a/hw/vendor/lowrisc_ibex/vendor/google_riscv-dv/src/riscv_signature_pkg.sv
+++ b/hw/vendor/lowrisc_ibex/vendor/google_riscv-dv/src/riscv_signature_pkg.sv
@@ -42,7 +42,13 @@
IN_SUPERVISOR_MODE,
IN_USER_MODE,
HANDLING_IRQ,
- HANDLING_EXCEPTION
+ FINISHED_IRQ,
+ HANDLING_EXCEPTION,
+ INSTR_FAULT_EXCEPTION,
+ ILLEGAL_INSTR_EXCEPTION,
+ LOAD_FAULT_EXCEPTION,
+ STORE_FAULT_EXCEPTION,
+ EBREAK_EXCEPTION
} core_status_t;
typedef enum bit {
@@ -50,5 +56,4 @@
TEST_FAIL
} test_result_t;
-
endpackage
diff --git a/hw/vendor/lowrisc_ibex/vendor/google_riscv-dv/test/riscv_instr_base_test.sv b/hw/vendor/lowrisc_ibex/vendor/google_riscv-dv/test/riscv_instr_base_test.sv
index f1d8186..0969437 100644
--- a/hw/vendor/lowrisc_ibex/vendor/google_riscv-dv/test/riscv_instr_base_test.sv
+++ b/hw/vendor/lowrisc_ibex/vendor/google_riscv-dv/test/riscv_instr_base_test.sv
@@ -14,6 +14,7 @@
* limitations under the License.
*/
+
// Base test
class riscv_instr_base_test extends uvm_test;
@@ -22,17 +23,21 @@
string asm_file_name = "riscv_asm_test";
riscv_asm_program_gen asm_gen;
string instr_seq;
+ int start_idx;
`uvm_component_utils(riscv_instr_base_test)
function new(string name="", uvm_component parent=null);
super.new(name, parent);
void'($value$plusargs("asm_file_name=%0s", asm_file_name));
+ void'($value$plusargs("start_idx=%0d", start_idx));
endfunction
virtual function void build_phase(uvm_phase phase);
super.build_phase(phase);
+ `uvm_info(`gfn, "Create configuration instance", UVM_LOW)
cfg = riscv_instr_gen_config::type_id::create("cfg");
+ `uvm_info(`gfn, "Create configuration instance...done", UVM_LOW)
uvm_config_db#(riscv_instr_gen_config)::set(null, "*", "instr_cfg", cfg);
if(cfg.asm_test_suffix != "")
asm_file_name = {asm_file_name, ".", cfg.asm_test_suffix};
@@ -63,43 +68,22 @@
super.report_phase(phase);
endfunction
- function void get_directed_instr_stream_opts();
- string cmd_opts_prefix;
- string opts;
- string opt[$];
- int i = 0;
- while(1) begin
- cmd_opts_prefix = $sformatf("directed_instr_%0d", i);
- if($value$plusargs({cmd_opts_prefix, "=%0s"}, opts)) begin
- uvm_split_string(opts, ",", opt);
- `DV_CHECK_FATAL(opt.size() == 2)
- asm_gen.add_directed_instr_stream(opt[0], opt[1].atoi());
- end else begin
- break;
- end
- `uvm_info(`gfn, $sformatf("Got directed instr[%0d] %0s, ratio = %0s/1000",
- i, opt[0], opt[1]), UVM_LOW)
- i++;
- end
-
- endfunction
-
virtual function void apply_directed_instr();
endfunction
task run_phase(uvm_phase phase);
int fd;
+ cfg.build_instruction_template();
for(int i = 0; i < cfg.num_of_tests; i++) begin
string test_name;
- cfg = riscv_instr_gen_config::type_id::create("cfg");
randomize_cfg();
+ cfg.build_instruction_list();
asm_gen = riscv_asm_program_gen::type_id::create("asm_gen");
- get_directed_instr_stream_opts();
asm_gen.cfg = cfg;
- test_name = $sformatf("%0s.%0d.S", asm_file_name, i);
+ asm_gen.get_directed_instr_stream();
+ test_name = $sformatf("%0s_%0d.S", asm_file_name, i+start_idx);
apply_directed_instr();
`uvm_info(`gfn, "All directed instruction is applied", UVM_LOW)
- cfg.build_instruction_template();
asm_gen.gen_program();
asm_gen.gen_test_file(test_name);
end
diff --git a/hw/vendor/lowrisc_ibex/vendor/google_riscv-dv/test/riscv_instr_cov_debug_test.sv b/hw/vendor/lowrisc_ibex/vendor/google_riscv-dv/test/riscv_instr_cov_debug_test.sv
new file mode 100644
index 0000000..edd2cc2
--- /dev/null
+++ b/hw/vendor/lowrisc_ibex/vendor/google_riscv-dv/test/riscv_instr_cov_debug_test.sv
@@ -0,0 +1,29 @@
+// This test is only used to debug covergroup implementation
+
+class riscv_instr_cov_debug_test extends uvm_test;
+
+ riscv_instr_gen_config cfg;
+ riscv_instr_cover_group instr_cg;
+ riscv_instr_cov_item instr;
+ int unsigned num_of_iterations = 10000;
+
+ `uvm_component_utils(riscv_instr_cov_debug_test)
+ `uvm_component_new
+
+ task run_phase(uvm_phase phase);
+ bit [XLEN-1:0] rand_val;
+ void'($value$plusargs("num_of_iterations=%0d", num_of_iterations));
+ cfg = riscv_instr_gen_config::type_id::create("cfg");
+ instr = riscv_instr_cov_item::type_id::create("instr");
+ instr_cg = new(cfg);
+ repeat(20000) begin
+ void'(instr.randomize() with {group == RV32I;
+ csr inside {implemented_csr};});
+ `uvm_info(`gfn, instr.convert2asm(), UVM_LOW)
+ instr.pre_sample();
+ instr_cg.sample(instr);
+ end
+ `uvm_info("", "TEST PASSED", UVM_NONE);
+ endtask
+
+endclass
diff --git a/hw/vendor/lowrisc_ibex/vendor/google_riscv-dv/test/riscv_instr_cov_test.sv b/hw/vendor/lowrisc_ibex/vendor/google_riscv-dv/test/riscv_instr_cov_test.sv
new file mode 100644
index 0000000..0f77567
--- /dev/null
+++ b/hw/vendor/lowrisc_ibex/vendor/google_riscv-dv/test/riscv_instr_cov_test.sv
@@ -0,0 +1,231 @@
+// This test read all trace CSV, and collect functional coverage from the instruction trace
+class riscv_instr_cov_test extends uvm_test;
+
+ typedef uvm_enum_wrapper#(riscv_instr_name_t) instr_enum;
+ typedef uvm_enum_wrapper#(riscv_reg_t) gpr_enum;
+ typedef uvm_enum_wrapper#(privileged_reg_t) preg_enum;
+
+ riscv_instr_gen_config cfg;
+ riscv_instr_cover_group instr_cg;
+ riscv_instr_cov_item instr;
+ string trace_csv[$];
+ string trace[string];
+ int unsigned entry_cnt;
+ int unsigned total_entry_cnt;
+ int unsigned skipped_cnt;
+ int unsigned illegal_instr_cnt;
+
+ `uvm_component_utils(riscv_instr_cov_test)
+ `uvm_component_new
+
+ task run_phase(uvm_phase phase);
+ int i;
+ string args;
+ string csv;
+ string line;
+ string header[$];
+ string entry[$];
+ int fd;
+ while(1) begin
+ args = {$sformatf("trace_csv_%0d", i), "=%s"};
+ if ($value$plusargs(args, csv)) begin
+ trace_csv.push_back(csv);
+ end else begin
+ break;
+ end
+ i++;
+ end
+ cfg = riscv_instr_gen_config::type_id::create("cfg");
+ cfg.build_instruction_template(.skip_instr_exclusion(1));
+ instr = riscv_instr_cov_item::type_id::create("instr");
+ instr.rand_mode(0);
+ instr.no_hint_illegal_instr_c.constraint_mode(0);
+ instr.imm_val_c.constraint_mode(0);
+ instr_cg = new(cfg);
+ `uvm_info(`gfn, $sformatf("%0d CSV trace files to be processed", trace_csv.size()), UVM_LOW)
+ foreach (trace_csv[i]) begin
+ entry_cnt = 0;
+ instr_cg.reset();
+ `uvm_info(`gfn, $sformatf("Processing CSV trace[%0d]: %s", i, trace_csv[i]), UVM_LOW)
+ fd = $fopen(trace_csv[i], "r");
+ if (fd) begin
+ // Get the header line
+ if ($fgets(line, fd)) begin
+ split_string(line, ",", header);
+ `uvm_info(`gfn, $sformatf("Header: %0s", line), UVM_HIGH);
+ end else begin
+ `uvm_info(`gfn, $sformatf("Skipping empty trace file: %0s", trace_csv[i]), UVM_LOW)
+ continue;
+ end
+ while ($fgets(line, fd)) begin
+ split_string(line, ",", entry);
+ if (entry.size() != header.size()) begin
+ `uvm_info(`gfn, $sformatf("Skipping malformed entry[%0d] : %0s", entry_cnt, line), UVM_LOW)
+ skipped_cnt += 1;
+ end else begin
+ trace["csv_entry"] = line;
+ foreach (header[j]) begin
+ trace[header[j]] = entry[j];
+ end
+ post_process_trace();
+ if (trace["instr"] inside {"li", "ret", "la"}) continue;
+ if (uvm_is_match("amo*",trace["instr"]) ||
+ uvm_is_match("lr*" ,trace["instr"]) ||
+ uvm_is_match("sc*" ,trace["instr"])) begin
+ // TODO: Enable functional coverage for AMO test
+ continue;
+ end
+ if (!sample()) begin
+ `uvm_info(`gfn, $sformatf("Skipping illegal instr name: %0s [%0s]",
+ trace["instr"], line), UVM_LOW)
+ end
+ end
+ entry_cnt += 1;
+ end
+ end else begin
+ `uvm_error(`gfn, $sformatf("%0s cannot be openned", trace_csv[i]))
+ end
+ `uvm_info(`gfn, $sformatf("[%s] : %0d instructions processed",
+ trace_csv[i], entry_cnt), UVM_LOW)
+ total_entry_cnt += entry_cnt;
+ end
+ `uvm_info(`gfn, $sformatf("Finished processing %0d trace CSV, %0d instructions",
+ trace_csv.size(), total_entry_cnt), UVM_LOW)
+ if ((skipped_cnt > 0) || (illegal_instr_cnt > 0)) begin
+ `uvm_error(`gfn, $sformatf("%0d instructions skipped, %0d illegal instruction",
+ skipped_cnt, illegal_instr_cnt))
+
+ end else begin
+ `uvm_info(`gfn, "TEST PASSED", UVM_NONE);
+ end
+ endtask
+
+ virtual function void post_process_trace();
+ endfunction
+
+ function bit sample();
+ riscv_instr_name_t instr_name;
+ if (instr_enum::from_name(process_instr_name(trace["instr"]), instr_name)) begin
+ if (cfg.instr_template.exists(instr_name)) begin
+ instr.copy_base_instr(cfg.instr_template[instr_name]);
+ assign_trace_info_to_instr(instr);
+ instr.pre_sample();
+ instr_cg.sample(instr);
+ return 1'b1;
+ end
+ end
+ illegal_instr_cnt++;
+ return 1'b0;
+ endfunction
+
+ virtual function void assign_trace_info_to_instr(riscv_instr_cov_item instr);
+ riscv_reg_t gpr;
+ privileged_reg_t preg;
+ get_val(trace["addr"], instr.pc);
+ get_val(trace["binary"], instr.binary);
+ instr.trace = trace["instr_str"];
+ if (instr.instr_name inside {ECALL, EBREAK, FENCE, FENCE_I, NOP,
+ C_NOP, WFI, MRET, C_EBREAK}) begin
+ return;
+ end
+ if (instr.has_rs2) begin
+ if (get_gpr(trace["rs2"], gpr)) begin
+ instr.rs2 = gpr;
+ get_val(trace["rs2_val"], instr.rs2_value);
+ end else begin
+ `uvm_error(`gfn, $sformatf("Unrecoganized rs2: [%0s] (%0s)",
+ trace["rs2"], trace["csv_entry"]))
+ end
+ end
+ if (instr.has_rd) begin
+ if (get_gpr(trace["rd"], gpr)) begin
+ instr.rd = gpr;
+ get_val(trace["rd_val"], instr.rd_value);
+ end else begin
+ `uvm_error(`gfn, $sformatf("Unrecoganized rd: [%0s] (%0s)",
+ trace["rd"], trace["csv_entry"]))
+ end
+ end
+ if (instr.has_rs1) begin
+ if (instr.format inside {CI_FORMAT, CR_FORMAT, CB_FORMAT}) begin
+ instr.rs1 = instr.rd;
+ end else begin
+ if (get_gpr(trace["rs1"], gpr)) begin
+ instr.rs1 = gpr;
+ get_val(trace["rs1_val"], instr.rs1_value);
+ end else begin
+ `uvm_error(`gfn, $sformatf("Unrecoganized rs1: [%0s] (%0s)",
+ trace["rs1"], trace["csv_entry"]))
+ end
+ end
+ end
+ if (instr.has_imm) begin
+ get_val(trace["imm"], instr.imm);
+ end
+ if (instr.category == CSR) begin
+ if (preg_enum::from_name(trace["csr"].toupper(), preg)) begin
+ instr.csr = preg;
+ end else begin
+ get_val(trace["csr"], instr.csr);
+ end
+ end
+ if (instr.category inside {LOAD, STORE}) begin
+ if (XLEN == 32) begin
+ instr.mem_addr = instr.rs1_value + instr.imm;
+ end else begin
+ bit [XLEN-32-1:0] padding;
+ if (instr.imm[31]) begin
+ padding = '1;
+ end else begin
+ padding = '0;
+ end
+ instr.mem_addr = instr.rs1_value + {padding, instr.imm};
+ end
+ end
+ endfunction
+
+ function bit get_gpr(input string str, output riscv_reg_t gpr);
+ str = str.toupper();
+ if (gpr_enum::from_name(str, gpr)) begin
+ return 1'b1;
+ end else begin
+ return 1'b0;
+ end
+ endfunction
+
+ function void get_val(input string str, output bit [XLEN-1:0] val);
+ val = str.atohex();
+ endfunction
+
+ function string process_instr_name(string instr_name);
+ instr_name = instr_name.toupper();
+ foreach (instr_name[i]) begin
+ if (instr_name[i] == ".") begin
+ instr_name[i] = "_";
+ end
+ end
+ return instr_name;
+ endfunction
+
+ function void split_string(string str, byte step, ref string result[$]);
+ string tmp_str;
+ int i;
+ bit in_quote;
+ result = {};
+ while (i < str.len()) begin
+ if (str[i] == "\"") begin
+ in_quote = ~in_quote;
+ end else if ((str[i] == step) && !in_quote) begin
+ result.push_back(tmp_str);
+ tmp_str = "";
+ end else begin
+ tmp_str = {tmp_str, str[i]};
+ end
+ if (i == str.len()-1) begin
+ result.push_back(tmp_str);
+ end
+ i++;
+ end
+ endfunction
+
+endclass
diff --git a/hw/vendor/lowrisc_ibex/vendor/google_riscv-dv/test/riscv_instr_gen_tb_top.sv b/hw/vendor/lowrisc_ibex/vendor/google_riscv-dv/test/riscv_instr_gen_tb_top.sv
index b889d01..8d54d05 100644
--- a/hw/vendor/lowrisc_ibex/vendor/google_riscv-dv/test/riscv_instr_gen_tb_top.sv
+++ b/hw/vendor/lowrisc_ibex/vendor/google_riscv-dv/test/riscv_instr_gen_tb_top.sv
@@ -16,8 +16,6 @@
module riscv_instr_gen_tb_top;
- `include "uvm_macros.svh"
-
import uvm_pkg::*;
import riscv_instr_test_pkg::*;
diff --git a/hw/vendor/lowrisc_ibex/vendor/google_riscv-dv/test/riscv_instr_test_lib.sv b/hw/vendor/lowrisc_ibex/vendor/google_riscv-dv/test/riscv_instr_test_lib.sv
index e4be2f4..4a3bee2 100644
--- a/hw/vendor/lowrisc_ibex/vendor/google_riscv-dv/test/riscv_instr_test_lib.sv
+++ b/hw/vendor/lowrisc_ibex/vendor/google_riscv-dv/test/riscv_instr_test_lib.sv
@@ -23,8 +23,7 @@
virtual function void randomize_cfg();
cfg.instr_cnt = 10000;
cfg.num_of_sub_program = 5;
- `DV_CHECK_RANDOMIZE_WITH_FATAL(cfg,
- max_nested_loop == 2;)
+ `DV_CHECK_RANDOMIZE_FATAL(cfg)
`uvm_info(`gfn, $sformatf("riscv_instr_gen_config is randomized:\n%0s",
cfg.sprint()), UVM_LOW)
endfunction
@@ -35,8 +34,8 @@
asm_gen.add_directed_instr_stream("riscv_loop_instr", 4);
asm_gen.add_directed_instr_stream("riscv_hazard_instr_stream", 4);
asm_gen.add_directed_instr_stream("riscv_load_store_hazard_instr_stream", 4);
- asm_gen.add_directed_instr_stream("riscv_cache_line_stress_instr_stream", 4);
asm_gen.add_directed_instr_stream("riscv_multi_page_load_store_instr_stream", 4);
+ asm_gen.add_directed_instr_stream("riscv_mem_region_stress_test", 4);
endfunction
endclass
diff --git a/hw/vendor/lowrisc_ibex/vendor/google_riscv-dv/test/riscv_instr_test_pkg.sv b/hw/vendor/lowrisc_ibex/vendor/google_riscv-dv/test/riscv_instr_test_pkg.sv
index a8a16a6..5e93bd0 100644
--- a/hw/vendor/lowrisc_ibex/vendor/google_riscv-dv/test/riscv_instr_test_pkg.sv
+++ b/hw/vendor/lowrisc_ibex/vendor/google_riscv-dv/test/riscv_instr_test_pkg.sv
@@ -19,8 +19,9 @@
import uvm_pkg::*;
import riscv_instr_pkg::*;
- `include "uvm_macros.svh"
`include "riscv_instr_base_test.sv"
`include "riscv_instr_test_lib.sv"
+ `include "riscv_instr_cov_debug_test.sv"
+ `include "riscv_instr_cov_test.sv"
endpackage
diff --git a/hw/vendor/lowrisc_ibex/vendor/google_riscv-dv/user_extension/user_define.h b/hw/vendor/lowrisc_ibex/vendor/google_riscv-dv/user_extension/user_define.h
new file mode 100644
index 0000000..e7e3557
--- /dev/null
+++ b/hw/vendor/lowrisc_ibex/vendor/google_riscv-dv/user_extension/user_define.h
@@ -0,0 +1 @@
+# Add user macros, routines in this file
diff --git a/hw/vendor/lowrisc_ibex/vendor/google_riscv-dv/user_extension/user_extension.svh b/hw/vendor/lowrisc_ibex/vendor/google_riscv-dv/user_extension/user_extension.svh
new file mode 100644
index 0000000..16fed2f
--- /dev/null
+++ b/hw/vendor/lowrisc_ibex/vendor/google_riscv-dv/user_extension/user_extension.svh
@@ -0,0 +1 @@
+// Add your custom extensions, you can list all your local extended SV files here
diff --git a/hw/vendor/lowrisc_ibex/vendor/google_riscv-dv/yaml/cov_testlist.yaml b/hw/vendor/lowrisc_ibex/vendor/google_riscv-dv/yaml/cov_testlist.yaml
new file mode 100644
index 0000000..b1ade51
--- /dev/null
+++ b/hw/vendor/lowrisc_ibex/vendor/google_riscv-dv/yaml/cov_testlist.yaml
@@ -0,0 +1,18 @@
+- test: riscv_instr_cov_debug_test
+ description: >
+ Functional coverage debug test, this is not a functional test to the core.
+ iterations: 1
+ gen_test: riscv_instr_cov_debug_test
+ no_iss: 1
+ no_gcc: 1
+ no_post_compare: 1
+
+- test: riscv_instr_cov_test
+ description: >
+ Parse the instruction information from the CSV trace log, sample functional
+ coverage from the instruction trace.
+ iterations: 1
+ gen_test: riscv_instr_cov_test
+ no_iss: 1
+ no_gcc: 1
+ no_post_compare: 1
diff --git a/hw/vendor/lowrisc_ibex/vendor/google_riscv-dv/yaml/iss.yaml b/hw/vendor/lowrisc_ibex/vendor/google_riscv-dv/yaml/iss.yaml
index 216cc6d..6856278 100644
--- a/hw/vendor/lowrisc_ibex/vendor/google_riscv-dv/yaml/iss.yaml
+++ b/hw/vendor/lowrisc_ibex/vendor/google_riscv-dv/yaml/iss.yaml
@@ -25,7 +25,7 @@
--override riscvOVPsim/cpu/PMP_registers=0
--override riscvOVPsim/cpu/simulateexceptions=T
--trace --tracechange --traceshowicount --program <elf>
- --finishafter 500000
+ --finishafter 1000000
- iss: sail
path_var: SAIL_RISCV
diff --git a/hw/vendor/lowrisc_ibex/vendor/google_riscv-dv/yaml/simulator.yaml b/hw/vendor/lowrisc_ibex/vendor/google_riscv-dv/yaml/simulator.yaml
index f73eca2..b47cb81 100644
--- a/hw/vendor/lowrisc_ibex/vendor/google_riscv-dv/yaml/simulator.yaml
+++ b/hw/vendor/lowrisc_ibex/vendor/google_riscv-dv/yaml/simulator.yaml
@@ -13,39 +13,74 @@
# limitations under the License.
- tool: vcs
- compile_cmd:
- - "vcs -file <cwd>/vcs.compile.option.f
- -f <cwd>/files.f -full64
- -l <out>/compile.log
- -Mdir=<out>/vcs_simv.csrc
- -o <out>/vcs_simv <cmp_opts>"
- sim_cmd: >
- <out>/vcs_simv +vcs+lic+wait <sim_opts> +ntb_random_seed=<seed>
+ compile:
+ cmd:
+ - "vcs -file <cwd>/vcs.compile.option.f
+ +incdir+<setting>
+ +incdir+<user_extension>
+ -f <cwd>/files.f -full64
+ -l <out>/compile.log
+ -Mdir=<out>/vcs_simv.csrc
+ -o <out>/vcs_simv <cmp_opts> <cov_opts> "
+ cov_opts: >
+ -cm_dir <out>/test.vdb
+ sim:
+ cmd: >
+ <out>/vcs_simv +vcs+lic+wait <sim_opts> +ntb_random_seed=<seed> <cov_opts>
+ cov_opts: >
+ -cm_dir <out>/test.vdb -cm_log /dev/null -cm_name test_<seed>
- tool: ius
- compile_cmd:
- - "irun -64bit -access +rwc -f <cwd>/files.f
- -q -sv -uvm -vlog_ext +.vh -I.
- -uvmhome CDNS-1.2
- -elaborate
- -l <out>/compile.log <cmp_opts>"
- sim_cmd: >
- irun -R <sim_opts> -svseed <seed>
+ compile:
+ cmd:
+ - "irun -64bit -access +rwc -f <cwd>/files.f
+ +incdir+<setting>
+ +incdir+<user_extension>
+ -q -sv -uvm -vlog_ext +.vh -I.
+ -uvmhome CDNS-1.2
+ -elaborate
+ -l <out>/compile.log <cmp_opts>"
+ sim:
+ cmd: >
+ irun -R <sim_opts> -svseed <seed>
- tool: questa
- compile_cmd:
- - "vmap mtiUvm $QUESTA_HOME/questasim/uvm-1.2"
- - "vlog -64
- -access=rwc
- -f <cwd>/files.f
- -sv
- -mfcu -cuname design_cuname
- +define+UVM_REGEX_NO_DPI
- -writetoplevels <out>/top.list
- -l <out>/compile.log <cmp_opts>"
- - "vopt -64 -debug
- +designfile -f <out>/top.list
- -l <out>/optimize.log <cmp_opts>
- -o design_opt"
- sim_cmd: >
- vsim -64 -c -do <cwd>/questa_sim.tcl design_opt <sim_opts> -sv_seed <seed>
+ compile:
+ cmd:
+ - "vmap mtiUvm $QUESTA_HOME/questasim/uvm-1.2"
+ - "vlog -64
+ +incdir+<setting>
+ +incdir+<user_extension>
+ -access=rwc
+ -f <cwd>/files.f
+ -sv
+ -mfcu -cuname design_cuname
+ +define+UVM_REGEX_NO_DPI
+ -writetoplevels <out>/top.list
+ -l <out>/compile.log <cmp_opts>"
+ - "vopt -64 -debug
+ +designfile -f <out>/top.list
+ -l <out>/optimize.log <cmp_opts>
+ -o design_opt"
+ sim:
+ cmd: >
+ vsim -64 -c -do <cwd>/questa_sim.tcl design_opt <sim_opts> -sv_seed <seed>
+
+- tool: dsim
+ env_var: DSIM,DSIM_LIB_PATH
+ compile:
+ cmd:
+ - "mkdir -p <out>/dsim"
+ - "<DSIM> -sv -work <out>/dsim
+ -genimage image
+ +incdir+$UVM_HOME/src
+ $UVM_HOME/src/uvm_pkg.sv
+ +define+DSIM
+ +incdir+<setting>
+ +incdir+<user_extension>
+ -f <cwd>/files.f
+ -l <out>/dsim/compile.log <cmp_opts>"
+ sim:
+ cmd: >
+ <DSIM> <sim_opts> -sv_seed <seed> -pli_lib <DSIM_LIB_PATH>/libuvm_dpi.so +acc+rwb -image image -work <out>/dsim
+
diff --git a/hw/vendor/lowrisc_ibex/vendor/google_riscv-dv/yaml/testlist.yaml b/hw/vendor/lowrisc_ibex/vendor/google_riscv-dv/yaml/testlist.yaml
index 22ce918..dfbdd1d 100644
--- a/hw/vendor/lowrisc_ibex/vendor/google_riscv-dv/yaml/testlist.yaml
+++ b/hw/vendor/lowrisc_ibex/vendor/google_riscv-dv/yaml/testlist.yaml
@@ -76,8 +76,19 @@
+directed_instr_1=riscv_loop_instr,4
+directed_instr_2=riscv_hazard_instr_stream,4
+directed_instr_3=riscv_load_store_hazard_instr_stream,4
- +directed_instr_4=riscv_cache_line_stress_instr_stream,4
- +directed_instr_5=riscv_multi_page_load_store_instr_stream,4
+ +directed_instr_4=riscv_multi_page_load_store_instr_stream,4
+ +directed_instr_5=riscv_mem_region_stress_test,4
+ rtl_test: core_base_test
+
+- test: riscv_loop_test
+ description: >
+ Random instruction stress test
+ iterations: 2
+ gen_test: riscv_instr_base_test
+ gen_opts: >
+ +instr_cnt=10000
+ +num_of_sub_program=5
+ +directed_instr_1=riscv_loop_instr,20
rtl_test: core_base_test
# TODO: Temporarily disable this as compiler seems to generate compressed instruction with rv64im
@@ -98,7 +109,7 @@
iterations: 2
gen_test: riscv_instr_base_test
gen_opts: >
- +instr_cnt=15000
+ +instr_cnt=10000
+num_of_sub_program=20
+directed_instr_0=riscv_load_store_rand_instr_stream,8
rtl_test: core_base_test
@@ -114,15 +125,16 @@
+num_of_sub_program=5
+directed_instr_0=riscv_load_store_rand_instr_stream,40
+directed_instr_1=riscv_load_store_hazard_instr_stream,40
- +directed_instr_2=riscv_cache_line_stress_instr_stream,40
- +directed_instr_3=riscv_multi_page_load_store_instr_stream,40
+ +directed_instr_2=riscv_multi_page_load_store_instr_stream,10
+ +directed_instr_3=riscv_mem_region_stress_test,10
rtl_test: core_base_test
+# TODO: Re-enable this test after all the data/instruction page organization changes are done
- test: riscv_page_table_exception_test
description: >
Test random page table exception handling. An exception handling routine is
designed to fix the page table error and resume execution.
- iterations: 2
+ iterations: 0
gen_test: riscv_rand_instr_test
gen_opts: >
+enable_page_table_exception=1
@@ -156,7 +168,7 @@
iterations: 2
gen_test: riscv_rand_instr_test
gen_opts: >
- +enable_illegal_instruction=1
+ +illegal_instr_ratio=5
rtl_test: core_base_test
- test: riscv_hint_instr_test
@@ -166,7 +178,7 @@
iterations: 2
gen_test: riscv_rand_instr_test
gen_opts: >
- +enable_hint_instruction=1
+ +hint_instr_ratio=5
rtl_test: core_base_test
- test: riscv_ebreak_test
@@ -228,8 +240,8 @@
+num_of_sub_program=5
+directed_instr_0=riscv_load_store_rand_instr_stream,20
+directed_instr_1=riscv_load_store_hazard_instr_stream,20
- +directed_instr_2=riscv_cache_line_stress_instr_stream,20
- +directed_instr_3=riscv_multi_page_load_store_instr_stream,20
+ +directed_instr_2=riscv_multi_page_load_store_instr_stream,5
+ +directed_instr_3=riscv_mem_region_stress_test,5
+enable_unaligned_load_store=1
rtl_test: core_ibex_base_test
