commit 17e9624c452e05f71f4ad2b7c75bf6bbb071c324
author Philipp Wagner <phw@lowrisc.org> Mon Oct 07 10:45:40 2019 +0100
committer Philipp Wagner <mail@philipp-wagner.com> Mon Oct 07 11:13:51 2019 +0100
tree 27d393583a5214db26c706f28b1e66951907d037
parent 03a0d17ec42c7b7ac4580891c9aec54f157cfb0d

Update lowrisc_ibex to lowRISC/ibex@ee1098f

Update code from upstream repository
https://github.com/lowRISC/ibex.git to revision
ee1098f9afb1a63a34d613a8949c00e5b0c75b47

* Tracer: Reference Verilator bug for miscompilation (Philipp Wagner)
* Include rs1 and rd in trace of c.addi16sp (Philipp Wagner)
* [DV] Top level toggle coverage (lowRISC/ibex#371) (udinator)
* [Doc] Add more pipeline details (Greg Chadwick)
* [Doc] Fix for table wrapping in RTD theme (Greg Chadwick)
* Add missing enum cast (Philipp Wagner)
* [Doc] Fix some rendering issues in cs_registers (Tom Roberts)
* [RTL PMP] Fix address matching bugs (Tom Roberts)
* [Priv modes] Add support for U-Mode (Tom Roberts)
* RISC-V Compliance test: Enable tracing (Philipp Wagner)
* [DV] Update ibex log regex (lowRISC/ibex#366) (udinator)
* Tracer: Fix default file name (Philipp Wagner)
* CI: Also check tracer in lint (Philipp Wagner)
* Lint: Enable lint for ibex_core_tracing (Philipp Wagner)
* Update gitignore to include trace log file (Philipp Wagner)
* Document new tracer implementation (Philipp Wagner)
* Implement Verilator-compatible tracer, and use it (Philipp Wagner)
* Remove tracer testbench (Philipp Wagner)
* [RTL] Fix timing path around exceptions and pc_set (Greg Chadwick)
* [RTL] Keep instr in ID valid for FLUSH state (Greg Chadwick)
* Pull `csr_we_int` around case in CSR (Marek Pikuła)
* CI: Unbreak build after simplesat breakage (Philipp Wagner)
* Docs: Fix Sphinx warnings and errors (Philipp Wagner)
* [DV] Debug single step test (lowRISC/ibex#362) (udinator)
* Add more parameters to core file (Philipp Wagner)
* ibex_core_tracing: Pass through all parameters (Philipp Wagner)
* ibex_core: Use correct width for param assignments (Philipp Wagner)
* Tracer: Update copyright notice to match other files (Philipp
  Wagner)
* [Prefetch buffer] - various bug fixes (Tom Roberts)
* [DV]Add Makefile target for functional coverage (lowRISC/ibex#358)
  (taoliug)
* [rtl/ibex_core] Added missing parameter assignment
  (lowRISC/ibex#356) (NilsGraf)
* [DV] Fix ovpsim compare issue (lowRISC/ibex#355) (udinator)
* [DV] Refactor debug stress stimulus to avoid race conditions
  (lowRISC/ibex#354) (udinator)
* Update google_riscv-dv to google/riscv-dv@d341944 (lowRISC/ibex#353)
  (udinator)
* [DV] Basic performance test (lowRISC/ibex#352) (udinator)
* Tighten debug stimulus assertion (lowRISC/ibex#351) (udinator)
* Update google_riscv-dv to google/riscv-dv@e3e1e30 (lowRISC/ibex#349)
  (udinator)
* Update google_riscv-dv to google/riscv-dv@4450592 (lowRISC/ibex#347)
  (udinator)
* [DV] Fix implemented_csr[] compile issue (lowRISC/ibex#346)
  (udinator)
* [DV] Update implemented CSRs (lowRISC/ibex#345) (udinator)
* Fix memory error test logic (lowRISC/ibex#344) (udinator)
* Tracing: Wrap fatal error message with `$fatal()` (Pirmin Vogel)
* [DV] Illegal instruction monitoring (lowRISC/ibex#338) (udinator)
* [DV] Shorten length of interrupt tests to prevent timeouts
  (lowRISC/ibex#337) (udinator)
* [DV] Drive external stimulus to 0 after reset (lowRISC/ibex#334)
  (udinator)
* Update google_riscv-dv to google/riscv-dv@80d4294 (lowRISC/ibex#333)
  (udinator)
* Add memory error testing (lowRISC/ibex#330) (udinator)
* Compliance test suite: Prefer D over I accesses (Philipp Wagner)
* Consolidate the script logging (lowRISC/ibex#329) (taoliug)
* Add dsim support (lowRISC/ibex#328) (taoliug)
* Lint: Enable RVFI when doing lint checks (Philipp Wagner)
* Lint: Fix signal width in tracer (Philipp Wagner)
* Ignore common editor files in Git (Philipp Wagner)
* Add interrupt testing, and update some debug test checks
  (lowRISC/ibex#324) (udinator)
* Integrate with the new riscv-dv user extension flow
  (lowRISC/ibex#323) (taoliug)
* Update google_riscv-dv to google/riscv-dv@0d2b5b7 (lowRISC/ibex#321)
  (udinator)
* ibex_riscv_compliance: Adjust to simutil_verilator (Philipp Wagner)
* simutil_verilator: Always produce toplevel class (Philipp Wagner)
* [DV] Fix latch in simple bus (Greg Chadwick)
* [DV] Standardize logging, allow parallel simulation
  (lowRISC/ibex#315) (taoliug)
* Fix ELF section name (lowRISC/ibex#314) (taoliug)
* Fix regression failure (lowRISC/ibex#313) (taoliug)
* Update google_riscv-dv to google/riscv-dv@c98d89c (lowRISC/ibex#312)
  (udinator)