[dv,chip] added chip csrng edn concurrency test with reduced freq
Signed-off-by: arielc <ariel.cohen@nuvoton.com>
diff --git a/hw/top_earlgrey/data/chip_testplan.hjson b/hw/top_earlgrey/data/chip_testplan.hjson
index 9c6536b..b3ea82c 100644
--- a/hw/top_earlgrey/data/chip_testplan.hjson
+++ b/hw/top_earlgrey/data/chip_testplan.hjson
@@ -953,21 +953,29 @@
This testpoint can be covered by extending the DV environment to support the extended
range clock option via a flag, and running several existing chip-level tests with that
- option, e.g.
+ option.
- chip_sw_clkmgr_jitter_reduced_freq
- chip_sw_flash_ctrl_ops_jitter_en_reduced_freq
- chip_sw_flash_ctrl_access_jitter_en_reduced_freq
- chip_sw_otbn_ecdsa_op_irq_jitter_en_reduced_freq
- chip_sw_aes_enc_jitter_en_reduced_freq
- chip_sw_hmac_enc_jitter_en_reduced_freq
- chip_sw_keymgr_key_derivation_jitter_en_reduced_freq
- chip_sw_kmac_mode_kmac_jitter_en_reduced_freq
- chip_sw_sram_ctrl_main_scrambled_access_jitter_en_reduced_freq
- chip_sw_flash_init_reduced_freq
+ Test the following functionalities with reduced clock:
+
+ - flash_ctrl initialization
+ - flash_ctrl program, read and erase operations
+ - AES, HMAC, KMAC and OTBN operations
+ - Keymgr key derivation
+ - Scramble-enabled access from the main SRAM
+ - Csrng edn concurrency
'''
stage: V2
- tests: []
+ tests: ["chip_sw_clkmgr_jitter_reduced_freq",
+ "chip_sw_flash_ctrl_ops_jitter_en_reduced_freq",
+ "chip_sw_flash_ctrl_access_jitter_en_reduced_freq",
+ "chip_sw_otbn_ecdsa_op_irq_jitter_en_reduced_freq",
+ "chip_sw_aes_enc_jitter_en_reduced_freq",
+ "chip_sw_hmac_enc_jitter_en_reduced_freq",
+ "chip_sw_keymgr_key_derivation_jitter_en_reduced_freq",
+ "chip_sw_kmac_mode_kmac_jitter_en_reduced_freq",
+ "chip_sw_sram_ctrl_main_scrambled_access_jitter_en_reduced_freq",
+ "chip_sw_flash_init_reduced_freq",
+ "chip_sw_csrng_edn_concurrency_reduced_freq"]
}
{
name: chip_sw_clkmgr_deep_sleep_frequency
diff --git a/hw/top_earlgrey/dv/chip_sim_cfg.hjson b/hw/top_earlgrey/dv/chip_sim_cfg.hjson
index ce654ce..954a3ae 100644
--- a/hw/top_earlgrey/dv/chip_sim_cfg.hjson
+++ b/hw/top_earlgrey/dv/chip_sim_cfg.hjson
@@ -1550,7 +1550,8 @@
// Starting the chip in prod LC state frees up all MIOs for this test.
run_opts: ["+use_otp_image=OtpTypeLcStProd"]
reseed: 10
- {
+ }
+ {
name: chip_sw_clkmgr_jitter_reduced_freq
uvm_test_seq: chip_sw_base_vseq
sw_images: ["//sw/device/tests:clkmgr_jitter_test:1"]
@@ -1623,6 +1624,15 @@
en_run_modes: ["sw_test_mode_common"]
run_opts: ["+sw_test_timeout_ns=25_000_000", "+cal_sys_clk_70mhz=1"]
}
+ {
+ name: chip_sw_csrng_edn_concurrency_reduced_freq
+ uvm_test_seq: chip_sw_base_vseq
+ sw_images: ["//sw/device/tests:csrng_edn_concurrency_test:1"]
+ en_run_modes: ["sw_test_mode_test_rom"]
+ run_opts: ["+sw_test_timeout_ns=20_000_000", "+rng_srate_value_min=15",
+ "+rng_srate_value_max=20", "+cal_sys_clk_70mhz=1", "+en_jitter=1"]
+ run_timeout_mins: 240
+ }
]
// List of regressions.
@@ -1663,7 +1673,9 @@
"chip_sw_hmac_enc_jitter_en_reduced_freq",
"chip_sw_keymgr_key_derivation_jitter_en_reduced_freq",
"chip_sw_kmac_mode_kmac_jitter_en_reduced_freq",
- "chip_sw_sram_ctrl_main_scrambled_access_jitter_en_reduced_freq"]
+ "chip_sw_sram_ctrl_main_scrambled_access_jitter_en_reduced_freq",
+ "chip_sw_flash_init_reduced_freq",
+ "chip_sw_csrng_edn_concurrency_reduced_freq"]
}
{
name: xcelium_ci_0
