[aon_timer] Remove temporary intr_enable for #5260
Signed-off-by: Weicai Yang <weicai@google.com>
diff --git a/hw/ip/aon_timer/data/aon_timer.hjson b/hw/ip/aon_timer/data/aon_timer.hjson
index 8c4a8aa..36910ef 100644
--- a/hw/ip/aon_timer/data/aon_timer.hjson
+++ b/hw/ip/aon_timer/data/aon_timer.hjson
@@ -219,25 +219,6 @@
tags: [// interrupt could be updated by HW
"excl:CsrNonInitTests:CsrExclWriteCheck"],
},
- { name: "INTR_ENABLE",
- desc: "Dummy interrupt enable register. This is only here because of #5260. DO NOT USE",
- swaccess: "rw",
- hwaccess: "hwo",
- hwqe: "true",
- hwext: "true",
- fields: [
- { bits: "0",
- name: "wkup_timer_expired",
- desc: "Raised if the wakeup timer has hit the specified threshold",
- }
- { bits: "1",
- name: "wdog_timer_expired",
- desc: "Raised if the watchdog timer has hit the bark threshold",
- }
- ],
- tags: [// dummy register due to #5260, don't bother checking
- "excl:CsrAllTests:CsrExclAll"],
- },
{ name: "INTR_TEST",
desc: "Interrupt Test Register",
swaccess: "wo",
diff --git a/hw/ip/aon_timer/rtl/aon_timer.sv b/hw/ip/aon_timer/rtl/aon_timer.sv
index 804070f..1435bb6 100644
--- a/hw/ip/aon_timer/rtl/aon_timer.sv
+++ b/hw/ip/aon_timer/rtl/aon_timer.sv
@@ -36,7 +36,7 @@
// Register structs
aon_timer_reg2hw_t reg2hw;
aon_timer_hw2reg_t hw2reg, aon_hw2reg, hw2reg_sync;
- logic [5:0] unused_intr_state_bits;
+ logic [1:0] unused_intr_state_bits;
// Register read signals
logic wkup_enable;
logic [11:0] wkup_prescaler;
@@ -95,7 +95,6 @@
assign aon_hw2reg.wdog_count.d = wdog_count;
assign aon_hw2reg.wkup_cause.d = aon_wkup_req_q;
assign aon_hw2reg.intr_state = '0; // Doesn't come from AON domain
- assign aon_hw2reg.intr_enable = '0; // dummy assignment due to #5260
// Register read values sampled into clk_i domain. These are sampled with a special slow to fast
// synchronizer which captures the value on the negative edge of the slow clock.
@@ -117,7 +116,7 @@
assign hw2reg.wdog_bite_thold.d = hw2reg_sync.wdog_bite_thold.d;
assign hw2reg.wdog_count.d = hw2reg_sync.wdog_count.d;
assign hw2reg.wkup_cause.d = hw2reg_sync.wkup_cause.d;
- assign unused_intr_state_bits = {hw2reg_sync.intr_state, hw2reg_sync.intr_enable};
+ assign unused_intr_state_bits = hw2reg_sync.intr_state;
//////////////////////////////
// Register Write Interface //
@@ -372,9 +371,6 @@
assign hw2reg.intr_state.wdog_timer_expired.d = intr_aon_state_d[AON_WDOG];
assign hw2reg.intr_state.wdog_timer_expired.de = intr_aon_state_de;
- // Dummy interrupt enable to get around #5260
- assign hw2reg.intr_enable = '0;
-
prim_intr_hw #(
.Width (2)
) u_intr_hw (
diff --git a/hw/ip/aon_timer/rtl/aon_timer_reg_pkg.sv b/hw/ip/aon_timer/rtl/aon_timer_reg_pkg.sv
index eb32dc3..c9c190f 100644
--- a/hw/ip/aon_timer/rtl/aon_timer_reg_pkg.sv
+++ b/hw/ip/aon_timer/rtl/aon_timer_reg_pkg.sv
@@ -135,15 +135,6 @@
} aon_timer_hw2reg_intr_state_reg_t;
typedef struct packed {
- struct packed {
- logic d;
- } wkup_timer_expired;
- struct packed {
- logic d;
- } wdog_timer_expired;
- } aon_timer_hw2reg_intr_enable_reg_t;
-
- typedef struct packed {
logic d;
} aon_timer_hw2reg_wkup_cause_reg_t;
@@ -168,15 +159,14 @@
// Internal design logic to register //
///////////////////////////////////////
typedef struct packed {
- aon_timer_hw2reg_wkup_ctrl_reg_t wkup_ctrl; // [181:169]
- aon_timer_hw2reg_wkup_thold_reg_t wkup_thold; // [168:137]
- aon_timer_hw2reg_wkup_count_reg_t wkup_count; // [136:105]
- aon_timer_hw2reg_wdog_ctrl_reg_t wdog_ctrl; // [104:103]
- aon_timer_hw2reg_wdog_bark_thold_reg_t wdog_bark_thold; // [102:71]
- aon_timer_hw2reg_wdog_bite_thold_reg_t wdog_bite_thold; // [70:39]
- aon_timer_hw2reg_wdog_count_reg_t wdog_count; // [38:7]
- aon_timer_hw2reg_intr_state_reg_t intr_state; // [6:3]
- aon_timer_hw2reg_intr_enable_reg_t intr_enable; // [2:1]
+ aon_timer_hw2reg_wkup_ctrl_reg_t wkup_ctrl; // [179:167]
+ aon_timer_hw2reg_wkup_thold_reg_t wkup_thold; // [166:135]
+ aon_timer_hw2reg_wkup_count_reg_t wkup_count; // [134:103]
+ aon_timer_hw2reg_wdog_ctrl_reg_t wdog_ctrl; // [102:101]
+ aon_timer_hw2reg_wdog_bark_thold_reg_t wdog_bark_thold; // [100:69]
+ aon_timer_hw2reg_wdog_bite_thold_reg_t wdog_bite_thold; // [68:37]
+ aon_timer_hw2reg_wdog_count_reg_t wdog_count; // [36:5]
+ aon_timer_hw2reg_intr_state_reg_t intr_state; // [4:1]
aon_timer_hw2reg_wkup_cause_reg_t wkup_cause; // [0:0]
} aon_timer_hw2reg_t;
@@ -190,9 +180,8 @@
parameter logic [BlockAw-1:0] AON_TIMER_WDOG_BITE_THOLD_OFFSET = 6'h 18;
parameter logic [BlockAw-1:0] AON_TIMER_WDOG_COUNT_OFFSET = 6'h 1c;
parameter logic [BlockAw-1:0] AON_TIMER_INTR_STATE_OFFSET = 6'h 20;
- parameter logic [BlockAw-1:0] AON_TIMER_INTR_ENABLE_OFFSET = 6'h 24;
- parameter logic [BlockAw-1:0] AON_TIMER_INTR_TEST_OFFSET = 6'h 28;
- parameter logic [BlockAw-1:0] AON_TIMER_WKUP_CAUSE_OFFSET = 6'h 2c;
+ parameter logic [BlockAw-1:0] AON_TIMER_INTR_TEST_OFFSET = 6'h 24;
+ parameter logic [BlockAw-1:0] AON_TIMER_WKUP_CAUSE_OFFSET = 6'h 28;
// Reset values for hwext registers and their fields
parameter logic [12:0] AON_TIMER_WKUP_CTRL_RESVAL = 13'h 0;
@@ -202,7 +191,6 @@
parameter logic [31:0] AON_TIMER_WDOG_BARK_THOLD_RESVAL = 32'h 0;
parameter logic [31:0] AON_TIMER_WDOG_BITE_THOLD_RESVAL = 32'h 0;
parameter logic [31:0] AON_TIMER_WDOG_COUNT_RESVAL = 32'h 0;
- parameter logic [1:0] AON_TIMER_INTR_ENABLE_RESVAL = 2'h 0;
parameter logic [1:0] AON_TIMER_INTR_TEST_RESVAL = 2'h 0;
parameter logic [0:0] AON_TIMER_WKUP_CAUSE_RESVAL = 1'h 0;
@@ -217,13 +205,12 @@
AON_TIMER_WDOG_BITE_THOLD,
AON_TIMER_WDOG_COUNT,
AON_TIMER_INTR_STATE,
- AON_TIMER_INTR_ENABLE,
AON_TIMER_INTR_TEST,
AON_TIMER_WKUP_CAUSE
} aon_timer_id_e;
// Register width information to check illegal writes
- parameter logic [3:0] AON_TIMER_PERMIT [12] = '{
+ parameter logic [3:0] AON_TIMER_PERMIT [11] = '{
4'b 0011, // index[ 0] AON_TIMER_WKUP_CTRL
4'b 1111, // index[ 1] AON_TIMER_WKUP_THOLD
4'b 1111, // index[ 2] AON_TIMER_WKUP_COUNT
@@ -233,9 +220,8 @@
4'b 1111, // index[ 6] AON_TIMER_WDOG_BITE_THOLD
4'b 1111, // index[ 7] AON_TIMER_WDOG_COUNT
4'b 0001, // index[ 8] AON_TIMER_INTR_STATE
- 4'b 0001, // index[ 9] AON_TIMER_INTR_ENABLE
- 4'b 0001, // index[10] AON_TIMER_INTR_TEST
- 4'b 0001 // index[11] AON_TIMER_WKUP_CAUSE
+ 4'b 0001, // index[ 9] AON_TIMER_INTR_TEST
+ 4'b 0001 // index[10] AON_TIMER_WKUP_CAUSE
};
endpackage
diff --git a/hw/ip/aon_timer/rtl/aon_timer_reg_top.sv b/hw/ip/aon_timer/rtl/aon_timer_reg_top.sv
index 291968b..4253ec6 100644
--- a/hw/ip/aon_timer/rtl/aon_timer_reg_top.sv
+++ b/hw/ip/aon_timer/rtl/aon_timer_reg_top.sv
@@ -144,14 +144,6 @@
logic intr_state_wdog_timer_expired_qs;
logic intr_state_wdog_timer_expired_wd;
logic intr_state_wdog_timer_expired_we;
- logic intr_enable_wkup_timer_expired_qs;
- logic intr_enable_wkup_timer_expired_wd;
- logic intr_enable_wkup_timer_expired_we;
- logic intr_enable_wkup_timer_expired_re;
- logic intr_enable_wdog_timer_expired_qs;
- logic intr_enable_wdog_timer_expired_wd;
- logic intr_enable_wdog_timer_expired_we;
- logic intr_enable_wdog_timer_expired_re;
logic intr_test_wkup_timer_expired_wd;
logic intr_test_wkup_timer_expired_we;
logic intr_test_wdog_timer_expired_wd;
@@ -391,38 +383,6 @@
);
- // R[intr_enable]: V(True)
-
- // F[wkup_timer_expired]: 0:0
- prim_subreg_ext #(
- .DW (1)
- ) u_intr_enable_wkup_timer_expired (
- .re (intr_enable_wkup_timer_expired_re),
- .we (intr_enable_wkup_timer_expired_we),
- .wd (intr_enable_wkup_timer_expired_wd),
- .d (hw2reg.intr_enable.wkup_timer_expired.d),
- .qre (),
- .qe (),
- .q (),
- .qs (intr_enable_wkup_timer_expired_qs)
- );
-
-
- // F[wdog_timer_expired]: 1:1
- prim_subreg_ext #(
- .DW (1)
- ) u_intr_enable_wdog_timer_expired (
- .re (intr_enable_wdog_timer_expired_re),
- .we (intr_enable_wdog_timer_expired_we),
- .wd (intr_enable_wdog_timer_expired_wd),
- .d (hw2reg.intr_enable.wdog_timer_expired.d),
- .qre (),
- .qe (),
- .q (),
- .qs (intr_enable_wdog_timer_expired_qs)
- );
-
-
// R[intr_test]: V(True)
// F[wkup_timer_expired]: 0:0
@@ -473,7 +433,7 @@
- logic [11:0] addr_hit;
+ logic [10:0] addr_hit;
always_comb begin
addr_hit = '0;
addr_hit[ 0] = (reg_addr == AON_TIMER_WKUP_CTRL_OFFSET);
@@ -485,9 +445,8 @@
addr_hit[ 6] = (reg_addr == AON_TIMER_WDOG_BITE_THOLD_OFFSET);
addr_hit[ 7] = (reg_addr == AON_TIMER_WDOG_COUNT_OFFSET);
addr_hit[ 8] = (reg_addr == AON_TIMER_INTR_STATE_OFFSET);
- addr_hit[ 9] = (reg_addr == AON_TIMER_INTR_ENABLE_OFFSET);
- addr_hit[10] = (reg_addr == AON_TIMER_INTR_TEST_OFFSET);
- addr_hit[11] = (reg_addr == AON_TIMER_WKUP_CAUSE_OFFSET);
+ addr_hit[ 9] = (reg_addr == AON_TIMER_INTR_TEST_OFFSET);
+ addr_hit[10] = (reg_addr == AON_TIMER_WKUP_CAUSE_OFFSET);
end
assign addrmiss = (reg_re || reg_we) ? ~|addr_hit : 1'b0 ;
@@ -506,7 +465,6 @@
if (addr_hit[ 8] && reg_we && (AON_TIMER_PERMIT[ 8] != (AON_TIMER_PERMIT[ 8] & reg_be))) wr_err = 1'b1 ;
if (addr_hit[ 9] && reg_we && (AON_TIMER_PERMIT[ 9] != (AON_TIMER_PERMIT[ 9] & reg_be))) wr_err = 1'b1 ;
if (addr_hit[10] && reg_we && (AON_TIMER_PERMIT[10] != (AON_TIMER_PERMIT[10] & reg_be))) wr_err = 1'b1 ;
- if (addr_hit[11] && reg_we && (AON_TIMER_PERMIT[11] != (AON_TIMER_PERMIT[11] & reg_be))) wr_err = 1'b1 ;
end
assign wkup_ctrl_enable_we = addr_hit[0] & reg_we & !reg_error;
@@ -554,23 +512,15 @@
assign intr_state_wdog_timer_expired_we = addr_hit[8] & reg_we & !reg_error;
assign intr_state_wdog_timer_expired_wd = reg_wdata[1];
- assign intr_enable_wkup_timer_expired_we = addr_hit[9] & reg_we & !reg_error;
- assign intr_enable_wkup_timer_expired_wd = reg_wdata[0];
- assign intr_enable_wkup_timer_expired_re = addr_hit[9] & reg_re & !reg_error;
-
- assign intr_enable_wdog_timer_expired_we = addr_hit[9] & reg_we & !reg_error;
- assign intr_enable_wdog_timer_expired_wd = reg_wdata[1];
- assign intr_enable_wdog_timer_expired_re = addr_hit[9] & reg_re & !reg_error;
-
- assign intr_test_wkup_timer_expired_we = addr_hit[10] & reg_we & !reg_error;
+ assign intr_test_wkup_timer_expired_we = addr_hit[9] & reg_we & !reg_error;
assign intr_test_wkup_timer_expired_wd = reg_wdata[0];
- assign intr_test_wdog_timer_expired_we = addr_hit[10] & reg_we & !reg_error;
+ assign intr_test_wdog_timer_expired_we = addr_hit[9] & reg_we & !reg_error;
assign intr_test_wdog_timer_expired_wd = reg_wdata[1];
- assign wkup_cause_we = addr_hit[11] & reg_we & !reg_error;
+ assign wkup_cause_we = addr_hit[10] & reg_we & !reg_error;
assign wkup_cause_wd = reg_wdata[0];
- assign wkup_cause_re = addr_hit[11] & reg_re & !reg_error;
+ assign wkup_cause_re = addr_hit[10] & reg_re & !reg_error;
// Read data return
always_comb begin
@@ -616,16 +566,11 @@
end
addr_hit[9]: begin
- reg_rdata_next[0] = intr_enable_wkup_timer_expired_qs;
- reg_rdata_next[1] = intr_enable_wdog_timer_expired_qs;
- end
-
- addr_hit[10]: begin
reg_rdata_next[0] = '0;
reg_rdata_next[1] = '0;
end
- addr_hit[11]: begin
+ addr_hit[10]: begin
reg_rdata_next[0] = wkup_cause_qs;
end
