[entropy_src/rtl] config bit to field conversion
The enable bits have been expanded to 4 bits per funtion to provide a counter meansure for attacks on register bits.
Signed-off-by: Mark Branstad <mark.branstad@wdc.com>
diff --git a/hw/ip/entropy_src/data/entropy_src.hjson b/hw/ip/entropy_src/data/entropy_src.hjson
index fcecf33..c7eb7d0 100644
--- a/hw/ip/entropy_src/data/entropy_src.hjson
+++ b/hw/ip/entropy_src/data/entropy_src.hjson
@@ -89,9 +89,8 @@
registers: [
{ name: "REGWEN",
desc: "Register write enable for all control registers",
- swaccess: "ro", // lock is managed by HW
- hwaccess: "hwo",
- hwext: "true",
+ swaccess: "rw0c",
+ hwaccess: "none",
fields: [
{
bits: "0",
@@ -128,48 +127,60 @@
desc: "Configuration register",
swaccess: "rw",
hwaccess: "hro",
+ hwqe: "true",
+ regwen: "REGWEN",
+ tags: [// Exclude from writes to these field because they cause side affects.
+ "excl:CsrAllTests:CsrExclAll"]
+// TODO: fix up exclusions after env is fixed
+// "excl:CsrAllTests:CsrExclWrite"]
fields: [
- { bits: "1:0",
+ { bits: "3:0",
name: "ENABLE",
- desc: '''This field is the module enable for the ENTROPY_SRC entropy generation function.
- This two bit field determines what source will be used for all processing:
- 0b00: Disabled
- 0b01: PTRNG mode enabled
- 0b10: LFSR mode enabled
- 0b11: Reserved
+ desc: '''
+ Setting this field to 0xA will enable the ENTROPY_SRC module.
'''
- tags: [// Exclude from writes to these bits to avoid Xs from entropy FIFO.
- "excl:CsrAllTests:CsrExclWrite"]
- }
- { bits: "3",
+ resval: "0x5"
+ },
+ { bits: "7:4",
+ name: "ENTROPY_DATA_REG_ENABLE",
+ desc: '''
+ Setting this field to 0xA will enable reading entropy values from the
+ ENTROPY_DATA register. This function also requires that the efuse_es_sw_reg_en
+ input is set.
+ '''
+ resval: "0x5"
+ },
+ { bits: "11:8",
+ name: "LFSR_ENABLE",
+ desc: '''
+ Setting this field to 0xA will enable the ENTROPY_SRC LFSR mode.
+ '''
+ resval: "0x5"
+ },
+ { bits: "15:12",
name: "BOOT_BYPASS_DISABLE",
- desc: "Setting this bit disables the initial generation of non-FIPS entropy."
- }
- { bits: "4",
- name: "REPCNT_DISABLE",
- desc: "Setting this bit disables the health test called Repetition Count test."
- }
- { bits: "5",
- name: "ADAPTP_DISABLE",
- desc: "Setting this bit disables the health test called Adaptive Proportion test."
- }
- { bits: "6",
- name: "BUCKET_DISABLE",
- desc: "Setting this bit disables the health test called Bucket test."
- }
- { bits: "7",
- name: "MARKOV_DISABLE",
- desc: "Setting this bit disables the health test called Markov test."
- }
- { bits: "8",
+ desc: '''
+ Setting this field to 0xA will disables the initial generation of non-FIPS entropy.
+ '''
+ resval: "0x5"
+ },
+ { bits: "19:16",
name: "HEALTH_TEST_CLR",
- desc: "Setting this bit will clear all registers related to the health test operations."
- }
- { bits: "9",
- name: "RNG_BIT_EN",
- desc: "Setting this bit enables the single RNG bit mode, where only one bit is sampled."
- }
- { bits: "11:10",
+ desc: '''
+ Setting this field to 0xA will clear all registers related to the
+ health test operations.
+ '''
+ resval: "0x5"
+ },
+ { bits: "23:20",
+ name: "RNG_BIT_ENABLE",
+ desc: '''
+ Setting this field to 0xA enables the single RNG bit mode, where only
+ one bit is sampled.
+ '''
+ resval: "0x5"
+ },
+ { bits: "25:24",
name: "RNG_BIT_SEL",
desc: '''When the above bit iset, this field selects which bit from the RNG bus will
be processed when in single RNG bit mode.
@@ -180,18 +191,6 @@
0b11: RNG bit 3
'''
}
- { bits: "12",
- name: "EXTHT_ENABLE",
- desc: '''Setting this bit enables the hardware-based health test that is external
- to ENTROPY_SRC."
- '''
- }
- { bits: "13",
- name: "REPCNTS_DISABLE",
- desc: '''Setting this bit disables the health test called Repetition Count test,
- which is based on counting symbols.
- '''
- }
]
},
{ name: "RATE",
@@ -213,22 +212,30 @@
desc: "Entropy control register",
swaccess: "rw",
hwaccess: "hro",
+ hwqe: "true",
regwen: "REGWEN",
+ tags: [// Exclude from writes to these field because they cause side affects.
+ "excl:CsrAllTests:CsrExclAll"]
+// TODO: remove above tag when working
fields: [
- { bits: "0",
+ { bits: "3:0",
name: "ES_ROUTE",
- desc: '''Setting this bit routes the generated entropy value to the ENTROPY_DATA
- register to be read by firmware. When this bit is zero, the generated
+ desc: '''
+ Setting this field to 0xA routes the generated entropy value to the ENTROPY_DATA
+ register to be read by firmware. When this field is 0x5, the generated
entropy will be forwarded out of this module to the hardware interface.
'''
- }
- { bits: "1",
+ resval: "0x5"
+ },
+ { bits: "7:4",
name: "ES_TYPE",
- desc: '''Setting this bit will bypass the conditioning logic and bring raw entropy
- data to the ENTROPY_DATA register. When zero, FIPS compliant entropy
+ desc: '''
+ Setting this field to 0xA will bypass the conditioning logic and bring raw entropy
+ data to the ENTROPY_DATA register. When 0x5, FIPS compliant entropy
will be brought the ENTROPY_DATA register, after being conditioned.
'''
- }
+ resval: "0x5"
+ },
]
},
{ name: "ENTROPY_DATA",
@@ -1001,24 +1008,31 @@
desc: "Firmware override control register",
swaccess: "rw",
hwaccess: "hro",
+ hwqe: "true",
regwen: "REGWEN",
fields: [
- { bits: "0",
+ { bits: "3:0",
name: "FW_OV_MODE",
- desc: '''Setting this bit will put the entropy flow in firmware override mode.
+ desc: '''
+ Setting this field to 0xA will put the entropy flow in firmware override mode.
In this mode, firmware can monitor the post-health test entropy by reading
- the observe FIFO.
+ the observe FIFO. This function also requires that the efuse_es_sw_ov_en
+ input is set.
'''
- }
- { bits: "1",
+ resval: "0x5"
+ },
+ { bits: "7:4",
name: "FW_OV_ENTROPY_INSERT",
- desc: '''Setting this bit will switch the input into the pre-conditioner packer FIFO.
- Firmware can directly write into the packer FIFO, enabling the ability to insert
- entropy bits back into the hardware flow. Firmware can read data from the health
- check packer FIFO, then do optional health checks or optional conditioning, then
- insert the results back into the flow. Also, the !!FW_OV_MODE bit must be set.
+ desc: '''
+ Setting this field to 0xA will switch the input into the pre-conditioner
+ packer FIFO. Firmware can directly write into the packer FIFO, enabling
+ the ability to insert entropy bits back into the hardware flow. Firmware
+ can read data from the health check packer FIFO, then do optional health
+ checks or optional conditioning, then insert the results back into the flow.
+ Also, the !!FW_OV_MODE bit must be set.
'''
- }
+ resval: "0x5"
+ },
]
},
{ name: "FW_OV_RD_DATA",
diff --git a/hw/ip/entropy_src/dv/env/seq_lib/entropy_src_base_vseq.sv b/hw/ip/entropy_src/dv/env/seq_lib/entropy_src_base_vseq.sv
index 999989f..f3c7864 100644
--- a/hw/ip/entropy_src/dv/env/seq_lib/entropy_src_base_vseq.sv
+++ b/hw/ip/entropy_src/dv/env/seq_lib/entropy_src_base_vseq.sv
@@ -36,13 +36,23 @@
cfg.efuse_es_sw_reg_en_vif.drive_pin(.idx(0), .val(cfg.efuse_es_sw_reg_en));
// Set entropy_src controls
- ral.entropy_control.es_type.set(cfg.type_bypass);
- ral.entropy_control.es_route.set(cfg.route_software);
+ // TODO: hardcode for now, fix up contraints
+ // ral.entropy_control.es_type.set(cfg.type_bypass);
+ // ral.entropy_control.es_route.set(cfg.route_software);
+ // csr_update(.csr(ral.entropy_control));
+ ral.entropy_control.es_type.set(4'h5);
+ ral.entropy_control.es_route.set(4'ha);
csr_update(.csr(ral.entropy_control));
// Enable entropy_src in ptrng or lfsr mode
- ral.conf.enable.set(cfg.mode);
- ral.conf.boot_bypass_disable.set(cfg.boot_bypass_disable);
+ // TODO: hardcode for now, fix up contraints
+ // ral.conf.enable.set(cfg.mode);
+ // ral.conf.boot_bypass_disable.set(cfg.boot_bypass_disable);
+ ral.entropy_control.es_route.set(4'ha);
+ csr_update(.csr(ral.entropy_control));
+ ral.conf.enable.set(4'ha);
+ ral.conf.entropy_data_reg_enable.set(4'ha);
+ ral.conf.boot_bypass_disable.set(4'h5);
csr_update(.csr(ral.conf));
endtask
diff --git a/hw/ip/entropy_src/rtl/entropy_src_core.sv b/hw/ip/entropy_src/rtl/entropy_src_core.sv
index eaca429..9e0a90e 100644
--- a/hw/ip/entropy_src/rtl/entropy_src_core.sv
+++ b/hw/ip/entropy_src/rtl/entropy_src_core.sv
@@ -62,6 +62,8 @@
localparam int ObserveFifoDepth = 64;
localparam int PreCondWidth = 64;
localparam int Clog2ObserveFifoDepth = $clog2(ObserveFifoDepth);
+ // TODO: remove or enable below
+ // localparam int FieldEnableWidth = 4;
//-----------------------
// SHA3 parameters
@@ -78,17 +80,24 @@
logic [RngBusWidth-1:0] seed_value;
logic load_seed;
logic fw_ov_mode;
+ logic fw_ov_mode_pfe;
logic fw_ov_entropy_insert;
+ logic fw_ov_entropy_insert_pfe;
logic [ObserveFifoWidth-1:0] fw_ov_wr_data;
logic fw_ov_fifo_rd_pulse;
logic fw_ov_fifo_wr_pulse;
logic es_enable;
+ logic es_enable_pfe;
logic es_enable_early;
logic es_enable_lfsr;
logic es_enable_rng;
logic rng_bit_en;
+ logic rng_bit_en_pfe;
logic [1:0] rng_bit_sel;
logic lfsr_incr;
+ logic lfsr_enable_pfe;
+ logic entropy_data_reg_en_pfe;
+ logic es_data_reg_rd_en;
logic sw_es_rd_pulse;
logic event_es_entropy_valid;
logic event_es_health_test_failed;
@@ -149,15 +158,19 @@
logic extht_active;
logic alert_cntrs_clr;
logic health_test_clr;
+ logic health_test_clr_pfe;
logic health_test_done_pulse;
logic [RngBusWidth-1:0] health_test_esbus;
logic health_test_esbus_vld;
+ logic es_route_pfe;
+ logic es_type_pfe;
logic es_route_to_sw;
logic es_bypass_to_sw;
logic es_bypass_mode;
logic rst_bypass_mode;
logic rst_alert_cntr;
logic boot_bypass_disable;
+ logic boot_bypass_dis_pfe;
logic fips_compliance;
logic [HalfRegWidth-1:0] health_test_fips_window;
@@ -368,6 +381,7 @@
logic unused_sha3_state;
logic unused_entropy_data;
logic unused_fw_ov_rd_data;
+ logic unused_rng_bit_sel;
// flops
logic [15:0] es_rate_cntr_q, es_rate_cntr_d;
@@ -424,18 +438,95 @@
es_rdata_capt_vld_q <= es_rdata_capt_vld_d;
end
- assign es_enable_d = reg2hw.conf.enable.q;
- assign es_enable_early = (|reg2hw.conf.enable.q);
+
+ //--------------------------------------------
+ // set up secure enable bits
+ //--------------------------------------------
+
+ // TODO: remove or enable prim_field_enable
+// prim_field_enable #(
+// .FieldW(FieldEnableWidth),
+// .FieldEnVal(int'(ES_FIELD_ON))
+// ) u_prim_field_enable_es_enable (
+// .clk_i (clk_i),
+// .rst_ni (rst_ni),
+// .wvalid_i (reg2hw.conf.enable.qe),
+// .wdata_i (reg2hw.conf.enable.q),
+// .enable_o (es_enable_pfe)
+// );
+
+ assign es_enable_pfe = (es_enb_e'(reg2hw.conf.enable.q) == ES_FIELD_ON);
+
+ // TODO: remove or enable prim_field_enable
+// prim_field_enable #(
+// .FieldW(FieldEnableWidth),
+// .FieldEnVal(int'(ES_FIELD_ON))
+// ) u_prim_field_enable_lfsr_enable (
+// .clk_i (clk_i),
+// .rst_ni (rst_ni),
+// .wvalid_i (reg2hw.conf.lfsr_enable.qe),
+// .wdata_i (reg2hw.conf.lfsr_enable.q),
+// .enable_o (lfsr_enable_pfe)
+// );
+
+ assign lfsr_enable_pfe = (es_enb_e'(reg2hw.conf.lfsr_enable.q) == ES_FIELD_ON);
+
+ // TODO: remove or enable prim_field_enable
+// prim_field_enable #(
+// .FieldW(FieldEnableWidth),
+// .FieldEnVal(int'(ES_FIELD_ON))
+// ) u_prim_field_enable_entropy_data_reg_en (
+// .clk_i (clk_i),
+// .rst_ni (rst_ni),
+// .wvalid_i (reg2hw.conf.entropy_data_reg_enable.qe),
+// .wdata_i (reg2hw.conf.entropy_data_reg_enable.q),
+// .enable_o (entropy_data_reg_en_pfe)
+// );
+
+ assign entropy_data_reg_en_pfe =
+ (es_enb_e'(reg2hw.conf.entropy_data_reg_enable.q) == ES_FIELD_ON);
+
+// assign es_enable_d = reg2hw.conf.enable.q; // TODO: remove
+ assign es_enable_d = {lfsr_enable_pfe,es_enable_pfe};
+ assign es_enable_early = lfsr_enable_pfe || es_enable_pfe;
assign es_enable = (|es_enable_q);
assign es_enable_lfsr = es_enable_q[1];
assign es_enable_rng = es_enable_q[0];
assign load_seed = !es_enable;
- assign hw2reg.regwen.d = !es_enable; // hw reg lock implementation
assign observe_fifo_thresh = reg2hw.observe_fifo_thresh.q;
+ // TODO: remove or enable prim_field_enable
+// prim_field_enable #(
+// .FieldW(FieldEnableWidth),
+// .FieldEnVal(int'(ES_FIELD_ON))
+// ) u_prim_field_enable_fw_ov_mode (
+// .clk_i (clk_i),
+// .rst_ni (rst_ni),
+// .wvalid_i (reg2hw.fw_ov_control.fw_ov_mode.qe),
+// .wdata_i (reg2hw.fw_ov_control.fw_ov_mode.q),
+// .enable_o (fw_ov_mode_pfe)
+// );
+
+ assign fw_ov_mode_pfe = (es_enb_e'(reg2hw.fw_ov_control.fw_ov_mode.q) == ES_FIELD_ON);
+
+ // TODO: remove or enable prim_field_enable
+// prim_field_enable #(
+// .FieldW(FieldEnableWidth),
+// .FieldEnVal(int'(ES_FIELD_ON))
+// ) u_prim_field_enable_fw_ov_entropy_insert (
+// .clk_i (clk_i),
+// .rst_ni (rst_ni),
+// .wvalid_i (reg2hw.fw_ov_control.fw_ov_entropy_insert.qe),
+// .wdata_i (reg2hw.fw_ov_control.fw_ov_entropy_insert.q),
+// .enable_o (fw_ov_entropy_insert_pfe)
+// );
+
+ assign fw_ov_entropy_insert_pfe =
+ (es_enb_e'(reg2hw.fw_ov_control.fw_ov_entropy_insert.q) == ES_FIELD_ON);
+
// firmware override controls
- assign fw_ov_mode = efuse_es_sw_ov_en_i && reg2hw.fw_ov_control.fw_ov_mode.q;
- assign fw_ov_entropy_insert = reg2hw.fw_ov_control.fw_ov_entropy_insert.q;
+ assign fw_ov_mode = efuse_es_sw_ov_en_i && fw_ov_mode_pfe;
+ assign fw_ov_entropy_insert = fw_ov_entropy_insert_pfe;
assign fw_ov_fifo_rd_pulse = reg2hw.fw_ov_rd_data.re;
assign hw2reg.fw_ov_rd_data.d = sfifo_observe_rdata;
assign fw_ov_fifo_wr_pulse = reg2hw.fw_ov_wr_data.qe;
@@ -702,7 +793,21 @@
// pack esrng bus into signal bit packer
- assign rng_bit_en = reg2hw.conf.rng_bit_en.q;
+ // TODO: remove or enable prim_field_enable
+// prim_field_enable #(
+// .FieldW(FieldEnableWidth),
+// .FieldEnVal(int'(ES_FIELD_ON))
+// ) u_prim_field_enable_rng_bit_en (
+// .clk_i (clk_i),
+// .rst_ni (rst_ni),
+// .wvalid_i (reg2hw.conf.rng_bit_enable.qe),
+// .wdata_i (reg2hw.conf.rng_bit_enable.q),
+// .enable_o (rng_bit_en_pfe)
+// );
+
+ assign rng_bit_en_pfe = (es_enb_e'(reg2hw.conf.rng_bit_enable.q) == ES_FIELD_ON);
+
+ assign rng_bit_en = rng_bit_en_pfe;
assign rng_bit_sel = reg2hw.conf.rng_bit_sel.q;
prim_packer_fifo #(
@@ -745,14 +850,28 @@
assign ht_esbus_dly_d = es_enable ? health_test_esbus : '0;
assign ht_esbus_vld_dly2_d = es_enable && ht_esbus_vld_dly_q;
- assign repcnt_active = !reg2hw.conf.repcnt_disable.q && es_enable;
- assign repcnts_active = !reg2hw.conf.repcnts_disable.q && es_enable;
- assign adaptp_active = !reg2hw.conf.adaptp_disable.q && es_enable;
- assign bucket_active = !reg2hw.conf.bucket_disable.q && es_enable;
- assign markov_active = !reg2hw.conf.markov_disable.q && es_enable;
- assign extht_active = reg2hw.conf.extht_enable.q && es_enable;
+ assign repcnt_active = es_enable;
+ assign repcnts_active = es_enable;
+ assign adaptp_active = es_enable;
+ assign bucket_active = es_enable;
+ assign markov_active = es_enable;
+ assign extht_active = es_enable;
- assign health_test_clr = reg2hw.conf.health_test_clr.q;
+ // TODO: remove or enable prim_field_enable
+// prim_field_enable #(
+// .FieldW(FieldEnableWidth),
+// .FieldEnVal(int'(ES_FIELD_ON))
+// ) u_prim_field_enable_health_test_clr (
+// .clk_i (clk_i),
+// .rst_ni (rst_ni),
+// .wvalid_i (reg2hw.conf.health_test_clr.qe),
+// .wdata_i (reg2hw.conf.health_test_clr.q),
+// .enable_o (health_test_clr_pfe)
+// );
+
+ assign health_test_clr_pfe = (es_enb_e'(reg2hw.conf.health_test_clr.q) == ES_FIELD_ON);
+
+ assign health_test_clr = health_test_clr_pfe;
assign health_test_fips_window = reg2hw.health_test_windows.fips_window.q;
assign health_test_bypass_window = reg2hw.health_test_windows.bypass_window.q;
@@ -1121,9 +1240,51 @@
assign event_es_health_test_failed = es_main_sm_alert;
assign event_es_observe_fifo_ready = observe_fifo_thresh_met;
- assign es_route_to_sw = reg2hw.entropy_control.es_route.q;
- assign es_bypass_to_sw = reg2hw.entropy_control.es_type.q;
- assign boot_bypass_disable = reg2hw.conf.boot_bypass_disable.q;
+ // TODO: remove or enable prim_field_enable
+// prim_field_enable #(
+// .FieldW(FieldEnableWidth),
+// .FieldEnVal(int'(ES_FIELD_ON))
+// ) u_prim_field_enable_es_route (
+// .clk_i (clk_i),
+// .rst_ni (rst_ni),
+// .wvalid_i (reg2hw.entropy_control.es_route.qe),
+// .wdata_i (reg2hw.entropy_control.es_route.q),
+// .enable_o (es_route_pfe)
+// );
+
+ assign es_route_pfe = (es_enb_e'(reg2hw.entropy_control.es_route.q) == ES_FIELD_ON);
+
+ // TODO: remove or enable prim_field_enable
+// prim_field_enable #(
+// .FieldW(FieldEnableWidth),
+// .FieldEnVal(int'(ES_FIELD_ON))
+// ) u_prim_field_enable_es_type (
+// .clk_i (clk_i),
+// .rst_ni (rst_ni),
+// .wvalid_i (reg2hw.entropy_control.es_type.qe),
+// .wdata_i (reg2hw.entropy_control.es_type.q),
+// .enable_o (es_type_pfe)
+// );
+
+ assign es_type_pfe = (es_enb_e'(reg2hw.entropy_control.es_type.q) == ES_FIELD_ON);
+
+ // TODO: remove or enable prim_field_enable
+// prim_field_enable #(
+// .FieldW(FieldEnableWidth),
+// .FieldEnVal(int'(ES_FIELD_ON))
+// ) u_prim_field_enable_boot_bypass_dis (
+// .clk_i (clk_i),
+// .rst_ni (rst_ni),
+// .wvalid_i (reg2hw.conf.boot_bypass_disable.qe),
+// .wdata_i (reg2hw.conf.boot_bypass_disable.q),
+// .enable_o (boot_bypass_dis_pfe)
+// );
+
+ assign boot_bypass_dis_pfe = (es_enb_e'(reg2hw.conf.boot_bypass_disable.q) == ES_FIELD_ON);
+
+ assign es_route_to_sw = es_route_pfe;
+ assign es_bypass_to_sw = es_type_pfe;
+ assign boot_bypass_disable = boot_bypass_dis_pfe;
assign boot_bypass_d =
(!es_enable_early) ? 1'b1 : // special case for reset
@@ -2179,8 +2340,9 @@
assign pfifo_swread_pop = es_enable && sw_es_rd_pulse;
// set the es entropy to the read reg
- assign hw2reg.entropy_data.d = es_enable ? pfifo_swread_rdata : '0;
- assign sw_es_rd_pulse = efuse_es_sw_reg_en_i && reg2hw.entropy_data.re;
+ assign es_data_reg_rd_en = es_enable && efuse_es_sw_reg_en_i && entropy_data_reg_en_pfe;
+ assign hw2reg.entropy_data.d = es_data_reg_rd_en ? pfifo_swread_rdata : '0;
+ assign sw_es_rd_pulse = es_data_reg_rd_en && reg2hw.entropy_data.re;
//--------------------------------------------
// unused signals
@@ -2190,6 +2352,17 @@
assign unused_sha3_state = (|sha3_state[0][sha3_pkg::StateW-1:SeedLen]);
assign unused_entropy_data = (|reg2hw.entropy_data.q);
assign unused_fw_ov_rd_data = (|reg2hw.fw_ov_rd_data.q);
-
+ assign unused_rng_bit_sel = reg2hw.conf.rng_bit_sel.qe ||
+ // TODO: remove or enable these
+ reg2hw.conf.enable.qe ||
+ reg2hw.conf.lfsr_enable.qe ||
+ reg2hw.conf.entropy_data_reg_enable.qe ||
+ reg2hw.fw_ov_control.fw_ov_mode.qe ||
+ reg2hw.fw_ov_control.fw_ov_entropy_insert.qe ||
+ reg2hw.conf.rng_bit_enable.qe ||
+ reg2hw.conf.health_test_clr.qe ||
+ reg2hw.entropy_control.es_route.qe ||
+ reg2hw.entropy_control.es_type.qe ||
+ reg2hw.conf.boot_bypass_disable.qe;
endmodule
diff --git a/hw/ip/entropy_src/rtl/entropy_src_pkg.sv b/hw/ip/entropy_src/rtl/entropy_src_pkg.sv
index accba47..48406e0 100644
--- a/hw/ip/entropy_src/rtl/entropy_src_pkg.sv
+++ b/hw/ip/entropy_src/rtl/entropy_src_pkg.sv
@@ -74,4 +74,10 @@
parameter entropy_src_xht_req_t ENTROPY_SRC_XHT_REQ_DEFAULT = '{default: '0};
parameter entropy_src_xht_rsp_t ENTROPY_SRC_XHT_RSP_DEFAULT = '{default: '0};
+ // Sparse four-value signal type
+ parameter int ES_MODE_WIDTH = 4;
+ typedef enum logic [ES_MODE_WIDTH-1:0] {
+ ES_FIELD_ON = 4'b1010
+ } es_enb_e;
+
endpackage : entropy_src_pkg
diff --git a/hw/ip/entropy_src/rtl/entropy_src_reg_pkg.sv b/hw/ip/entropy_src/rtl/entropy_src_reg_pkg.sv
index eef59cd..2038ebe 100644
--- a/hw/ip/entropy_src/rtl/entropy_src_reg_pkg.sv
+++ b/hw/ip/entropy_src/rtl/entropy_src_reg_pkg.sv
@@ -78,38 +78,33 @@
typedef struct packed {
struct packed {
- logic [1:0] q;
+ logic [3:0] q;
+ logic qe;
} enable;
struct packed {
- logic q;
+ logic [3:0] q;
+ logic qe;
+ } entropy_data_reg_enable;
+ struct packed {
+ logic [3:0] q;
+ logic qe;
+ } lfsr_enable;
+ struct packed {
+ logic [3:0] q;
+ logic qe;
} boot_bypass_disable;
struct packed {
- logic q;
- } repcnt_disable;
- struct packed {
- logic q;
- } adaptp_disable;
- struct packed {
- logic q;
- } bucket_disable;
- struct packed {
- logic q;
- } markov_disable;
- struct packed {
- logic q;
+ logic [3:0] q;
+ logic qe;
} health_test_clr;
struct packed {
- logic q;
- } rng_bit_en;
+ logic [3:0] q;
+ logic qe;
+ } rng_bit_enable;
struct packed {
logic [1:0] q;
+ logic qe;
} rng_bit_sel;
- struct packed {
- logic q;
- } extht_enable;
- struct packed {
- logic q;
- } repcnts_disable;
} entropy_src_reg2hw_conf_reg_t;
typedef struct packed {
@@ -118,10 +113,12 @@
typedef struct packed {
struct packed {
- logic q;
+ logic [3:0] q;
+ logic qe;
} es_route;
struct packed {
- logic q;
+ logic [3:0] q;
+ logic qe;
} es_type;
} entropy_src_reg2hw_entropy_control_reg_t;
@@ -249,10 +246,12 @@
typedef struct packed {
struct packed {
- logic q;
+ logic [3:0] q;
+ logic qe;
} fw_ov_mode;
struct packed {
- logic q;
+ logic [3:0] q;
+ logic qe;
} fw_ov_entropy_insert;
} entropy_src_reg2hw_fw_ov_control_reg_t;
@@ -299,10 +298,6 @@
} entropy_src_hw2reg_intr_state_reg_t;
typedef struct packed {
- logic d;
- } entropy_src_hw2reg_regwen_reg_t;
-
- typedef struct packed {
logic [31:0] d;
} entropy_src_hw2reg_entropy_data_reg_t;
@@ -620,26 +615,26 @@
// Register -> HW type
typedef struct packed {
- entropy_src_reg2hw_intr_state_reg_t intr_state; // [538:535]
- entropy_src_reg2hw_intr_enable_reg_t intr_enable; // [534:531]
- entropy_src_reg2hw_intr_test_reg_t intr_test; // [530:523]
- entropy_src_reg2hw_alert_test_reg_t alert_test; // [522:519]
- entropy_src_reg2hw_conf_reg_t conf; // [518:506]
- entropy_src_reg2hw_rate_reg_t rate; // [505:490]
- entropy_src_reg2hw_entropy_control_reg_t entropy_control; // [489:488]
- entropy_src_reg2hw_entropy_data_reg_t entropy_data; // [487:455]
- entropy_src_reg2hw_health_test_windows_reg_t health_test_windows; // [454:423]
- entropy_src_reg2hw_repcnt_thresholds_reg_t repcnt_thresholds; // [422:389]
- entropy_src_reg2hw_repcnts_thresholds_reg_t repcnts_thresholds; // [388:355]
- entropy_src_reg2hw_adaptp_hi_thresholds_reg_t adaptp_hi_thresholds; // [354:321]
- entropy_src_reg2hw_adaptp_lo_thresholds_reg_t adaptp_lo_thresholds; // [320:287]
- entropy_src_reg2hw_bucket_thresholds_reg_t bucket_thresholds; // [286:253]
- entropy_src_reg2hw_markov_hi_thresholds_reg_t markov_hi_thresholds; // [252:219]
- entropy_src_reg2hw_markov_lo_thresholds_reg_t markov_lo_thresholds; // [218:185]
- entropy_src_reg2hw_extht_hi_thresholds_reg_t extht_hi_thresholds; // [184:151]
- entropy_src_reg2hw_extht_lo_thresholds_reg_t extht_lo_thresholds; // [150:117]
- entropy_src_reg2hw_alert_threshold_reg_t alert_threshold; // [116:85]
- entropy_src_reg2hw_fw_ov_control_reg_t fw_ov_control; // [84:83]
+ entropy_src_reg2hw_intr_state_reg_t intr_state; // [574:571]
+ entropy_src_reg2hw_intr_enable_reg_t intr_enable; // [570:567]
+ entropy_src_reg2hw_intr_test_reg_t intr_test; // [566:559]
+ entropy_src_reg2hw_alert_test_reg_t alert_test; // [558:555]
+ entropy_src_reg2hw_conf_reg_t conf; // [554:522]
+ entropy_src_reg2hw_rate_reg_t rate; // [521:506]
+ entropy_src_reg2hw_entropy_control_reg_t entropy_control; // [505:496]
+ entropy_src_reg2hw_entropy_data_reg_t entropy_data; // [495:463]
+ entropy_src_reg2hw_health_test_windows_reg_t health_test_windows; // [462:431]
+ entropy_src_reg2hw_repcnt_thresholds_reg_t repcnt_thresholds; // [430:397]
+ entropy_src_reg2hw_repcnts_thresholds_reg_t repcnts_thresholds; // [396:363]
+ entropy_src_reg2hw_adaptp_hi_thresholds_reg_t adaptp_hi_thresholds; // [362:329]
+ entropy_src_reg2hw_adaptp_lo_thresholds_reg_t adaptp_lo_thresholds; // [328:295]
+ entropy_src_reg2hw_bucket_thresholds_reg_t bucket_thresholds; // [294:261]
+ entropy_src_reg2hw_markov_hi_thresholds_reg_t markov_hi_thresholds; // [260:227]
+ entropy_src_reg2hw_markov_lo_thresholds_reg_t markov_lo_thresholds; // [226:193]
+ entropy_src_reg2hw_extht_hi_thresholds_reg_t extht_hi_thresholds; // [192:159]
+ entropy_src_reg2hw_extht_lo_thresholds_reg_t extht_lo_thresholds; // [158:125]
+ entropy_src_reg2hw_alert_threshold_reg_t alert_threshold; // [124:93]
+ entropy_src_reg2hw_fw_ov_control_reg_t fw_ov_control; // [92:83]
entropy_src_reg2hw_fw_ov_rd_data_reg_t fw_ov_rd_data; // [82:50]
entropy_src_reg2hw_fw_ov_wr_data_reg_t fw_ov_wr_data; // [49:17]
entropy_src_reg2hw_observe_fifo_thresh_reg_t observe_fifo_thresh; // [16:10]
@@ -649,8 +644,7 @@
// HW -> register type
typedef struct packed {
- entropy_src_hw2reg_intr_state_reg_t intr_state; // [1027:1020]
- entropy_src_hw2reg_regwen_reg_t regwen; // [1019:1019]
+ entropy_src_hw2reg_intr_state_reg_t intr_state; // [1026:1019]
entropy_src_hw2reg_entropy_data_reg_t entropy_data; // [1018:987]
entropy_src_hw2reg_repcnt_thresholds_reg_t repcnt_thresholds; // [986:955]
entropy_src_hw2reg_repcnts_thresholds_reg_t repcnts_thresholds; // [954:923]
@@ -750,8 +744,6 @@
parameter logic [1:0] ENTROPY_SRC_ALERT_TEST_RESVAL = 2'h 0;
parameter logic [0:0] ENTROPY_SRC_ALERT_TEST_RECOV_ALERT_RESVAL = 1'h 0;
parameter logic [0:0] ENTROPY_SRC_ALERT_TEST_FATAL_ALERT_RESVAL = 1'h 0;
- parameter logic [0:0] ENTROPY_SRC_REGWEN_RESVAL = 1'h 1;
- parameter logic [0:0] ENTROPY_SRC_REGWEN_REGWEN_RESVAL = 1'h 1;
parameter logic [31:0] ENTROPY_SRC_ENTROPY_DATA_RESVAL = 32'h 0;
parameter logic [31:0] ENTROPY_SRC_REPCNT_THRESHOLDS_RESVAL = 32'h ffffffff;
parameter logic [15:0] ENTROPY_SRC_REPCNT_THRESHOLDS_FIPS_THRESH_RESVAL = 16'h ffff;
@@ -874,7 +866,7 @@
4'b 0001, // index[ 3] ENTROPY_SRC_ALERT_TEST
4'b 0001, // index[ 4] ENTROPY_SRC_REGWEN
4'b 0111, // index[ 5] ENTROPY_SRC_REV
- 4'b 0011, // index[ 6] ENTROPY_SRC_CONF
+ 4'b 1111, // index[ 6] ENTROPY_SRC_CONF
4'b 0011, // index[ 7] ENTROPY_SRC_RATE
4'b 0001, // index[ 8] ENTROPY_SRC_ENTROPY_CONTROL
4'b 1111, // index[ 9] ENTROPY_SRC_ENTROPY_DATA
diff --git a/hw/ip/entropy_src/rtl/entropy_src_reg_top.sv b/hw/ip/entropy_src/rtl/entropy_src_reg_top.sv
index 2f714c4..5d57f64 100644
--- a/hw/ip/entropy_src/rtl/entropy_src_reg_top.sv
+++ b/hw/ip/entropy_src/rtl/entropy_src_reg_top.sv
@@ -134,42 +134,35 @@
logic alert_test_we;
logic alert_test_recov_alert_wd;
logic alert_test_fatal_alert_wd;
- logic regwen_re;
+ logic regwen_we;
logic regwen_qs;
+ logic regwen_wd;
logic [7:0] rev_abi_revision_qs;
logic [7:0] rev_hw_revision_qs;
logic [7:0] rev_chip_type_qs;
logic conf_we;
- logic [1:0] conf_enable_qs;
- logic [1:0] conf_enable_wd;
- logic conf_boot_bypass_disable_qs;
- logic conf_boot_bypass_disable_wd;
- logic conf_repcnt_disable_qs;
- logic conf_repcnt_disable_wd;
- logic conf_adaptp_disable_qs;
- logic conf_adaptp_disable_wd;
- logic conf_bucket_disable_qs;
- logic conf_bucket_disable_wd;
- logic conf_markov_disable_qs;
- logic conf_markov_disable_wd;
- logic conf_health_test_clr_qs;
- logic conf_health_test_clr_wd;
- logic conf_rng_bit_en_qs;
- logic conf_rng_bit_en_wd;
+ logic [3:0] conf_enable_qs;
+ logic [3:0] conf_enable_wd;
+ logic [3:0] conf_entropy_data_reg_enable_qs;
+ logic [3:0] conf_entropy_data_reg_enable_wd;
+ logic [3:0] conf_lfsr_enable_qs;
+ logic [3:0] conf_lfsr_enable_wd;
+ logic [3:0] conf_boot_bypass_disable_qs;
+ logic [3:0] conf_boot_bypass_disable_wd;
+ logic [3:0] conf_health_test_clr_qs;
+ logic [3:0] conf_health_test_clr_wd;
+ logic [3:0] conf_rng_bit_enable_qs;
+ logic [3:0] conf_rng_bit_enable_wd;
logic [1:0] conf_rng_bit_sel_qs;
logic [1:0] conf_rng_bit_sel_wd;
- logic conf_extht_enable_qs;
- logic conf_extht_enable_wd;
- logic conf_repcnts_disable_qs;
- logic conf_repcnts_disable_wd;
logic rate_we;
logic [15:0] rate_qs;
logic [15:0] rate_wd;
logic entropy_control_we;
- logic entropy_control_es_route_qs;
- logic entropy_control_es_route_wd;
- logic entropy_control_es_type_qs;
- logic entropy_control_es_type_wd;
+ logic [3:0] entropy_control_es_route_qs;
+ logic [3:0] entropy_control_es_route_wd;
+ logic [3:0] entropy_control_es_type_qs;
+ logic [3:0] entropy_control_es_type_wd;
logic entropy_data_re;
logic [31:0] entropy_data_qs;
logic health_test_windows_we;
@@ -295,10 +288,10 @@
logic [3:0] extht_fail_counts_extht_hi_fail_count_qs;
logic [3:0] extht_fail_counts_extht_lo_fail_count_qs;
logic fw_ov_control_we;
- logic fw_ov_control_fw_ov_mode_qs;
- logic fw_ov_control_fw_ov_mode_wd;
- logic fw_ov_control_fw_ov_entropy_insert_qs;
- logic fw_ov_control_fw_ov_entropy_insert_wd;
+ logic [3:0] fw_ov_control_fw_ov_mode_qs;
+ logic [3:0] fw_ov_control_fw_ov_mode_wd;
+ logic [3:0] fw_ov_control_fw_ov_entropy_insert_qs;
+ logic [3:0] fw_ov_control_fw_ov_entropy_insert_wd;
logic fw_ov_rd_data_re;
logic [31:0] fw_ov_rd_data_qs;
logic fw_ov_wr_data_we;
@@ -628,17 +621,28 @@
);
- // R[regwen]: V(True)
- prim_subreg_ext #(
- .DW (1)
+ // R[regwen]: V(False)
+ prim_subreg #(
+ .DW (1),
+ .SwAccess(prim_subreg_pkg::SwAccessW0C),
+ .RESVAL (1'h1)
) u_regwen (
- .re (regwen_re),
- .we (1'b0),
- .wd ('0),
- .d (hw2reg.regwen.d),
- .qre (),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (regwen_we),
+ .wd (regwen_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
.qe (),
.q (),
+
+ // to register interface (read)
.qs (regwen_qs)
);
@@ -658,17 +662,17 @@
// R[conf]: V(False)
- // F[enable]: 1:0
+ // F[enable]: 3:0
prim_subreg #(
- .DW (2),
+ .DW (4),
.SwAccess(prim_subreg_pkg::SwAccessRW),
- .RESVAL (2'h0)
+ .RESVAL (4'h5)
) u_conf_enable (
.clk_i (clk_i),
.rst_ni (rst_ni),
// from register interface
- .we (conf_we),
+ .we (conf_we & regwen_qs),
.wd (conf_enable_wd),
// from internal hardware
@@ -676,24 +680,74 @@
.d ('0),
// to internal hardware
- .qe (),
+ .qe (reg2hw.conf.enable.qe),
.q (reg2hw.conf.enable.q),
// to register interface (read)
.qs (conf_enable_qs)
);
- // F[boot_bypass_disable]: 3:3
+ // F[entropy_data_reg_enable]: 7:4
prim_subreg #(
- .DW (1),
+ .DW (4),
.SwAccess(prim_subreg_pkg::SwAccessRW),
- .RESVAL (1'h0)
+ .RESVAL (4'h5)
+ ) u_conf_entropy_data_reg_enable (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (conf_we & regwen_qs),
+ .wd (conf_entropy_data_reg_enable_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (reg2hw.conf.entropy_data_reg_enable.qe),
+ .q (reg2hw.conf.entropy_data_reg_enable.q),
+
+ // to register interface (read)
+ .qs (conf_entropy_data_reg_enable_qs)
+ );
+
+ // F[lfsr_enable]: 11:8
+ prim_subreg #(
+ .DW (4),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (4'h5)
+ ) u_conf_lfsr_enable (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+
+ // from register interface
+ .we (conf_we & regwen_qs),
+ .wd (conf_lfsr_enable_wd),
+
+ // from internal hardware
+ .de (1'b0),
+ .d ('0),
+
+ // to internal hardware
+ .qe (reg2hw.conf.lfsr_enable.qe),
+ .q (reg2hw.conf.lfsr_enable.q),
+
+ // to register interface (read)
+ .qs (conf_lfsr_enable_qs)
+ );
+
+ // F[boot_bypass_disable]: 15:12
+ prim_subreg #(
+ .DW (4),
+ .SwAccess(prim_subreg_pkg::SwAccessRW),
+ .RESVAL (4'h5)
) u_conf_boot_bypass_disable (
.clk_i (clk_i),
.rst_ni (rst_ni),
// from register interface
- .we (conf_we),
+ .we (conf_we & regwen_qs),
.wd (conf_boot_bypass_disable_wd),
// from internal hardware
@@ -701,124 +755,24 @@
.d ('0),
// to internal hardware
- .qe (),
+ .qe (reg2hw.conf.boot_bypass_disable.qe),
.q (reg2hw.conf.boot_bypass_disable.q),
// to register interface (read)
.qs (conf_boot_bypass_disable_qs)
);
- // F[repcnt_disable]: 4:4
+ // F[health_test_clr]: 19:16
prim_subreg #(
- .DW (1),
+ .DW (4),
.SwAccess(prim_subreg_pkg::SwAccessRW),
- .RESVAL (1'h0)
- ) u_conf_repcnt_disable (
- .clk_i (clk_i),
- .rst_ni (rst_ni),
-
- // from register interface
- .we (conf_we),
- .wd (conf_repcnt_disable_wd),
-
- // from internal hardware
- .de (1'b0),
- .d ('0),
-
- // to internal hardware
- .qe (),
- .q (reg2hw.conf.repcnt_disable.q),
-
- // to register interface (read)
- .qs (conf_repcnt_disable_qs)
- );
-
- // F[adaptp_disable]: 5:5
- prim_subreg #(
- .DW (1),
- .SwAccess(prim_subreg_pkg::SwAccessRW),
- .RESVAL (1'h0)
- ) u_conf_adaptp_disable (
- .clk_i (clk_i),
- .rst_ni (rst_ni),
-
- // from register interface
- .we (conf_we),
- .wd (conf_adaptp_disable_wd),
-
- // from internal hardware
- .de (1'b0),
- .d ('0),
-
- // to internal hardware
- .qe (),
- .q (reg2hw.conf.adaptp_disable.q),
-
- // to register interface (read)
- .qs (conf_adaptp_disable_qs)
- );
-
- // F[bucket_disable]: 6:6
- prim_subreg #(
- .DW (1),
- .SwAccess(prim_subreg_pkg::SwAccessRW),
- .RESVAL (1'h0)
- ) u_conf_bucket_disable (
- .clk_i (clk_i),
- .rst_ni (rst_ni),
-
- // from register interface
- .we (conf_we),
- .wd (conf_bucket_disable_wd),
-
- // from internal hardware
- .de (1'b0),
- .d ('0),
-
- // to internal hardware
- .qe (),
- .q (reg2hw.conf.bucket_disable.q),
-
- // to register interface (read)
- .qs (conf_bucket_disable_qs)
- );
-
- // F[markov_disable]: 7:7
- prim_subreg #(
- .DW (1),
- .SwAccess(prim_subreg_pkg::SwAccessRW),
- .RESVAL (1'h0)
- ) u_conf_markov_disable (
- .clk_i (clk_i),
- .rst_ni (rst_ni),
-
- // from register interface
- .we (conf_we),
- .wd (conf_markov_disable_wd),
-
- // from internal hardware
- .de (1'b0),
- .d ('0),
-
- // to internal hardware
- .qe (),
- .q (reg2hw.conf.markov_disable.q),
-
- // to register interface (read)
- .qs (conf_markov_disable_qs)
- );
-
- // F[health_test_clr]: 8:8
- prim_subreg #(
- .DW (1),
- .SwAccess(prim_subreg_pkg::SwAccessRW),
- .RESVAL (1'h0)
+ .RESVAL (4'h5)
) u_conf_health_test_clr (
.clk_i (clk_i),
.rst_ni (rst_ni),
// from register interface
- .we (conf_we),
+ .we (conf_we & regwen_qs),
.wd (conf_health_test_clr_wd),
// from internal hardware
@@ -826,39 +780,39 @@
.d ('0),
// to internal hardware
- .qe (),
+ .qe (reg2hw.conf.health_test_clr.qe),
.q (reg2hw.conf.health_test_clr.q),
// to register interface (read)
.qs (conf_health_test_clr_qs)
);
- // F[rng_bit_en]: 9:9
+ // F[rng_bit_enable]: 23:20
prim_subreg #(
- .DW (1),
+ .DW (4),
.SwAccess(prim_subreg_pkg::SwAccessRW),
- .RESVAL (1'h0)
- ) u_conf_rng_bit_en (
+ .RESVAL (4'h5)
+ ) u_conf_rng_bit_enable (
.clk_i (clk_i),
.rst_ni (rst_ni),
// from register interface
- .we (conf_we),
- .wd (conf_rng_bit_en_wd),
+ .we (conf_we & regwen_qs),
+ .wd (conf_rng_bit_enable_wd),
// from internal hardware
.de (1'b0),
.d ('0),
// to internal hardware
- .qe (),
- .q (reg2hw.conf.rng_bit_en.q),
+ .qe (reg2hw.conf.rng_bit_enable.qe),
+ .q (reg2hw.conf.rng_bit_enable.q),
// to register interface (read)
- .qs (conf_rng_bit_en_qs)
+ .qs (conf_rng_bit_enable_qs)
);
- // F[rng_bit_sel]: 11:10
+ // F[rng_bit_sel]: 25:24
prim_subreg #(
.DW (2),
.SwAccess(prim_subreg_pkg::SwAccessRW),
@@ -868,7 +822,7 @@
.rst_ni (rst_ni),
// from register interface
- .we (conf_we),
+ .we (conf_we & regwen_qs),
.wd (conf_rng_bit_sel_wd),
// from internal hardware
@@ -876,63 +830,13 @@
.d ('0),
// to internal hardware
- .qe (),
+ .qe (reg2hw.conf.rng_bit_sel.qe),
.q (reg2hw.conf.rng_bit_sel.q),
// to register interface (read)
.qs (conf_rng_bit_sel_qs)
);
- // F[extht_enable]: 12:12
- prim_subreg #(
- .DW (1),
- .SwAccess(prim_subreg_pkg::SwAccessRW),
- .RESVAL (1'h0)
- ) u_conf_extht_enable (
- .clk_i (clk_i),
- .rst_ni (rst_ni),
-
- // from register interface
- .we (conf_we),
- .wd (conf_extht_enable_wd),
-
- // from internal hardware
- .de (1'b0),
- .d ('0),
-
- // to internal hardware
- .qe (),
- .q (reg2hw.conf.extht_enable.q),
-
- // to register interface (read)
- .qs (conf_extht_enable_qs)
- );
-
- // F[repcnts_disable]: 13:13
- prim_subreg #(
- .DW (1),
- .SwAccess(prim_subreg_pkg::SwAccessRW),
- .RESVAL (1'h0)
- ) u_conf_repcnts_disable (
- .clk_i (clk_i),
- .rst_ni (rst_ni),
-
- // from register interface
- .we (conf_we),
- .wd (conf_repcnts_disable_wd),
-
- // from internal hardware
- .de (1'b0),
- .d ('0),
-
- // to internal hardware
- .qe (),
- .q (reg2hw.conf.repcnts_disable.q),
-
- // to register interface (read)
- .qs (conf_repcnts_disable_qs)
- );
-
// R[rate]: V(False)
prim_subreg #(
@@ -961,11 +865,11 @@
// R[entropy_control]: V(False)
- // F[es_route]: 0:0
+ // F[es_route]: 3:0
prim_subreg #(
- .DW (1),
+ .DW (4),
.SwAccess(prim_subreg_pkg::SwAccessRW),
- .RESVAL (1'h0)
+ .RESVAL (4'h5)
) u_entropy_control_es_route (
.clk_i (clk_i),
.rst_ni (rst_ni),
@@ -979,18 +883,18 @@
.d ('0),
// to internal hardware
- .qe (),
+ .qe (reg2hw.entropy_control.es_route.qe),
.q (reg2hw.entropy_control.es_route.q),
// to register interface (read)
.qs (entropy_control_es_route_qs)
);
- // F[es_type]: 1:1
+ // F[es_type]: 7:4
prim_subreg #(
- .DW (1),
+ .DW (4),
.SwAccess(prim_subreg_pkg::SwAccessRW),
- .RESVAL (1'h0)
+ .RESVAL (4'h5)
) u_entropy_control_es_type (
.clk_i (clk_i),
.rst_ni (rst_ni),
@@ -1004,7 +908,7 @@
.d ('0),
// to internal hardware
- .qe (),
+ .qe (reg2hw.entropy_control.es_type.qe),
.q (reg2hw.entropy_control.es_type.q),
// to register interface (read)
@@ -1952,11 +1856,11 @@
// R[fw_ov_control]: V(False)
- // F[fw_ov_mode]: 0:0
+ // F[fw_ov_mode]: 3:0
prim_subreg #(
- .DW (1),
+ .DW (4),
.SwAccess(prim_subreg_pkg::SwAccessRW),
- .RESVAL (1'h0)
+ .RESVAL (4'h5)
) u_fw_ov_control_fw_ov_mode (
.clk_i (clk_i),
.rst_ni (rst_ni),
@@ -1970,18 +1874,18 @@
.d ('0),
// to internal hardware
- .qe (),
+ .qe (reg2hw.fw_ov_control.fw_ov_mode.qe),
.q (reg2hw.fw_ov_control.fw_ov_mode.q),
// to register interface (read)
.qs (fw_ov_control_fw_ov_mode_qs)
);
- // F[fw_ov_entropy_insert]: 1:1
+ // F[fw_ov_entropy_insert]: 7:4
prim_subreg #(
- .DW (1),
+ .DW (4),
.SwAccess(prim_subreg_pkg::SwAccessRW),
- .RESVAL (1'h0)
+ .RESVAL (4'h5)
) u_fw_ov_control_fw_ov_entropy_insert (
.clk_i (clk_i),
.rst_ni (rst_ni),
@@ -1995,7 +1899,7 @@
.d ('0),
// to internal hardware
- .qe (),
+ .qe (reg2hw.fw_ov_control.fw_ov_entropy_insert.qe),
.q (reg2hw.fw_ov_control.fw_ov_entropy_insert.q),
// to register interface (read)
@@ -2625,38 +2529,32 @@
assign alert_test_recov_alert_wd = reg_wdata[0];
assign alert_test_fatal_alert_wd = reg_wdata[1];
- assign regwen_re = addr_hit[4] & reg_re & !reg_error;
+ assign regwen_we = addr_hit[4] & reg_we & !reg_error;
+
+ assign regwen_wd = reg_wdata[0];
assign conf_we = addr_hit[6] & reg_we & !reg_error;
- assign conf_enable_wd = reg_wdata[1:0];
+ assign conf_enable_wd = reg_wdata[3:0];
- assign conf_boot_bypass_disable_wd = reg_wdata[3];
+ assign conf_entropy_data_reg_enable_wd = reg_wdata[7:4];
- assign conf_repcnt_disable_wd = reg_wdata[4];
+ assign conf_lfsr_enable_wd = reg_wdata[11:8];
- assign conf_adaptp_disable_wd = reg_wdata[5];
+ assign conf_boot_bypass_disable_wd = reg_wdata[15:12];
- assign conf_bucket_disable_wd = reg_wdata[6];
+ assign conf_health_test_clr_wd = reg_wdata[19:16];
- assign conf_markov_disable_wd = reg_wdata[7];
+ assign conf_rng_bit_enable_wd = reg_wdata[23:20];
- assign conf_health_test_clr_wd = reg_wdata[8];
-
- assign conf_rng_bit_en_wd = reg_wdata[9];
-
- assign conf_rng_bit_sel_wd = reg_wdata[11:10];
-
- assign conf_extht_enable_wd = reg_wdata[12];
-
- assign conf_repcnts_disable_wd = reg_wdata[13];
+ assign conf_rng_bit_sel_wd = reg_wdata[25:24];
assign rate_we = addr_hit[7] & reg_we & !reg_error;
assign rate_wd = reg_wdata[15:0];
assign entropy_control_we = addr_hit[8] & reg_we & !reg_error;
- assign entropy_control_es_route_wd = reg_wdata[0];
+ assign entropy_control_es_route_wd = reg_wdata[3:0];
- assign entropy_control_es_type_wd = reg_wdata[1];
+ assign entropy_control_es_type_wd = reg_wdata[7:4];
assign entropy_data_re = addr_hit[9] & reg_re & !reg_error;
assign health_test_windows_we = addr_hit[10] & reg_we & !reg_error;
@@ -2745,9 +2643,9 @@
assign extht_fail_counts_re = addr_hit[41] & reg_re & !reg_error;
assign fw_ov_control_we = addr_hit[42] & reg_we & !reg_error;
- assign fw_ov_control_fw_ov_mode_wd = reg_wdata[0];
+ assign fw_ov_control_fw_ov_mode_wd = reg_wdata[3:0];
- assign fw_ov_control_fw_ov_entropy_insert_wd = reg_wdata[1];
+ assign fw_ov_control_fw_ov_entropy_insert_wd = reg_wdata[7:4];
assign fw_ov_rd_data_re = addr_hit[43] & reg_re & !reg_error;
assign fw_ov_wr_data_we = addr_hit[44] & reg_we & !reg_error;
@@ -2809,17 +2707,13 @@
end
addr_hit[6]: begin
- reg_rdata_next[1:0] = conf_enable_qs;
- reg_rdata_next[3] = conf_boot_bypass_disable_qs;
- reg_rdata_next[4] = conf_repcnt_disable_qs;
- reg_rdata_next[5] = conf_adaptp_disable_qs;
- reg_rdata_next[6] = conf_bucket_disable_qs;
- reg_rdata_next[7] = conf_markov_disable_qs;
- reg_rdata_next[8] = conf_health_test_clr_qs;
- reg_rdata_next[9] = conf_rng_bit_en_qs;
- reg_rdata_next[11:10] = conf_rng_bit_sel_qs;
- reg_rdata_next[12] = conf_extht_enable_qs;
- reg_rdata_next[13] = conf_repcnts_disable_qs;
+ reg_rdata_next[3:0] = conf_enable_qs;
+ reg_rdata_next[7:4] = conf_entropy_data_reg_enable_qs;
+ reg_rdata_next[11:8] = conf_lfsr_enable_qs;
+ reg_rdata_next[15:12] = conf_boot_bypass_disable_qs;
+ reg_rdata_next[19:16] = conf_health_test_clr_qs;
+ reg_rdata_next[23:20] = conf_rng_bit_enable_qs;
+ reg_rdata_next[25:24] = conf_rng_bit_sel_qs;
end
addr_hit[7]: begin
@@ -2827,8 +2721,8 @@
end
addr_hit[8]: begin
- reg_rdata_next[0] = entropy_control_es_route_qs;
- reg_rdata_next[1] = entropy_control_es_type_qs;
+ reg_rdata_next[3:0] = entropy_control_es_route_qs;
+ reg_rdata_next[7:4] = entropy_control_es_type_qs;
end
addr_hit[9]: begin
@@ -2991,8 +2885,8 @@
end
addr_hit[42]: begin
- reg_rdata_next[0] = fw_ov_control_fw_ov_mode_qs;
- reg_rdata_next[1] = fw_ov_control_fw_ov_entropy_insert_qs;
+ reg_rdata_next[3:0] = fw_ov_control_fw_ov_mode_qs;
+ reg_rdata_next[7:4] = fw_ov_control_fw_ov_entropy_insert_qs;
end
addr_hit[43]: begin
diff --git a/sw/device/boot_rom/rom_crt.S b/sw/device/boot_rom/rom_crt.S
index 8c61ec4..cba6163 100644
--- a/sw/device/boot_rom/rom_crt.S
+++ b/sw/device/boot_rom/rom_crt.S
@@ -83,7 +83,7 @@
// Enable entropy complex - this is not the full enable
li a0, TOP_EARLGREY_ENTROPY_SRC_BASE_ADDR
- li t0, 0x2
+ li t0, 0xa0a
sw t0, ENTROPY_SRC_CONF_REG_OFFSET(a0)
li a0, TOP_EARLGREY_CSRNG_BASE_ADDR
diff --git a/sw/device/silicon_creator/mask_rom/mask_rom_start.S b/sw/device/silicon_creator/mask_rom/mask_rom_start.S
index 20af78a..771d30e 100644
--- a/sw/device/silicon_creator/mask_rom/mask_rom_start.S
+++ b/sw/device/silicon_creator/mask_rom/mask_rom_start.S
@@ -136,7 +136,7 @@
// FIXME: Enable entropy complex - this is not the full enable.
// TODO(#7221): Switch entropy source mode from LFSR to PTRNG.
li a0, TOP_EARLGREY_ENTROPY_SRC_BASE_ADDR
- li t0, (2 << ENTROPY_SRC_CONF_ENABLE_OFFSET) // LFSR mode.
+ li t0, (0xa0a) // LFSR mode, Enable
sw t0, ENTROPY_SRC_CONF_REG_OFFSET(a0)
li a0, TOP_EARLGREY_CSRNG_BASE_ADDR
