[sw] Remove Interrupt Definitions from PLIC DIF
With the changes in #2025 to support auto-generating the PLIC interrupt
ID names based on the information in top_earlgrey.hjson, this commit
removes all those IDs from the implementation of the DIF.
This leads to having the PLIC DIF use `uint32_t`s almost everywhere in
its interface, and it slightly changes how the claim/complete functions
work to make the caller do more work to explicitly name the target they
are using.
We also use the generated parameter definitions in the code, including
adding some static asserts so the build fails if these parameters are
updated without changes to the PLIC DIF itself. These parameters are
also used in precondition checks for the DIF arguments they correspond
to.
This commit also updates the `consecutive_irqs_test.c` to use the
auto-generated PLIC interrupt IDs so it continues to pass.
Signed-off-by: Sam Elliott <selliott@lowrisc.org>
diff --git a/sw/device/lib/dif/dif_plic.c b/sw/device/lib/dif/dif_plic.c
index 4ea3fd9..42374d0 100644
--- a/sw/device/lib/dif/dif_plic.c
+++ b/sw/device/lib/dif/dif_plic.c
@@ -11,6 +11,14 @@
#include "rv_plic_regs.h" // Generated.
#include "sw/device/lib/base/mmio.h"
+// If either of these static assertions fail, then the assumptions in this DIF
+// implementation should be revisited. In particular, `plic_target_reg_offsets`
+// may need updating,
+_Static_assert(RV_PLIC_PARAM_NUMSRC == 81,
+ "PLIC instantiation parameters have changed.");
+_Static_assert(RV_PLIC_PARAM_NUMTARGET == 1,
+ "PLIC instantiation parameters have changed.");
+
// The highest interrupt priority.
#define RV_PLIC_MAX_PRIORITY 0x3u
@@ -44,73 +52,28 @@
ptrdiff_t threshold; /*<< Threshold register offset. */
} plic_target_reg_offset_t;
-/**
- * PLIC peripheral IRQ range.
- *
- * PLIC IRQ source IDs are grouped together by a peripheral they belong to.
- * Meaning that all IRQ IDs of the same peripheral are guaranteed to be
- * consecutive. This data type is used to store IRQ ID ranges of a peripheral.
- */
-typedef struct plic_peripheral_range {
- dif_plic_irq_id_t first_irq_id; /*<< The first IRQ ID of a peripheral. */
- dif_plic_irq_id_t last_irq_id; /*<< The last IRQ ID of a peripheral. */
-} plic_peripheral_range_t;
-
-// An array of target specific set of register offsets. Every supported PLIC
-// target must have an entry in this array.
+// This array gives a way of getting the target-specific register offsets from
+// a `dif_plic_target_t`.
+//
+// There should be an instance of `plic_target_reg_offset_t` for each possible
+// target, so there should be `RV_PLIC_PARAM_NUMTARGET` entries in this array.
+// The `i`th entry should contain the offsets of the `i`th target specific
+// registers:
+// - `RV_PLIC_IE<i>0_REG_OFFSET` (the first IE reg for target `i`).
+// - `RV_PLIC_CC<i>_REG_OFFSET`
+// - `RV_PLIC_THRESHOLD<i>_REG_OFFSET`
static const plic_target_reg_offset_t plic_target_reg_offsets[] = {
- [kDifPlicTargetIbex0] =
+ [0] =
{
.ie = RV_PLIC_IE00_REG_OFFSET,
.cc = RV_PLIC_CC0_REG_OFFSET,
.threshold = RV_PLIC_THRESHOLD0_REG_OFFSET,
},
};
-
-// An array of IRQ source ID ranges per peripheral. Every peripheral supported
-// by the PLIC, must have an entry in this array.
-static const plic_peripheral_range_t plic_peripheral_ranges[] = {
- [kDifPlicPeripheralGpio] =
- {
- .first_irq_id = kDifPlicIrqIdGpio0,
- .last_irq_id = kDifPlicIrqIdGpio31,
- },
- [kDifPlicPeripheralUart] =
- {
- .first_irq_id = kDifPlicIrqIdUartTxWatermark,
- .last_irq_id = kDifPlicIrqIdUartRxParityErr,
- },
- [kDifPlicPeripheralSpiDevice] =
- {
- .first_irq_id = kDifPlicIrqIdSpiDeviceRxF,
- .last_irq_id = kDifPlicIrqIdSpiDeviceTxUnderflow,
- },
- [kDifPlicPeripheralFlashCtrl] =
- {
- .first_irq_id = kDifPlicIrqIdFlashCtrlProgEmpty,
- .last_irq_id = kDifPlicIrqIdFlashCtrlOpError,
- },
- [kDifPlicPeripheralHmac] =
- {
- .first_irq_id = kDifPlicIrqIdHmacDone,
- .last_irq_id = kDifPlicIrqIdHmacErr,
- },
- [kDifPlicPeripheralAlertHandler] =
- {
- .first_irq_id = kDifPlicIrqIdAlertHandlerClassA,
- .last_irq_id = kDifPlicIrqIdAlertHandlerClassD,
- },
- [kDifPlicPeripheralNmiGen] =
- {
- .first_irq_id = kDifPlicIrqIdNmiGenEsc0,
- .last_irq_id = kDifPlicIrqIdNmiGenEsc3,
- },
- [kDifPlicPeripheralUsbDev] =
- {
- .first_irq_id = kDifPlicIrqIdUsbDevPktReceived,
- .last_irq_id = kDifPlicIrqIdUsbDevConnected,
- },
-};
+_Static_assert(
+ sizeof(plic_target_reg_offsets) / sizeof(*plic_target_reg_offsets) ==
+ RV_PLIC_PARAM_NUMTARGET,
+ "There should be an entry in plic_target_reg_offsets for every target");
/**
* Get a number of IE, IP or LE registers (IE00, IE01, ...).
@@ -119,10 +82,10 @@
* accommodate all the bits (1 bit per IRQ source).
*/
static size_t plic_num_irq_reg(void) {
- size_t register_num = kDifPlicIrqIdLast / PLIC_ID_TO_INDEX_REG_SIZE;
+ size_t register_num = RV_PLIC_PARAM_NUMSRC / PLIC_ID_TO_INDEX_REG_SIZE;
// Determine whether there are remaining IRQ sources that have a register.
- if ((kDifPlicIrqIdLast % PLIC_ID_TO_INDEX_REG_SIZE) != 0) {
+ if ((RV_PLIC_PARAM_NUMSRC % PLIC_ID_TO_INDEX_REG_SIZE) != 0) {
++register_num;
}
@@ -185,14 +148,6 @@
}
/**
- * Get a total number of priority registers (one for every IRQ source).
- *
- * As PRIO0 register is not used, last IRQ + 1 is the total number of
- * priority register.
- */
-static size_t plic_num_priority_reg(void) { return kDifPlicIrqIdLast + 1; }
-
-/**
* Get a PRIO register offset (PRIO0, PRIO1, ...) from an IRQ source ID.
*
* There is one PRIO register per IRQ source, this function calculates the IRQ
@@ -222,14 +177,14 @@
}
// Clear all of the priority registers.
- for (int i = 0; i < plic_num_priority_reg(); ++i) {
+ for (int i = 0; i < RV_PLIC_PARAM_NUMSRC; ++i) {
ptrdiff_t offset = RV_PLIC_PRIO0_REG_OFFSET + (i * sizeof(uint32_t));
mmio_region_write32(plic->base_addr, offset, 0);
}
// Clear all of the target threshold registers.
- for (dif_plic_target_t target = kDifPlicTargetIbex0;
- target <= kDifPlicTargetLast; ++target) {
+ for (dif_plic_target_t target = 0; target < RV_PLIC_PARAM_NUMTARGET;
+ ++target) {
ptrdiff_t offset = plic_target_reg_offsets[target].threshold;
mmio_region_write32(plic->base_addr, offset, 0);
}
@@ -253,7 +208,8 @@
bool dif_plic_irq_enable_set(const dif_plic_t *plic, dif_plic_irq_id_t irq,
dif_plic_target_t target,
dif_plic_enable_t enable) {
- if (plic == NULL) {
+ if (plic == NULL || irq >= RV_PLIC_PARAM_NUMSRC ||
+ target >= RV_PLIC_PARAM_NUMTARGET) {
return false;
}
@@ -275,7 +231,7 @@
bool dif_plic_irq_trigger_type_set(const dif_plic_t *plic,
dif_plic_irq_id_t irq,
dif_plic_enable_t enable) {
- if (plic == NULL) {
+ if (plic == NULL || irq >= RV_PLIC_PARAM_NUMSRC) {
return false;
}
@@ -296,7 +252,8 @@
bool dif_plic_irq_priority_set(const dif_plic_t *plic, dif_plic_irq_id_t irq,
uint32_t priority) {
- if (plic == NULL || priority > RV_PLIC_MAX_PRIORITY) {
+ if (plic == NULL || irq >= RV_PLIC_PARAM_NUMSRC ||
+ priority > RV_PLIC_MAX_PRIORITY) {
return false;
}
@@ -309,7 +266,8 @@
bool dif_plic_target_threshold_set(const dif_plic_t *plic,
dif_plic_target_t target,
uint32_t threshold) {
- if (plic == NULL || threshold > RV_PLIC_MAX_PRIORITY) {
+ if (plic == NULL || target >= RV_PLIC_PARAM_NUMTARGET ||
+ threshold > RV_PLIC_MAX_PRIORITY) {
return false;
}
@@ -322,7 +280,7 @@
bool dif_plic_irq_pending_status_get(const dif_plic_t *plic,
dif_plic_irq_id_t irq,
dif_plic_flag_t *status) {
- if (plic == NULL || status == NULL) {
+ if (plic == NULL || irq >= RV_PLIC_PARAM_NUMSRC || status == NULL) {
return false;
}
@@ -340,8 +298,8 @@
}
bool dif_plic_irq_claim(const dif_plic_t *plic, dif_plic_target_t target,
- dif_irq_claim_data_t *claim_data) {
- if (plic == NULL || claim_data == NULL) {
+ dif_plic_irq_id_t *claim_data) {
+ if (plic == NULL || target >= RV_PLIC_PARAM_NUMTARGET || claim_data == NULL) {
return false;
}
@@ -349,34 +307,22 @@
ptrdiff_t cc_offset = plic_target_reg_offsets[target].cc;
uint32_t irq_id = mmio_region_read32(plic->base_addr, cc_offset);
- // Validate an IRQ source, and determine which peripheral it belongs to.
- dif_plic_irq_id_t irq_src = (dif_plic_irq_id_t)irq_id;
- for (dif_plic_peripheral_t peripheral = kDifPlicPeripheralGpio;
- peripheral <= kDifPlicPeripheralLast; ++peripheral) {
- if (irq_src < plic_peripheral_ranges[peripheral].first_irq_id ||
- irq_src > plic_peripheral_ranges[peripheral].last_irq_id) {
- continue;
- }
-
- claim_data->peripheral = peripheral;
- claim_data->source = irq_src;
- claim_data->cc_offset = cc_offset;
- return true;
- }
-
- return false;
+ // Return the IRQ ID directly.
+ *claim_data = irq_id;
+ return true;
}
-bool dif_plic_irq_complete(const dif_plic_t *plic,
- const dif_irq_claim_data_t *complete_data) {
- if (plic == NULL || complete_data == NULL) {
+bool dif_plic_irq_complete(const dif_plic_t *plic, dif_plic_target_t target,
+ const dif_plic_irq_id_t *complete_data) {
+ if (plic == NULL || target >= RV_PLIC_PARAM_NUMTARGET ||
+ complete_data == NULL) {
return false;
}
// Write back the claimed IRQ ID to the target specific CC register,
// to notify the PLIC of the IRQ completion.
- mmio_region_write32(plic->base_addr, complete_data->cc_offset,
- (uint32_t)complete_data->source);
+ ptrdiff_t cc_offset = plic_target_reg_offsets[target].cc;
+ mmio_region_write32(plic->base_addr, cc_offset, (uint32_t)*complete_data);
return true;
}
diff --git a/sw/device/lib/dif/dif_plic.h b/sw/device/lib/dif/dif_plic.h
index 419fcb9..754209f 100644
--- a/sw/device/lib/dif/dif_plic.h
+++ b/sw/device/lib/dif/dif_plic.h
@@ -11,125 +11,29 @@
#include "sw/device/lib/base/mmio.h"
/**
- * PLIC IRQ IDs enumeration.
+ * PLIC interrupt source identifier.
*
- * Enumeration of all PLIC interrupt source IDs. The IRQ IDs belonging to
- * the same peripheral are guaranteed to be consecutive.
+ * This corresponds to a specific interrupt, and not the device it originates
+ * from.
+ *
+ * This is an unsigned 32-bit value that is at least zero and is less than the
+ * `NumSrc` instantiation parameter of the `rv_plic` device.
+ *
+ * The value 0 corresponds to "No Interrupt".
*/
-typedef enum dif_plic_irq_id {
- kDifPlicIrqIdNone = 0, /**< No IRQ */
- kDifPlicIrqIdGpio0 = 1, /**< GPIO pin 0. */
- kDifPlicIrqIdGpio1 = 2, /**< GPIO pin 1. */
- kDifPlicIrqIdGpio2 = 3, /**< GPIO pin 2. */
- kDifPlicIrqIdGpio3 = 4, /**< GPIO pin 3. */
- kDifPlicIrqIdGpio4 = 5, /**< GPIO pin 4. */
- kDifPlicIrqIdGpio5 = 6, /**< GPIO pin 5. */
- kDifPlicIrqIdGpio6 = 7, /**< GPIO pin 6. */
- kDifPlicIrqIdGpio7 = 8, /**< GPIO pin 7. */
- kDifPlicIrqIdGpio8 = 9, /**< GPIO pin 8. */
- kDifPlicIrqIdGpio9 = 10, /**< GPIO pin 9. */
- kDifPlicIrqIdGpio10 = 11, /**< GPIO pin 10. */
- kDifPlicIrqIdGpio11 = 12, /**< GPIO pin 11. */
- kDifPlicIrqIdGpio12 = 13, /**< GPIO pin 12. */
- kDifPlicIrqIdGpio13 = 14, /**< GPIO pin 13. */
- kDifPlicIrqIdGpio14 = 15, /**< GPIO pin 14. */
- kDifPlicIrqIdGpio15 = 16, /**< GPIO pin 15. */
- kDifPlicIrqIdGpio16 = 17, /**< GPIO pin 16. */
- kDifPlicIrqIdGpio17 = 18, /**< GPIO pin 17. */
- kDifPlicIrqIdGpio18 = 19, /**< GPIO pin 18. */
- kDifPlicIrqIdGpio19 = 20, /**< GPIO pin 19. */
- kDifPlicIrqIdGpio20 = 21, /**< GPIO pin 20. */
- kDifPlicIrqIdGpio21 = 22, /**< GPIO pin 21. */
- kDifPlicIrqIdGpio22 = 23, /**< GPIO pin 22. */
- kDifPlicIrqIdGpio23 = 24, /**< GPIO pin 23. */
- kDifPlicIrqIdGpio24 = 25, /**< GPIO pin 24. */
- kDifPlicIrqIdGpio25 = 26, /**< GPIO pin 25. */
- kDifPlicIrqIdGpio26 = 27, /**< GPIO pin 26. */
- kDifPlicIrqIdGpio27 = 28, /**< GPIO pin 27. */
- kDifPlicIrqIdGpio28 = 29, /**< GPIO pin 28. */
- kDifPlicIrqIdGpio29 = 30, /**< GPIO pin 29. */
- kDifPlicIrqIdGpio30 = 31, /**< GPIO pin 30. */
- kDifPlicIrqIdGpio31 = 32, /**< GPIO pin 31. */
- kDifPlicIrqIdUartTxWatermark = 33, /**< UART TX FIFO watermark. */
- kDifPlicIrqIdUartRxWatermark = 34, /**< UART RX FIFO watermark. */
- kDifPlicIrqIdUartTxEmpty = 35, /**< UART TX FIFO empty. */
- kDifPlicIrqIdUartRxOverflow = 36, /**< UART RX FIFO overflow. */
- kDifPlicIrqIdUartRxFrameErr = 37, /**< UART RX frame error. */
- kDifPlicIrqIdUartRxBreakErr = 38, /**< UART RX break error. */
- kDifPlicIrqIdUartRxTimeout = 39, /**< UART RX timeout. */
- kDifPlicIrqIdUartRxParityErr = 40, /**< UART RX parity error. */
- kDifPlicIrqIdSpiDeviceRxF = 41, /**< SPI RX SRAM FIFO full. */
- kDifPlicIrqIdSpiDeviceRxLvl = 42, /**< SPI RX SRAM FIFO above the level. */
- kDifPlicIrqIdSpiDeviceTxLvl = 43, /**< SPI TX SRAM FIFO under the level. */
- kDifPlicIrqIdSpiDeviceRxErr = 44, /**< SPI MOSI in FwMode has error. */
- kDifPlicIrqIdSpiDeviceRxOverflow = 45, /**< SPI RX Async FIFO overflow. */
- kDifPlicIrqIdSpiDeviceTxUnderflow = 46, /**< SPI TX Async FIFO underflow. */
- kDifPlicIrqIdFlashCtrlProgEmpty = 47, /**< Flash prog FIFO empty. */
- kDifPlicIrqIdFlashCtrlProgLvl = 48, /**< Flash prog FIFO drained to lvl. */
- kDifPlicIrqIdFlashCtrlRdFull = 49, /**< Flash read FIFO full. */
- kDifPlicIrqIdFlashCtrlRdLvl = 50, /**< Flash read FIFO filled to lvl. */
- kDifPlicIrqIdFlashCtrlOpDone = 51, /**< Flash operation complete. */
- kDifPlicIrqIdFlashCtrlOpError = 52, /**< Flash operation failed with err. */
- kDifPlicIrqIdHmacDone = 53, /**< HMAC done. */
- kDifPlicIrqIdHmacFifoFull = 54, /**< HMAC FIFO full. */
- kDifPlicIrqIdHmacErr = 55, /**< HMAC error. */
- kDifPlicIrqIdAlertHandlerClassA = 56, /**< Alert Handler class A alert. */
- kDifPlicIrqIdAlertHandlerClassB = 57, /**< Alert Handler class B alert. */
- kDifPlicIrqIdAlertHandlerClassC = 58, /**< Alert Handler class C alert. */
- kDifPlicIrqIdAlertHandlerClassD = 59, /**< Alert Handler class D alert. */
- kDifPlicIrqIdNmiGenEsc0 = 60, /**< NMI Gen escalation interrupt 0. */
- kDifPlicIrqIdNmiGenEsc1 = 61, /**< NMI Gen escalation interrupt 1. */
- kDifPlicIrqIdNmiGenEsc2 = 62, /**< NMI Gen escalation interrupt 2. */
- kDifPlicIrqIdNmiGenEsc3 = 63, /**< NMI Gen escalation interrupt 3. */
- kDifPlicIrqIdUsbDevPktReceived = 64, /**< USB packet received (OUT/SETUP). */
- kDifPlicIrqIdUsbDevPktSent = 65, /**< USB packet sent (IN). */
- kDifPlicIrqIdUsbDevDisconnected = 66, /**< USB link disconn (VBUS lost). */
- kDifPlicIrqIdUsbDevHostLost = 67, /*<< USB frame not received in time. */
- kDifPlicIrqIdUsbDevLinkReset = 68, /*<< USB link reset. */
- kDifPlicIrqIdUsbDevLinkSuspend = 69, /*<< USB link suspend. */
- kDifPlicIrqIdUsbDevLinkResume = 70, /*<< USB link resume. */
- kDifPlicIrqIdUsbDevAvEmpty = 71, /*<< USB AvBuffer FIFO empty (OUT/SETUP). */
- kDifPlicIrqIdUsbDevRxFull = 72, /*<< USB Receive FIFO full (OUT/SETUP). */
- kDifPlicIrqIdUsbDevAvOverflow = 73, /*<< USB AvBuffer FIFO overflow. */
- kDifPlicIrqIdUsbDevLinkInErr = 74, /*<< USB IN error. */
- kDifPlicIrqIdUsbDevRxCrcErr = 75, /*<< USB CRC error. */
- kDifPlicIrqIdUsbDevRxPidErr = 76, /*<< USB PID invalid error. */
- kDifPlicIrqIdUsbDevRxBitstuffErr = 77, /*<< USB bitstuffing invalid error. */
- kDifPlicIrqIdUsbDevFrame = 78, /*<< USB frame number updated, SOF valid. */
- kDifPlicIrqIdUsbDevConnected = 79, /*<< USB connected (VBUS applied). */
- kDifPlicIrqIdLast =
- kDifPlicIrqIdUsbDevConnected, /**< The last valid IRQ ID. */
-} dif_plic_irq_id_t;
+typedef uint32_t dif_plic_irq_id_t;
/**
- * PLIC IRQ source peripheral enumeration.
+ * PLIC interrupt target.
*
- * Enumeration used to determine which peripheral asserted the corresponding
- * IRQ source.
- */
-typedef enum dif_plic_peripheral {
- kDifPlicPeripheralGpio = 0, /**< GPIO */
- kDifPlicPeripheralUart, /**< UART */
- kDifPlicPeripheralSpiDevice, /**< SPI */
- kDifPlicPeripheralFlashCtrl, /**< Flash */
- kDifPlicPeripheralHmac, /**< HMAC */
- kDifPlicPeripheralAlertHandler, /**< Alert handler */
- kDifPlicPeripheralNmiGen, /**< NMI generator */
- kDifPlicPeripheralUsbDev, /**< USB device */
- kDifPlicPeripheralLast =
- kDifPlicPeripheralUsbDev, /**< \internal Final PLIC peripheral */
-} dif_plic_peripheral_t;
-
-/**
- * PLIC external interrupt target.
+ * This corresponds to a specific system that can service an interrupt. In
+ * OpenTitan's case, that is the Ibex core. If there were multiple cores in the
+ * system, each core would have its own specific interrupt target ID.
*
- * Enumeration used to determine which set of IE, CC, threshold registers to
- * access dependent on the target.
+ * This is an unsigned 32-bit value that is at least 0 and is less than the
+ * `NumTarget` instantiation parameter of the `rv_plic` device.
*/
-typedef enum dif_plic_target {
- kDifPlicTargetIbex0 = 0, /**< Ibex CPU */
- kDifPlicTargetLast = kDifPlicTargetIbex0, /**< \internal Final PLIC target */
-} dif_plic_target_t;
+typedef uint32_t dif_plic_target_t;
/**
* Generic enable/disable enumeration.
@@ -152,19 +56,6 @@
} dif_plic_flag_t;
/**
- * PLIC CC (IRQ claim register data).
- *
- * Data that is populated by the PLIC DIF when interrupt is claimed. Is used by
- * the PLIC DIF consumers to establish the IRQ source ID, and the peripheral
- * that asserted this IRQ.
- */
-typedef struct dif_irq_claim_data {
- dif_plic_peripheral_t peripheral; /**< Peripheral that interrupted */
- dif_plic_irq_id_t source; /**< IRQ type */
- ptrdiff_t cc_offset; /**< Target specifc CC offset */
-} dif_irq_claim_data_t;
-
-/**
* PLIC instance state.
*
* PLIC persistent data that is required by all the PLIC API.
@@ -266,11 +157,11 @@
*
* @param plic PLIC state data
* @param target Target that claimed the IRQ
- * @param claim_data Data that describes the origin and belonging of the IRQ.
+ * @param claim_data Data that describes the origin of the IRQ.
* @return true if the function was successful, false otherwise
*/
bool dif_plic_irq_claim(const dif_plic_t *plic, dif_plic_target_t target,
- dif_irq_claim_data_t *claim_data);
+ dif_plic_irq_id_t *claim_data);
/**
* Completes the claimed IRQ.
@@ -280,11 +171,12 @@
* dif_plic_claim_irq, when a caller has finished servicing the IRQ.
*
* @param plic PLIC state data
+ * @param target Target that claimed the IRQ
* @param complete_data Previously claimed IRQ data that is used to signal PLIC
* of the IRQ servicing completion.
* @return true if the function was successful, false otherwise
*/
-bool dif_plic_irq_complete(const dif_plic_t *plic,
- const dif_irq_claim_data_t *complete_data);
+bool dif_plic_irq_complete(const dif_plic_t *plic, dif_plic_target_t target,
+ const dif_plic_irq_id_t *complete_data);
#endif // OPENTITAN_SW_DEVICE_LIB_DIF_DIF_PLIC_H_
diff --git a/sw/device/tests/consecutive_irqs/consecutive_irqs_test.c b/sw/device/tests/consecutive_irqs/consecutive_irqs_test.c
index 1bf23e3..6b237a6 100644
--- a/sw/device/tests/consecutive_irqs/consecutive_irqs_test.c
+++ b/sw/device/tests/consecutive_irqs/consecutive_irqs_test.c
@@ -13,9 +13,9 @@
#include "sw/device/lib/runtime/hart.h"
#include "sw/device/lib/runtime/ibex.h"
-#include "hw/top_earlgrey/sw/autogen/top_earlgrey.h"
+#include "hw/top_earlgrey/sw/autogen/top_earlgrey.h" // Generated.
-#define PLIC_TARGET kDifPlicTargetIbex0
+#define PLIC_TARGET kTopEarlgreyPlicTargetIbex0
#define PLIC_PRIORITY_MIN 0u
#define PLIC_PRIORITY_MAX 3u
@@ -54,12 +54,12 @@
* Services UART interrupts, sets the appropriate flags that are used to
* determine success or failure of the test.
*/
-static void handler_uart_isr(const dif_irq_claim_data_t *data) {
+static void handle_uart_isr(const dif_plic_irq_id_t interrupt_id) {
const dif_uart_t *uart = &uart0;
dif_uart_interrupt_t uart_irq;
- switch (data->source) {
- case kDifPlicIrqIdUartRxOverflow:
+ switch (interrupt_id) {
+ case kTopEarlgreyPlicIrqIdUartRxOverflow:
uart_irq = kDifUartInterruptRxOverflow;
// It is an error if this IRQ is asserted more than once.
@@ -69,7 +69,7 @@
uart_rx_overflow_handled = true;
}
break;
- case kDifPlicIrqIdUartTxEmpty:
+ case kTopEarlgreyPlicIrqIdUartTxEmpty:
uart_irq = kDifUartInterruptTxEmpty;
// It is an error if this IRQ is asserted more than once.
@@ -98,20 +98,22 @@
*/
void handler_irq_external(void) {
// Claim the IRQ by reading the Ibex specific CC register.
- dif_irq_claim_data_t claim_data;
- if (!dif_plic_irq_claim(&plic0, PLIC_TARGET, &claim_data)) {
+ dif_plic_irq_id_t interrupt_id;
+ if (!dif_plic_irq_claim(&plic0, PLIC_TARGET, &interrupt_id)) {
LOG_FATAL_AND_ABORT("ISR is not implemented!");
}
// Check if the interrupted peripheral is UART.
- if (claim_data.peripheral != kDifPlicPeripheralUart) {
+ top_earlgrey_plic_peripheral_t peripheral_id =
+ top_earlgrey_plic_interrupt_for_peripheral[interrupt_id];
+ if (peripheral_id != kTopEarlgreyPlicPeripheralUart) {
LOG_FATAL_AND_ABORT("ISR interrupted peripheral is not UART!");
}
- handler_uart_isr(&claim_data);
+ handle_uart_isr(interrupt_id);
// Complete the IRQ by writing the IRQ source to the Ibex specific CC
// register.
- if (!dif_plic_irq_complete(&plic0, &claim_data)) {
+ if (!dif_plic_irq_complete(&plic0, PLIC_TARGET, &interrupt_id)) {
LOG_FATAL_AND_ABORT("Unable to complete the IRQ request!");
}
}
@@ -161,24 +163,24 @@
*/
static bool plic_configure_irqs(dif_plic_t *plic) {
// Set IRQ triggers to be level triggered
- if (!dif_plic_irq_trigger_type_set(plic, kDifPlicIrqIdUartRxOverflow,
+ if (!dif_plic_irq_trigger_type_set(plic, kTopEarlgreyPlicIrqIdUartRxOverflow,
kDifPlicDisable)) {
LOG_ERROR("RX overflow trigger type set failed!");
return false;
}
- if (!dif_plic_irq_trigger_type_set(plic, kDifPlicIrqIdUartTxEmpty,
+ if (!dif_plic_irq_trigger_type_set(plic, kTopEarlgreyPlicIrqIdUartTxEmpty,
kDifPlicDisable)) {
LOG_ERROR("TX empty trigger type set failed!");
return false;
}
// Set IRQ priorities to MAX
- if (!dif_plic_irq_priority_set(plic, kDifPlicIrqIdUartRxOverflow,
+ if (!dif_plic_irq_priority_set(plic, kTopEarlgreyPlicIrqIdUartRxOverflow,
PLIC_PRIORITY_MAX)) {
LOG_ERROR("priority set for RX overflow failed!");
return false;
}
- if (!dif_plic_irq_priority_set(plic, kDifPlicIrqIdUartTxEmpty,
+ if (!dif_plic_irq_priority_set(plic, kTopEarlgreyPlicIrqIdUartTxEmpty,
PLIC_PRIORITY_MAX)) {
LOG_ERROR("priority set for TX empty failed!");
return false;
@@ -191,13 +193,13 @@
}
// Enable IRQs in PLIC
- if (!dif_plic_irq_enable_set(plic, kDifPlicIrqIdUartRxOverflow, PLIC_TARGET,
- kDifPlicEnable)) {
+ if (!dif_plic_irq_enable_set(plic, kTopEarlgreyPlicIrqIdUartRxOverflow,
+ PLIC_TARGET, kDifPlicEnable)) {
LOG_ERROR("interrupt Enable for RX overflow failed!");
return false;
}
- if (!dif_plic_irq_enable_set(plic, kDifPlicIrqIdUartTxEmpty, PLIC_TARGET,
- kDifPlicEnable)) {
+ if (!dif_plic_irq_enable_set(plic, kTopEarlgreyPlicIrqIdUartTxEmpty,
+ PLIC_TARGET, kDifPlicEnable)) {
LOG_ERROR("interrupt Enable for TX empty failed!");
return false;
}
