[ast] Add Fix AscentLint Errors
Signed-off-by: Jacob Levy <jacob.levy@opentitan.org>
diff --git a/hw/top_earlgrey/ip/ast/ast.core b/hw/top_earlgrey/ip/ast/ast.core
index 82a220d..351cf53 100644
--- a/hw/top_earlgrey/ip/ast/ast.core
+++ b/hw/top_earlgrey/ip/ast/ast.core
@@ -26,6 +26,7 @@
- rtl/ast_bhv_pkg.sv
- rtl/ast.sv
- rtl/adc.sv
+ - rtl/adc_ana.sv
- rtl/aon_clk.sv
- rtl/aon_osc.sv
- rtl/ast_dft.sv
@@ -83,6 +84,9 @@
- tool_veriblelint ? (files_veriblelint_waiver)
- files_rtl
toplevel: ast
+ parameters:
+ - SYNTHESIS
+
lint:
<<: *default_target
diff --git a/hw/top_earlgrey/ip/ast/rtl/adc.sv b/hw/top_earlgrey/ip/ast/rtl/adc.sv
index a7d7d59..652ec64 100644
--- a/hw/top_earlgrey/ip/ast/rtl/adc.sv
+++ b/hw/top_earlgrey/ip/ast/rtl/adc.sv
@@ -51,23 +51,22 @@
// TODO: Add assertion that channel change always happen on ADC_IDLE!
assign new_convert = chn_selected && !chn_selected_d && !adc_busy;
-// Behavioral Model
+////////////////////////////////////////
+// ADC Analog Model
////////////////////////////////////////
logic [10-1:0] adc_d_ch0, adc_d_ch1;
-`ifndef SYNTHESIS
-ast_pkg::awire_t vref;
-ast_pkg::awire_t adc_vi0, adc_vi1;
-assign vref = 2.3;
-assign adc_vi0 = adc_a0_ai;
-assign adc_vi1 = adc_a1_ai;
-assign adc_d_ch0 = $rtoi((adc_vi0/vref) * $itor(10'h3ff));
-assign adc_d_ch1 = $rtoi((adc_vi1/vref) * $itor(10'h3ff));
-`else
-assign adc_d_ch0 = 10'h031 || {9'h000, adc_a0_ai}; // 0.111V
-assign adc_d_ch1 = 10'h21f || {9'h000, adc_a1_ai}; // 1.222V
-`endif
+adc_ana u_adc_ana (
+ .adc_a0_ai ( adc_a0_ai ),
+ .adc_a1_ai ( adc_a1_ai ),
+ .adc_d_ch0_o ( adc_d_ch0[10-1:0] ),
+ .adc_d_ch1_o ( adc_d_ch1[10-1:0] )
+);
+
+////////////////////////////////////////
+// ADC Digital Model
+////////////////////////////////////////
logic [8-1:0] cnv_cyc;
logic [8-1:0] ConvertCount;
diff --git a/hw/top_earlgrey/ip/ast/rtl/adc_ana.sv b/hw/top_earlgrey/ip/ast/rtl/adc_ana.sv
new file mode 100644
index 0000000..4c0801f
--- /dev/null
+++ b/hw/top_earlgrey/ip/ast/rtl/adc_ana.sv
@@ -0,0 +1,35 @@
+// Copyright lowRISC contributors.
+// Licensed under the Apache License, Version 2.0, see LICENSE for details.
+// SPDX-License-Identifier: Apache-2.0
+//############################################################################
+// *Name: sdc_ana
+// *Module Description: ADC Analog
+//############################################################################
+
+module adc_ana (
+ input ast_pkg::awire_t adc_a0_ai, // ADC A0 Analog Input
+ input ast_pkg::awire_t adc_a1_ai, // ADC A1 Analog Input
+ output logic [10-1:0] adc_d_ch0_o, // ADC A0 Digital Output
+ output logic [10-1:0] adc_d_ch1_o // ADC A1 Digital Output
+);
+
+`ifndef SYNTHESIS
+// Behavioral Model
+////////////////////////////////////////
+ast_pkg::awire_t vref;
+ast_pkg::awire_t adc_vi0, adc_vi1;
+
+assign vref = 2.3;
+assign adc_vi0 = adc_a0_ai;
+assign adc_vi1 = adc_a1_ai;
+assign adc_d_ch0_o = $rtoi((adc_vi0/vref) * $itor(10'h3ff));
+assign adc_d_ch1_o = $rtoi((adc_vi1/vref) * $itor(10'h3ff));
+`else // of SYNTHESIS
+// FPGA/VERILATOR
+////////////////////////////////////////
+
+assign adc_d_ch0_o = {9'h018, adc_a0_ai}; // 0.111V
+assign adc_d_ch1_o = {9'h10f, adc_a1_ai}; // 1.222V
+`endif
+
+endmodule : adc_ana
diff --git a/hw/top_earlgrey/ip/ast/rtl/ast.sv b/hw/top_earlgrey/ip/ast/rtl/ast.sv
index d813da5..447379d 100644
--- a/hw/top_earlgrey/ip/ast/rtl/ast.sv
+++ b/hw/top_earlgrey/ip/ast/rtl/ast.sv
@@ -146,6 +146,7 @@
import ast_reg_pkg::* ;
import ast_bhv_pkg::* ;
+
logic vcaon_pok, vcaon_pok_h, scan_mode, scan_reset_n;
logic vcmain_pok, vcmain_pok_h, vcaon_pok_por;
@@ -356,7 +357,7 @@
assign clk_aon = clk_src_aon_o;
-logic vcm_pokpor_aon_syn_n;
+logic vcmpp_aon_sync_n;
// Reset De-Assert Sync
prim_flop_2sync #(
@@ -579,6 +580,7 @@
ast_pkg::ast_dif_t ot0_alert_src;
assign ot0_alert_src = '{p: 1'b0, n: 1'b1};
+
ast_alert u_alert_ot0 (
.clk_i ( clk_ast_alert_i ),
.rst_ni ( rst_ast_alert_ni ),
@@ -661,7 +663,6 @@
.devmode_i ( 1'b0 )
); // u_reg
-
// AST to Registers Input
for (genvar i=0; i<10; i++ ) begin : gen_regb
assign hw2reg.regb[i].d = 32'h0000_0000;
@@ -754,4 +755,150 @@
`ASSERT_KNOWN(ScanShiftEnKnownO_A, scan_shift_en_o, clk_ast_tlul_i, vcaon_pok_o)
`ASSERT_KNOWN(ScanResetKnownO_A, scan_reset_no, clk_ast_tlul_i, vcaon_pok_o) //TODO)
+/////////////////////
+// Unused Signals
+////////////////////
+logic unused_sigs;
+`ifndef ANALOGSIM
+assign unused_sigs = ^{ clk_ast_usb_i,
+ rst_ast_usb_ni,
+ padmux2ast_i[5:0],
+ pad2ast_t0_ai,
+ pad2ast_t1_ai,
+ dft_strap_test_i.valid,
+ dft_strap_test_i.straps[1:0],
+ lc_dft_en_i[3:0],
+ reg2hw.rega[0].q, // [0:49]
+ reg2hw.rega[1].q, // [0:49]
+ reg2hw.rega[2].q, // [0:49]
+ reg2hw.rega[3].q, // [0:49]
+ reg2hw.rega[4].q, // [0:49]
+ reg2hw.rega[5].q, // [0:49]
+ reg2hw.rega[6].q, // [0:49]
+ reg2hw.rega[7].q, // [0:49]
+ reg2hw.rega[8].q, // [0:49]
+ reg2hw.rega[9].q, // [0:49]
+ reg2hw.rega[10].q, // [0:49]
+ reg2hw.rega[11].q, // [0:49]
+ reg2hw.rega[12].q, // [0:49]
+ reg2hw.rega[13].q, // [0:49]
+ reg2hw.rega[14].q, // [0:49]
+ reg2hw.rega[15].q, // [0:49]
+ reg2hw.rega[16].q, // [0:49]
+ reg2hw.rega[17].q, // [0:49]
+ reg2hw.rega[18].q, // [0:49]
+ reg2hw.rega[19].q, // [0:49]
+ reg2hw.rega[20].q, // [0:49]
+ reg2hw.rega[21].q, // [0:49]
+ reg2hw.rega[22].q, // [0:49]
+ reg2hw.rega[23].q, // [0:49]
+ reg2hw.rega[24].q, // [0:49]
+ reg2hw.rega[25].q, // [0:49]
+ reg2hw.rega[26].q, // [0:49]
+ reg2hw.rega[27].q, // [0:49]
+ reg2hw.rega[28].q, // [0:49]
+ reg2hw.rega[29].q, // [0:49]
+ reg2hw.rega[30].q, // [0:49]
+ reg2hw.rega[31].q, // [0:49]
+ reg2hw.rega[32].q, // [0:49]
+ reg2hw.rega[33].q, // [0:49]
+ reg2hw.rega[34].q, // [0:49]
+ reg2hw.rega[35].q, // [0:49]
+ reg2hw.rega[36].q, // [0:49]
+ reg2hw.rega[37].q, // [0:49]
+ reg2hw.rega[38].q, // [0:49]
+ reg2hw.rega[39].q, // [0:49]
+ reg2hw.rega[40].q, // [0:49]
+ reg2hw.rega[41].q, // [0:49]
+ reg2hw.rega[42].q, // [0:49]
+ reg2hw.rega[43].q, // [0:49]
+ reg2hw.rega[44].q, // [0:49]
+ reg2hw.rega[45].q, // [0:49]
+ reg2hw.rega[46].q, // [0:49]
+ reg2hw.rega[47].q, // [0:49]
+ reg2hw.rega[48].q, // [0:49]
+ reg2hw.rega[49].q, // [0:49]
+ reg2hw.regb[0].q, // [0:9]
+ reg2hw.regb[1].q, // [0:9]
+ reg2hw.regb[2].q, // [0:9]
+ reg2hw.regb[3].q, // [0:9]
+ reg2hw.regb[4].q, // [0:9]
+ reg2hw.regb[5].q, // [0:9]
+ reg2hw.regb[6].q, // [0:9]
+ reg2hw.regb[7].q, // [0:9]
+ reg2hw.regb[8].q, // [0:9]
+ reg2hw.regb[9].q, // [0:9]
+ reg2hw.revid.q
+ };
+`else
+assign unused_sigs = ^{ clk_ast_usb_i,
+ rst_ast_usb_ni,
+ padmux2ast_i[5:0],
+ dft_strap_test_i.valid,
+ dft_strap_test_i.straps[1:0],
+ lc_dft_en_i[3:0],
+ reg2hw.rega[0].q, // [0:49]
+ reg2hw.rega[1].q, // [0:49]
+ reg2hw.rega[2].q, // [0:49]
+ reg2hw.rega[3].q, // [0:49]
+ reg2hw.rega[4].q, // [0:49]
+ reg2hw.rega[5].q, // [0:49]
+ reg2hw.rega[6].q, // [0:49]
+ reg2hw.rega[7].q, // [0:49]
+ reg2hw.rega[8].q, // [0:49]
+ reg2hw.rega[9].q, // [0:49]
+ reg2hw.rega[10].q, // [0:49]
+ reg2hw.rega[11].q, // [0:49]
+ reg2hw.rega[12].q, // [0:49]
+ reg2hw.rega[13].q, // [0:49]
+ reg2hw.rega[14].q, // [0:49]
+ reg2hw.rega[15].q, // [0:49]
+ reg2hw.rega[16].q, // [0:49]
+ reg2hw.rega[17].q, // [0:49]
+ reg2hw.rega[18].q, // [0:49]
+ reg2hw.rega[19].q, // [0:49]
+ reg2hw.rega[20].q, // [0:49]
+ reg2hw.rega[21].q, // [0:49]
+ reg2hw.rega[22].q, // [0:49]
+ reg2hw.rega[23].q, // [0:49]
+ reg2hw.rega[24].q, // [0:49]
+ reg2hw.rega[25].q, // [0:49]
+ reg2hw.rega[26].q, // [0:49]
+ reg2hw.rega[27].q, // [0:49]
+ reg2hw.rega[28].q, // [0:49]
+ reg2hw.rega[29].q, // [0:49]
+ reg2hw.rega[30].q, // [0:49]
+ reg2hw.rega[31].q, // [0:49]
+ reg2hw.rega[32].q, // [0:49]
+ reg2hw.rega[33].q, // [0:49]
+ reg2hw.rega[34].q, // [0:49]
+ reg2hw.rega[35].q, // [0:49]
+ reg2hw.rega[36].q, // [0:49]
+ reg2hw.rega[37].q, // [0:49]
+ reg2hw.rega[38].q, // [0:49]
+ reg2hw.rega[39].q, // [0:49]
+ reg2hw.rega[40].q, // [0:49]
+ reg2hw.rega[41].q, // [0:49]
+ reg2hw.rega[42].q, // [0:49]
+ reg2hw.rega[43].q, // [0:49]
+ reg2hw.rega[44].q, // [0:49]
+ reg2hw.rega[45].q, // [0:49]
+ reg2hw.rega[46].q, // [0:49]
+ reg2hw.rega[47].q, // [0:49]
+ reg2hw.rega[48].q, // [0:49]
+ reg2hw.rega[49].q, // [0:49]
+ reg2hw.regb[0].q, // [0:9]
+ reg2hw.regb[1].q, // [0:9]
+ reg2hw.regb[2].q, // [0:9]
+ reg2hw.regb[3].q, // [0:9]
+ reg2hw.regb[4].q, // [0:9]
+ reg2hw.regb[5].q, // [0:9]
+ reg2hw.regb[6].q, // [0:9]
+ reg2hw.regb[7].q, // [0:9]
+ reg2hw.regb[8].q, // [0:9]
+ reg2hw.regb[9].q, // [0:9]
+ reg2hw.revid.q
+ };
+`endif
+
endmodule : ast
diff --git a/hw/top_earlgrey/ip/ast/rtl/ast_dft.sv b/hw/top_earlgrey/ip/ast/rtl/ast_dft.sv
index 6a0cfdc..d75707a 100644
--- a/hw/top_earlgrey/ip/ast/rtl/ast_dft.sv
+++ b/hw/top_earlgrey/ip/ast/rtl/ast_dft.sv
@@ -65,6 +65,7 @@
end
end
+logic clk_osc_en;
assign clk_osc_en = clk_osc_sel && (clk_osc_en_q || clk_osc_aoff);
prim_clock_gating u_clk_osc_ckgt (
@@ -100,6 +101,7 @@
end
end
+logic clk_byp_en;
assign clk_byp_en = clk_byp_sel && (clk_byp_en_q || clk_byp_aoff);
prim_clock_gating u_clk_byp_ckgt (
@@ -130,4 +132,13 @@
assign sprgf_rm_o = 5'h00;
assign sprom_rm_o = 5'h00;
+
+///////////////////////
+// Unused Signals
+///////////////////////
+logic unused_sigs;
+assign unused_sigs = ^{ clk_i, // Used in ASIC implementation
+ rst_ni // Used in ASIC implementation
+ };
+
endmodule : ast_dft
diff --git a/hw/top_earlgrey/ip/ast/rtl/ast_entropy.sv b/hw/top_earlgrey/ip/ast/rtl/ast_entropy.sv
index f8af468..e439f05 100644
--- a/hw/top_earlgrey/ip/ast/rtl/ast_entropy.sv
+++ b/hw/top_earlgrey/ip/ast/rtl/ast_entropy.sv
@@ -23,10 +23,10 @@
////////////////////////////////////////
// Entropy Request FSM
////////////////////////////////////////
-typedef enum logic [3-1:0] {
- ERQ_REQ0 = 3'd1, // Device-0 Request (source)
- ERQ_ACK0 = 3'd3, // Device-0 Acknowledge
- ERQ_IDLE = 3'd0 // IDLE/RESET
+typedef enum logic [2-1:0] {
+ ERQ_REQ0 = 2'd1, // Device-0 Request (source)
+ ERQ_ACK0 = 2'd3, // Device-0 Acknowledge
+ ERQ_IDLE = 2'd0 // IDLE/RESET
} erq_sm_e;
erq_sm_e erq_sm;
@@ -44,7 +44,7 @@
edn_req <= 1'b0;
erq_sm <= ERQ_IDLE;
end else begin
- case ( erq_sm )
+ unique case ( erq_sm )
ERQ_IDLE: begin
if ( dev0_wready ) begin
edn_req <= 1'b1;
@@ -109,4 +109,13 @@
);
+
+/////////////////////
+// Unused Signals
+/////////////////////
+logic unused_sigs;
+assign unused_sigs = ^{ entropy_rsp_i.edn_fips,
+ dev0_entropy // Used in ASIC implementation
+ };
+
endmodule : ast_entropy
diff --git a/hw/top_earlgrey/ip/ast/rtl/dev_entropy.sv b/hw/top_earlgrey/ip/ast/rtl/dev_entropy.sv
index 91da4c1..9ad5fd4 100644
--- a/hw/top_earlgrey/ip/ast/rtl/dev_entropy.sv
+++ b/hw/top_earlgrey/ip/ast/rtl/dev_entropy.sv
@@ -223,7 +223,7 @@
// Packer FIFO (32to1 bit)
////////////////////////////////////////
logic rdata, rvalid;
-logic [6-1:0] unc_depth;
+logic [6-1:0] depth;
prim_packer_fifo #(
.InW ( 32 ),
@@ -231,18 +231,27 @@
) u_dev_fifo (
.clk_i ( clk_dev_i ),
.rst_ni ( rst_dev_ni ),
- .clr_i ( 1'b0 ), // !dev_en_dev ), // Clear (sync)
- .wvalid_i ( wvalid ), // Write Valid
- .wdata_i ( wdata ), // Write Data (32-bit)
- .wready_o ( wready ), // Write Ready
+ .clr_i ( 1'b0 ), // !dev_en_dev ), // Clear (sync)
+ .wvalid_i ( wvalid ), // Write Valid
+ .wdata_i ( wdata ), // Write Data (32-bit)
+ .wready_o ( wready ), // Write Ready
//
- .rvalid_o ( rvalid ), // Read Valid
- .rdata_o ( rdata ), // Read Data
- .rready_i ( rready ), // Read Ready (done)
- .depth_o ( unc_depth[6-1:0] ) // empty when (depth_o == `0)
+ .rvalid_o ( rvalid ), // Read Valid
+ .rdata_o ( rdata ), // Read Data
+ .rready_i ( rready ), // Read Ready (done)
+ .depth_o ( depth[6-1:0] ) // empty when (depth_o == `0)
);
assign rready = rvalid && rate_pulse;
assign dev_data_o = rdata && rate_pulse;
+
+///////////////////////
+// Unused Signals
+///////////////////////
+logic unused_sigs;
+assign unused_sigs = ^{ depth[6-1:0],
+ dev_rate[31:16]
+ };
+
endmodule : dev_entropy
diff --git a/hw/top_earlgrey/ip/ast/rtl/rglts_pdm_3p3v.sv b/hw/top_earlgrey/ip/ast/rtl/rglts_pdm_3p3v.sv
index 2bcb1f0..5691e6c 100644
--- a/hw/top_earlgrey/ip/ast/rtl/rglts_pdm_3p3v.sv
+++ b/hw/top_earlgrey/ip/ast/rtl/rglts_pdm_3p3v.sv
@@ -27,10 +27,10 @@
);
`ifndef SYNTHESIS
-import ast_bhv_pkg::* ;
-
// Behavioral Model
///////////////////////////////////////
+import ast_bhv_pkg::* ;
+
// localparam time MPVCC_RDLY = 5us,
// MPVCC_FDLY = 100ns,
// MPPD_RDLY = 50us,
@@ -78,14 +78,14 @@
assign vcaon_pok_h_o = vcaon_pok_h && vcc_pok_h_i;
`else // of SYNTHESIS
-localparam prim_pkg::impl_e Impl = `PRIM_DEFAULT_IMPL;
-
// SYNTHESUS/VERILATOR/LINTER/FPGA
///////////////////////////////////////
+localparam prim_pkg::impl_e Impl = `PRIM_DEFAULT_IMPL;
+
logic dummy0, dummy1;
-assign dummy0 = vcmain_pok_h_i && vcmain_pok_o_h_i && clk_src_aon_h_i && 1'b0;
-assign dummy1 = vcmain_pok_h_i || vcmain_pok_o_h_i || clk_src_aon_h_i || 1'b1;
+assign dummy0 = vcmain_pok_h_i && vcmain_pok_o_h_i && 1'b0;
+assign dummy1 = vcmain_pok_h_i || vcmain_pok_o_h_i || 1'b1;
assign vcaon_pok_h_o = dummy0 || !dummy0; // 1'b1
assign main_pwr_dly_o = dummy1 || !dummy1; // 1'b1
@@ -113,4 +113,14 @@
assign otp_power_seq_h_o[0] = !flash_power_down_h_o && otp_power_seq_h_i[0]; // TODO Scan mode
assign otp_power_seq_h_o[1] = flash_power_down_h_o || otp_power_seq_h_i[1]; // TODO Scan mode
+
+///////////////////////
+// Unused Signals
+///////////////////////
+logic unused_sigs;
+assign unused_sigs = ^{ main_env_iso_en_h_i, // Used in ASIC implementation
+ vcmain_pok_h_i, // Used in ASIC implementation
+ clk_src_aon_h_i // Used in ASIC implementation
+ };
+
endmodule : rglts_pdm_3p3v
diff --git a/hw/top_earlgrey/ip/ast/rtl/rng.sv b/hw/top_earlgrey/ip/ast/rtl/rng.sv
index 8440583..6f442c2 100644
--- a/hw/top_earlgrey/ip/ast/rtl/rng.sv
+++ b/hw/top_earlgrey/ip/ast/rtl/rng.sv
@@ -36,7 +36,7 @@
.StatePermEn ( 1'b1 ),
.StatePerm ( ast_pkg::RndCnstLfsrPermDefault ),
.ExtSeedSVA ( 1'b0 ) // ext seed is unused
-) u_sys_lfsr (
+) u_rng_lfsr (
.clk_i ( clk_i ),
.rst_ni ( rst_n ),
.lfsr_en_i ( rng_en_i ),
@@ -102,4 +102,11 @@
end
end
+
+///////////////////////
+// Unused Signals
+///////////////////////
+logic unused_sigs;
+assign unused_sigs = ^{ rng_fips_i }; // Used in ASIC implementation
+
endmodule : rng
diff --git a/hw/top_earlgrey/ip/ast/rtl/sys_osc.sv b/hw/top_earlgrey/ip/ast/rtl/sys_osc.sv
index 0ccb179..a70109d 100644
--- a/hw/top_earlgrey/ip/ast/rtl/sys_osc.sv
+++ b/hw/top_earlgrey/ip/ast/rtl/sys_osc.sv
@@ -48,7 +48,7 @@
end
`else // of SYNTHESIS
// SYNTHESIS/VERILATOR/LINTER/FPGA
-///////////////////////////////////////
+////////////////////////////////////////
logic sys_clk_dly;
assign sys_clk_dly = 1'b1;
@@ -86,4 +86,13 @@
.clk_o ( sys_clk_o )
);
+
+`ifdef SYNTHESIS
+/////////////////////////
+// Unused Signals
+/////////////////////////
+logic unused_sigs;
+assign unused_sigs = ^{ sys_jen_i }; // Used in ASIC implementation
+`endif
+
endmodule : sys_osc
diff --git a/hw/top_earlgrey/ip/ast/rtl/usb_clk.sv b/hw/top_earlgrey/ip/ast/rtl/usb_clk.sv
index 811bff6..d5be299 100644
--- a/hw/top_earlgrey/ip/ast/rtl/usb_clk.sv
+++ b/hw/top_earlgrey/ip/ast/rtl/usb_clk.sv
@@ -21,6 +21,7 @@
output logic clk_src_usb_val_o // USB Source Clock Valid
);
+
logic clk, osc_en, usb_clk_en, rst_n;
assign rst_n = rst_usb_clk_ni; // Scan enabled
@@ -58,4 +59,11 @@
.q_o ( clk_src_usb_val_o )
);
+
+/////////////////////////
+// Unused Signals
+/////////////////////////
+logic unused_sigs;
+assign unused_sigs = ^{ usb_ref_pulse_i }; // Used in ASIC implementation
+
endmodule : usb_clk
diff --git a/sw/device/tock/tock/Cargo.toml b/sw/device/tock/tock/Cargo.toml
new file mode 120000
index 0000000..1f62a36
--- /dev/null
+++ b/sw/device/tock/tock/Cargo.toml
@@ -0,0 +1 @@
+/tanap1/proj_cd14/opentitan/jlevy/ot_pr/opentitan/sw/device/tock/tock/Cargo_remote.toml
\ No newline at end of file
