[doc] Use consistent spelling/capitalization of names
Consistently use the following spelling for document formats,
programming languages, and names:
- Markdown
- Hjson
- JSON
- Verilog
- HTML
- GitHub
- CSS
- Python
Also avoid abbreviations:
- repo -> repository
Signed-off-by: Philipp Wagner <phw@lowrisc.org>
diff --git a/util/reggen/README.md b/util/reggen/README.md
index 4b798e7..94a84d2 100644
--- a/util/reggen/README.md
+++ b/util/reggen/README.md
@@ -2,9 +2,9 @@
The utility script `regtool.py` and collateral under `reggen` are Python
tools to read register descriptions in Hjson and generate various output
-formats. The tool can output html documentation, standard json, compact
-standard json (whitespace removed) and Hjson. The example commands assume
-`$REPO_TOP` is set to the toplevel directory of the repo.
+formats. The tool can output HTML documentation, standard JSON, compact
+standard JSON (whitespace removed) and Hjson. The example commands assume
+`$REPO_TOP` is set to the toplevel directory of the repository.
### Setup
@@ -19,9 +19,9 @@
### Register JSON Format
-To ensure things stay up to date, the register json format information
+To ensure things stay up to date, the register JSON format information
is documented by the tool itself. Documentation can be generated by
-running the tool to produce markdown and processing that into html.
+running the tool to produce Markdown and processing that into HTML.
This information can also be found in the
[register tool documentation](../../doc/rm/register_tool.md).
This references features in the [docgen](../docgen/README.md) suite
@@ -40,8 +40,8 @@
The script `regtool.py` provides a standalone way to run `reggen`.
Note that the same example inputs are used here as for `docgen`.
-This generates html from the register description and is verbose. Since
-embeddable html is generated, the css is not included, so the output will
+This generates HTML from the register description and is verbose. Since
+embeddable HTML is generated, the CSS is not included, so the output will
not be perfectly formatted.
```console
@@ -50,7 +50,7 @@
```
The following shows an example of how to generate the full featured
-standard json from the register description Hjson file:
+standard JSON from the register description Hjson file:
```console
$ cd $REPO_TOP/util
diff --git a/util/reggen/gen_cfg_html.py b/util/reggen/gen_cfg_html.py
index 7d07102..5170dab 100644
--- a/util/reggen/gen_cfg_html.py
+++ b/util/reggen/gen_cfg_html.py
@@ -2,7 +2,7 @@
# Licensed under the Apache License, Version 2.0, see LICENSE for details.
# SPDX-License-Identifier: Apache-2.0
"""
-Generate html documentation from validated configuration json tree
+Generate HTML documentation from validated configuration Hjson tree
"""
import sys
diff --git a/util/reggen/gen_cheader.py b/util/reggen/gen_cheader.py
index 7f8836d..6d242cb 100644
--- a/util/reggen/gen_cheader.py
+++ b/util/reggen/gen_cheader.py
@@ -2,7 +2,7 @@
# Licensed under the Apache License, Version 2.0, see LICENSE for details.
# SPDX-License-Identifier: Apache-2.0
"""
-Generate C header from validated register json tree
+Generate C header from validated register JSON tree
"""
import io
diff --git a/util/reggen/gen_ctheader.py b/util/reggen/gen_ctheader.py
index 3fa1594..a433e2d 100644
--- a/util/reggen/gen_ctheader.py
+++ b/util/reggen/gen_ctheader.py
@@ -2,7 +2,7 @@
# Licensed under the Apache License, Version 2.0, see LICENSE for details.
# SPDX-License-Identifier: Apache-2.0
"""
-Generate C header (Titan style) from validated register json tree
+Generate C header (Titan style) from validated register JSON tree
"""
import io
diff --git a/util/reggen/gen_dv.py b/util/reggen/gen_dv.py
index 20d7ed1..ac0e225 100644
--- a/util/reggen/gen_dv.py
+++ b/util/reggen/gen_dv.py
@@ -1,7 +1,7 @@
# Copyright lowRISC contributors.
# Licensed under the Apache License, Version 2.0, see LICENSE for details.
# SPDX-License-Identifier: Apache-2.0
-"""Generate SystemVerilog designs from validated register json tree
+"""Generate SystemVerilog designs from validated register JSON tree
"""
import logging as log
diff --git a/util/reggen/gen_html.py b/util/reggen/gen_html.py
index d888532..a4c6116 100644
--- a/util/reggen/gen_html.py
+++ b/util/reggen/gen_html.py
@@ -2,7 +2,7 @@
# Licensed under the Apache License, Version 2.0, see LICENSE for details.
# SPDX-License-Identifier: Apache-2.0
"""
-Generate html documentation from validated register json tree
+Generate HTML documentation from validated register Hjson tree
"""
import logging as log
@@ -14,7 +14,7 @@
outfile.write(msg)
-# expand !!register references into html links, gen **bold** and *italic*
+# expand !!register references into HTML links, gen **bold** and *italic*
def desc_expand(s, rnames):
def fieldsub(match):
base = match.group(1).partition('.')[0].lower()
diff --git a/util/reggen/gen_json.py b/util/reggen/gen_json.py
index 7088d17..ffab523 100644
--- a/util/reggen/gen_json.py
+++ b/util/reggen/gen_json.py
@@ -2,7 +2,7 @@
# Copyright lowRISC contributors.
# Licensed under the Apache License, Version 2.0, see LICENSE for details.
# SPDX-License-Identifier: Apache-2.0
-"""Generate json/compact json/hjson from register json tree
+"""Generate JSON/compact JSON/Hjson from register JSON tree
"""
import hjson
@@ -29,4 +29,4 @@
hjson.dump(
obj, outfile, ensure_ascii=False, for_json=True, use_decimal=True)
else:
- raise ValueError('Invalid json format ' + format)
+ raise ValueError('Invalid JSON format ' + format)
diff --git a/util/reggen/gen_rtl.py b/util/reggen/gen_rtl.py
index 9161192..5e762a7 100644
--- a/util/reggen/gen_rtl.py
+++ b/util/reggen/gen_rtl.py
@@ -1,7 +1,7 @@
# Copyright lowRISC contributors.
# Licensed under the Apache License, Version 2.0, see LICENSE for details.
# SPDX-License-Identifier: Apache-2.0
-"""Generate SystemVerilog designs from validated register json tree
+"""Generate SystemVerilog designs from validated register JSON tree
"""
import logging as log
@@ -122,7 +122,7 @@
def json_to_reg(obj):
- """Converts json OrderedDict into structure having useful information for
+ """Converts JSON OrderedDict into structure having useful information for
Template to use.
Main purpose of this function is:
diff --git a/util/reggen/gen_selfdoc.py b/util/reggen/gen_selfdoc.py
index 49dd7df..7d80402 100644
--- a/util/reggen/gen_selfdoc.py
+++ b/util/reggen/gen_selfdoc.py
@@ -89,7 +89,7 @@
Field names should be relatively short because they will be used
frequently (and need to fit in the register layout picture!) The field
description is expected to be longer and will most likely make use of
-the hjson ability to include multi-line strings. An example with three
+the Hjson ability to include multi-line strings. An example with three
fields:
```hjson
@@ -234,7 +234,7 @@
doc_tbl_line(outfile, x, None, validate.hwaccess_permitted[x][0])
genout(outfile,
- "\n\nThe top level of the json is a group containing "\
+ "\n\nThe top level of the JSON is a group containing "\
"the following keys:\n")
doc_tbl_head(outfile, 1)
for x in validate.top_required:
diff --git a/util/reggen/reg_html.css b/util/reggen/reg_html.css
index 9beaf15..c657573 100644
--- a/util/reggen/reg_html.css
+++ b/util/reggen/reg_html.css
@@ -1,4 +1,4 @@
-/* Stylesheet for reggen html register output */
+/* Stylesheet for reggen HTML register output */
/* Copyright lowRISC contributors. */
/* Licensed under the Apache License, Version 2.0, see LICENSE for details.*/
/* SPDX-License-Identifier: Apache-2.0 */
diff --git a/util/reggen/validate.py b/util/reggen/validate.py
index 89fed02..4ffbaf4 100644
--- a/util/reggen/validate.py
+++ b/util/reggen/validate.py
@@ -2,7 +2,7 @@
# Licensed under the Apache License, Version 2.0, see LICENSE for details.
# SPDX-License-Identifier: Apache-2.0
"""
-Register json validation
+Register JSON validation
"""
import logging as log
@@ -11,7 +11,7 @@
from reggen.field_enums import *
-# Routine that can be used for hjson object_pairs_hook
+# Routine that can be used for Hjson object_pairs_hook
# The baseline is dict(pairs) i.e. construct a dictonary from pairs
# The usual is OrderedDict(pairs) which is redundant in latest python
# Both of these silently allow repeated keys, which this version detects
@@ -277,10 +277,10 @@
't': ["text", "string, may be multi-line enclosed in `'''` "\
"may use `**bold**`, `*italic*` or `!!Reg` markup"],
'T': ["tuple", "tuple enclosed in ()"],
- 'pi': ["python int", "Native python type int (generated)"],
- 'pb': ["python Bool", "Native python type Bool (generated)"],
- 'pl': ["python list", "Native python type list (generated)"],
- 'pe': ["python enum", "Native python type enum (generated)"]
+ 'pi': ["python int", "Native Python type int (generated)"],
+ 'pb': ["python Bool", "Native Python type Bool (generated)"],
+ 'pl': ["python list", "Native Python type list (generated)"],
+ 'pe': ["python enum", "Native Python type enum (generated)"]
}
# Toplevel keys
@@ -603,7 +603,7 @@
fname = field['name']
if fname in keywords_verilog:
error += 1
- log.error(rname + " field " + fname + " uses verilog keywords")
+ log.error(rname + " field " + fname + " uses Verilog keywords")
if (fname == ""):
fname = rname + ".field" + str(fcount)
else:
@@ -855,7 +855,7 @@
if rname in keywords_verilog:
error += 1
log.error("Register at +" + hex(offset) + rname +
- " uses verilog keywords")
+ " uses Verilog keywords")
if rname.lower() in top['genrnames']:
error += 1
log.error("Register at +" + hex(offset) + " duplicate name " +
