| commit | fe2779ee5413a14815112c1e8ae78378dc07e54b | [log] [tgz] |
|---|---|---|
| author | Rupert Swarbrick <rswarbrick@lowrisc.org> | Thu Oct 21 17:04:54 2021 +0100 |
| committer | Rupert Swarbrick <rswarbrick@gmail.com> | Fri Nov 12 22:38:08 2021 +0000 |
| tree | d5e569f0986dd55b5ad91b64a4aed2db57bb614a | |
| parent | ee94ef27ef02b98b0d021999f8e866318eb45c1a [diff] |
[rstmgr] Fix width of counter in rstmgr_cnsty_chk The definition of CntWidth wasn't correct for all values of MaxSyncDelay. In particular, it wouldn't work properly for a MaxSyncDelay of 3 (where representing the next value takes another bit). Also, add an explicit cast to avoid a width mismatch warning. Now that we've got the widths right, we could alternatively slice MaxSyncDelay. But this seems slightly safer (and we've just got it wrong once!). Signed-off-by: Rupert Swarbrick <rswarbrick@lowrisc.org>
OpenTitan is an open source silicon Root of Trust (RoT) project. OpenTitan will make the silicon RoT design and implementation more transparent, trustworthy, and secure for enterprises, platform providers, and chip manufacturers. OpenTitan is administered by lowRISC CIC as a collaborative project to produce high quality, open IP for instantiation as a full-featured product. See the OpenTitan site and OpenTitan docs for more information about the project.
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