commit 13f0f588f035e1db1e49e1080624424a490af230
author Michael Schaffner <msf@google.com> Wed Apr 13 14:37:41 2022 -0700
committer Michael Schaffner <msf@google.com> Thu Apr 14 16:00:54 2022 -0700
tree eb8d9a9a594712e185ca9a4229d5ad1fdf0f8d6a
parent 3a6c574f12af7ed4b0ad62a51b1bd403b296027e

Update lowrisc_ibex to lowRISC/ibex@ccc9bef3

Update code from upstream repository
https://github.com/lowRISC/ibex.git to revision
ccc9bef3ecbc31b02b1aeec1544fa3412b618a32

* [regfile] Add countermeasure label (Michael Schaffner)
* [regfile] Add spurious write enable check for secure ibex (Michael
  Schaffner)
* Update lowrisc_ip to lowRISC/opentitan@1740ccd1a (Michael Schaffner)
* Fixup .rtl.tb_compile vars.mk filename (Harry Callahan)
* Improve docs explaining Makefile variable dependencies (Harry
  Callahan)
* Add better dependencies for the coverage targets using stampfiles
  (Harry Callahan)
* Handle stdstreams from submakefile commands cleanly (Harry Callahan)
* Add parallelism to instr_gen_run and iss_sim steps (Harry Callahan)
* Changed whitespaces to be consistent throughout Makefile (Harry
  Callahan)
* [lint] Minor fixes (Michael Schaffner)
* assign irq_nm_int_cause to all zeros (mbaykenar)
* Update ibex_controller.sv (mbaykenar)
* [dv] Remove support for building against ibex-cosim-v0.1 (Rupert
  Swarbrick)
* [ci,docs] Bump minimum Spike version to ibex-cosim-v0.2 (Rupert
  Swarbrick)
* [rtl] Remove "mispredict" ports from icache (Rupert Swarbrick)
* [rtl] Remove "mispredict" ports from prefetch buffer (Rupert
  Swarbrick)
* [rtl] Combine the two branch signals in the IF stage (Rupert
  Swarbrick)
* [dv,fcov] Timeout fix + removing .ccf from yaml (Canberk Topal)
* Update google_riscv-dv to google/riscv-dv@6e0dc18 (Canberk Topal)
* Update lowrisc_ip to lowRISC/opentitan@3a33c4df2 (Canberk Topal)
* [doc, fcov] Remove coverpoint names from unimplemented coverage
  (Greg Chadwick)
* [doc, fcov] Tweak and add coverpoints (Greg Chadwick)
* Introduce internal interrupt concept (Greg Chadwick)
* Fix cov_report directory in sim.py (Canberk Topal)
* [ram_2p] Set DataBitsPerMask parameter for prim_ram_2p (Pirmin
  Vogel)
* Update google_riscv-dv to google/riscv-dv@cb4295f (Pirmin Vogel)
* [dv,xlm] Pass simulator flag to cov.py in Makefile (Canberk Topal)
* Update lowrisc_ip to lowRISC/opentitan@0747afbdd (Canberk Topal)
* Include the main C++ file only with Verilator (Canberk Topal)
* [dv,xlm] Save each UCM file in <test_name>.<seed> (Canberk Topal)
* Coverage support with Cadence Tools (Canberk Topal)
* [icache, dv] Added ram interface and enables ecc error injection.
  (Prajwala Puttappa)
* [icache, dv] Removed ecc agent (Prajwala Puttappa)
* Remove logfile param in Ibex RTL Sim for Xcelium (Harry Callahan)
* [fcov, doc] Update coverage plan (Greg Chadwick)
* [fcov] Add and improve functional coverage (Greg Chadwick)
* [rtl] Refactor pmp logic (Greg Chadwick)
* [rtl] Refactor illegal instruction logic (Greg Chadwick)
* [rtl] Refactor illegal debug CSR logic (Greg Chadwick)
* [ci] Fix coremark cosim job (Greg Chadwick)
* [simple_system_cosim] Switch to latest cosim version (Greg Chadwick)
* [simple_system] Fix GetIsaString (Greg Chadwick)
* [cosim] Fix cosim mcycle update (Greg Chadwick)
* [doc] Update coverage plan (Greg Chadwick)
* [ibex, dv] Removed extra hierarchy of ic_top inside icache TB
  (Prajwala Puttappa)
* Update spike_cosim.cc to be able to build against newer Spikes
  (Rupert Swarbrick)
* [dv,core_ibex] Fix order of 'm' and 'c' in ISA string (Rupert
  Swarbrick)
* [icache, dv] Added scrambling agent to verify scrambling in RAMs
  (Prajwala Puttappa)
* [icache, dv] Removed support for single clock cycle PMP error
  response (Prajwala Puttappa)
* Update lowrisc_ip to lowRISC/opentitan@7c4f8b3fd (Prajwala Puttappa)
* [icache, dv] Fixed regression failure in ibex_icache_back_line
  (Prajwala Puttappa)

Signed-off-by: Michael Schaffner <msf@google.com>