[util] allow separate "pass" parameters for FIFOs
Signed-off-by: Timothy Chen <timothytim@google.com>
diff --git a/hw/top_earlgrey/data/autogen/top_earlgrey.gen.hjson b/hw/top_earlgrey/data/autogen/top_earlgrey.gen.hjson
index c1f2c81..0b506cd 100644
--- a/hw/top_earlgrey/data/autogen/top_earlgrey.gen.hjson
+++ b/hw/top_earlgrey/data/autogen/top_earlgrey.gen.hjson
@@ -8316,40 +8316,44 @@
type: host
clock: clk_main_i
reset: rst_main_ni
- pipeline: "false"
+ pipeline: false
xbar: false
stub: false
inst_type: ""
- pipeline_byp: "true"
+ req_fifo_pass: true
+ rsp_fifo_pass: true
}
{
name: rv_core_ibex.cored
type: host
clock: clk_main_i
reset: rst_main_ni
- pipeline: "false"
+ pipeline: false
xbar: false
stub: false
inst_type: ""
- pipeline_byp: "true"
+ req_fifo_pass: true
+ rsp_fifo_pass: true
}
{
name: rv_dm.sba
type: host
clock: clk_main_i
reset: rst_main_ni
- pipeline_byp: "false"
+ req_fifo_pass: false
+ rsp_fifo_pass: false
xbar: false
stub: false
inst_type: ""
- pipeline: "true"
+ pipeline: true
}
{
name: rv_dm.regs
type: device
clock: clk_main_i
reset: rst_main_ni
- pipeline_byp: "false"
+ req_fifo_pass: false
+ rsp_fifo_pass: false
inst_type: rv_dm
addr_range:
[
@@ -8360,14 +8364,15 @@
]
xbar: false
stub: false
- pipeline: "true"
+ pipeline: true
}
{
name: rv_dm.rom
type: device
clock: clk_main_i
reset: rst_main_ni
- pipeline_byp: "false"
+ req_fifo_pass: false
+ rsp_fifo_pass: false
inst_type: rv_dm
addr_range:
[
@@ -8378,14 +8383,14 @@
]
xbar: false
stub: false
- pipeline: "true"
+ pipeline: true
}
{
name: rom_ctrl.rom
type: device
clock: clk_main_i
reset: rst_main_ni
- pipeline: "false"
+ pipeline: false
inst_type: rom_ctrl
addr_range:
[
@@ -8396,14 +8401,14 @@
]
xbar: false
stub: false
- pipeline_byp: "true"
+ req_fifo_pass: true
}
{
name: rom_ctrl.regs
type: device
clock: clk_main_i
reset: rst_main_ni
- pipeline: "false"
+ pipeline: false
inst_type: rom_ctrl
addr_range:
[
@@ -8414,17 +8419,18 @@
]
xbar: false
stub: false
- pipeline_byp: "true"
+ req_fifo_pass: true
}
{
name: peri
type: device
clock: clk_fixed_i
reset: rst_fixed_ni
- pipeline_byp: "false"
+ req_fifo_pass: false
+ rsp_fifo_pass: false
xbar: true
stub: false
- pipeline: "true"
+ pipeline: true
addr_range:
[
{
@@ -8442,7 +8448,7 @@
type: device
clock: clk_spi_host0_i
reset: rst_spi_host0_ni
- pipeline: "false"
+ pipeline: false
inst_type: spi_host
addr_range:
[
@@ -8453,14 +8459,14 @@
]
xbar: false
stub: false
- pipeline_byp: "true"
+ req_fifo_pass: true
}
{
name: spi_host1
type: device
clock: clk_spi_host1_i
reset: rst_spi_host1_ni
- pipeline: "false"
+ pipeline: false
inst_type: spi_host
addr_range:
[
@@ -8471,14 +8477,15 @@
]
xbar: false
stub: false
- pipeline_byp: "true"
+ req_fifo_pass: true
}
{
name: flash_ctrl.core
type: device
clock: clk_main_i
reset: rst_main_ni
- pipeline_byp: "false"
+ req_fifo_pass: false
+ rsp_fifo_pass: false
inst_type: flash_ctrl
addr_range:
[
@@ -8489,14 +8496,15 @@
]
xbar: false
stub: false
- pipeline: "true"
+ pipeline: true
}
{
name: flash_ctrl.prim
type: device
clock: clk_main_i
reset: rst_main_ni
- pipeline_byp: "false"
+ req_fifo_pass: false
+ rsp_fifo_pass: false
inst_type: flash_ctrl
addr_range:
[
@@ -8507,14 +8515,15 @@
]
xbar: false
stub: false
- pipeline: "true"
+ pipeline: true
}
{
name: flash_ctrl.mem
type: device
clock: clk_main_i
reset: rst_main_ni
- pipeline_byp: "false"
+ req_fifo_pass: false
+ rsp_fifo_pass: false
inst_type: flash_ctrl
addr_range:
[
@@ -8525,14 +8534,15 @@
]
xbar: false
stub: false
- pipeline: "true"
+ pipeline: true
}
{
name: hmac
type: device
clock: clk_main_i
reset: rst_main_ni
- pipeline_byp: "false"
+ req_fifo_pass: false
+ rsp_fifo_pass: false
inst_type: hmac
addr_range:
[
@@ -8543,14 +8553,15 @@
]
xbar: false
stub: false
- pipeline: "true"
+ pipeline: true
}
{
name: kmac
type: device
clock: clk_main_i
reset: rst_main_ni
- pipeline_byp: "false"
+ req_fifo_pass: false
+ rsp_fifo_pass: false
inst_type: kmac
addr_range:
[
@@ -8561,14 +8572,15 @@
]
xbar: false
stub: false
- pipeline: "true"
+ pipeline: true
}
{
name: aes
type: device
clock: clk_main_i
reset: rst_main_ni
- pipeline_byp: "false"
+ req_fifo_pass: false
+ rsp_fifo_pass: false
inst_type: aes
addr_range:
[
@@ -8579,14 +8591,15 @@
]
xbar: false
stub: false
- pipeline: "true"
+ pipeline: true
}
{
name: entropy_src
type: device
clock: clk_main_i
reset: rst_main_ni
- pipeline_byp: "false"
+ req_fifo_pass: false
+ rsp_fifo_pass: false
inst_type: entropy_src
addr_range:
[
@@ -8597,14 +8610,15 @@
]
xbar: false
stub: false
- pipeline: "true"
+ pipeline: true
}
{
name: csrng
type: device
clock: clk_main_i
reset: rst_main_ni
- pipeline_byp: "false"
+ req_fifo_pass: false
+ rsp_fifo_pass: false
inst_type: csrng
addr_range:
[
@@ -8615,14 +8629,15 @@
]
xbar: false
stub: false
- pipeline: "true"
+ pipeline: true
}
{
name: edn0
type: device
clock: clk_main_i
reset: rst_main_ni
- pipeline_byp: "false"
+ req_fifo_pass: false
+ rsp_fifo_pass: false
inst_type: edn
addr_range:
[
@@ -8633,14 +8648,15 @@
]
xbar: false
stub: false
- pipeline: "true"
+ pipeline: true
}
{
name: edn1
type: device
clock: clk_main_i
reset: rst_main_ni
- pipeline_byp: "false"
+ req_fifo_pass: false
+ rsp_fifo_pass: false
inst_type: edn
addr_range:
[
@@ -8651,7 +8667,7 @@
]
xbar: false
stub: false
- pipeline: "true"
+ pipeline: true
}
{
name: rv_plic
@@ -8659,7 +8675,8 @@
clock: clk_main_i
reset: rst_main_ni
inst_type: rv_plic
- pipeline_byp: "false"
+ req_fifo_pass: false
+ rsp_fifo_pass: false
addr_range:
[
{
@@ -8669,14 +8686,15 @@
]
xbar: false
stub: false
- pipeline: "true"
+ pipeline: true
}
{
name: otbn
type: device
clock: clk_main_i
reset: rst_main_ni
- pipeline_byp: "false"
+ req_fifo_pass: false
+ rsp_fifo_pass: false
inst_type: otbn
addr_range:
[
@@ -8687,14 +8705,15 @@
]
xbar: false
stub: false
- pipeline: "true"
+ pipeline: true
}
{
name: keymgr
type: device
clock: clk_main_i
reset: rst_main_ni
- pipeline_byp: "false"
+ req_fifo_pass: false
+ rsp_fifo_pass: false
inst_type: keymgr
addr_range:
[
@@ -8705,14 +8724,15 @@
]
xbar: false
stub: false
- pipeline: "true"
+ pipeline: true
}
{
name: rv_core_ibex.cfg
type: device
clock: clk_main_i
reset: rst_main_ni
- pipeline_byp: "false"
+ req_fifo_pass: false
+ rsp_fifo_pass: false
inst_type: rv_core_ibex
addr_range:
[
@@ -8723,14 +8743,14 @@
]
xbar: false
stub: false
- pipeline: "true"
+ pipeline: true
}
{
name: sram_ctrl_main.regs
type: device
clock: clk_main_i
reset: rst_main_ni
- pipeline: "false"
+ pipeline: false
inst_type: sram_ctrl
addr_range:
[
@@ -8741,14 +8761,14 @@
]
xbar: false
stub: false
- pipeline_byp: "true"
+ req_fifo_pass: true
}
{
name: sram_ctrl_main.ram
type: device
clock: clk_main_i
reset: rst_main_ni
- pipeline: "false"
+ pipeline: false
inst_type: sram_ctrl
addr_range:
[
@@ -8759,7 +8779,7 @@
]
xbar: false
stub: false
- pipeline_byp: "true"
+ req_fifo_pass: true
}
]
clock: clk_main_i
@@ -9150,17 +9170,18 @@
clock: clk_peri_i
reset: rst_peri_ni
xbar: true
- pipeline: "false"
+ pipeline: false
stub: false
inst_type: ""
- pipeline_byp: "true"
+ req_fifo_pass: true
+ rsp_fifo_pass: true
}
{
name: uart0
type: device
clock: clk_peri_i
reset: rst_peri_ni
- pipeline: "false"
+ pipeline: false
inst_type: uart
addr_range:
[
@@ -9171,14 +9192,14 @@
]
xbar: false
stub: false
- pipeline_byp: "true"
+ req_fifo_pass: true
}
{
name: uart1
type: device
clock: clk_peri_i
reset: rst_peri_ni
- pipeline: "false"
+ pipeline: false
inst_type: uart
addr_range:
[
@@ -9189,14 +9210,14 @@
]
xbar: false
stub: false
- pipeline_byp: "true"
+ req_fifo_pass: true
}
{
name: uart2
type: device
clock: clk_peri_i
reset: rst_peri_ni
- pipeline: "false"
+ pipeline: false
inst_type: uart
addr_range:
[
@@ -9207,14 +9228,14 @@
]
xbar: false
stub: false
- pipeline_byp: "true"
+ req_fifo_pass: true
}
{
name: uart3
type: device
clock: clk_peri_i
reset: rst_peri_ni
- pipeline: "false"
+ pipeline: false
inst_type: uart
addr_range:
[
@@ -9225,14 +9246,14 @@
]
xbar: false
stub: false
- pipeline_byp: "true"
+ req_fifo_pass: true
}
{
name: i2c0
type: device
clock: clk_peri_i
reset: rst_peri_ni
- pipeline: "false"
+ pipeline: false
inst_type: i2c
addr_range:
[
@@ -9243,14 +9264,14 @@
]
xbar: false
stub: false
- pipeline_byp: "true"
+ req_fifo_pass: true
}
{
name: i2c1
type: device
clock: clk_peri_i
reset: rst_peri_ni
- pipeline: "false"
+ pipeline: false
inst_type: i2c
addr_range:
[
@@ -9261,14 +9282,14 @@
]
xbar: false
stub: false
- pipeline_byp: "true"
+ req_fifo_pass: true
}
{
name: i2c2
type: device
clock: clk_peri_i
reset: rst_peri_ni
- pipeline: "false"
+ pipeline: false
inst_type: i2c
addr_range:
[
@@ -9279,14 +9300,14 @@
]
xbar: false
stub: false
- pipeline_byp: "true"
+ req_fifo_pass: true
}
{
name: pattgen
type: device
clock: clk_peri_i
reset: rst_peri_ni
- pipeline: "false"
+ pipeline: false
inst_type: pattgen
addr_range:
[
@@ -9297,14 +9318,14 @@
]
xbar: false
stub: false
- pipeline_byp: "true"
+ req_fifo_pass: true
}
{
name: pwm_aon
type: device
clock: clk_peri_i
reset: rst_peri_ni
- pipeline: "false"
+ pipeline: false
inst_type: pwm
addr_range:
[
@@ -9315,14 +9336,14 @@
]
xbar: false
stub: false
- pipeline_byp: "true"
+ req_fifo_pass: true
}
{
name: gpio
type: device
clock: clk_peri_i
reset: rst_peri_ni
- pipeline: "false"
+ pipeline: false
inst_type: gpio
addr_range:
[
@@ -9333,14 +9354,14 @@
]
xbar: false
stub: false
- pipeline_byp: "true"
+ req_fifo_pass: true
}
{
name: spi_device
type: device
clock: clk_peri_i
reset: rst_peri_ni
- pipeline: "false"
+ pipeline: false
inst_type: spi_device
addr_range:
[
@@ -9351,14 +9372,14 @@
]
xbar: false
stub: false
- pipeline_byp: "true"
+ req_fifo_pass: true
}
{
name: rv_timer
type: device
clock: clk_peri_i
reset: rst_peri_ni
- pipeline: "false"
+ pipeline: false
inst_type: rv_timer
addr_range:
[
@@ -9369,14 +9390,14 @@
]
xbar: false
stub: false
- pipeline_byp: "true"
+ req_fifo_pass: true
}
{
name: usbdev
type: device
clock: clk_peri_i
reset: rst_peri_ni
- pipeline: "false"
+ pipeline: false
inst_type: usbdev
addr_range:
[
@@ -9387,14 +9408,14 @@
]
xbar: false
stub: false
- pipeline_byp: "true"
+ req_fifo_pass: true
}
{
name: pwrmgr_aon
type: device
clock: clk_peri_i
reset: rst_peri_ni
- pipeline: "false"
+ pipeline: false
inst_type: pwrmgr
addr_range:
[
@@ -9405,14 +9426,14 @@
]
xbar: false
stub: false
- pipeline_byp: "true"
+ req_fifo_pass: true
}
{
name: rstmgr_aon
type: device
clock: clk_peri_i
reset: rst_peri_ni
- pipeline: "false"
+ pipeline: false
inst_type: rstmgr
addr_range:
[
@@ -9423,14 +9444,14 @@
]
xbar: false
stub: false
- pipeline_byp: "true"
+ req_fifo_pass: true
}
{
name: clkmgr_aon
type: device
clock: clk_peri_i
reset: rst_peri_ni
- pipeline: "false"
+ pipeline: false
inst_type: clkmgr
addr_range:
[
@@ -9441,14 +9462,14 @@
]
xbar: false
stub: false
- pipeline_byp: "true"
+ req_fifo_pass: true
}
{
name: pinmux_aon
type: device
clock: clk_peri_i
reset: rst_peri_ni
- pipeline: "false"
+ pipeline: false
inst_type: pinmux
addr_range:
[
@@ -9459,14 +9480,14 @@
]
xbar: false
stub: false
- pipeline_byp: "true"
+ req_fifo_pass: true
}
{
name: otp_ctrl.core
type: device
clock: clk_peri_i
reset: rst_peri_ni
- pipeline: "false"
+ pipeline: false
inst_type: otp_ctrl
addr_range:
[
@@ -9477,14 +9498,14 @@
]
xbar: false
stub: false
- pipeline_byp: "true"
+ req_fifo_pass: true
}
{
name: otp_ctrl.prim
type: device
clock: clk_peri_i
reset: rst_peri_ni
- pipeline: "false"
+ pipeline: false
inst_type: otp_ctrl
addr_range:
[
@@ -9495,14 +9516,14 @@
]
xbar: false
stub: false
- pipeline_byp: "true"
+ req_fifo_pass: true
}
{
name: lc_ctrl
type: device
clock: clk_peri_i
reset: rst_peri_ni
- pipeline: "false"
+ pipeline: false
inst_type: lc_ctrl
addr_range:
[
@@ -9513,14 +9534,14 @@
]
xbar: false
stub: false
- pipeline_byp: "true"
+ req_fifo_pass: true
}
{
name: sensor_ctrl
type: device
clock: clk_peri_i
reset: rst_peri_ni
- pipeline: "false"
+ pipeline: false
inst_type: sensor_ctrl
addr_range:
[
@@ -9531,14 +9552,14 @@
]
xbar: false
stub: false
- pipeline_byp: "true"
+ req_fifo_pass: true
}
{
name: alert_handler
type: device
clock: clk_peri_i
reset: rst_peri_ni
- pipeline: "false"
+ pipeline: false
inst_type: alert_handler
addr_range:
[
@@ -9549,14 +9570,14 @@
]
xbar: false
stub: false
- pipeline_byp: "true"
+ req_fifo_pass: true
}
{
name: sram_ctrl_ret_aon.regs
type: device
clock: clk_peri_i
reset: rst_peri_ni
- pipeline: "false"
+ pipeline: false
inst_type: sram_ctrl
addr_range:
[
@@ -9567,14 +9588,14 @@
]
xbar: false
stub: false
- pipeline_byp: "true"
+ req_fifo_pass: true
}
{
name: sram_ctrl_ret_aon.ram
type: device
clock: clk_peri_i
reset: rst_peri_ni
- pipeline: "false"
+ pipeline: false
inst_type: sram_ctrl
addr_range:
[
@@ -9585,14 +9606,14 @@
]
xbar: false
stub: false
- pipeline_byp: "true"
+ req_fifo_pass: true
}
{
name: aon_timer_aon
type: device
clock: clk_peri_i
reset: rst_peri_ni
- pipeline: "false"
+ pipeline: false
inst_type: aon_timer
addr_range:
[
@@ -9603,14 +9624,14 @@
]
xbar: false
stub: false
- pipeline_byp: "true"
+ req_fifo_pass: true
}
{
name: sysrst_ctrl_aon
type: device
clock: clk_peri_i
reset: rst_peri_ni
- pipeline: "false"
+ pipeline: false
inst_type: sysrst_ctrl
addr_range:
[
@@ -9621,14 +9642,14 @@
]
xbar: false
stub: false
- pipeline_byp: "true"
+ req_fifo_pass: true
}
{
name: adc_ctrl_aon
type: device
clock: clk_peri_i
reset: rst_peri_ni
- pipeline: "false"
+ pipeline: false
inst_type: adc_ctrl
addr_range:
[
@@ -9639,14 +9660,14 @@
]
xbar: false
stub: false
- pipeline_byp: "true"
+ req_fifo_pass: true
}
{
name: ast
type: device
clock: clk_peri_i
reset: rst_peri_ni
- pipeline: "false"
+ pipeline: false
inst_type: ast
addr_range:
[
@@ -9657,7 +9678,7 @@
]
xbar: false
stub: true
- pipeline_byp: "true"
+ req_fifo_pass: true
}
]
clock: clk_peri_i
diff --git a/hw/top_earlgrey/data/xbar_main.hjson b/hw/top_earlgrey/data/xbar_main.hjson
index 93d2f11..12a58b9 100644
--- a/hw/top_earlgrey/data/xbar_main.hjson
+++ b/hw/top_earlgrey/data/xbar_main.hjson
@@ -13,159 +13,177 @@
type: "host",
clock: "clk_main_i",
reset: "rst_main_ni",
- pipeline: "false"
+ pipeline: false
},
{ name: "rv_core_ibex.cored",
type: "host",
clock: "clk_main_i",
reset: "rst_main_ni",
- pipeline: "false"
+ pipeline: false
},
{ name: "rv_dm.sba",
type: "host",
clock: "clk_main_i",
reset: "rst_main_ni",
- pipeline_byp: "false"
+ req_fifo_pass: false,
+ rsp_fifo_pass: false,
},
{ name: "rv_dm.regs",
type: "device",
clock: "clk_main_i",
reset: "rst_main_ni",
- pipeline_byp: "false"
+ req_fifo_pass: false,
+ rsp_fifo_pass: false,
},
{ name: "rv_dm.rom",
type: "device",
clock: "clk_main_i",
reset: "rst_main_ni",
- pipeline_byp: "false"
+ req_fifo_pass: false,
+ rsp_fifo_pass: false,
},
{ name: "rom_ctrl.rom",
type: "device",
clock: "clk_main_i",
reset: "rst_main_ni",
- pipeline: "false",
+ pipeline: false,
},
{ name: "rom_ctrl.regs",
type: "device",
clock: "clk_main_i",
reset: "rst_main_ni",
- pipeline: "false",
+ pipeline: false,
},
{ name: "peri",
type: "device",
clock: "clk_fixed_i",
reset: "rst_fixed_ni",
- pipeline_byp: "false"
+ req_fifo_pass: false,
+ rsp_fifo_pass: false,
},
{ name: "spi_host0",
type: "device",
clock: "clk_spi_host0_i",
reset: "rst_spi_host0_ni",
- pipeline: "false"
+ pipeline: false
},
{ name: "spi_host1",
type: "device",
clock: "clk_spi_host1_i",
reset: "rst_spi_host1_ni",
- pipeline: "false"
+ pipeline: false
},
{ name: "flash_ctrl.core",
type: "device",
clock: "clk_main_i",
reset: "rst_main_ni",
- pipeline_byp: "false"
+ req_fifo_pass: false,
+ rsp_fifo_pass: false,
},
{ name: "flash_ctrl.prim",
type: "device",
clock: "clk_main_i",
reset: "rst_main_ni",
- pipeline_byp: "false"
+ req_fifo_pass: false,
+ rsp_fifo_pass: false,
},
{ name: "flash_ctrl.mem",
type: "device",
clock: "clk_main_i",
reset: "rst_main_ni",
- pipeline_byp: "false"
+ req_fifo_pass: false,
+ rsp_fifo_pass: false,
},
{ name: "hmac",
type: "device",
clock: "clk_main_i",
reset: "rst_main_ni",
- pipeline_byp: "false"
+ req_fifo_pass: false,
+ rsp_fifo_pass: false,
},
{ name: "kmac"
type: "device"
clock: "clk_main_i"
reset: "rst_main_ni"
- pipeline_byp: "false"
+ req_fifo_pass: false,
+ rsp_fifo_pass: false,
}
{ name: "aes",
type: "device",
clock: "clk_main_i"
reset: "rst_main_ni"
- pipeline_byp: "false"
+ req_fifo_pass: false,
+ rsp_fifo_pass: false,
},
{ name: "entropy_src",
type: "device",
clock: "clk_main_i"
reset: "rst_main_ni"
- pipeline_byp: "false"
+ req_fifo_pass: false,
+ rsp_fifo_pass: false,
},
{ name: "csrng",
type: "device",
clock: "clk_main_i"
reset: "rst_main_ni"
- pipeline_byp: "false"
+ req_fifo_pass: false,
+ rsp_fifo_pass: false,
},
{ name: "edn0",
type: "device",
clock: "clk_main_i"
reset: "rst_main_ni"
- pipeline_byp: "false"
+ req_fifo_pass: false,
+ rsp_fifo_pass: false,
},
{ name: "edn1",
type: "device",
clock: "clk_main_i"
reset: "rst_main_ni"
- pipeline_byp: "false"
+ req_fifo_pass: false,
+ rsp_fifo_pass: false,
},
{ name: "rv_plic",
type: "device",
clock: "clk_main_i",
reset: "rst_main_ni",
inst_type: "rv_plic",
- pipeline_byp: "false"
+ req_fifo_pass: false,
+ rsp_fifo_pass: false,
},
{ name: "otbn",
type: "device",
clock: "clk_main_i"
reset: "rst_main_ni"
- pipeline_byp: "false"
+ req_fifo_pass: false,
+ rsp_fifo_pass: false,
},
{ name: "keymgr",
type: "device",
clock: "clk_main_i"
reset: "rst_main_ni"
- pipeline_byp: "false"
+ req_fifo_pass: false,
+ rsp_fifo_pass: false,
},
{ name: "rv_core_ibex.cfg",
type: "device",
clock: "clk_main_i"
reset: "rst_main_ni"
- pipeline_byp: "false"
+ req_fifo_pass: false,
+ rsp_fifo_pass: false,
},
{ name: "sram_ctrl_main.regs",
type: "device",
clock: "clk_main_i",
reset: "rst_main_ni",
- pipeline: "false"
+ pipeline: false
},
{ name: "sram_ctrl_main.ram",
type: "device",
clock: "clk_main_i",
reset: "rst_main_ni",
- pipeline: "false"
+ pipeline: false
},
],
connections: {
diff --git a/hw/top_earlgrey/data/xbar_peri.hjson b/hw/top_earlgrey/data/xbar_peri.hjson
index 2f6b473..79dd217 100644
--- a/hw/top_earlgrey/data/xbar_peri.hjson
+++ b/hw/top_earlgrey/data/xbar_peri.hjson
@@ -14,176 +14,176 @@
clock: "clk_peri_i",
reset: "rst_peri_ni",
xbar: "true",
- pipeline: "false"
+ pipeline: false
},
{ name: "uart0",
type: "device",
clock: "clk_peri_i",
reset: "rst_peri_ni",
- pipeline: "false"
+ pipeline: false
},
{ name: "uart1",
type: "device",
clock: "clk_peri_i",
reset: "rst_peri_ni",
- pipeline: "false"
+ pipeline: false
},
{ name: "uart2",
type: "device",
clock: "clk_peri_i",
reset: "rst_peri_ni",
- pipeline: "false"
+ pipeline: false
},
{ name: "uart3",
type: "device",
clock: "clk_peri_i",
reset: "rst_peri_ni",
- pipeline: "false"
+ pipeline: false
},
{ name: "i2c0",
type: "device",
clock: "clk_peri_i",
reset: "rst_peri_ni",
- pipeline: "false"
+ pipeline: false
},
{ name: "i2c1",
type: "device",
clock: "clk_peri_i",
reset: "rst_peri_ni",
- pipeline: "false"
+ pipeline: false
},
{ name: "i2c2",
type: "device",
clock: "clk_peri_i",
reset: "rst_peri_ni",
- pipeline: "false"
+ pipeline: false
},
{ name: "pattgen",
type: "device",
clock: "clk_peri_i",
reset: "rst_peri_ni",
- pipeline: "false"
+ pipeline: false
},
{ name: "pwm_aon",
type: "device",
clock: "clk_peri_i",
reset: "rst_peri_ni",
- pipeline: "false"
+ pipeline: false
},
{ name: "gpio",
type: "device",
clock: "clk_peri_i",
reset: "rst_peri_ni",
- pipeline: "false"
+ pipeline: false
},
{ name: "spi_device",
type: "device",
clock: "clk_peri_i",
reset: "rst_peri_ni",
- pipeline: "false"
+ pipeline: false
},
{ name: "rv_timer",
type: "device",
clock: "clk_peri_i",
reset: "rst_peri_ni",
- pipeline: "false"
+ pipeline: false
},
{ name: "usbdev",
type: "device",
clock: "clk_peri_i",
reset: "rst_peri_ni",
- pipeline: "false"
+ pipeline: false
},
{ name: "pwrmgr_aon",
type: "device",
clock: "clk_peri_i",
reset: "rst_peri_ni",
- pipeline: "false"
+ pipeline: false
},
{ name: "rstmgr_aon",
type: "device",
clock: "clk_peri_i",
reset: "rst_peri_ni",
- pipeline: "false"
+ pipeline: false
},
{ name: "clkmgr_aon",
type: "device",
clock: "clk_peri_i",
reset: "rst_peri_ni",
- pipeline: "false"
+ pipeline: false
},
{ name: "pinmux_aon",
type: "device",
clock: "clk_peri_i",
reset: "rst_peri_ni",
- pipeline: "false"
+ pipeline: false
},
{ name: "otp_ctrl.core",
type: "device",
clock: "clk_peri_i",
reset: "rst_peri_ni",
- pipeline: "false"
+ pipeline: false
},
{ name: "otp_ctrl.prim",
type: "device",
clock: "clk_peri_i",
reset: "rst_peri_ni",
- pipeline: "false"
+ pipeline: false
},
{ name: "lc_ctrl",
type: "device",
clock: "clk_peri_i",
reset: "rst_peri_ni",
- pipeline: "false"
+ pipeline: false
},
{ name: "sensor_ctrl",
type: "device",
clock: "clk_peri_i",
reset: "rst_peri_ni",
- pipeline: "false",
+ pipeline: false,
},
{ name: "alert_handler",
type: "device",
clock: "clk_peri_i",
reset: "rst_peri_ni",
- pipeline: "false",
+ pipeline: false,
},
{ name: "sram_ctrl_ret_aon.regs",
type: "device",
clock: "clk_peri_i",
reset: "rst_peri_ni",
- pipeline: "false"
+ pipeline: false
},
{ name: "sram_ctrl_ret_aon.ram",
type: "device",
clock: "clk_peri_i",
reset: "rst_peri_ni",
- pipeline: "false"
+ pipeline: false
},
{ name: "aon_timer_aon",
type: "device",
clock: "clk_peri_i",
reset: "rst_peri_ni",
- pipeline: "false",
+ pipeline: false,
},
{ name: "sysrst_ctrl_aon",
type: "device",
clock: "clk_peri_i",
reset: "rst_peri_ni",
- pipeline: "false",
+ pipeline: false,
}
{ name: "adc_ctrl_aon",
type: "device",
clock: "clk_peri_i",
reset: "rst_peri_ni",
- pipeline: "false",
+ pipeline: false,
}
{ name: "ast",
type: "device",
clock: "clk_peri_i",
reset: "rst_peri_ni",
- pipeline: "false",
+ pipeline: false,
},
],
connections: {
diff --git a/hw/top_earlgrey/ip/xbar_main/data/autogen/xbar_main.gen.hjson b/hw/top_earlgrey/ip/xbar_main/data/autogen/xbar_main.gen.hjson
index c1902a5..3daa602 100644
--- a/hw/top_earlgrey/ip/xbar_main/data/autogen/xbar_main.gen.hjson
+++ b/hw/top_earlgrey/ip/xbar_main/data/autogen/xbar_main.gen.hjson
@@ -119,40 +119,44 @@
type: host
clock: clk_main_i
reset: rst_main_ni
- pipeline: "false"
+ pipeline: false
xbar: false
stub: false
inst_type: ""
- pipeline_byp: "true"
+ req_fifo_pass: true
+ rsp_fifo_pass: true
}
{
name: rv_core_ibex.cored
type: host
clock: clk_main_i
reset: rst_main_ni
- pipeline: "false"
+ pipeline: false
xbar: false
stub: false
inst_type: ""
- pipeline_byp: "true"
+ req_fifo_pass: true
+ rsp_fifo_pass: true
}
{
name: rv_dm.sba
type: host
clock: clk_main_i
reset: rst_main_ni
- pipeline_byp: "false"
+ req_fifo_pass: false
+ rsp_fifo_pass: false
xbar: false
stub: false
inst_type: ""
- pipeline: "true"
+ pipeline: true
}
{
name: rv_dm.regs
type: device
clock: clk_main_i
reset: rst_main_ni
- pipeline_byp: "false"
+ req_fifo_pass: false
+ rsp_fifo_pass: false
inst_type: rv_dm
addr_range:
[
@@ -163,14 +167,15 @@
]
xbar: false
stub: false
- pipeline: "true"
+ pipeline: true
}
{
name: rv_dm.rom
type: device
clock: clk_main_i
reset: rst_main_ni
- pipeline_byp: "false"
+ req_fifo_pass: false
+ rsp_fifo_pass: false
inst_type: rv_dm
addr_range:
[
@@ -181,14 +186,14 @@
]
xbar: false
stub: false
- pipeline: "true"
+ pipeline: true
}
{
name: rom_ctrl.rom
type: device
clock: clk_main_i
reset: rst_main_ni
- pipeline: "false"
+ pipeline: false
inst_type: rom_ctrl
addr_range:
[
@@ -199,14 +204,14 @@
]
xbar: false
stub: false
- pipeline_byp: "true"
+ req_fifo_pass: true
}
{
name: rom_ctrl.regs
type: device
clock: clk_main_i
reset: rst_main_ni
- pipeline: "false"
+ pipeline: false
inst_type: rom_ctrl
addr_range:
[
@@ -217,17 +222,18 @@
]
xbar: false
stub: false
- pipeline_byp: "true"
+ req_fifo_pass: true
}
{
name: peri
type: device
clock: clk_fixed_i
reset: rst_fixed_ni
- pipeline_byp: "false"
+ req_fifo_pass: false
+ rsp_fifo_pass: false
xbar: true
stub: false
- pipeline: "true"
+ pipeline: true
addr_range:
[
{
@@ -245,7 +251,7 @@
type: device
clock: clk_spi_host0_i
reset: rst_spi_host0_ni
- pipeline: "false"
+ pipeline: false
inst_type: spi_host
addr_range:
[
@@ -256,14 +262,14 @@
]
xbar: false
stub: false
- pipeline_byp: "true"
+ req_fifo_pass: true
}
{
name: spi_host1
type: device
clock: clk_spi_host1_i
reset: rst_spi_host1_ni
- pipeline: "false"
+ pipeline: false
inst_type: spi_host
addr_range:
[
@@ -274,14 +280,15 @@
]
xbar: false
stub: false
- pipeline_byp: "true"
+ req_fifo_pass: true
}
{
name: flash_ctrl.core
type: device
clock: clk_main_i
reset: rst_main_ni
- pipeline_byp: "false"
+ req_fifo_pass: false
+ rsp_fifo_pass: false
inst_type: flash_ctrl
addr_range:
[
@@ -292,14 +299,15 @@
]
xbar: false
stub: false
- pipeline: "true"
+ pipeline: true
}
{
name: flash_ctrl.prim
type: device
clock: clk_main_i
reset: rst_main_ni
- pipeline_byp: "false"
+ req_fifo_pass: false
+ rsp_fifo_pass: false
inst_type: flash_ctrl
addr_range:
[
@@ -310,14 +318,15 @@
]
xbar: false
stub: false
- pipeline: "true"
+ pipeline: true
}
{
name: flash_ctrl.mem
type: device
clock: clk_main_i
reset: rst_main_ni
- pipeline_byp: "false"
+ req_fifo_pass: false
+ rsp_fifo_pass: false
inst_type: flash_ctrl
addr_range:
[
@@ -328,14 +337,15 @@
]
xbar: false
stub: false
- pipeline: "true"
+ pipeline: true
}
{
name: hmac
type: device
clock: clk_main_i
reset: rst_main_ni
- pipeline_byp: "false"
+ req_fifo_pass: false
+ rsp_fifo_pass: false
inst_type: hmac
addr_range:
[
@@ -346,14 +356,15 @@
]
xbar: false
stub: false
- pipeline: "true"
+ pipeline: true
}
{
name: kmac
type: device
clock: clk_main_i
reset: rst_main_ni
- pipeline_byp: "false"
+ req_fifo_pass: false
+ rsp_fifo_pass: false
inst_type: kmac
addr_range:
[
@@ -364,14 +375,15 @@
]
xbar: false
stub: false
- pipeline: "true"
+ pipeline: true
}
{
name: aes
type: device
clock: clk_main_i
reset: rst_main_ni
- pipeline_byp: "false"
+ req_fifo_pass: false
+ rsp_fifo_pass: false
inst_type: aes
addr_range:
[
@@ -382,14 +394,15 @@
]
xbar: false
stub: false
- pipeline: "true"
+ pipeline: true
}
{
name: entropy_src
type: device
clock: clk_main_i
reset: rst_main_ni
- pipeline_byp: "false"
+ req_fifo_pass: false
+ rsp_fifo_pass: false
inst_type: entropy_src
addr_range:
[
@@ -400,14 +413,15 @@
]
xbar: false
stub: false
- pipeline: "true"
+ pipeline: true
}
{
name: csrng
type: device
clock: clk_main_i
reset: rst_main_ni
- pipeline_byp: "false"
+ req_fifo_pass: false
+ rsp_fifo_pass: false
inst_type: csrng
addr_range:
[
@@ -418,14 +432,15 @@
]
xbar: false
stub: false
- pipeline: "true"
+ pipeline: true
}
{
name: edn0
type: device
clock: clk_main_i
reset: rst_main_ni
- pipeline_byp: "false"
+ req_fifo_pass: false
+ rsp_fifo_pass: false
inst_type: edn
addr_range:
[
@@ -436,14 +451,15 @@
]
xbar: false
stub: false
- pipeline: "true"
+ pipeline: true
}
{
name: edn1
type: device
clock: clk_main_i
reset: rst_main_ni
- pipeline_byp: "false"
+ req_fifo_pass: false
+ rsp_fifo_pass: false
inst_type: edn
addr_range:
[
@@ -454,7 +470,7 @@
]
xbar: false
stub: false
- pipeline: "true"
+ pipeline: true
}
{
name: rv_plic
@@ -462,7 +478,8 @@
clock: clk_main_i
reset: rst_main_ni
inst_type: rv_plic
- pipeline_byp: "false"
+ req_fifo_pass: false
+ rsp_fifo_pass: false
addr_range:
[
{
@@ -472,14 +489,15 @@
]
xbar: false
stub: false
- pipeline: "true"
+ pipeline: true
}
{
name: otbn
type: device
clock: clk_main_i
reset: rst_main_ni
- pipeline_byp: "false"
+ req_fifo_pass: false
+ rsp_fifo_pass: false
inst_type: otbn
addr_range:
[
@@ -490,14 +508,15 @@
]
xbar: false
stub: false
- pipeline: "true"
+ pipeline: true
}
{
name: keymgr
type: device
clock: clk_main_i
reset: rst_main_ni
- pipeline_byp: "false"
+ req_fifo_pass: false
+ rsp_fifo_pass: false
inst_type: keymgr
addr_range:
[
@@ -508,14 +527,15 @@
]
xbar: false
stub: false
- pipeline: "true"
+ pipeline: true
}
{
name: rv_core_ibex.cfg
type: device
clock: clk_main_i
reset: rst_main_ni
- pipeline_byp: "false"
+ req_fifo_pass: false
+ rsp_fifo_pass: false
inst_type: rv_core_ibex
addr_range:
[
@@ -526,14 +546,14 @@
]
xbar: false
stub: false
- pipeline: "true"
+ pipeline: true
}
{
name: sram_ctrl_main.regs
type: device
clock: clk_main_i
reset: rst_main_ni
- pipeline: "false"
+ pipeline: false
inst_type: sram_ctrl
addr_range:
[
@@ -544,14 +564,14 @@
]
xbar: false
stub: false
- pipeline_byp: "true"
+ req_fifo_pass: true
}
{
name: sram_ctrl_main.ram
type: device
clock: clk_main_i
reset: rst_main_ni
- pipeline: "false"
+ pipeline: false
inst_type: sram_ctrl
addr_range:
[
@@ -562,7 +582,7 @@
]
xbar: false
stub: false
- pipeline_byp: "true"
+ req_fifo_pass: true
}
]
clock: clk_main_i
diff --git a/hw/top_earlgrey/ip/xbar_peri/data/autogen/xbar_peri.gen.hjson b/hw/top_earlgrey/ip/xbar_peri/data/autogen/xbar_peri.gen.hjson
index 3523875..0aec9a2 100644
--- a/hw/top_earlgrey/ip/xbar_peri/data/autogen/xbar_peri.gen.hjson
+++ b/hw/top_earlgrey/ip/xbar_peri/data/autogen/xbar_peri.gen.hjson
@@ -72,17 +72,18 @@
clock: clk_peri_i
reset: rst_peri_ni
xbar: true
- pipeline: "false"
+ pipeline: false
stub: false
inst_type: ""
- pipeline_byp: "true"
+ req_fifo_pass: true
+ rsp_fifo_pass: true
}
{
name: uart0
type: device
clock: clk_peri_i
reset: rst_peri_ni
- pipeline: "false"
+ pipeline: false
inst_type: uart
addr_range:
[
@@ -93,14 +94,14 @@
]
xbar: false
stub: false
- pipeline_byp: "true"
+ req_fifo_pass: true
}
{
name: uart1
type: device
clock: clk_peri_i
reset: rst_peri_ni
- pipeline: "false"
+ pipeline: false
inst_type: uart
addr_range:
[
@@ -111,14 +112,14 @@
]
xbar: false
stub: false
- pipeline_byp: "true"
+ req_fifo_pass: true
}
{
name: uart2
type: device
clock: clk_peri_i
reset: rst_peri_ni
- pipeline: "false"
+ pipeline: false
inst_type: uart
addr_range:
[
@@ -129,14 +130,14 @@
]
xbar: false
stub: false
- pipeline_byp: "true"
+ req_fifo_pass: true
}
{
name: uart3
type: device
clock: clk_peri_i
reset: rst_peri_ni
- pipeline: "false"
+ pipeline: false
inst_type: uart
addr_range:
[
@@ -147,14 +148,14 @@
]
xbar: false
stub: false
- pipeline_byp: "true"
+ req_fifo_pass: true
}
{
name: i2c0
type: device
clock: clk_peri_i
reset: rst_peri_ni
- pipeline: "false"
+ pipeline: false
inst_type: i2c
addr_range:
[
@@ -165,14 +166,14 @@
]
xbar: false
stub: false
- pipeline_byp: "true"
+ req_fifo_pass: true
}
{
name: i2c1
type: device
clock: clk_peri_i
reset: rst_peri_ni
- pipeline: "false"
+ pipeline: false
inst_type: i2c
addr_range:
[
@@ -183,14 +184,14 @@
]
xbar: false
stub: false
- pipeline_byp: "true"
+ req_fifo_pass: true
}
{
name: i2c2
type: device
clock: clk_peri_i
reset: rst_peri_ni
- pipeline: "false"
+ pipeline: false
inst_type: i2c
addr_range:
[
@@ -201,14 +202,14 @@
]
xbar: false
stub: false
- pipeline_byp: "true"
+ req_fifo_pass: true
}
{
name: pattgen
type: device
clock: clk_peri_i
reset: rst_peri_ni
- pipeline: "false"
+ pipeline: false
inst_type: pattgen
addr_range:
[
@@ -219,14 +220,14 @@
]
xbar: false
stub: false
- pipeline_byp: "true"
+ req_fifo_pass: true
}
{
name: pwm_aon
type: device
clock: clk_peri_i
reset: rst_peri_ni
- pipeline: "false"
+ pipeline: false
inst_type: pwm
addr_range:
[
@@ -237,14 +238,14 @@
]
xbar: false
stub: false
- pipeline_byp: "true"
+ req_fifo_pass: true
}
{
name: gpio
type: device
clock: clk_peri_i
reset: rst_peri_ni
- pipeline: "false"
+ pipeline: false
inst_type: gpio
addr_range:
[
@@ -255,14 +256,14 @@
]
xbar: false
stub: false
- pipeline_byp: "true"
+ req_fifo_pass: true
}
{
name: spi_device
type: device
clock: clk_peri_i
reset: rst_peri_ni
- pipeline: "false"
+ pipeline: false
inst_type: spi_device
addr_range:
[
@@ -273,14 +274,14 @@
]
xbar: false
stub: false
- pipeline_byp: "true"
+ req_fifo_pass: true
}
{
name: rv_timer
type: device
clock: clk_peri_i
reset: rst_peri_ni
- pipeline: "false"
+ pipeline: false
inst_type: rv_timer
addr_range:
[
@@ -291,14 +292,14 @@
]
xbar: false
stub: false
- pipeline_byp: "true"
+ req_fifo_pass: true
}
{
name: usbdev
type: device
clock: clk_peri_i
reset: rst_peri_ni
- pipeline: "false"
+ pipeline: false
inst_type: usbdev
addr_range:
[
@@ -309,14 +310,14 @@
]
xbar: false
stub: false
- pipeline_byp: "true"
+ req_fifo_pass: true
}
{
name: pwrmgr_aon
type: device
clock: clk_peri_i
reset: rst_peri_ni
- pipeline: "false"
+ pipeline: false
inst_type: pwrmgr
addr_range:
[
@@ -327,14 +328,14 @@
]
xbar: false
stub: false
- pipeline_byp: "true"
+ req_fifo_pass: true
}
{
name: rstmgr_aon
type: device
clock: clk_peri_i
reset: rst_peri_ni
- pipeline: "false"
+ pipeline: false
inst_type: rstmgr
addr_range:
[
@@ -345,14 +346,14 @@
]
xbar: false
stub: false
- pipeline_byp: "true"
+ req_fifo_pass: true
}
{
name: clkmgr_aon
type: device
clock: clk_peri_i
reset: rst_peri_ni
- pipeline: "false"
+ pipeline: false
inst_type: clkmgr
addr_range:
[
@@ -363,14 +364,14 @@
]
xbar: false
stub: false
- pipeline_byp: "true"
+ req_fifo_pass: true
}
{
name: pinmux_aon
type: device
clock: clk_peri_i
reset: rst_peri_ni
- pipeline: "false"
+ pipeline: false
inst_type: pinmux
addr_range:
[
@@ -381,14 +382,14 @@
]
xbar: false
stub: false
- pipeline_byp: "true"
+ req_fifo_pass: true
}
{
name: otp_ctrl.core
type: device
clock: clk_peri_i
reset: rst_peri_ni
- pipeline: "false"
+ pipeline: false
inst_type: otp_ctrl
addr_range:
[
@@ -399,14 +400,14 @@
]
xbar: false
stub: false
- pipeline_byp: "true"
+ req_fifo_pass: true
}
{
name: otp_ctrl.prim
type: device
clock: clk_peri_i
reset: rst_peri_ni
- pipeline: "false"
+ pipeline: false
inst_type: otp_ctrl
addr_range:
[
@@ -417,14 +418,14 @@
]
xbar: false
stub: false
- pipeline_byp: "true"
+ req_fifo_pass: true
}
{
name: lc_ctrl
type: device
clock: clk_peri_i
reset: rst_peri_ni
- pipeline: "false"
+ pipeline: false
inst_type: lc_ctrl
addr_range:
[
@@ -435,14 +436,14 @@
]
xbar: false
stub: false
- pipeline_byp: "true"
+ req_fifo_pass: true
}
{
name: sensor_ctrl
type: device
clock: clk_peri_i
reset: rst_peri_ni
- pipeline: "false"
+ pipeline: false
inst_type: sensor_ctrl
addr_range:
[
@@ -453,14 +454,14 @@
]
xbar: false
stub: false
- pipeline_byp: "true"
+ req_fifo_pass: true
}
{
name: alert_handler
type: device
clock: clk_peri_i
reset: rst_peri_ni
- pipeline: "false"
+ pipeline: false
inst_type: alert_handler
addr_range:
[
@@ -471,14 +472,14 @@
]
xbar: false
stub: false
- pipeline_byp: "true"
+ req_fifo_pass: true
}
{
name: sram_ctrl_ret_aon.regs
type: device
clock: clk_peri_i
reset: rst_peri_ni
- pipeline: "false"
+ pipeline: false
inst_type: sram_ctrl
addr_range:
[
@@ -489,14 +490,14 @@
]
xbar: false
stub: false
- pipeline_byp: "true"
+ req_fifo_pass: true
}
{
name: sram_ctrl_ret_aon.ram
type: device
clock: clk_peri_i
reset: rst_peri_ni
- pipeline: "false"
+ pipeline: false
inst_type: sram_ctrl
addr_range:
[
@@ -507,14 +508,14 @@
]
xbar: false
stub: false
- pipeline_byp: "true"
+ req_fifo_pass: true
}
{
name: aon_timer_aon
type: device
clock: clk_peri_i
reset: rst_peri_ni
- pipeline: "false"
+ pipeline: false
inst_type: aon_timer
addr_range:
[
@@ -525,14 +526,14 @@
]
xbar: false
stub: false
- pipeline_byp: "true"
+ req_fifo_pass: true
}
{
name: sysrst_ctrl_aon
type: device
clock: clk_peri_i
reset: rst_peri_ni
- pipeline: "false"
+ pipeline: false
inst_type: sysrst_ctrl
addr_range:
[
@@ -543,14 +544,14 @@
]
xbar: false
stub: false
- pipeline_byp: "true"
+ req_fifo_pass: true
}
{
name: adc_ctrl_aon
type: device
clock: clk_peri_i
reset: rst_peri_ni
- pipeline: "false"
+ pipeline: false
inst_type: adc_ctrl
addr_range:
[
@@ -561,14 +562,14 @@
]
xbar: false
stub: false
- pipeline_byp: "true"
+ req_fifo_pass: true
}
{
name: ast
type: device
clock: clk_peri_i
reset: rst_peri_ni
- pipeline: "false"
+ pipeline: false
inst_type: ast
addr_range:
[
@@ -579,7 +580,7 @@
]
xbar: false
stub: true
- pipeline_byp: "true"
+ req_fifo_pass: true
}
]
clock: clk_peri_i
diff --git a/hw/top_englishbreakfast/data/xbar_main.hjson b/hw/top_englishbreakfast/data/xbar_main.hjson
index 35962ca..03c1229 100644
--- a/hw/top_englishbreakfast/data/xbar_main.hjson
+++ b/hw/top_englishbreakfast/data/xbar_main.hjson
@@ -13,99 +13,111 @@
type: "host",
clock: "clk_main_i",
reset: "rst_main_ni",
- pipeline: "false"
+ pipeline: false
},
{ name: "rv_core_ibex.cored",
type: "host",
clock: "clk_main_i",
reset: "rst_main_ni",
- pipeline: "false"
+ pipeline: false
},
{ name: "rv_dm.regs",
type: "device",
clock: "clk_main_i",
reset: "rst_main_ni",
- pipeline_byp: "false"
+ req_fifo_pass: true,
+ rsp_fifo_pass: false,
},
{ name: "rv_dm.rom",
type: "device",
clock: "clk_main_i",
reset: "rst_main_ni",
- pipeline_byp: "false"
+ req_fifo_pass: true,
+ rsp_fifo_pass: false,
},
{ name: "rom_ctrl.rom",
type: "device",
clock: "clk_main_i",
reset: "rst_main_ni",
- pipeline: "false",
+ req_fifo_pass: true,
+ rsp_fifo_pass: false,
},
{ name: "rom_ctrl.regs",
type: "device",
clock: "clk_main_i",
reset: "rst_main_ni",
- pipeline: "false",
+ req_fifo_pass: true,
+ rsp_fifo_pass: false,
},
{ name: "peri",
type: "device",
clock: "clk_fixed_i",
reset: "rst_fixed_ni",
- pipeline_byp: "false"
+ req_fifo_pass: true,
+ rsp_fifo_pass: false,
},
{ name: "flash_ctrl.core",
type: "device",
clock: "clk_main_i",
reset: "rst_main_ni",
- pipeline_byp: "false"
+ req_fifo_pass: true,
+ rsp_fifo_pass: false,
},
{ name: "flash_ctrl.prim",
type: "device",
clock: "clk_main_i",
reset: "rst_main_ni",
- pipeline_byp: "false"
+ req_fifo_pass: true,
+ rsp_fifo_pass: false,
},
{ name: "flash_ctrl.mem",
type: "device",
clock: "clk_main_i",
reset: "rst_main_ni",
- pipeline_byp: "false"
+ req_fifo_pass: true,
+ rsp_fifo_pass: false,
},
{ name: "hmac",
type: "device",
clock: "clk_main_i",
reset: "rst_main_ni",
- pipeline_byp: "false"
+ req_fifo_pass: true,
+ rsp_fifo_pass: false,
},
{ name: "aes",
type: "device",
clock: "clk_main_i"
reset: "rst_main_ni"
- pipeline_byp: "false"
+ req_fifo_pass: true,
+ rsp_fifo_pass: false,
},
{ name: "rv_plic",
type: "device",
clock: "clk_main_i",
reset: "rst_main_ni",
inst_type: "rv_plic",
- pipeline_byp: "false"
+ req_fifo_pass: true,
+ rsp_fifo_pass: false,
},
{ name: "rv_core_ibex.cfg",
type: "device",
clock: "clk_main_i"
reset: "rst_main_ni"
- pipeline_byp: "false"
+ req_fifo_pass: true,
+ rsp_fifo_pass: false,
},
{ name: "sram_ctrl_main.regs",
type: "device",
clock: "clk_main_i",
reset: "rst_main_ni",
- pipeline: "false"
+ pipeline: false
},
{ name: "sram_ctrl_main.ram",
type: "device",
clock: "clk_main_i",
reset: "rst_main_ni",
- pipeline: "false"
+ pipeline: false
},
],
connections: {
diff --git a/hw/top_englishbreakfast/data/xbar_peri.hjson b/hw/top_englishbreakfast/data/xbar_peri.hjson
index de3fd29..bfe3ec1 100644
--- a/hw/top_englishbreakfast/data/xbar_peri.hjson
+++ b/hw/top_englishbreakfast/data/xbar_peri.hjson
@@ -14,86 +14,86 @@
clock: "clk_peri_i",
reset: "rst_peri_ni",
xbar: "true",
- pipeline: "false"
+ pipeline: false
},
{ name: "uart0",
type: "device",
clock: "clk_peri_i",
reset: "rst_peri_ni",
- pipeline: "false"
+ pipeline: false
},
{ name: "gpio",
type: "device",
clock: "clk_peri_i",
reset: "rst_peri_ni",
- pipeline: "false"
+ pipeline: false
},
{ name: "spi_device",
type: "device",
clock: "clk_peri_i",
reset: "rst_peri_ni",
- pipeline: "false"
+ pipeline: false
},
{ name: "spi_host0",
type: "device",
clock: "clk_spi_host0_i",
reset: "rst_spi_host0_ni",
- pipeline: "false"
+ pipeline: false
},
{ name: "rv_timer",
type: "device",
clock: "clk_peri_i",
reset: "rst_peri_ni",
- pipeline: "false"
+ pipeline: false
},
{ name: "usbdev",
type: "device",
clock: "clk_peri_i",
reset: "rst_peri_ni",
- pipeline: "false"
+ pipeline: false
},
{ name: "pwrmgr_aon",
type: "device",
clock: "clk_peri_i",
reset: "rst_peri_ni",
- pipeline: "false"
+ pipeline: false
},
{ name: "rstmgr_aon",
type: "device",
clock: "clk_peri_i",
reset: "rst_peri_ni",
- pipeline: "false"
+ pipeline: false
},
{ name: "clkmgr_aon",
type: "device",
clock: "clk_peri_i",
reset: "rst_peri_ni",
- pipeline: "false"
+ pipeline: false
},
{ name: "pinmux_aon",
type: "device",
clock: "clk_peri_i",
reset: "rst_peri_ni",
- pipeline: "false"
+ pipeline: false
},
{ name: "sram_ctrl_ret_aon.regs",
type: "device",
clock: "clk_peri_i",
reset: "rst_peri_ni",
- pipeline: "false"
+ pipeline: false
},
{ name: "sram_ctrl_ret_aon.ram",
type: "device",
clock: "clk_peri_i",
reset: "rst_peri_ni",
- pipeline: "false"
+ pipeline: false
},
{ name: "ast",
type: "device",
clock: "clk_peri_i",
reset: "rst_peri_ni",
- pipeline: "false",
+ pipeline: false,
},
],
connections: {
diff --git a/util/tlgen/elaborate.py b/util/tlgen/elaborate.py
index 6b2b935..4edae1b 100644
--- a/util/tlgen/elaborate.py
+++ b/util/tlgen/elaborate.py
@@ -87,9 +87,11 @@
# By default, assume connecting to SOCKET_1N upstream and bypass all FIFOs
# If upstream requires pipelining, it will be added through process pipeline
new_node.hdepth = 0
- new_node.hpass = 2**len(node.us) - 1
+ new_node.hreq_pass = 2**len(node.us) - 1
+ new_node.hrsp_pass = 2**len(node.us) - 1
new_node.ddepth = 0
- new_node.dpass = 1
+ new_node.dreq_pass = 1
+ new_node.drsp_pass = 1
xbar.insert_node(new_node, node)
process_node(new_node, xbar)
@@ -104,9 +106,11 @@
# By default, assume connecting to SOCKET_M1 downstream and bypass all FIFOs
# If upstream requires pipelining, it will be added through process pipeline
new_node.hdepth = 0
- new_node.hpass = 1
+ new_node.hreq_pass = 1
+ new_node.hrsp_pass = 1
new_node.ddepth = 0
- new_node.dpass = 2**len(node.ds) - 1
+ new_node.dreq_pass = 2**len(node.ds) - 1
+ new_node.drsp_pass = 2**len(node.ds) - 1
xbar.insert_node(new_node, node)
# (for loop) Repeat the algorithm with SOCKET_1N's other side node
@@ -130,16 +134,18 @@
log.info("Processing pipeline for host {}".format(host.name))
+ fifo_pass = host.req_fifo_pass or host.rsp_fifo_pass
+
# FIFO present with no passthrough option
# FIFO present with passthrough option
# FIFO not present and full passthrough
full_fifo = False
fifo_passthru = False
full_passthru = True
- if host.pipeline is True and host.pipeline_byp is False:
+ if host.pipeline is True and fifo_pass is False:
full_fifo = True
- elif host.pipeline is True and host.pipeline_byp is True:
+ elif host.pipeline is True and fifo_pass is True:
fifo_passthru = True
elif host.pipeline is False:
@@ -150,39 +156,49 @@
if dnode.node_type == NodeType.ASYNC_FIFO:
continue
+ req_pass = 1 if host.req_fifo_pass else 0
+ rsp_pass = 1 if host.rsp_fifo_pass else 0
if dnode.node_type == NodeType.SOCKET_1N:
if full_fifo:
- dnode.hpass = 0
+ dnode.hreq_pass = 0
+ dnode.hrsp_pass = 0
dnode.hdepth = 2
elif fifo_passthru:
- dnode.hpass = 0
+ dnode.hreq_pass = req_pass
+ dnode.hrsp_pass = rsp_pass
dnode.hdepth = 2
elif full_passthru:
- dnode.hpass = 1
+ dnode.hreq_pass = 1
+ dnode.hrsp_pass = 1
dnode.hdepth = 0
log.info(
- "Finished processing socket1n {}, pass={}, depth={}".format(
- dnode.name, dnode.hpass, dnode.hdepth))
+ "Finished processing socket1n {}, req pass={}, rsp pass={}, depth={}".format(
+ dnode.name, dnode.hreq_pass, dnode.hrsp_pass, dnode.hdepth))
elif dnode.node_type == NodeType.SOCKET_M1:
idx = dnode.us.index(host.ds[0])
+
+ # first clear out entry
+ dnode.hreq_pass = dnode.hreq_pass & ~(1 << idx)
+ dnode.hreq_pass = dnode.hreq_pass & ~(1 << idx)
if full_fifo:
log.info("fifo present no bypass")
- dnode.hpass = dnode.hpass & ~(1 << idx)
dnode.hdepth = dnode.hdepth | (2 << idx * 4)
elif fifo_passthru:
log.info("fifo present with bypass")
- dnode.hpass = dnode.hpass | (1 << idx)
+ dnode.hreq_pass = dnode.hreq_pass | (req_pass << idx)
+ dnode.hreq_pass = dnode.hrsp_pass | (rsp_pass << idx)
dnode.hdepth = dnode.hdepth | (2 << idx * 4)
elif full_passthru:
log.info("fifo not present")
- dnode.hpass = dnode.hpass | (1 << idx)
+ dnode.hreq_pass = dnode.hreq_pass | (1 << idx)
+ dnode.hreq_pass = dnode.hrsp_pass | (1 << idx)
dnode.hdepth = dnode.hdepth & ~(0xF << idx * 4)
log.info(
- "Finished processing socketm1 {}, pass={}, depth={}".format(
- dnode.name, dnode.hpass, dnode.hdepth))
+ "Finished processing socketm1 {}, req pass={}, rsp pass={}, depth={}".format(
+ dnode.name, dnode.hreq_pass, dnode.hrsp_pass, dnode.hdepth))
for device in xbar.devices:
# go upstream and set DReq/RspPass at the first instance.
@@ -198,14 +214,14 @@
# FIFO present with no passthrough option
# FIFO present with passthrough option
# FIFO not present and full passthrough
-
+ fifo_pass = device.req_fifo_pass or device.rsp_fifo_pass
full_fifo = False
fifo_passthru = False
full_passthru = True
- if device.pipeline is True and device.pipeline_byp is False:
+ if device.pipeline is True and fifo_pass is False:
full_fifo = True
- elif device.pipeline is True and device.pipeline_byp is True:
+ elif device.pipeline is True and fifo_pass is True:
fifo_passthru = True
elif device.pipeline is False:
@@ -216,37 +232,46 @@
if unode.node_type == NodeType.ASYNC_FIFO:
continue
+ req_pass = 1 if device.req_fifo_pass else 0
+ rsp_pass = 1 if device.rsp_fifo_pass else 0
if unode.node_type == NodeType.SOCKET_1N:
idx = unode.ds.index(device.us[0])
+ # first clear out entry
+ unode.dreq_pass = unode.dreq_pass & ~(1 << idx)
+ unode.drsp_pass = unode.drsp_pass & ~(1 << idx)
if full_fifo:
- unode.dpass = unode.dpass & ~(1 << idx)
unode.ddepth = unode.ddepth | (2 << idx * 4)
elif fifo_passthru:
- unode.dpass = unode.dpass | (1 << idx)
+ unode.dreq_pass = unode.dreq_pass | (req_pass << idx)
+ unode.drsp_pass = unode.drsp_pass | (rsp_pass << idx)
unode.ddepth = unode.ddepth | (2 << idx * 4)
elif full_passthru:
- unode.dpass = unode.dpass | (1 << idx)
+ unode.dreq_pass = unode.dreq_pass | (1 << idx)
+ unode.drsp_pass = unode.drsp_pass | (1 << idx)
unode.ddepth = unode.ddepth & ~(0xF << idx * 4)
- log.info("Finished processing socket1n {}, pass={:x}, depth={:x}".
- format(unode.name, unode.dpass, unode.ddepth))
+ log.info("Finished processing socket1n {}, req pass={:x}, req pass={:x} depth={:x}".
+ format(unode.name, unode.dreq_pass, unode.drsp_pass, unode.ddepth))
elif unode.node_type == NodeType.SOCKET_M1:
if full_fifo:
log.info("Fifo present with no passthrough")
- unode.dpass = 0
+ unode.dreq_pass = 0
+ unode.drsp_pass = 0
unode.ddepth = 2
elif fifo_passthru:
log.info("Fifo present with passthrough")
- unode.dpass = 0
+ unode.dreq_pass = req_pass
+ unode.drsp_pass = rsp_pass
unode.ddepth = 2
elif full_passthru:
log.info("No Fifo")
- unode.dpass = 1
+ unode.dreq_pass = 1
+ unode.drsp_pass = 1
unode.ddepth = 0
- log.info("Finished processing socketm1 {}, pass={:x}, depth={:x}".
- format(unode.name, unode.dpass, unode.ddepth))
+ log.info("Finished processing socketm1 {}, req pass={:x}, rsp pass={:x}, depth={:x}".
+ format(unode.name, unode.dreq_pass, unode.drsp_pass, unode.ddepth))
return xbar
diff --git a/util/tlgen/item.py b/util/tlgen/item.py
index d1796a4..5947ee9 100644
--- a/util/tlgen/item.py
+++ b/util/tlgen/item.py
@@ -56,13 +56,18 @@
ds = [] # Edges
# Req/Rsp FIFO. default False
- # when False, FIFO fully passthrough, no storage element
- # when True, FIFO present with default depth, "pipeline_byp"
- # controls passthrough option
- pipeline = False
+ # when False, no storage element
+ # when True, FIFO present with default depth, the "fifo_pass"
+ # variables control whether a particular direction in the fifo
+ # has the passthrough behvaior
+ pipeline = True
# FIFO passtru option. default True
- pipeline_byp = True
+ # If pipeline is false, these fields have no meaning
+ # passthrough behavior refers to a FIFO passing the trasnaction
+ # through if the FIFO is currently empty
+ req_fifo_pass = True
+ rsp_fifo_pass = True
def __init__(self, name, node_type, clock, reset):
self.name = name
diff --git a/util/tlgen/validate.py b/util/tlgen/validate.py
index ebccbef..992b9d1 100644
--- a/util/tlgen/validate.py
+++ b/util/tlgen/validate.py
@@ -68,10 +68,10 @@
'clock': ['s', 'main clock of the port'],
'reset': ['s', 'main reset of the port'],
'pipeline': ['pb', 'If true, pipeline is added in front of the port'],
- 'pipeline_byp': [
- 'pb', 'Pipeline bypass. If true, '
- 'request/response are not latched'
- ],
+ 'req_fifo_pass': ['pb',
+ 'If true, pipeline fifo has passthrough behavior on req'],
+ 'rsp_fifo_pass': ['pb',
+ 'If true, pipeline fifo has passthrough behavior on rsp'],
'inst_type': ['s', 'Instance type'],
'xbar': ['pb', 'If true, the node is connected to another Xbar'],
'addr_range': ['lg', addr]
@@ -305,18 +305,19 @@
if node.node_type in [NodeType.DEVICE, NodeType.HOST
] and "pipeline" in nodeobj:
- node.pipeline = True if nodeobj["pipeline"].lower() in [
- "true", "1"
- ] else False
+ node.pipeline = True if nodeobj["pipeline"] else False
else:
node.pipeline = False
- if node.node_type in [NodeType.DEVICE, NodeType.HOST
- ] and "pipeline_byp" in nodeobj:
- node.pipeline_byp = True if nodeobj["pipeline_byp"].lower() in [
- "true", "1"
- ] else False
+ if node.node_type in [NodeType.DEVICE, NodeType.HOST]:
+ node.req_fifo_pass = nodeobj["req_fifo_pass"] \
+ if "req_fifo_pass" in nodeobj else False
+
+ node.rsp_fifo_pass = nodeobj["rsp_fifo_pass"] \
+ if "rsp_fifo_pass" in nodeobj else False
+
else:
- node.pipeline_byp = True
+ node.req_fifo_pass = False
+ node.rsp_fifo_pass = False
xbar.nodes.append(node)
# Edge
diff --git a/util/tlgen/xbar.rtl.sv.tpl b/util/tlgen/xbar.rtl.sv.tpl
index c5bd9d5..fc78418 100644
--- a/util/tlgen/xbar.rtl.sv.tpl
+++ b/util/tlgen/xbar.rtl.sv.tpl
@@ -221,17 +221,21 @@
);
% elif block.node_type.name == "SOCKET_1N":
tlul_socket_1n #(
- % if block.hpass != 1:
- .HReqPass (1'b${block.hpass}),
- .HRspPass (1'b${block.hpass}),
+ % if block.hreq_pass != 1:
+ .HReqPass (1'b${block.hreq_pass}),
+ % endif
+ % if block.hrsp_pass != 1:
+ .HRspPass (1'b${block.hrsp_pass}),
% endif
% if block.hdepth != 2:
.HReqDepth (4'h${block.hdepth}),
.HRspDepth (4'h${block.hdepth}),
% endif
- % if block.dpass != 2**(len(block.ds)) -1:
- .DReqPass (${len(block.ds)}'h${"%x" % block.dpass}),
- .DRspPass (${len(block.ds)}'h${"%x" % block.dpass}),
+ % if block.dreq_pass != 2**(len(block.ds)) -1:
+ .DReqPass (${len(block.ds)}'h${"%x" % block.dreq_pass}),
+ % endif
+ % if block.drsp_pass != 2**(len(block.ds)) -1:
+ .DRspPass (${len(block.ds)}'h${"%x" % block.drsp_pass}),
% endif
% if block.ddepth != 2:
.DReqDepth (${len(block.ds)*4}'h${"%x" % block.ddepth}),
@@ -249,17 +253,21 @@
);
% elif block.node_type.name == "SOCKET_M1":
tlul_socket_m1 #(
- % if block.hpass != 2**(len(block.us)) - 1:
- .HReqPass (${len(block.us)}'h${"%x" % block.hpass}),
- .HRspPass (${len(block.us)}'h${"%x" % block.hpass}),
+ % if block.hreq_pass != 2**(len(block.us)) - 1:
+ .HReqPass (${len(block.us)}'h${"%x" % block.hreq_pass}),
+ % endif
+ % if block.hrsp_pass != 2**(len(block.us)) - 1:
+ .HRspPass (${len(block.us)}'h${"%x" % block.hrsp_pass}),
% endif
% if block.hdepth != 2:
.HReqDepth (${len(block.us)*4}'h${"%x" % block.hdepth}),
.HRspDepth (${len(block.us)*4}'h${"%x" % block.hdepth}),
% endif
- % if block.dpass != 1:
- .DReqPass (1'b${block.dpass}),
- .DRspPass (1'b${block.dpass}),
+ % if block.dreq_pass != 1:
+ .DReqPass (1'b${block.dreq_pass}),
+ % endif
+ % if block.drsp_pass != 1:
+ .DRspPass (1'b${block.drsp_pass}),
% endif
% if block.ddepth != 2:
.DReqDepth (4'h${block.ddepth}),
diff --git a/util/topgen/merge.py b/util/topgen/merge.py
index 3838c38..828f1e6 100644
--- a/util/topgen/merge.py
+++ b/util/topgen/merge.py
@@ -260,8 +260,9 @@
("stub", False),
# The default matches RTL default
# pipeline_byp is don't care if pipeline is false
- ("pipeline", "true"),
- ("pipeline_byp", "true")
+ ("pipeline", True),
+ ("req_fifo_pass", True),
+ ("rsp_fifo_pass", True)
])
xbar["nodes"].append(obj)
return
@@ -281,9 +282,11 @@
obj[0]["stub"] = False
obj[0]["inst_type"] = predefined_modules[
host] if host in predefined_modules else ""
- obj[0]["pipeline"] = obj[0]["pipeline"] if "pipeline" in obj[0] else "true"
- obj[0]["pipeline_byp"] = obj[0]["pipeline_byp"] if obj[0][
- "pipeline"] == "true" and "pipeline_byp" in obj[0] else "true"
+ obj[0]["pipeline"] = obj[0]["pipeline"] if "pipeline" in obj[0] else True
+ obj[0]["req_fifo_pass"] = obj[0]["req_fifo_pass"] if obj[0][
+ "pipeline"] and "req_fifo_pass" in obj[0] else True
+ obj[0]["rsp_fifo_pass"] = obj[0]["rsp_fifo_pass"] if obj[0][
+ "pipeline"] and "rsp_fifo_pass" in obj[0] else True
def process_pipeline_var(node):
@@ -291,9 +294,11 @@
- Supply a default of true / true if not defined by xbar
"""
- node["pipeline"] = node["pipeline"] if "pipeline" in node else "true"
- node["pipeline_byp"] = node[
- "pipeline_byp"] if "pipeline_byp" in node else "true"
+ node["pipeline"] = node["pipeline"] if "pipeline" in node else True
+ node["req_fifo_pass"] = node[
+ "req_fifo_pass"] if "req_fifo_pass" in node else True
+ node["req_fifo_pass"] = node[
+ "req_fifo_pass"] if "req_fifo_pass" in node else True
def xbar_adddevice(top: Dict[str, object],
