[verilator] Minor verilator updates to reflect clock division
- this change is temporary, need to split into different clocks
Signed-off-by: Timothy Chen <timothytim@google.com>
[sw] Minor updates to software to pass tests
- Increase dif_rv_timer_sanity_test deadline since each tick now counts 4x.
Without increasing the deadline, the interrupt fires in the middle of a uart print and the test never completes.
Signed-off-by: Timothy Chen <timothytim@google.com>
[verilator, sw] update for verilator frequency change
Signed-off-by: Timothy Chen <timothytim@google.com>
diff --git a/sw/device/lib/arch/device_sim_verilator.c b/sw/device/lib/arch/device_sim_verilator.c
index c98f462..859d048 100644
--- a/sw/device/lib/arch/device_sim_verilator.c
+++ b/sw/device/lib/arch/device_sim_verilator.c
@@ -13,11 +13,11 @@
const uint64_t kClockFreqCpuHz = 500 * 1000; // 500kHz
-const uint64_t kClockFreqPeripheralHz = 500 * 1000; // 500kHz
+const uint64_t kClockFreqPeripheralHz = 125 * 1000; // 125kHz
const uint64_t kClockFreqUsbHz = 500 * 1000; // 500kHz
-const uint64_t kUartBaudrate = 9600;
+const uint64_t kUartBaudrate = 7200;
// Defined in `hw/top_earlgrey/top_earlgrey_verilator.core`
const uintptr_t kDeviceStopAddress = 0x10008000;
