| commit | 121847e2ad89d2866ea7864898a9783101c612cd | [log] [tgz] |
|---|---|---|
| author | Greg Chadwick <gac@lowrisc.org> | Wed Sep 02 15:31:28 2020 +0100 |
| committer | Greg Chadwick <gac@lowrisc.org> | Mon Sep 07 13:01:41 2020 +0100 |
| tree | aab78b8a89381e5c6ee77edadb61a37ae795690c | |
| parent | 9e9111573e722ec25839d7ebe25c5abeadfa7b24 [diff] |
[otbn] Tweaks to ld/st control signals * Register write was entirely controlled by controller for loads, this alters it so decoder signals rf_we for loads and the write is supressed by the controller until the load data is available. * Rearranges ordering of lines for assigning load_insn/store_insn. Now straight after insn_subset. Signed-off-by: Greg Chadwick <gac@lowrisc.org>
OpenTitan is an open source silicon Root of Trust (RoT) project. OpenTitan will make the silicon RoT design and implementation more transparent, trustworthy, and secure for enterprises, platform providers, and chip manufacturers. OpenTitan is administered by lowRISC CIC as a collaborative project to produce high quality, open IP for instantiation as a full-featured product. See the OpenTitan site and OpenTitan docs for more information about the project.
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