commit 11ea58d7f61072a6db7b85d700ac227ffe397fd0
author Michael Munday <mike.munday@lowrisc.org> Tue Dec 07 10:40:38 2021 +0000
committer Alphan Ulusoy <alphan@google.com> Tue Dec 14 15:54:36 2021 -0500
tree 7ac16425862065c6af46b2ca638bf8d610d62599
parent 269a0d1b3a6895a97d5b7229f07b64463b8474e0

[mask_rom] Perform basic AST initialization

Copy the configuration from OTP unconditionally and then poll the
ast_init_done flag until it is set.

Future commits will make this initialization more flexible. In
particular we need to skip AST configuration if OTP is not yet
programmed and also we need to add a timeout to the polling.

Note that the open source AST model does not validate the
configuration and ast_init_done is hardcoded in the RTL to 1.

Signed-off-by: Michael Munday <mike.munday@lowrisc.org>

sw/device/silicon_creator/mask_rom/mask_rom_start.S

diff --git a/sw/device/silicon_creator/mask_rom/mask_rom_start.S b/sw/device/silicon_creator/mask_rom/mask_rom_start.S
index ea84020..7093d25 100644
--- a/sw/device/silicon_creator/mask_rom/mask_rom_start.S
+++ b/sw/device/silicon_creator/mask_rom/mask_rom_start.S
@@ -3,9 +3,12 @@
 // SPDX-License-Identifier: Apache-2.0
 
 #include "hw/top_earlgrey/sw/autogen/top_earlgrey_memory.h"
-#include "entropy_src_regs.h"
+#include "ast_regs.h"
 #include "csrng_regs.h"
 #include "edn_regs.h"
+#include "entropy_src_regs.h"
+#include "otp_ctrl_regs.h"
+#include "sensor_ctrl_regs.h"
 #include "sram_ctrl_regs.h"
 
 /**
@@ -131,6 +134,22 @@
   li   t0, 0xFFFF0888
   csrc mie, t0
 
+  // Copy the AST configuration from OTP.
+  li   a0, (TOP_EARLGREY_AST_BASE_ADDR + AST_REGA_0_REG_OFFSET)
+  li   a1, (TOP_EARLGREY_AST_BASE_ADDR + AST_REGAL_REG_OFFSET + 4)
+  li   a2, (TOP_EARLGREY_OTP_CTRL_CORE_BASE_ADDR + \
+            OTP_CTRL_SW_CFG_WINDOW_REG_OFFSET + \
+            OTP_CTRL_PARAM_CREATOR_SW_CFG_AST_CFG_OFFSET)
+  call crt_section_copy
+
+  // Wait for AST initialization to complete.
+  li   a0, TOP_EARLGREY_SENSOR_CTRL_BASE_ADDR
+.L_ast_done_loop:
+  lw   t0, SENSOR_CTRL_STATUS_REG_OFFSET(a0)
+  srli t0, t0, SENSOR_CTRL_STATUS_AST_INIT_DONE_BIT // no-op as bit index is currently 0
+  andi t0, t0, 0x1
+  beqz t0, .L_ast_done_loop
+
   // The following sequence enables the minimum level of entropy required to
   // initialize memory scrambling, as well as the entropy distribution network.
   li a0, TOP_EARLGREY_ENTROPY_SRC_BASE_ADDR

sw/device/silicon_creator/mask_rom/meson.build

diff --git a/sw/device/silicon_creator/mask_rom/meson.build b/sw/device/silicon_creator/mask_rom/meson.build
index ffdcb4b..fa36a7d 100644
--- a/sw/device/silicon_creator/mask_rom/meson.build
+++ b/sw/device/silicon_creator/mask_rom/meson.build
@@ -62,11 +62,13 @@
 mask_rom_epmp_test_lib = declare_dependency(
   sources: [
     hw_ip_aon_timer_reg_h,
-    hw_ip_entropy_src_reg_h,
+    hw_ip_ast_reg_h,
     hw_ip_csrng_reg_h,
     hw_ip_edn_reg_h,
+    hw_ip_entropy_src_reg_h,
+    hw_ip_otp_ctrl_reg_h,
+    hw_ip_sensor_ctrl_reg_h,
     hw_ip_sram_ctrl_reg_h,
-    hw_ip_pwrmgr_reg_h,
     'mask_rom_start.S',
   ],
   link_args: rom_link_args,
@@ -183,9 +185,12 @@
 mask_rom_lib = declare_dependency(
   sources: [
     hw_ip_aon_timer_reg_h,
-    hw_ip_entropy_src_reg_h,
+    hw_ip_ast_reg_h,
     hw_ip_csrng_reg_h,
     hw_ip_edn_reg_h,
+    hw_ip_entropy_src_reg_h,
+    hw_ip_otp_ctrl_reg_h,
+    hw_ip_sensor_ctrl_reg_h,
     hw_ip_sram_ctrl_reg_h,
     'mask_rom_start.S',
   ],