[doc/otbn] Clear external CSRs
Specification for clearing INSN_CNT and ERR_BITS registers.
Signed-off-by: Vladimir Rozic <vrozic@lowrisc.org>
diff --git a/hw/ip/otbn/doc/_index.md b/hw/ip/otbn/doc/_index.md
index 19735a5..ab5c626 100644
--- a/hw/ip/otbn/doc/_index.md
+++ b/hw/ip/otbn/doc/_index.md
@@ -490,6 +490,9 @@
## Instruction Counter
In order to detect and mitigate fault injection attacks on the OTBN, the host CPU can read the number of executed instructions from {{< regref "INSN_CNT">}} and verify whether it matches the expectation.
+The host CPU can clear the instruction counter when OTBN is not running.
+Writing any value to {{< regref "INSN_CNT">}} clears this register to zero.
+Write attempts while OTBN is running are ignored.
## Key Sideloading
@@ -797,6 +800,10 @@
If OTBN was running, this value will also be reflected in the {{< regref "ERR_BITS" >}} register.
A fatal alert can only be cleared by resetting OTBN through the `rst_ni` line.
+The host CPU can clear the {{< regref "ERR_BITS" >}} when OTBN is not running.
+Writing any value to {{< regref "ERR_BITS" >}} clears this register to zero.
+Write attempts while OTBN is running are ignored.
+
### Reaction to Life Cycle Escalation Requests {#design-details-lifecycle-escalation}
OTBN receives and reacts to escalation signals from the [life cycle controller]({{< relref "/hw/ip/lc_ctrl/doc#security-escalation" >}}).
