commit | 110bf9869abd71c82a894790a62ec8956dda7b14 | [log] [tgz] |
---|---|---|
author | Nigel Scales <nigel.scales@gmail.com> | Tue Mar 22 18:11:17 2022 +0000 |
committer | cindychip <cindy.chen0316@gmail.com> | Tue Mar 22 14:24:55 2022 -0700 |
tree | dd31b160a3a14161c89c477fe3e2e6502bc94f2b | |
parent | f95a6861273d99c46663532772a8a3b081e6efaf [diff] |
[adc_ctrl/dv] Added adc_ctrl_stress_all test - Added tests - adc_ctrl_stress_all - Added test sequences - adc_ctrl_stress_all_vseq - runs a random choice of the others test sequences - Fixed adc_ctrl_intr - Disabled scoreboard and enabled autopredict - Fixed adc_ctrl_bit_bash - Added assertion control ADC_CTRL_FSM_A_CTRL - Fixed adc_ctrl_clock_gating - Disabled interrupts for this test - Corrected filter parameter coverage - Enhanced variable filter config constraints to generate maximum and minimum values for min_v and max_v - Added reads of channel value registers to interrupt/both tests - Aligned capture of interrupt channel values in model with RTL - Modelling intr_test in scoreboard - Added interrupt cover groups sampling to scoreboard Signed-off-by: Nigel Scales <nigel.scales@gmail.com>
OpenTitan is an open source silicon Root of Trust (RoT) project. OpenTitan will make the silicon RoT design and implementation more transparent, trustworthy, and secure for enterprises, platform providers, and chip manufacturers. OpenTitan is administered by lowRISC CIC as a collaborative project to produce high quality, open IP for instantiation as a full-featured product. See the OpenTitan site and OpenTitan docs for more information about the project.
This repository contains hardware, software and utilities written as part of the OpenTitan project. It is structured as monolithic repository, or “monorepo”, where all components live in one repository. It exists to enable collaboration across partners participating in the OpenTitan project.
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Unless otherwise noted, everything in this repository is covered by the Apache License, Version 2.0 (see LICENSE for full text).