[dcd] add auto generated tb
Signed-off-by: Timothy Chen <timothytim@google.com>
[dcd] update fifo depth
pending #5028
Signed-off-by: Timothy Chen <timothytim@google.com>
[dv] add dcd csr tests to smoke regression
Signed-off-by: Timothy Chen <timothytim@google.com>
[dcd] updates to address comments
Signed-off-by: Timothy Chen <timothytim@google.com>
[dcd] Add doc placeholder
Signed-off-by: Timothy Chen <timothytim@google.com>
diff --git a/hw/ip/dcd/data/dcd_testplan.hjson b/hw/ip/dcd/data/dcd_testplan.hjson
new file mode 100644
index 0000000..01d8824
--- /dev/null
+++ b/hw/ip/dcd/data/dcd_testplan.hjson
@@ -0,0 +1,33 @@
+// Copyright lowRISC contributors.
+// Licensed under the Apache License, Version 2.0, see LICENSE for details.
+// SPDX-License-Identifier: Apache-2.0
+{
+ name: "dcd"
+ // TODO: remove the common testplans if not applicable
+ import_testplans: ["hw/dv/tools/dvsim/testplans/csr_testplan.hjson",
+ "hw/dv/tools/dvsim/testplans/mem_testplan.hjson",
+ "hw/dv/tools/dvsim/testplans/intr_test_testplan.hjson",
+ "hw/dv/tools/dvsim/testplans/tl_device_access_types_testplan.hjson"]
+ entries: [
+ {
+ name: smoke
+ desc: '''
+ Smoke test accessing a major datapath within the dcd.
+
+ **Stimulus**:
+ - TBD
+
+ **Checks**:
+ - TBD
+ '''
+ milestone: V1
+ tests: ["dcd_smoke"]
+ }
+ {
+ name: feature1
+ desc: '''Add more test entries here like above.'''
+ milestone: V1
+ tests: []
+ }
+ ]
+}
diff --git a/hw/ip/dcd/doc/_index.md b/hw/ip/dcd/doc/_index.md
new file mode 100644
index 0000000..d468126
--- /dev/null
+++ b/hw/ip/dcd/doc/_index.md
@@ -0,0 +1,35 @@
+---
+title: "ADC_CTRL HWIP Technical Specification"
+---
+
+# Overview
+
+
+
+## Features
+
+
+
+## Description
+
+
+
+# Theory of Operation
+
+## Block Diagram
+
+
+## Hardware Interface
+
+{{< hwcfg "hw/ip/dcd/data/dcd.hjson" >}}
+
+## Design Details
+
+
+# Programmers Guide
+
+
+
+## Registers
+
+{{< registers "hw/ip/dcd/data/dcd.hjson" >}}
diff --git a/hw/ip/dcd/doc/checklist.md b/hw/ip/dcd/doc/checklist.md
new file mode 100644
index 0000000..c6c62bc
--- /dev/null
+++ b/hw/ip/dcd/doc/checklist.md
@@ -0,0 +1,240 @@
+---
+title: "DCD Checklist"
+---
+
+<!--
+NOTE: This is a template checklist document that is required to be copied over to the 'doc'
+directory for a new design that transitions from L0 (Specification) to L1 (Development)
+stage, and updated as needed. Once done, please remove this comment before checking it in.
+-->
+This checklist is for [Hardware Stage]({{< relref "/doc/project/development_stages.md" >}}) transitions for the [DCD peripheral.]()
+All checklist items refer to the content in the [Checklist.]({{< relref "/doc/project/checklist.md" >}})
+
+## Design Checklist
+
+### D1
+
+Type | Item | Resolution | Note/Collaterals
+--------------|--------------------------------|-------------|------------------
+Documentation | [SPEC_COMPLETE][] | Not Started | [DCD Design Spec]({{<relref "hw/ip/dcd/doc" >}})
+Documentation | [CSR_DEFINED][] | Not Started |
+RTL | [CLKRST_CONNECTED][] | Not Started |
+RTL | [IP_TOP][] | Not Started |
+RTL | [IP_INSTANTIABLE][] | Not Started |
+RTL | [PHYSICAL_MACROS_DEFINED_80][] | Not Started |
+RTL | [FUNC_IMPLEMENTED][] | Not Started |
+RTL | [ASSERT_KNOWN_ADDED][] | Not Started |
+Code Quality | [LINT_SETUP][] | Not Started |
+
+[SPEC_COMPLETE]: {{<relref "/doc/project/checklist.md#spec_complete" >}}
+[CSR_DEFINED]: {{<relref "/doc/project/checklist.md#csr_defined" >}}
+[CLKRST_CONNECTED]: {{<relref "/doc/project/checklist.md#clkrst_connected" >}}
+[IP_TOP]: {{<relref "/doc/project/checklist.md#ip_top" >}}
+[IP_INSTANTIABLE]: {{<relref "/doc/project/checklist.md#ip_instantiable" >}}
+[PHYSICAL_MACROS_DEFINED_80]: {{<relref "/doc/project/checklist.md#physical_macros_defined_80" >}}
+[FUNC_IMPLEMENTED]: {{<relref "/doc/project/checklist.md#func_implemented" >}}
+[ASSERT_KNOWN_ADDED]: {{<relref "/doc/project/checklist.md#assert_known_added" >}}
+[LINT_SETUP]: {{<relref "/doc/project/checklist.md#lint_setup" >}}
+
+### D2
+
+Type | Item | Resolution | Note/Collaterals
+--------------|-------------------------|-------------|------------------
+Documentation | [NEW_FEATURES][] | Not Started |
+Documentation | [BLOCK_DIAGRAM][] | Not Started |
+Documentation | [DOC_INTERFACE][] | Not Started |
+Documentation | [MISSING_FUNC][] | Not Started |
+Documentation | [FEATURE_FROZEN][] | Not Started |
+RTL | [FEATURE_COMPLETE][] | Not Started |
+RTL | [AREA_CHECK][] | Not Started |
+RTL | [PORT_FROZEN][] | Not Started |
+RTL | [ARCHITECTURE_FROZEN][] | Not Started |
+RTL | [REVIEW_TODO][] | Not Started |
+RTL | [STYLE_X][] | Not Started |
+Code Quality | [LINT_PASS][] | Not Started |
+Code Quality | [CDC_SETUP][] | Not Started |
+Code Quality | [FPGA_TIMING][] | Not Started |
+Code Quality | [CDC_SYNCMACRO][] | Not Started |
+Security | [SEC_CM_IMPLEMENTED][] | Not Started |
+Security | [SEC_NON_RESET_FLOPS][] | Not Started |
+Security | [SEC_SHADOW_REGS][] | Not Started |
+Security | [SEC_RND_CNST][] | Not Started |
+
+[NEW_FEATURES]: {{<relref "/doc/project/checklist.md#new_features" >}}
+[BLOCK_DIAGRAM]: {{<relref "/doc/project/checklist.md#block_diagram" >}}
+[DOC_INTERFACE]: {{<relref "/doc/project/checklist.md#doc_interface" >}}
+[MISSING_FUNC]: {{<relref "/doc/project/checklist.md#missing_func" >}}
+[FEATURE_FROZEN]: {{<relref "/doc/project/checklist.md#feature_frozen" >}}
+[FEATURE_COMPLETE]: {{<relref "/doc/project/checklist.md#feature_complete" >}}
+[AREA_CHECK]: {{<relref "/doc/project/checklist.md#area_check" >}}
+[PORT_FROZEN]: {{<relref "/doc/project/checklist.md#port_frozen" >}}
+[ARCHITECTURE_FROZEN]: {{<relref "/doc/project/checklist.md#architecture_frozen" >}}
+[REVIEW_TODO]: {{<relref "/doc/project/checklist.md#review_todo" >}}
+[STYLE_X]: {{<relref "/doc/project/checklist.md#style_x" >}}
+[LINT_PASS]: {{<relref "/doc/project/checklist.md#lint_pass" >}}
+[CDC_SETUP]: {{<relref "/doc/project/checklist.md#cdc_setup" >}}
+[FPGA_TIMING]: {{<relref "/doc/project/checklist.md#fpga_timing" >}}
+[CDC_SYNCMACRO]: {{<relref "/doc/project/checklist.md#cdc_syncmacro" >}}
+[SEC_CM_IMPLEMENTED]: {{<relref "/doc/project/checklist.md#sec_cm_implemented" >}}
+[SEC_NON_RESET_FLOPS]: {{<relref "/doc/project/checklist.md#sec_non_reset_flops" >}}
+[SEC_SHADOW_REGS]: {{<relref "/doc/project/checklist.md#sec_shadow_regs" >}}
+[SEC_RND_CNST]: {{<relref "/doc/project/checklist.md#sec_rnd_cnst" >}}
+
+### D3
+
+ Type | Item | Resolution | Note/Collaterals
+--------------|-------------------------|-------------|------------------
+Documentation | [NEW_FEATURES_D3][] | Not Started |
+RTL | [TODO_COMPLETE][] | Not Started |
+Code Quality | [LINT_COMPLETE][] | Not Started |
+Code Quality | [CDC_COMPLETE][] | Not Started |
+Review | [REVIEW_RTL][] | Not Started |
+Review | [REVIEW_DELETED_FF][] | Not Started |
+Review | [REVIEW_SW_CSR][] | Not Started |
+Review | [REVIEW_SW_FATAL_ERR][] | Not Started |
+Review | [REVIEW_SW_CHANGE][] | Not Started |
+Review | [REVIEW_SW_ERRATA][] | Not Started |
+Review | Reviewer(s) | Not Started |
+Review | Signoff date | Not Started |
+
+[NEW_FEATURES_D3]: {{<relref "/doc/project/checklist.md#new_features_d3" >}}
+[TODO_COMPLETE]: {{<relref "/doc/project/checklist.md#todo_complete" >}}
+[LINT_COMPLETE]: {{<relref "/doc/project/checklist.md#lint_complete" >}}
+[CDC_COMPLETE]: {{<relref "/doc/project/checklist.md#cdc_complete" >}}
+[REVIEW_RTL]: {{<relref "/doc/project/checklist.md#review_rtl" >}}
+[REVIEW_DBG]: {{<relref "/doc/project/checklist.md#review_dbg" >}}
+[REVIEW_DELETED_FF]: {{<relref "/doc/project/checklist.md#review_deleted_ff" >}}
+[REVIEW_SW_CSR]: {{<relref "/doc/project/checklist.md#review_sw_csr" >}}
+[REVIEW_SW_FATAL_ERR]: {{<relref "/doc/project/checklist.md#review_sw_fatal_err" >}}
+[REVIEW_SW_CHANGE]: {{<relref "/doc/project/checklist.md#review_sw_change" >}}
+[REVIEW_SW_ERRATA]: {{<relref "/doc/project/checklist.md#review_sw_errata" >}}
+
+## Verification Checklist
+
+### V1
+
+ Type | Item | Resolution | Note/Collaterals
+--------------|---------------------------------------|-------------|------------------
+Documentation | [DV_DOC_DRAFT_COMPLETED][] | Not Started | [DCD DV document]({{<relref "hw/ip/dcd/doc/dv/index.md" >}})
+Documentation | [DV_PLAN_COMPLETED][] | Not Started | [DCD DV Plan]({{<relref "hw/ip/dcd/doc/dv/index.md#dv_plan" >}})
+Testbench | [TB_TOP_CREATED][] | Not Started |
+Testbench | [PRELIMINARY_ASSERTION_CHECKS_ADDED][]| Not Started |
+Testbench | [SIM_TB_ENV_CREATED][] | Not Started |
+Testbench | [SIM_RAL_MODEL_GEN_AUTOMATED][] | Not Started |
+Testbench | [CSR_CHECK_GEN_AUTOMATED][] | Not Started |
+Testbench | [TB_GEN_AUTOMATED][] | Not Started |
+Tests | [SIM_SMOKE_TEST_PASSING][] | Not Started |
+Tests | [SIM_CSR_MEM_TEST_SUITE_PASSING][] | Not Started |
+Tests | [FPV_MAIN_ASSERTIONS_PROVEN][] | Not Started |
+Tool Setup | [SIM_ALT_TOOL_SETUP][] | Not Started |
+Regression | [SIM_SMOKE_REGRESSION_SETUP][] | Not Started |
+Regression | [SIM_NIGHTLY_REGRESSION_SETUP][] | Not Started |
+Regression | [FPV_REGRESSION_SETUP][] | Not Started |
+Coverage | [SIM_COVERAGE_MODEL_ADDED][] | Not Started |
+Code Quality | [TB_LINT_SETUP][] | Not Started |
+Integration | [PRE_VERIFIED_SUB_MODULES_V1][] | Not Started |
+Review | [DESIGN_SPEC_REVIEWED][] | Not Started |
+Review | [DV_PLAN_TESTPLAN_REVIEWED][] | Not Started |
+Review | [STD_TEST_CATEGORIES_PLANNED][] | Not Started | Exception (?)
+Review | [V2_CHECKLIST_SCOPED][] | Not Started |
+
+[DV_DOC_DRAFT_COMPLETED]: {{<relref "/doc/project/checklist.md#dv_doc_draft_completed" >}}
+[DV_PLAN_COMPLETED]: {{<relref "/doc/project/checklist.md#dv_plan_completed" >}}
+[TB_TOP_CREATED]: {{<relref "/doc/project/checklist.md#tb_top_created" >}}
+[PRELIMINARY_ASSERTION_CHECKS_ADDED]: {{<relref "/doc/project/checklist.md#preliminary_assertion_checks_added" >}}
+[SIM_TB_ENV_CREATED]: {{<relref "/doc/project/checklist.md#sim_tb_env_created" >}}
+[SIM_RAL_MODEL_GEN_AUTOMATED]: {{<relref "/doc/project/checklist.md#sim_ral_model_gen_automated" >}}
+[CSR_CHECK_GEN_AUTOMATED]: {{<relref "/doc/project/checklist.md#csr_check_gen_automated" >}}
+[TB_GEN_AUTOMATED]: {{<relref "/doc/project/checklist.md#tb_gen_automated" >}}
+[SIM_SMOKE_TEST_PASSING]: {{<relref "/doc/project/checklist.md#sim_smoke_test_passing" >}}
+[SIM_CSR_MEM_TEST_SUITE_PASSING]: {{<relref "/doc/project/checklist.md#sim_csr_mem_test_suite_passing" >}}
+[FPV_MAIN_ASSERTIONS_PROVEN]: {{<relref "/doc/project/checklist.md#fpv_main_assertions_proven" >}}
+[SIM_ALT_TOOL_SETUP]: {{<relref "/doc/project/checklist.md#sim_alt_tool_setup" >}}
+[SIM_SMOKE_REGRESSION_SETUP]: {{<relref "/doc/project/checklist.md#sim_smoke_regression_setup" >}}
+[SIM_NIGHTLY_REGRESSION_SETUP]: {{<relref "/doc/project/checklist.md#sim_nightly_regression_setup" >}}
+[FPV_REGRESSION_SETUP]: {{<relref "/doc/project/checklist.md#fpv_regression_setup" >}}
+[SIM_COVERAGE_MODEL_ADDED]: {{<relref "/doc/project/checklist.md#sim_coverage_model_added" >}}
+[TB_LINT_SETUP]: {{<relref "/doc/project/checklist.md#tb_lint_setup" >}}
+[PRE_VERIFIED_SUB_MODULES_V1]: {{<relref "/doc/project/checklist.md#pre_verified_sub_modules_v1" >}}
+[DESIGN_SPEC_REVIEWED]: {{<relref "/doc/project/checklist.md#design_spec_reviewed" >}}
+[DV_PLAN_TESTPLAN_REVIEWED]: {{<relref "/doc/project/checklist.md#dv_plan_testplan_reviewed" >}}
+[STD_TEST_CATEGORIES_PLANNED]: {{<relref "/doc/project/checklist.md#std_test_categories_planned" >}}
+[V2_CHECKLIST_SCOPED]: {{<relref "/doc/project/checklist.md#v2_checklist_scoped" >}}
+
+### V2
+
+ Type | Item | Resolution | Note/Collaterals
+--------------|-----------------------------------------|-------------|------------------
+Documentation | [DESIGN_DELTAS_CAPTURED_V2][] | Not Started |
+Documentation | [DV_PLAN_COMPLETED][] | Not Started |
+Testbench | [ALL_INTERFACES_EXERCISED][] | Not Started |
+Testbench | [ALL_ASSERTION_CHECKS_ADDED][] | Not Started |
+Testbench | [SIM_TB_ENV_COMPLETED][] | Not Started |
+Tests | [SIM_ALL_TESTS_PASSING][] | Not Started |
+Tests | [FPV_ALL_ASSERTIONS_WRITTEN][] | Not Started |
+Tests | [FPV_ALL_ASSUMPTIONS_REVIEWED][] | Not Started |
+Tests | [SIM_FW_SIMULATED][] | Not Started |
+Regression | [SIM_NIGHTLY_REGRESSION_V2][] | Not Started |
+Coverage | [SIM_CODE_COVERAGE_V2][] | Not Started |
+Coverage | [SIM_FUNCTIONAL_COVERAGE_V2][] | Not Started |
+Coverage | [FPV_CODE_COVERAGE_V2][] | Not Started |
+Coverage | [FPV_COI_COVERAGE_V2][] | Not Started |
+Code Quality | [TB_LINT_PASS][] | Not Started |
+Issues | [NO_HIGH_PRIORITY_ISSUES_PENDING][] | Not Started |
+Issues | [ALL_LOW_PRIORITY_ISSUES_ROOT_CAUSED][] | Not Started |
+Integration | [PRE_VERIFIED_SUB_MODULES_V2][] | Not Started |
+Review | [V3_CHECKLIST_SCOPED][] | Not Started |
+
+[DESIGN_DELTAS_CAPTURED_V2]: {{<relref "/doc/project/checklist.md#design_deltas_captured_v2" >}}
+[DV_PLAN_COMPLETED]: {{<relref "/doc/project/checklist.md#dv_doc_completed" >}}
+[ALL_INTERFACES_EXERCISED]: {{<relref "/doc/project/checklist.md#all_interfaces_exercised" >}}
+[ALL_ASSERTION_CHECKS_ADDED]: {{<relref "/doc/project/checklist.md#all_assertion_checks_added" >}}
+[SIM_TB_ENV_COMPLETED]: {{<relref "/doc/project/checklist.md#sim_tb_env_completed" >}}
+[SIM_ALL_TESTS_PASSING]: {{<relref "/doc/project/checklist.md#sim_all_tests_passing" >}}
+[FPV_ALL_ASSERTIONS_WRITTEN]: {{<relref "/doc/project/checklist.md#fpv_all_assertions_written" >}}
+[FPV_ALL_ASSUMPTIONS_REVIEWED]: {{<relref "/doc/project/checklist.md#fpv_all_assumptions_reviewed" >}}
+[SIM_FW_SIMULATED]: {{<relref "/doc/project/checklist.md#sim_fw_simulated" >}}
+[SIM_NIGHTLY_REGRESSION_V2]: {{<relref "/doc/project/checklist.md#sim_nightly_regression_v2" >}}
+[SIM_CODE_COVERAGE_V2]: {{<relref "/doc/project/checklist.md#sim_code_coverage_v2" >}}
+[SIM_FUNCTIONAL_COVERAGE_V2]: {{<relref "/doc/project/checklist.md#sim_functional_coverage_v2" >}}
+[FPV_CODE_COVERAGE_V2]: {{<relref "/doc/project/checklist.md#fpv_code_coverage_v2" >}}
+[FPV_COI_COVERAGE_V2]: {{<relref "/doc/project/checklist.md#fpv_coi_coverage_v2" >}}
+[TB_LINT_PASS]: {{<relref "/doc/project/checklist.md#tb_lint_pass" >}}
+[NO_HIGH_PRIORITY_ISSUES_PENDING]: {{<relref "/doc/project/checklist.md#no_high_priority_issues_pending" >}}
+[ALL_LOW_PRIORITY_ISSUES_ROOT_CAUSED]:{{<relref "/doc/project/checklist.md#all_low_priority_issues_root_caused" >}}
+[PRE_VERIFIED_SUB_MODULES_V2]: {{<relref "/doc/project/checklist.md#pre_verified_sub_modules_v2" >}}
+[V3_CHECKLIST_SCOPED]: {{<relref "/doc/project/checklist.md#v3_checklist_scoped" >}}
+
+### V3
+
+ Type | Item | Resolution | Note/Collaterals
+--------------|-----------------------------------|-------------|------------------
+Documentation | [DESIGN_DELTAS_CAPTURED_V3][] | Not Started |
+Testbench | [ALL_TODOS_RESOLVED][] | Not Started |
+Tests | [X_PROP_ANALYSIS_COMPLETED][] | Not Started |
+Tests | [FPV_ASSERTIONS_PROVEN_AT_V3][] | Not Started |
+Regression | [SIM_NIGHTLY_REGRESSION_AT_V3][] | Not Started |
+Coverage | [SIM_CODE_COVERAGE_AT_100][] | Not Started |
+Coverage | [SIM_FUNCTIONAL_COVERAGE_AT_100][]| Not Started |
+Coverage | [FPV_CODE_COVERAGE_AT_100][] | Not Started |
+Coverage | [FPV_COI_COVERAGE_AT_100][] | Not Started |
+Issues | [NO_ISSUES_PENDING][] | Not Started |
+Code Quality | [NO_TOOL_WARNINGS_THROWN][] | Not Started |
+Code Quality | [TB_LINT_COMPLETE][] | Not Started |
+Integration | [PRE_VERIFIED_SUB_MODULES_V3][] | Not Started |
+Review | Reviewer(s) | Not Started |
+Review | Signoff date | Not Started |
+
+[DESIGN_DELTAS_CAPTURED_V3]: {{<relref "/doc/project/checklist.md#design_deltas_captured_v3" >}}
+[ALL_TODOS_RESOLVED]: {{<relref "/doc/project/checklist.md#all_todos_resolved" >}}
+[X_PROP_ANALYSIS_COMPLETED]: {{<relref "/doc/project/checklist.md#x_prop_analysis_completed" >}}
+[FPV_ASSERTIONS_PROVEN_AT_V3]: {{<relref "/doc/project/checklist.md#fpv_assertions_proven_at_v3" >}}
+[SIM_NIGHTLY_REGRESSION_AT_V3]: {{<relref "/doc/project/checklist.md#sim_nightly_regression_at_v3" >}}
+[SIM_CODE_COVERAGE_AT_100]: {{<relref "/doc/project/checklist.md#sim_code_coverage_at_100" >}}
+[SIM_FUNCTIONAL_COVERAGE_AT_100]:{{<relref "/doc/project/checklist.md#sim_functional_coverage_at_100" >}}
+[FPV_CODE_COVERAGE_AT_100]: {{<relref "/doc/project/checklist.md#fpv_code_coverage_at_100" >}}
+[FPV_COI_COVERAGE_AT_100]: {{<relref "/doc/project/checklist.md#fpv_coi_coverage_at_100" >}}
+[NO_ISSUES_PENDING]: {{<relref "/doc/project/checklist.md#no_issues_pending" >}}
+[NO_TOOL_WARNINGS_THROWN]: {{<relref "/doc/project/checklist.md#no_tool_warnings_thrown" >}}
+[TB_LINT_COMPLETE]: {{<relref "/doc/project/checklist.md#tb_lint_complete" >}}
+[PRE_VERIFIED_SUB_MODULES_V3]: {{<relref "/doc/project/checklist.md#pre_verified_sub_modules_v3" >}}
diff --git a/hw/ip/dcd/doc/dv/index.md b/hw/ip/dcd/doc/dv/index.md
new file mode 100644
index 0000000..3301656
--- /dev/null
+++ b/hw/ip/dcd/doc/dv/index.md
@@ -0,0 +1,117 @@
+---
+title: "DCD DV document"
+---
+
+<!-- Copy this file to hw/ip/dcd/doc/dv/index.md and make changes as needed.
+For convenience 'dcd' in the document can be searched and replaced easily with the
+desired IP (with case sensitivity!). Also, use the testbench block diagram
+located at OpenTitan team drive / 'design verification'
+as a starting point and modify it to reflect your dcd testbench and save it
+to hw/ip/dcd/doc/dv/tb.svg. It should get linked and rendered under the block
+diagram section below. Please update / modify / remove sections below as
+applicable. Once done, remove this comment before making a PR. -->
+
+## Goals
+* **DV**
+ * Verify all DCD IP features by running dynamic simulations with a SV/UVM based testbench
+ * Develop and run all tests based on the [DV plan](#dv-plan) below towards closing code and functional coverage on the IP and all of its sub-modules
+* **FPV**
+ * Verify TileLink device protocol compliance with an SVA based testbench
+
+## Current status
+* [Design & verification stage]({{< relref "hw" >}})
+ * [HW development stages]({{< relref "doc/project/development_stages" >}})
+* [Simulation results](https://reports.opentitan.org/hw/ip/dcd/dv/latest/results.html)
+
+## Design features
+For detailed information on DCD design features, please see the [DCD HWIP technical specification]().
+
+## Testbench architecture
+DCD testbench has been constructed based on the [CIP testbench architecture]({{< relref "hw/dv/sv/cip_lib/doc" >}}).
+
+### Block diagram
+
+
+### Top level testbench
+Top level testbench is located at `hw/ip/dcd/dv/tb/tb.sv`. It instantiates the DCD DUT module `hw/ip/dcd/rtl/dcd.sv`.
+In addition, it instantiates the following interfaces, connects them to the DUT and sets their handle into `uvm_config_db`:
+* [Clock and reset interface]({{< relref "hw/dv/sv/common_ifs" >}})
+* [TileLink host interface]({{< relref "hw/dv/sv/tl_agent/README.md" >}})
+* DCD IOs
+* Interrupts ([`pins_if`]({{< relref "hw/dv/sv/common_ifs" >}})
+* Alerts ([`pins_if`]({{< relref "hw/dv/sv/common_ifs" >}})
+* Devmode ([`pins_if`]({{< relref "hw/dv/sv/common_ifs" >}})
+
+### Common DV utility components
+The following utilities provide generic helper tasks and functions to perform activities that are common across the project:
+* [dv_utils_pkg]({{< relref "hw/dv/sv/dv_utils/README.md" >}})
+* [csr_utils_pkg]({{< relref "hw/dv/sv/csr_utils/README.md" >}})
+
+### Compile-time configurations
+[list compile time configurations, if any and what are they used for]
+
+### Global types & methods
+All common types and methods defined at the package level can be found in
+`dcd_env_pkg`. Some of them in use are:
+```systemverilog
+[list a few parameters, types & methods; no need to mention all]
+```
+### TL_agent
+DCD testbench instantiates (already handled in CIP base env) [tl_agent]({{< relref "hw/dv/sv/tl_agent/README.md" >}})
+which provides the ability to drive and independently monitor random traffic via
+TL host interface into DCD device.
+
+### UVC/agent 1
+[Describe here or add link to its README]
+
+### UVC/agent 2
+[Describe here or add link to its README]
+
+### UVM RAL Model
+The DCD RAL model is created with the [`ralgen`]({{< relref "hw/dv/tools/ralgen/README.md" >}}) FuseSoC generator script automatically when the simulation is at the build stage.
+
+It can be created manually by invoking [`regtool`]({{< relref "util/reggen/README.md" >}}):
+
+### Reference models
+[Describe reference models in use if applicable, example: SHA256/HMAC]
+
+### Stimulus strategy
+#### Test sequences
+All test sequences reside in `hw/ip/dcd/dv/env/seq_lib`.
+The `dcd_base_vseq` virtual sequence is extended from `cip_base_vseq` and serves as a starting point.
+All test sequences are extended from `dcd_base_vseq`.
+It provides commonly used handles, variables, functions and tasks that the test sequences can simple use / call.
+Some of the most commonly used tasks / functions are as follows:
+* task 1:
+* task 2:
+
+#### Functional coverage
+To ensure high quality constrained random stimulus, it is necessary to develop a functional coverage model.
+The following covergroups have been developed to prove that the test intent has been adequately met:
+* cg1:
+* cg2:
+
+### Self-checking strategy
+#### Scoreboard
+The `dcd_scoreboard` is primarily used for end to end checking.
+It creates the following analysis ports to retrieve the data monitored by corresponding interface agents:
+* analysis port1:
+* analysis port2:
+<!-- explain inputs monitored, flow of data and outputs checked -->
+
+#### Assertions
+* TLUL assertions: The `tb/dcd_bind.sv` binds the `tlul_assert` [assertions]({{< relref "hw/ip/tlul/doc/TlulProtocolChecker.md" >}}) to the IP to ensure TileLink interface protocol compliance.
+* Unknown checks on DUT outputs: The RTL has assertions to ensure all outputs are initialized to known values after coming out of reset.
+* assert prop 1:
+* assert prop 2:
+
+## Building and running tests
+We are using our in-house developed [regression tool]({{< relref "hw/dv/tools/README.md" >}}) for building and running our tests and regressions.
+Please take a look at the link for detailed information on the usage, capabilities, features and known issues.
+Here's how to run a smoke test:
+```console
+$ $REPO_TOP/util/dvsim/dvsim.py $REPO_TOP/hw/ip/dcd/dv/dcd_sim_cfg.hjson -i dcd_smoke
+```
+
+## DV plan
+{{< testplan "hw/ip/dcd/data/dcd_testplan.hjson" >}}
diff --git a/hw/ip/dcd/dv/dcd_sim.core b/hw/ip/dcd/dv/dcd_sim.core
new file mode 100644
index 0000000..04a2839
--- /dev/null
+++ b/hw/ip/dcd/dv/dcd_sim.core
@@ -0,0 +1,29 @@
+CAPI=2:
+# Copyright lowRISC contributors.
+# Licensed under the Apache License, Version 2.0, see LICENSE for details.
+# SPDX-License-Identifier: Apache-2.0
+name: "lowrisc:dv:dcd_sim:0.1"
+description: "DCD DV sim target"
+filesets:
+ files_rtl:
+ depend:
+ - lowrisc:ip:dcd
+
+ files_dv:
+ depend:
+ - lowrisc:dv:dcd_test
+ - lowrisc:dv:dcd_sva
+ files:
+ - tb.sv
+ file_type: systemVerilogSource
+
+targets:
+ sim: &sim_target
+ toplevel: tb
+ filesets:
+ - files_rtl
+ - files_dv
+ default_tool: vcs
+
+ lint:
+ <<: *sim_target
diff --git a/hw/ip/dcd/dv/dcd_sim_cfg.hjson b/hw/ip/dcd/dv/dcd_sim_cfg.hjson
new file mode 100644
index 0000000..a00da5a
--- /dev/null
+++ b/hw/ip/dcd/dv/dcd_sim_cfg.hjson
@@ -0,0 +1,64 @@
+// Copyright lowRISC contributors.
+// Licensed under the Apache License, Version 2.0, see LICENSE for details.
+// SPDX-License-Identifier: Apache-2.0
+{
+ // Name of the sim cfg - typically same as the name of the DUT.
+ name: dcd
+
+ // Top level dut name (sv module).
+ dut: dcd
+
+ // Top level testbench name (sv module).
+ tb: tb
+
+ // Simulator used to sign off this block
+ tool: vcs
+
+ // Fusesoc core file used for building the file list.
+ fusesoc_core: lowrisc:dv:dcd_sim:0.1
+
+ // Testplan hjson file.
+ testplan: "{proj_root}/hw/ip/dcd/data/dcd_testplan.hjson"
+
+ // RAL spec - used to generate the RAL model.
+ ral_spec: "{proj_root}/hw/ip/dcd/data/dcd.hjson"
+
+ // Import additional common sim cfg files.
+ // TODO: remove imported cfgs that do not apply.
+ import_cfgs: [// Project wide common sim cfg file
+ "{proj_root}/hw/dv/tools/dvsim/common_sim_cfg.hjson",
+ // Common CIP test lists
+ "{proj_root}/hw/dv/tools/dvsim/tests/csr_tests.hjson",
+ "{proj_root}/hw/dv/tools/dvsim/tests/intr_test.hjson",
+ "{proj_root}/hw/dv/tools/dvsim/tests/tl_access_tests.hjson",
+ "{proj_root}/hw/dv/tools/dvsim/tests/stress_tests.hjson"]
+
+ // Add additional tops for simulation.
+ sim_tops: ["dcd_bind"]
+
+ // Default iterations for all tests - each test entry can override this.
+ reseed: 50
+
+ // Default UVM test and seq class name.
+ uvm_test: dcd_base_test
+ uvm_test_seq: dcd_base_vseq
+
+ // List of test specifications.
+ tests: [
+ {
+ name: dcd_smoke
+ uvm_test_seq: dcd_smoke_vseq
+ }
+
+ // TODO: add more tests here
+ ]
+
+ // List of regressions.
+ regressions: [
+ {
+ // TODO: Create smoke test and add back
+ name: smoke
+ tests: []
+ }
+ ]
+}
diff --git a/hw/ip/dcd/dv/env/dcd_env.core b/hw/ip/dcd/dv/env/dcd_env.core
new file mode 100644
index 0000000..509a200
--- /dev/null
+++ b/hw/ip/dcd/dv/env/dcd_env.core
@@ -0,0 +1,37 @@
+CAPI=2:
+# Copyright lowRISC contributors.
+# Licensed under the Apache License, Version 2.0, see LICENSE for details.
+# SPDX-License-Identifier: Apache-2.0
+name: "lowrisc:dv:dcd_env:0.1"
+description: "DCD DV UVM environment"
+filesets:
+ files_dv:
+ depend:
+ - lowrisc:dv:ralgen
+ - lowrisc:dv:cip_lib
+ files:
+ - dcd_env_pkg.sv
+ - dcd_env_cfg.sv: {is_include_file: true}
+ - dcd_env_cov.sv: {is_include_file: true}
+ - dcd_virtual_sequencer.sv: {is_include_file: true}
+ - dcd_scoreboard.sv: {is_include_file: true}
+ - dcd_env.sv: {is_include_file: true}
+ - seq_lib/dcd_vseq_list.sv: {is_include_file: true}
+ - seq_lib/dcd_base_vseq.sv: {is_include_file: true}
+ - seq_lib/dcd_common_vseq.sv: {is_include_file: true}
+ - seq_lib/dcd_smoke_vseq.sv: {is_include_file: true}
+ file_type: systemVerilogSource
+
+generate:
+ ral:
+ generator: ralgen
+ parameters:
+ name: dcd
+ ip_hjson: ../../data/dcd.hjson
+
+targets:
+ default:
+ filesets:
+ - files_dv
+ generate:
+ - ral
diff --git a/hw/ip/dcd/dv/env/dcd_env.sv b/hw/ip/dcd/dv/env/dcd_env.sv
new file mode 100644
index 0000000..985645a
--- /dev/null
+++ b/hw/ip/dcd/dv/env/dcd_env.sv
@@ -0,0 +1,29 @@
+// Copyright lowRISC contributors.
+// Licensed under the Apache License, Version 2.0, see LICENSE for details.
+// SPDX-License-Identifier: Apache-2.0
+
+class dcd_env extends cip_base_env #(
+ .CFG_T (dcd_env_cfg),
+ .COV_T (dcd_env_cov),
+ .VIRTUAL_SEQUENCER_T(dcd_virtual_sequencer),
+ .SCOREBOARD_T (dcd_scoreboard)
+ );
+ `uvm_component_utils(dcd_env)
+
+ `uvm_component_new
+
+ function void build_phase(uvm_phase phase);
+ super.build_phase(phase);
+
+ // get the vifs from config db
+ if (!uvm_config_db#(virtual clk_rst_if)::get(this, "", "clk_aon_rst_vif",
+ cfg.clk_aon_rst_vif)) begin
+ `uvm_fatal(`gfn, "failed to get clk_aon_rst_vif from uvm_config_db")
+ end
+ endfunction
+
+ function void connect_phase(uvm_phase phase);
+ super.connect_phase(phase);
+ endfunction
+
+endclass
diff --git a/hw/ip/dcd/dv/env/dcd_env_cfg.sv b/hw/ip/dcd/dv/env/dcd_env_cfg.sv
new file mode 100644
index 0000000..88d1596
--- /dev/null
+++ b/hw/ip/dcd/dv/env/dcd_env_cfg.sv
@@ -0,0 +1,28 @@
+// Copyright lowRISC contributors.
+// Licensed under the Apache License, Version 2.0, see LICENSE for details.
+// SPDX-License-Identifier: Apache-2.0
+
+class dcd_env_cfg extends cip_base_env_cfg #(.RAL_T(dcd_reg_block));
+
+ virtual clk_rst_if clk_aon_rst_vif;
+
+ // ext component cfgs
+
+ `uvm_object_utils_begin(dcd_env_cfg)
+ `uvm_object_utils_end
+
+ `uvm_object_new
+
+ virtual function void initialize(bit [31:0] csr_base_addr = '1);
+ super.initialize(csr_base_addr);
+
+ // set num_interrupts & num_alerts
+ begin
+ uvm_reg rg = ral.get_reg_by_name("intr_state");
+ if (rg != null) begin
+ num_interrupts = ral.intr_state.get_n_used_bits();
+ end
+ end
+ endfunction
+
+endclass
diff --git a/hw/ip/dcd/dv/env/dcd_env_cov.sv b/hw/ip/dcd/dv/env/dcd_env_cov.sv
new file mode 100644
index 0000000..cabad77
--- /dev/null
+++ b/hw/ip/dcd/dv/env/dcd_env_cov.sv
@@ -0,0 +1,32 @@
+// Copyright lowRISC contributors.
+// Licensed under the Apache License, Version 2.0, see LICENSE for details.
+// SPDX-License-Identifier: Apache-2.0
+
+/**
+ * Covergoups that are dependent on run-time parameters that may be available
+ * only in build_phase can be defined here
+ * Covergroups may also be wrapped inside helper classes if needed.
+ */
+
+class dcd_env_cov extends cip_base_env_cov #(.CFG_T(dcd_env_cfg));
+ `uvm_component_utils(dcd_env_cov)
+
+ // the base class provides the following handles for use:
+ // dcd_env_cfg: cfg
+
+ // covergroups
+ // [add covergroups here]
+
+ function new(string name, uvm_component parent);
+ super.new(name, parent);
+ // [instantiate covergroups here]
+ endfunction : new
+
+ virtual function void build_phase(uvm_phase phase);
+ super.build_phase(phase);
+ // [or instantiate covergroups here]
+ // Please instantiate sticky_intr_cov array of objects for all interrupts that are sticky
+ // See cip_base_env_cov for details
+ endfunction
+
+endclass
diff --git a/hw/ip/dcd/dv/env/dcd_env_pkg.sv b/hw/ip/dcd/dv/env/dcd_env_pkg.sv
new file mode 100644
index 0000000..0700228
--- /dev/null
+++ b/hw/ip/dcd/dv/env/dcd_env_pkg.sv
@@ -0,0 +1,35 @@
+// Copyright lowRISC contributors.
+// Licensed under the Apache License, Version 2.0, see LICENSE for details.
+// SPDX-License-Identifier: Apache-2.0
+
+package dcd_env_pkg;
+ // dep packages
+ import uvm_pkg::*;
+ import top_pkg::*;
+ import dv_utils_pkg::*;
+ import dv_lib_pkg::*;
+ import tl_agent_pkg::*;
+ import cip_base_pkg::*;
+ import dv_base_reg_pkg::*;
+ import csr_utils_pkg::*;
+ import dcd_ral_pkg::*;
+
+ // macro includes
+ `include "uvm_macros.svh"
+ `include "dv_macros.svh"
+
+ // parameters
+
+ // types
+
+ // functions
+
+ // package sources
+ `include "dcd_env_cfg.sv"
+ `include "dcd_env_cov.sv"
+ `include "dcd_virtual_sequencer.sv"
+ `include "dcd_scoreboard.sv"
+ `include "dcd_env.sv"
+ `include "dcd_vseq_list.sv"
+
+endpackage
diff --git a/hw/ip/dcd/dv/env/dcd_scoreboard.sv b/hw/ip/dcd/dv/env/dcd_scoreboard.sv
new file mode 100644
index 0000000..4e82735
--- /dev/null
+++ b/hw/ip/dcd/dv/env/dcd_scoreboard.sv
@@ -0,0 +1,99 @@
+// Copyright lowRISC contributors.
+// Licensed under the Apache License, Version 2.0, see LICENSE for details.
+// SPDX-License-Identifier: Apache-2.0
+
+class dcd_scoreboard extends cip_base_scoreboard #(
+ .CFG_T(dcd_env_cfg),
+ .RAL_T(dcd_reg_block),
+ .COV_T(dcd_env_cov)
+ );
+ `uvm_component_utils(dcd_scoreboard)
+
+ // local variables
+
+ // TLM agent fifos
+
+ // local queues to hold incoming packets pending comparison
+
+ `uvm_component_new
+
+ function void build_phase(uvm_phase phase);
+ super.build_phase(phase);
+ endfunction
+
+ function void connect_phase(uvm_phase phase);
+ super.connect_phase(phase);
+ endfunction
+
+ task run_phase(uvm_phase phase);
+ super.run_phase(phase);
+ fork
+ join_none
+ endtask
+
+ virtual task process_tl_access(tl_seq_item item, tl_channels_e channel = DataChannel);
+ uvm_reg csr;
+ bit do_read_check = 1'b1;
+ bit write = item.is_write();
+ uvm_reg_addr_t csr_addr = ral.get_word_aligned_addr(item.a_addr);
+
+ bit addr_phase_read = (!write && channel == AddrChannel);
+ bit addr_phase_write = (write && channel == AddrChannel);
+ bit data_phase_read = (!write && channel == DataChannel);
+ bit data_phase_write = (write && channel == DataChannel);
+
+ // if access was to a valid csr, get the csr handle
+ if (csr_addr inside {cfg.csr_addrs}) begin
+ csr = ral.default_map.get_reg_by_offset(csr_addr);
+ `DV_CHECK_NE_FATAL(csr, null)
+ end
+ else begin
+ `uvm_fatal(`gfn, $sformatf("Access unexpected addr 0x%0h", csr_addr))
+ end
+
+ // if incoming access is a write to a valid csr, then make updates right away
+ if (addr_phase_write) begin
+ void'(csr.predict(.value(item.a_data), .kind(UVM_PREDICT_WRITE), .be(item.a_mask)));
+ end
+
+ // process the csr req
+ // for write, update local variable and fifo at address phase
+ // for read, update predication at address phase and compare at data phase
+ case (csr.get_name())
+ // add individual case item for each csr
+ "intr_state": begin
+ // FIXME
+ do_read_check = 1'b0;
+ end
+ "intr_enable": begin
+ // FIXME
+ end
+ "intr_test": begin
+ // FIXME
+ end
+ default: begin
+ `uvm_fatal(`gfn, $sformatf("invalid csr: %0s", csr.get_full_name()))
+ end
+ endcase
+
+ // On reads, if do_read_check, is set, then check mirrored_value against item.d_data
+ if (data_phase_read) begin
+ if (do_read_check) begin
+ `DV_CHECK_EQ(csr.get_mirrored_value(), item.d_data,
+ $sformatf("reg name: %0s", csr.get_full_name()))
+ end
+ void'(csr.predict(.value(item.d_data), .kind(UVM_PREDICT_READ)));
+ end
+ endtask
+
+ virtual function void reset(string kind = "HARD");
+ super.reset(kind);
+ // reset local fifos queues and variables
+ endfunction
+
+ function void check_phase(uvm_phase phase);
+ super.check_phase(phase);
+ // post test checks - ensure that all local fifos and queues are empty
+ endfunction
+
+endclass
diff --git a/hw/ip/dcd/dv/env/dcd_virtual_sequencer.sv b/hw/ip/dcd/dv/env/dcd_virtual_sequencer.sv
new file mode 100644
index 0000000..0689f19
--- /dev/null
+++ b/hw/ip/dcd/dv/env/dcd_virtual_sequencer.sv
@@ -0,0 +1,14 @@
+// Copyright lowRISC contributors.
+// Licensed under the Apache License, Version 2.0, see LICENSE for details.
+// SPDX-License-Identifier: Apache-2.0
+
+class dcd_virtual_sequencer extends cip_base_virtual_sequencer #(
+ .CFG_T(dcd_env_cfg),
+ .COV_T(dcd_env_cov)
+ );
+ `uvm_component_utils(dcd_virtual_sequencer)
+
+
+ `uvm_component_new
+
+endclass
diff --git a/hw/ip/dcd/dv/env/seq_lib/dcd_base_vseq.sv b/hw/ip/dcd/dv/env/seq_lib/dcd_base_vseq.sv
new file mode 100644
index 0000000..e617ff2
--- /dev/null
+++ b/hw/ip/dcd/dv/env/seq_lib/dcd_base_vseq.sv
@@ -0,0 +1,40 @@
+// Copyright lowRISC contributors.
+// Licensed under the Apache License, Version 2.0, see LICENSE for details.
+// SPDX-License-Identifier: Apache-2.0
+
+class dcd_base_vseq extends cip_base_vseq #(
+ .RAL_T (dcd_reg_block),
+ .CFG_T (dcd_env_cfg),
+ .COV_T (dcd_env_cov),
+ .VIRTUAL_SEQUENCER_T (dcd_virtual_sequencer)
+ );
+ `uvm_object_utils(dcd_base_vseq)
+
+ // various knobs to enable certain routines
+ bit do_dcd_init = 1'b1;
+
+ `uvm_object_new
+
+ virtual task dut_init(string reset_kind = "HARD");
+ super.dut_init();
+ if (do_dcd_init) dcd_init();
+ endtask
+
+ virtual task dut_shutdown();
+ // check for pending dcd operations and wait for them to complete
+ // TODO
+ endtask
+
+ // setup basic dcd features
+ virtual task dcd_init();
+ `uvm_info(`gfn, "Initializating dcd, nothing to do at the moment", UVM_MEDIUM)
+ endtask // dcd_init
+
+ virtual task apply_reset(string kind = "HARD");
+ if (kind == "HARD") begin
+ cfg.clk_aon_rst_vif.apply_reset();
+ end
+ super.apply_reset(kind);
+ endtask // apply_reset
+
+endclass : dcd_base_vseq
diff --git a/hw/ip/dcd/dv/env/seq_lib/dcd_common_vseq.sv b/hw/ip/dcd/dv/env/seq_lib/dcd_common_vseq.sv
new file mode 100644
index 0000000..1235569
--- /dev/null
+++ b/hw/ip/dcd/dv/env/seq_lib/dcd_common_vseq.sv
@@ -0,0 +1,17 @@
+// Copyright lowRISC contributors.
+// Licensed under the Apache License, Version 2.0, see LICENSE for details.
+// SPDX-License-Identifier: Apache-2.0
+
+class dcd_common_vseq extends dcd_base_vseq;
+ `uvm_object_utils(dcd_common_vseq)
+
+ constraint num_trans_c {
+ num_trans inside {[1:2]};
+ }
+ `uvm_object_new
+
+ virtual task body();
+ run_common_vseq_wrapper(num_trans);
+ endtask : body
+
+endclass
diff --git a/hw/ip/dcd/dv/env/seq_lib/dcd_smoke_vseq.sv b/hw/ip/dcd/dv/env/seq_lib/dcd_smoke_vseq.sv
new file mode 100644
index 0000000..64e48f7
--- /dev/null
+++ b/hw/ip/dcd/dv/env/seq_lib/dcd_smoke_vseq.sv
@@ -0,0 +1,15 @@
+// Copyright lowRISC contributors.
+// Licensed under the Apache License, Version 2.0, see LICENSE for details.
+// SPDX-License-Identifier: Apache-2.0
+
+// smoke test vseq
+class dcd_smoke_vseq extends dcd_base_vseq;
+ `uvm_object_utils(dcd_smoke_vseq)
+
+ `uvm_object_new
+
+ task body();
+ `uvm_error(`gfn, "FIXME")
+ endtask : body
+
+endclass : dcd_smoke_vseq
diff --git a/hw/ip/dcd/dv/env/seq_lib/dcd_vseq_list.sv b/hw/ip/dcd/dv/env/seq_lib/dcd_vseq_list.sv
new file mode 100644
index 0000000..3386e4f
--- /dev/null
+++ b/hw/ip/dcd/dv/env/seq_lib/dcd_vseq_list.sv
@@ -0,0 +1,7 @@
+// Copyright lowRISC contributors.
+// Licensed under the Apache License, Version 2.0, see LICENSE for details.
+// SPDX-License-Identifier: Apache-2.0
+
+`include "dcd_base_vseq.sv"
+`include "dcd_smoke_vseq.sv"
+`include "dcd_common_vseq.sv"
diff --git a/hw/ip/dcd/dv/sva/dcd_bind.sv b/hw/ip/dcd/dv/sva/dcd_bind.sv
new file mode 100644
index 0000000..9c2ad4c
--- /dev/null
+++ b/hw/ip/dcd/dv/sva/dcd_bind.sv
@@ -0,0 +1,26 @@
+// Copyright lowRISC contributors.
+// Licensed under the Apache License, Version 2.0, see LICENSE for details.
+// SPDX-License-Identifier: Apache-2.0
+
+module dcd_bind;
+
+ bind dcd tlul_assert #(
+ .EndpointType("Device")
+ ) tlul_assert_device (
+ .clk_i,
+ .rst_ni,
+ .h2d (tl_i),
+ .d2h (tl_o)
+ );
+
+ import dcd_reg_pkg::*;
+ bind dcd dcd_csr_assert_fpv dcd_csr_assert (
+ .clk_i,
+ .rst_ni,
+ .h2d (tl_i),
+ .d2h (tl_o),
+ .reg2hw (reg2hw),
+ .hw2reg (hw2reg)
+ );
+
+endmodule
diff --git a/hw/ip/dcd/dv/sva/dcd_sva.core b/hw/ip/dcd/dv/sva/dcd_sva.core
new file mode 100644
index 0000000..c4e7ae6
--- /dev/null
+++ b/hw/ip/dcd/dv/sva/dcd_sva.core
@@ -0,0 +1,38 @@
+CAPI=2:
+# Copyright lowRISC contributors.
+# Licensed under the Apache License, Version 2.0, see LICENSE for details.
+# SPDX-License-Identifier: Apache-2.0
+name: "lowrisc:dv:dcd_sva:0.1"
+description: "DCD assertion modules and bind file."
+filesets:
+ files_dv:
+ depend:
+ - lowrisc:tlul:headers
+ - lowrisc:fpv:csr_assert_gen
+ files:
+ - dcd_bind.sv
+ file_type: systemVerilogSource
+
+ files_formal:
+ depend:
+ - lowrisc:ip:dcd
+
+generate:
+ csr_assert_gen:
+ generator: csr_assert_gen
+ parameters:
+ spec: ../../data/dcd.hjson
+ depend: lowrisc:ip:dcd
+
+targets:
+ default: &default_target
+ filesets:
+ - files_dv
+ generate:
+ - csr_assert_gen
+ formal:
+ <<: *default_target
+ filesets:
+ - files_formal
+ - files_dv
+ toplevel: dcd
diff --git a/hw/ip/dcd/dv/tb.sv b/hw/ip/dcd/dv/tb.sv
new file mode 100644
index 0000000..6f0abb0
--- /dev/null
+++ b/hw/ip/dcd/dv/tb.sv
@@ -0,0 +1,56 @@
+// Copyright lowRISC contributors.
+// Licensed under the Apache License, Version 2.0, see LICENSE for details.
+// SPDX-License-Identifier: Apache-2.0
+//
+module tb;
+ // dep packages
+ import uvm_pkg::*;
+ import dv_utils_pkg::*;
+ import dcd_env_pkg::*;
+ import dcd_test_pkg::*;
+
+ // macro includes
+ `include "uvm_macros.svh"
+ `include "dv_macros.svh"
+
+ wire clk, rst_n;
+ wire devmode;
+ wire [NUM_MAX_INTERRUPTS-1:0] interrupts;
+
+ // interfaces
+ clk_rst_if clk_rst_if(.clk(clk), .rst_n(rst_n));
+ clk_rst_if clk_aon_rst_if(.clk(clk_aon), .rst_n(rst_aon_n));
+ pins_if #(NUM_MAX_INTERRUPTS) intr_if(interrupts);
+ pins_if #(1) devmode_if(devmode);
+ tl_if tl_if(.clk(clk), .rst_n(rst_n));
+
+
+ // dut
+ dcd dut (
+ .clk_i (clk ),
+ .rst_ni (rst_n ),
+ .clk_aon_i (clk_aon ),
+ .rst_slow_ni (rst_aon_n),
+ .tl_i (tl_if.h2d),
+ .tl_o (tl_if.d2h),
+ .adc_o (),
+ .adc_i ('0),
+ .intr_debug_cable_o (interrupts[0]),
+ .debug_cable_wakeup_o ()
+ );
+
+ initial begin
+ // drive clk and rst_n from clk_if
+ clk_aon_rst_if.set_active();
+ clk_rst_if.set_active();
+ clk_aon_rst_if.set_freq_khz(200);
+ uvm_config_db#(virtual clk_rst_if)::set(null, "*.env", "clk_rst_vif", clk_rst_if);
+ uvm_config_db#(virtual clk_rst_if)::set(null, "*.env", "clk_aon_rst_vif", clk_aon_rst_if);
+ uvm_config_db#(intr_vif)::set(null, "*.env", "intr_vif", intr_if);
+ uvm_config_db#(devmode_vif)::set(null, "*.env", "devmode_vif", devmode_if);
+ uvm_config_db#(virtual tl_if)::set(null, "*.env.m_tl_agent*", "vif", tl_if);
+ $timeformat(-12, 0, " ps", 12);
+ run_test();
+ end
+
+endmodule
diff --git a/hw/ip/dcd/dv/tests/dcd_base_test.sv b/hw/ip/dcd/dv/tests/dcd_base_test.sv
new file mode 100644
index 0000000..f4ff243
--- /dev/null
+++ b/hw/ip/dcd/dv/tests/dcd_base_test.sv
@@ -0,0 +1,20 @@
+// Copyright lowRISC contributors.
+// Licensed under the Apache License, Version 2.0, see LICENSE for details.
+// SPDX-License-Identifier: Apache-2.0
+
+class dcd_base_test extends cip_base_test #(
+ .CFG_T(dcd_env_cfg),
+ .ENV_T(dcd_env)
+ );
+
+ `uvm_component_utils(dcd_base_test)
+ `uvm_component_new
+
+ // the base class dv_base_test creates the following instances:
+ // dcd_env_cfg: cfg
+ // dcd_env: env
+
+ // the base class also looks up UVM_TEST_SEQ plusarg to create and run that seq in
+ // the run_phase; as such, nothing more needs to be done
+
+endclass : dcd_base_test
diff --git a/hw/ip/dcd/dv/tests/dcd_test.core b/hw/ip/dcd/dv/tests/dcd_test.core
new file mode 100644
index 0000000..fc4182a
--- /dev/null
+++ b/hw/ip/dcd/dv/tests/dcd_test.core
@@ -0,0 +1,19 @@
+CAPI=2:
+# Copyright lowRISC contributors.
+# Licensed under the Apache License, Version 2.0, see LICENSE for details.
+# SPDX-License-Identifier: Apache-2.0
+name: "lowrisc:dv:dcd_test:0.1"
+description: "DCD DV UVM test"
+filesets:
+ files_dv:
+ depend:
+ - lowrisc:dv:dcd_env
+ files:
+ - dcd_test_pkg.sv
+ - dcd_base_test.sv: {is_include_file: true}
+ file_type: systemVerilogSource
+
+targets:
+ default:
+ filesets:
+ - files_dv
diff --git a/hw/ip/dcd/dv/tests/dcd_test_pkg.sv b/hw/ip/dcd/dv/tests/dcd_test_pkg.sv
new file mode 100644
index 0000000..3112cb8
--- /dev/null
+++ b/hw/ip/dcd/dv/tests/dcd_test_pkg.sv
@@ -0,0 +1,22 @@
+// Copyright lowRISC contributors.
+// Licensed under the Apache License, Version 2.0, see LICENSE for details.
+// SPDX-License-Identifier: Apache-2.0
+
+package dcd_test_pkg;
+ // dep packages
+ import uvm_pkg::*;
+ import cip_base_pkg::*;
+ import dcd_env_pkg::*;
+
+ // macro includes
+ `include "uvm_macros.svh"
+ `include "dv_macros.svh"
+
+ // local types
+
+ // functions
+
+ // package sources
+ `include "dcd_base_test.sv"
+
+endpackage
diff --git a/hw/ip/dcd/rtl/dcd_core.sv b/hw/ip/dcd/rtl/dcd_core.sv
index 558943e..47f80f3 100644
--- a/hw/ip/dcd/rtl/dcd_core.sv
+++ b/hw/ip/dcd/rtl/dcd_core.sv
@@ -114,7 +114,7 @@
);
prim_fifo_async #(
.Width(4),
- .Depth(2)
+ .Depth(4)
) i_cfg_pwrup_time (
.clk_wr_i (clk_i),
.rst_wr_ni (rst_ni),
@@ -141,7 +141,7 @@
prim_fifo_async #(
.Width(24),
- .Depth(2)
+ .Depth(4)
) i_cfg_wakeup_time (
.clk_wr_i (clk_i),
.rst_wr_ni (rst_ni),
@@ -168,7 +168,7 @@
prim_fifo_async #(
.Width(8),
- .Depth(2)
+ .Depth(4)
) i_cfg_lp_sample_cnt (
.clk_wr_i (clk_i),
.rst_wr_ni (rst_ni),
@@ -195,7 +195,7 @@
prim_fifo_async #(
.Width(16),
- .Depth(2)
+ .Depth(4)
) i_cfg_np_sample_cnt (
.clk_wr_i (clk_i),
.rst_wr_ni (rst_ni),
@@ -251,7 +251,7 @@
prim_fifo_async #(
.Width(10),
- .Depth(2)
+ .Depth(4)
) i_cfg_chn0_min_v (
.clk_wr_i (clk_i),
.rst_wr_ni (rst_ni),
@@ -279,7 +279,7 @@
prim_fifo_async #(
.Width(10),
- .Depth(2)
+ .Depth(4)
) i_cfg_chn1_min_v (
.clk_wr_i (clk_i),
.rst_wr_ni (rst_ni),
@@ -306,7 +306,7 @@
prim_fifo_async #(
.Width(10),
- .Depth(2)
+ .Depth(4)
) i_cfg_chn0_max_v (
.clk_wr_i (clk_i),
.rst_wr_ni (rst_ni),
@@ -333,7 +333,7 @@
prim_fifo_async #(
.Width(10),
- .Depth(2)
+ .Depth(4)
) i_cfg_chn1_max_v (
.clk_wr_i (clk_i),
.rst_wr_ni (rst_ni),
@@ -534,7 +534,7 @@
prim_fifo_async #(
.Width(10),
- .Depth(2)
+ .Depth(4)
) i_cfg_chn0_val (
.clk_wr_i (clk_aon_i),
.rst_wr_ni (rst_slow_ni),
@@ -553,7 +553,7 @@
prim_fifo_async #(
.Width(10),
- .Depth(2)
+ .Depth(4)
) i_cfg_chn1_val (
.clk_wr_i (clk_aon_i),
.rst_wr_ni (rst_slow_ni),
@@ -572,7 +572,7 @@
prim_fifo_async #(
.Width(10),
- .Depth(2)
+ .Depth(4)
) i_cfg_chn0_val_intr (
.clk_wr_i (clk_aon_i),
.rst_wr_ni (rst_slow_ni),
@@ -591,7 +591,7 @@
prim_fifo_async #(
.Width(10),
- .Depth(2)
+ .Depth(4)
) i_cfg_chn1_val_intr (
.clk_wr_i (clk_aon_i),
.rst_wr_ni (rst_slow_ni),
diff --git a/hw/top_earlgrey/dv/top_earlgrey_sim_cfgs.hjson b/hw/top_earlgrey/dv/top_earlgrey_sim_cfgs.hjson
index 231f9d9..2dbe98e 100644
--- a/hw/top_earlgrey/dv/top_earlgrey_sim_cfgs.hjson
+++ b/hw/top_earlgrey/dv/top_earlgrey_sim_cfgs.hjson
@@ -17,6 +17,7 @@
"{proj_root}/hw/ip/aes/dv/aes_sim_cfg.hjson",
"{proj_root}/hw/ip/aon_timer/dv/aon_timer_sim_cfg.hjson",
"{proj_root}/hw/ip/csrng/dv/csrng_sim_cfg.hjson",
+ "{proj_root}/hw/ip/dcd/dv/dcd_sim_cfg.hjson",
"{proj_root}/hw/ip/entropy_src/dv/entropy_src_sim_cfg.hjson",
"{proj_root}/hw/ip/flash_ctrl/dv/flash_ctrl_sim_cfg.hjson",
"{proj_root}/hw/ip/gpio/dv/gpio_sim_cfg.hjson",
diff --git a/hw/top_earlgrey/lint/top_earlgrey_dv_lint_cfgs.hjson b/hw/top_earlgrey/lint/top_earlgrey_dv_lint_cfgs.hjson
index 32b5c1c..8ac2301 100644
--- a/hw/top_earlgrey/lint/top_earlgrey_dv_lint_cfgs.hjson
+++ b/hw/top_earlgrey/lint/top_earlgrey_dv_lint_cfgs.hjson
@@ -38,6 +38,11 @@
import_cfgs: ["{proj_root}/hw/lint/tools/dvsim/common_lint_cfg.hjson"]
rel_path: "hw/ip/csrng/dv/lint/{tool}"
},
+ { name: dcd
+ fusesoc_core: lowrisc:dv:dcd_sim
+ import_cfgs: ["{proj_root}/hw/lint/tools/dvsim/common_lint_cfg.hjson"]
+ rel_path: "hw/ip/dcd/dv/lint/{tool}"
+ },
{ name: entropy_src
fusesoc_core: lowrisc:dv:entropy_src_sim
import_cfgs: ["{proj_root}/hw/lint/tools/dvsim/common_lint_cfg.hjson"]
diff --git a/util/build_docs.py b/util/build_docs.py
index cc4ee04..e45d5f4 100755
--- a/util/build_docs.py
+++ b/util/build_docs.py
@@ -57,6 +57,7 @@
"hw/top_earlgrey/ip/alert_handler/data/autogen/alert_handler.hjson",
"hw/ip/entropy_src/data/entropy_src.hjson",
"hw/ip/csrng/data/csrng.hjson",
+ "hw/ip/dcd/data/dcd.hjson",
"hw/ip/edn/data/edn.hjson",
"hw/ip/flash_ctrl/data/flash_ctrl.hjson",
"hw/ip/gpio/data/gpio.hjson",
@@ -96,6 +97,7 @@
"hw/ip/aon_timer/data/aon_timer_testplan.hjson",
"hw/ip/entropy_src/data/entropy_src_testplan.hjson",
"hw/ip/csrng/data/csrng_testplan.hjson",
+ "hw/ip/dcd/data/dcd_testplan.hjson",
"hw/ip/edn/data/edn_testplan.hjson",
"hw/ip/flash_ctrl/data/flash_ctrl_testplan.hjson",
"hw/ip/gpio/data/gpio_testplan.hjson",
