[primgen] Instantiate tech libs in stable order
The wrapper SV module instantiates primitives for all technology
libraries it finds. The ordering is not deterministic. Functionally,
the ordering doesn't matter, but if primitives are checked in or
otherwise compared, it changes in order lead to unnecessary churn. Sort
the list to make give stability.
Signed-off-by: Philipp Wagner <phw@lowrisc.org>
diff --git a/hw/ip/prim/util/primgen.py b/hw/ip/prim/util/primgen.py
index 3a3f1a3..c2b265b 100755
--- a/hw/ip/prim/util/primgen.py
+++ b/hw/ip/prim/util/primgen.py
@@ -328,9 +328,12 @@
def _create_instances(prim_name, techlibs, parameters):
""" Build SystemVerilog code instantiating primitives from the techlib """
- techlibs_wo_generic = [
+
+ # Sort list of technology libraries to produce a stable ordering in the
+ # generated wrapper.
+ techlibs_wo_generic = sorted([
techlib for techlib in techlibs if techlib != 'generic'
- ]
+ ])
techlibs_generic_last = techlibs_wo_generic + ['generic']
if not techlibs_wo_generic:
