commit 0f1a9f2f8b372069c3913d4710199c839969c6c8
author Philipp Wagner <phw@lowrisc.org> Tue Jul 20 15:15:20 2021 +0100
committer Philipp Wagner <mail@philipp-wagner.com> Tue Jul 20 17:16:33 2021 +0100
tree 12e8b0aee8da9947d1970e4abd5ea839cbcf698b
parent cc906c0a8e91e9566794561fc5573cd709e3fe0c

[otbn] Make WSR numbers match the implementation

In 19afa99bead8fa0c44c1e9e6067deb6ed233f7cc we swapped the ACC and URND
WSRs, but ultimately the documentation wasn't updated to reflect that.
(I'm sure I had those changes at some point, seems like they got lost
during a rebase.)

Signed-off-by: Philipp Wagner <phw@lowrisc.org>

hw/ip/otbn/doc/_index.md

diff --git a/hw/ip/otbn/doc/_index.md b/hw/ip/otbn/doc/_index.md
index 4784f7a..ff44d4c 100644
--- a/hw/ip/otbn/doc/_index.md
+++ b/hw/ip/otbn/doc/_index.md
@@ -355,14 +355,6 @@
     </tr>
     <tr>
       <td>0x2</td>
-      <td>RW</td>
-      <td>ACC</td>
-      <td>
-        The accumulator register used by the {{< otbnInsnRef "BN.MULQACC" >}} instruction.
-      </td>
-    </tr>
-    <tr>
-      <td>0x3</td>
       <td>URND</td>
       <td>R</td>
       <td>
@@ -374,6 +366,14 @@
 Reads never stall.
       </td>
     </tr>
+    <tr>
+      <td>0x3</td>
+      <td>RW</td>
+      <td>ACC</td>
+      <td>
+        The accumulator register used by the {{< otbnInsnRef "BN.MULQACC" >}} instruction.
+      </td>
+    </tr>
   </tbody>
 </table>