| commit | 0e0c1a99f5a45584017d42bc8cba0aa376745908 | [log] [tgz] |
|---|---|---|
| author | Eunchan Kim <eunchan@opentitan.org> | Wed Nov 17 22:10:34 2021 +0000 |
| committer | Eunchan Kim <eunchan@opentitan.org> | Thu Nov 18 16:41:58 2021 +0000 |
| tree | 6ded13e09376750f65f944a167016e945e8ff859 | |
| parent | 085cef5b6b2b7dc2044cb4679623999871d561c3 [diff] |
[kmac] Use Empty signal from FIFO The issue has been discussed in #9202 KMAC MsgFIFO sees the FIFO depth to calculate the empty status of SYNC FIFO. When the logic writes data and the receiver acked the read data at the same time and the FIFO has been empty already, the empty status won't be de-asserted as the `depth` wont be increased. The issue is that SW will not get the fifo empty event due to the behavior described above if the receiver logic is faster than the SW. This commit revises the msgfifo logic to see the `rvalid` as an inversion of the empty status. The scenario above will lower the `empty` signal with the fix. Co-Authored-by: Cindy Chen <chencindy@opentitan.org> Signed-off-by: Eunchan Kim <eunchan@opentitan.org>
OpenTitan is an open source silicon Root of Trust (RoT) project. OpenTitan will make the silicon RoT design and implementation more transparent, trustworthy, and secure for enterprises, platform providers, and chip manufacturers. OpenTitan is administered by lowRISC CIC as a collaborative project to produce high quality, open IP for instantiation as a full-featured product. See the OpenTitan site and OpenTitan docs for more information about the project.
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