[otbn] Don't flop `done_o` output from otbn_core

The `done_o` output flops into top-level register/interrupt primitives
so there's no need to flop it internally.

Signed-off-by: Greg Chadwick <gac@lowrisc.org>

hw/ip/otbn/dv/verilator/otbn_top_sim.sv

diff --git a/hw/ip/otbn/dv/verilator/otbn_top_sim.sv b/hw/ip/otbn/dv/verilator/otbn_top_sim.sv
index 9414c0e..decac66 100644
--- a/hw/ip/otbn/dv/verilator/otbn_top_sim.sv
+++ b/hw/ip/otbn/dv/verilator/otbn_top_sim.sv
@@ -18,7 +18,7 @@
   localparam int ImemAddrWidth = prim_util_pkg::vbits(ImemSizeByte);
   localparam int DmemAddrWidth = prim_util_pkg::vbits(DmemSizeByte);
 
-  logic otbn_done;
+  logic otbn_done_d, otbn_done_q;
   logic otbn_start;
   logic otbn_start_done;
 
@@ -49,7 +49,7 @@
     .rst_ni        ( IO_RST_N      ),
 
     .start_i       ( otbn_start    ),
-    .done_o        ( otbn_done     ),
+    .done_o        ( otbn_done_d   ),
 
     .start_addr_i  ( ImemStartAddr ),
 
@@ -73,11 +73,13 @@
   bind otbn_core otbn_trace_intf #(.ImemAddrWidth, .DmemAddrWidth) i_otbn_trace_intf (.*);
   bind otbn_core otbn_tracer u_otbn_tracer(.*, .otbn_trace(i_otbn_trace_intf));
 
-  // Pulse otbn_start for 1 cycle immediately out of reset
+  // Pulse otbn_start for 1 cycle immediately out of reset.
+  // Flop `done_o` from otbn_core to match up with model done signal.
   always @(posedge IO_CLK or negedge IO_RST_N) begin
     if(!IO_RST_N) begin
       otbn_start      <= 1'b0;
       otbn_start_done <= 1'b0;
+      otbn_done_q     <= 1'b0;
     end else begin
       if (!otbn_start_done) begin
         otbn_start      <= 1'b1;
@@ -85,6 +87,8 @@
       end else if (otbn_start) begin
         otbn_start <= 1'b0;
       end
+
+      otbn_done_q <= otbn_done_d;
     end
   end
 
@@ -155,7 +159,7 @@
     if (!IO_RST_N) begin
       finish_counter <= 2'd0;
     end else begin
-      if (otbn_done) begin
+      if (otbn_done_q) begin
         finish_counter <= 2'd1;
       end
 
@@ -209,9 +213,9 @@
       done_mismatch_latched <= 1'b0;
       model_err_latched     <= 1'b0;
     end else begin
-      if (otbn_done != otbn_model_done) begin
-        $display("ERROR: At time %0t, otbn_done != otbn_model_done (%0d != %0d).",
-                 $time, otbn_done, otbn_model_done);
+      if (otbn_done_q != otbn_model_done) begin
+        $display("ERROR: At time %0t, otbn_done_q != otbn_model_done (%0d != %0d).",
+                 $time, otbn_done_q, otbn_model_done);
         done_mismatch_latched <= 1'b1;
       end
       model_err_latched <= model_err_latched | otbn_model_err;

hw/ip/otbn/rtl/otbn_controller.sv

diff --git a/hw/ip/otbn/rtl/otbn_controller.sv b/hw/ip/otbn/rtl/otbn_controller.sv
index 289c224..7af857e 100644
--- a/hw/ip/otbn/rtl/otbn_controller.sv
+++ b/hw/ip/otbn/rtl/otbn_controller.sv
@@ -100,9 +100,6 @@
   output logic                        ispr_bignum_wr_en_o,
   input  logic [WLEN-1:0]             ispr_rdata_i
 );
-
-  logic done_d, done_q;
-
   otbn_state_e state_q, state_d;
 
   logic stall;
@@ -158,17 +155,7 @@
   assign mem_stall = lsu_load_req_o;
 
   assign stall = mem_stall;
-  assign done_d = insn_valid_i && insn_dec_shared_i.ecall_insn;
-
-  always_ff @(posedge clk_i or negedge rst_ni) begin
-    if (!rst_ni) begin
-      done_q <= 1'b0;
-    end else begin
-      done_q <= done_d;
-    end
-  end
-
-  assign done_o = done_q;
+  assign done_o = insn_valid_i && insn_dec_shared_i.ecall_insn;
 
   // Branch taken when there is a valid branch instruction and comparison passes or a valid jump
   // instruction (which is always taken)
@@ -198,7 +185,7 @@
       OtbnStateRun: begin
         insn_fetch_req_valid_o = 1'b1;
 
-        if (done_d) begin
+        if (done_o) begin
           state_d                = OtbnStateHalt;
           insn_fetch_req_valid_o = 1'b0;
         end else begin